Semiconductor device

Abstract

Embodiments provide a semiconductor device capable of improving current measurement accuracy. A semiconductor device according to one embodiment includes: a first circuit configured to drive a load connected to a first terminal by supplying a load current to the load; and a third circuit that includes a second circuit that copies the load current on the basis of a first voltage at the first terminal and outputs the copied first current, and that monitors a second current on the basis of the first current. The third circuit further includes a fourth circuit that adjusts the second current when the load current is not supplied to the load.

Description

[0001] This application claims the priority of Japanese Patent Application No. 2023-160083 (filing date: September 25, 2023) as a basic application. The present application incorporates the entire contents of the basic application by reference. Technical Field

[0002] Embodiments of the present invention relate to a semiconductor device. Background Art

[0003] A semiconductor device is known that includes a driver circuit that drives an external load and a current monitor circuit that monitors a current flowing through the load. Summary of the invention

[0004] The technical problem to be solved by the present invention is to provide a semiconductor device capable of improving the accuracy of current measurement.

[0005] A semiconductor device according to an embodiment includes: a first circuit for driving a load by supplying a load current to a load connectable to a first terminal; and a third circuit including a second circuit for replicating (copying) the load current based on a first voltage of the first terminal and outputting the copied first current, and monitoring a second current based on the first current. The third circuit also includes a fourth circuit for adjusting the second current when the load current is not supplied to the load. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figure 1 This is a circuit diagram showing an example of the configuration of the semiconductor device according to the first embodiment.

[0007] Figure 2 This is a diagram showing the distribution of a voltage applied to an inverting input terminal of an operational amplifier when an input offset voltage is present and no load is applied in the semiconductor device according to the first embodiment.

[0008] Figure 3 This is a diagram showing the distribution of the monitoring current output from the current monitoring terminal when an input bias voltage is present and there is no load in the semiconductor device according to the first embodiment.

[0009] Figure 4 This is a circuit diagram showing the connection relationship during the determination operation of the semiconductor device according to the first embodiment.

[0010] Figure 5 This is a circuit diagram showing a connection relationship during a first adjustment operation of the semiconductor device according to the first embodiment.

[0011] Figure 6This is a diagram showing an example of the relationship between the transition of the current value and the transition of the value of the voltage comparison result when the first adjustment operation of the semiconductor device according to the first embodiment is executed.

[0012] Figure 7 This is a circuit diagram showing the connection relationship during the second adjustment operation of the semiconductor device according to the first embodiment.

[0013] Figure 8 This is a diagram showing an example of the relationship between the transition of the current value and the transition of the value of the voltage comparison result when the second adjustment operation of the semiconductor device according to the first embodiment is executed.

[0014] Fig. 9 This is a flowchart showing an example of the current adjustment operation of the semiconductor device according to the first embodiment.

[0015] Fig.10 This is a flowchart showing an example of the current monitoring operation of the semiconductor device according to the first embodiment.

[0016] Fig.11 This is a circuit diagram showing the connection relationship during the current monitoring operation of the semiconductor device according to the first embodiment.

[0017] Fig.12 This is a circuit diagram showing the connection relationship during the current monitoring operation of the semiconductor device according to the first embodiment.

[0018] Fig.13 This is a circuit diagram showing an example of the configuration of a semiconductor device according to the second embodiment.

[0019] Fig.14 This is a circuit diagram showing the connection relationship during the first adjustment operation of the semiconductor device according to the second embodiment.

[0020] Fig.15 This is a circuit diagram showing the connection relationship during the second adjustment operation of the semiconductor device according to the second embodiment.

[0021] Fig.16 This is a circuit diagram showing an example of the configuration of a semiconductor device according to the third embodiment.

[0022] Fig.17 This is a circuit diagram showing an example of the configuration of a semiconductor device according to a modification of the third embodiment.

[0023] Description of symbols

[0024] 1, 1A, 1B, 1C semiconductor devices; 2 control circuit; 3 drive circuit; 4, 4A current monitoring circuit; 5, 5A mirror circuit; 6 current adjustment circuit; 7 current detection circuit; 8 A / D converter; 41, 42 variable current source; 61 trimming control circuit; 62 register; T1 first power supply voltage terminal; T2 second power supply voltage terminal; T3 ground voltage terminal; T4 input / output terminal; T5 current monitoring terminal; N1~N7 NMOS transistors; P1~P3 PMOS transistors; AMP operational amplifier; SW1~SW4 switches; CMP converter; RL, Rm resistor elements; LD load. DETAILED DESCRIPTION

[0025] Hereinafter, the embodiments will be described with reference to the accompanying drawings. In the following description, the same reference numerals are used for components having substantially the same function and structure, and repeated descriptions are sometimes omitted. In particular, when elements having the same structure are to be distinguished from each other, different characters or numbers are sometimes added to the end of the same reference numeral. In addition, all descriptions of a certain embodiment are also applicable to the descriptions of other embodiments unless explicitly or self-evidently excluded.

[0026] 1. First Implementation Method

[0027] A semiconductor device according to the first embodiment will be described.

[0028] 1.1 Composition

[0029] 1.1.1 Circuit Configuration (Structure) of Semiconductor Device

[0030] use Figure 1 The circuit configuration of the semiconductor device according to this embodiment will be described. Figure 1 A circuit diagram showing an example of the structure of a semiconductor device. In the following description, when the source and drain of a transistor are not limited, either the source or the drain of the transistor is described as "one end of the transistor", and the other of the source or the drain of the transistor is described as "the other end of the transistor".

[0031] The semiconductor device 1 is, for example, an IC (Integrated Circuit) chip. The semiconductor device 1 drives an external load LD by supplying current to the load LD. The load LD is, for example, a motor. Hereinafter, the current supplied to the load LD (flowing through the load LD) is referred to as "load current". In addition, the semiconductor device 1 monitors the load current.

[0032] like Figure 1As shown, the semiconductor device 1 includes a first power supply voltage terminal T1 , a second power supply voltage terminal T2 , a ground voltage terminal T3 , an input / output terminal T4 , a current monitoring terminal T5 , a control circuit 2 , a drive circuit 3 , and a current monitoring circuit 4 .

[0033] The first power supply voltage terminal T1 is a terminal for supplying a power supply voltage VCC to a circuit (eg, current monitoring circuit 4) within the semiconductor device 1. The power supply voltage VCC is supplied to the first power supply voltage terminal T1 from outside the semiconductor device 1.

[0034] The second power supply voltage terminal T2 is a terminal for supplying power supply voltage VB to the circuits (e.g., drive circuit 3 and current monitoring circuit 4) in semiconductor device 1. Voltage VB is, for example, a voltage higher than voltage VCC. Power supply voltage VB is supplied to second power supply voltage terminal T2 from outside semiconductor device 1.

[0035] The ground voltage terminal T3 is a terminal for supplying the ground voltage GND to the circuits (eg, the drive circuit 3 and the current monitoring circuit 4) in the semiconductor device 1. The ground voltage GND is supplied to the ground voltage terminal T3 from outside the semiconductor device 1. Alternatively, the ground voltage terminal T3 may be grounded.

[0036] The input / output terminal T4 is a terminal for supplying a load current to the load LD. The input / output terminal T4 is connected to the load LD. The load current is input to the input / output terminal T4 or output from the input / output terminal T4. The voltage VOUT of the input / output terminal T4 is input to the input / output terminal T4 or output from the input / output terminal T4.

[0037] The current monitoring terminal T5 is a terminal for outputting a monitoring current described later. The monitoring current is, for example, a current that is 1 / k times (k is an integer greater than 1) the load current. The current monitoring terminal T5 is, for example, connected to one end of a resistor element RL outside the semiconductor device 1. The other end of the resistor element RL is grounded. By detecting the voltage VCM of the current monitoring terminal T5, the monitoring current can be detected.

[0038] The control circuit 2 is a circuit that controls the overall operation of the semiconductor device 1. The control circuit 2 controls the operation of the drive circuit 3 and the current monitoring circuit 4 based on a request signal (not shown) (for example, a signal received from outside the semiconductor device 1). For example, the control circuit 2 generates control signals CS1 and CS2 for controlling the drive circuit 3 and a control signal CS3 for controlling the current monitoring circuit 4 based on the request signal.

[0039] The drive circuit 3 is a circuit that drives the load LD by supplying a load current to the load LD. The details of the drive circuit 3 will be described later.

[0040] The current monitoring circuit 4 is a circuit that monitors the load current flowing through the load LD, more specifically, the current based on the load current. In addition, the current monitoring circuit 4 adjusts the current based on the load current. The details of the current monitoring circuit 4 will be described later.

[0041] 1.1.2 Configuration of the drive circuit

[0042] The circuit configuration of the drive circuit 3 will be described.

[0043] like Figure 1 As shown, the driving circuit 3 includes n-channel MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) N1 and N2. Hereinafter, the n-channel MOSFETs are referred to as "NMOS transistors".

[0044] The NMOS transistor N1 has, for example, a gate width W1. The gate of the NMOS transistor N1 is connected to a node ND1. A control signal CS1 is input to the node ND1 from the control circuit 2. That is, the control signal CS1 is input to the gate of the NMOS transistor N1. One end of the NMOS transistor N1 is connected to the second power supply voltage terminal T2. The other end of the NMOS transistor N1 is connected to a node ND3.

[0045] The NMOS transistor N2 has, for example, a gate width W2. The gate of the NMOS transistor N2 is connected to the node ND2. A control signal CS2 is input to the node ND2 from the control circuit 2. That is, the control signal CS2 is input to the gate of the NMOS transistor N2. The control signal CS2 is a signal that inverts the logic level of the control signal CS1. One end of the NMOS transistor N2 is connected to the node ND3. The other end of the NMOS transistor N2 is connected to the ground voltage terminal T3.

[0046] The input / output terminal T4 is connected to the node ND3 . That is, the other end of the NMOS transistor N1 and one end of the NMOS transistor N2 are connected to the input / output terminal T4 .

[0047] When the control signal CS1 is at "H" level and the control signal CS2 is at "L" level, the NMOS transistor N1 is turned on and the NMOS transistor N2 is turned off. As a result, the load current flows from the second power supply voltage terminal T2 to the load LD via the NMOS transistor N1 and the input / output terminal T4.

[0048] On the other hand, when the control signal CS1 is at the "L" level and the control signal CS2 is at the "H" level, the NMOS transistor N1 is set to the cut-off state, and the NMOS transistor N2 is set to the conducting state. As a result, a load current flows through the load LD. That is, the load current flows from the load LD through the input / output terminal T4 and the NMOS transistor N2 to the ground voltage terminal T3. Hereinafter, the load current will be referred to as "load current Idrv". In Figure 1 FIG. shows the case where the load current Idrv flows from the load LD through the input / output terminal T4 and the NMOS transistor N2 to the ground voltage terminal T3.

[0049] 1.1.3 Configuration of Current Monitoring Circuit

[0050] The circuit configuration of the current monitoring circuit 4 will be described. The semiconductor device 1 according to the present embodiment monitors the load current Idrv when the load LD is driven by the NMOS transistor N2 of the drive circuit 3. That is, the current monitoring circuit 4 is a current monitoring circuit for low-side driving.

[0051] As Figure 1 shown, the current monitoring circuit 4 includes a mirror circuit 5, p-channel MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) P1 and P2, switches SW1 and SW2, variable current sources 41 and 42, and a current adjustment circuit 6. Hereinafter, the p-channel MOSFET will be referred to as "PMOS transistor".

[0052] The mirror circuit 5 is a circuit that replicates the load current Idrv based on the voltage VOUT of the input / output terminal T4 and outputs the replicated current. As Figure 1 shown, the mirror circuit 5 includes NMOS transistors N3 and N4, and an operational amplifier AMP.

[0053] The NMOS transistor N3 has, for example, a gate width w2 (w2 < W2). The gate of the NMOS transistor N3 is connected to the node ND2. That is, the control signal CS2 is input to the gate of the NMOS transistor N3. One end of the NMOS transistor N3 is connected to the node ND5. The other end of the NMOS transistor N3 is connected to the ground voltage terminal T3.

[0054] The operational amplifier AMP has a first input terminal, a second input terminal, and an output terminal. The first input terminal of the operational amplifier AMP is a non-inverting input terminal. The second input terminal of the operational amplifier AMP is an inverting input terminal. The first input terminal of the operational amplifier AMP is connected to the node ND3. That is, the voltage VOUT of the input-output terminal T4 is applied to the first input terminal of the operational amplifier AMP. The second input terminal of the operational amplifier AMP is connected to the node ND5. That is, the voltage V5 of the node ND5 is applied to the second input-output terminal of the operational amplifier AMP. The operational amplifier AMP outputs a voltage Va from the output terminal based on the voltage VOUT and the voltage V5. The output terminal of the operational amplifier AMP is connected to the node ND4.

[0055] The gate of the NMOS transistor N4 is connected to the node ND4. That is, the voltage Va is applied to the gate of the NMOS transistor N4. One end of the NMOS transistor N4 is connected to the node ND6. The other end of the NMOS transistor N4 is connected to the node ND5.

[0056] The gate of the PMOS transistor P1 is connected to the node ND6. One end of the PMOS transistor P1 is connected to the first power supply voltage terminal T1. The other end of the PMOS transistor P1 is connected to the node ND6.

[0057] The gate of the PMOS transistor P2 is connected to the node ND6. One end of the PMOS transistor P2 is connected to the first power supply voltage terminal T1. The other end of the PMOS transistor P2 is connected to the node ND7.

[0058] The switch SW1 is an element that switches connection and disconnection (disconnection) between the first power supply voltage terminal T1 and the variable current source 41. One end of the switch SW1 is connected to the first power supply voltage terminal T1. The other end of the switch SW1 is connected to the node ND8.

[0059] The switch SW2 is an element that switches between connection and disconnection between the node ND6 and the variable current source 42. One end of the switch SW2 is connected to the node ND6, and the other end of the switch SW2 is connected to the node ND9.

[0060] The variable current source 41 supplies a current In1 from the first power supply voltage terminal T1 to the node ND6. The current In1 is variable. One end of the variable current source 41 is connected to the node ND8. The other end of the variable current source 41 is connected to the node ND6.

[0061] The variable current source 42 supplies a current Ip1 from the node ND6 to the ground voltage terminal T3. The current Ip1 is variable. One end of the variable current source 42 is connected to the node ND9. The other end of the variable current source 42 is connected to the ground voltage terminal T3.

[0062] Through the operational amplifier AMP and the NMOS transistor N4, the operational amplifier AMP outputs a voltage Va that makes the voltage VOUT equal to the voltage V5. That is, the voltage V5 is controlled to be equal to the voltage VOUT. Therefore, when the load LD is driven by the NMOS transistor N2 and the load current Idrv flows through the load LD, the current Idrv×(w2 / W2) flows from the first power supply voltage terminal T1 to the ground voltage terminal T3 via the PMOS transistor P1, the NMOS transistor N4 and the NMOS transistor N3. Hereinafter, this current is recorded as "copy current Imr1". Since the PMOS transistor P1 and the PMOS transistor P2 form a current mirror, a current of the same magnitude as the current Imr1 also flows from the first power supply voltage terminal T1 to the node ND7 via the PMOS transistor P2. Hereinafter, this current is recorded as "monitoring current Icm". By connecting the node ND7 to the current monitoring terminal T5, the monitoring current Icm can be monitored at the current monitoring terminal T5. Since the monitoring current Icm is smaller than the load current Idrv, the power consumption of the current monitoring circuit 4 can be reduced.

[0063] The operational amplifier AMP sometimes has an input bias voltage. The input bias voltage changes over time. In addition, the input bias voltage also changes according to temperature and stress. When the operational amplifier AMP has an input bias voltage, due to the input bias voltage, the voltage V5 of the node ND5 becomes a voltage that is offset (shifted) to the positive (plus) side compared to the voltage VOUT of the input / output terminal T4, or a voltage that is offset to the negative (minus) side compared to the voltage VOUT.

[0064] When the voltage V5 is shifted to the positive side compared with the voltage VOUT, the voltage between the gate and the source of the NMOS transistor N4 increases, so the replica current Imr1 increases compared with the case where the voltage V5 is equal to the voltage VOUT.

[0065] On the other hand, when the voltage V5 is shifted to the negative side compared with the voltage VOUT, since the gate-source voltage of the NMOS transistor N4 becomes smaller, the replica current Imr1 becomes smaller than when the voltage V5 is equal to the voltage VOUT.

[0066] Here, consider the case where the load current Idrv is not supplied to the load LD, that is, the case where the load current Idrv is 0. Hereinafter, the case where the load current Idrv is not supplied to the load LD is also described as "no-load case". When there is no load and the voltage V5 is equal to the voltage VOUT, the replica current Imr1 becomes 0, and the monitoring current Icm also becomes 0. On the other hand, when there is no load and the voltage V5 is offset to the positive side compared with the voltage VOUT, as described above, the replica current Imr1 is larger than the current value (=0) when the voltage V5 is equal to the voltage VOUT, and the monitoring current Icm is also larger than 0. On the other hand, when there is no load and the voltage V5 is offset to the negative side compared with the voltage VOUT, as described above, the replica current Imr1 is smaller than the current value (=0) when the voltage V5 is equal to the voltage VOUT. In this case, the monitoring current Icm can only output 0.

[0067] Based on the above, when the operational amplifier AMP has an input bias voltage and is unloaded, the voltage V5 is expressed as follows: Figure 2 That kind of distribution. Figure 2 : This is a diagram showing the distribution of the voltage V5 when there is an input bias voltage and no load. The vertical axis is the number of samples, and the horizontal axis is the voltage V5 when there is no load.

[0068] As described above, when the voltage V5 deviates to the positive side compared with the voltage VOUT, the monitoring current Icm is distributed on the positive side of 0. When the voltage V5 deviates to the negative side compared with the voltage VOUT, the monitoring current Icm becomes zero.

[0069] When there is no load and the voltage V5 is offset to the negative side compared to the voltage VOUT, as described above, the replica current Imr1 is less than 0. That is, the replica current Imr1 becomes a negative value. Therefore, in reality, the replica current Imr1 does not flow through the nodes ND5 and ND6, and the monitoring current Icm does not flow through the node ND7. That is, the monitoring current Icm outputs only 0 from the current monitoring terminal T5. Therefore, when the operational amplifier AMP has an input bias voltage and there is no load, the monitoring current Icm output from the current monitoring terminal T5 is expressed as follows: Figure 3 That kind of distribution. Figure 3 : is a graph showing the distribution of the monitoring current Icm output from the current monitoring terminal T5 when there is an input bias voltage and no load. The vertical axis is the number of samples. The horizontal axis is the monitoring current Icm when there is no load. Figure 3 In FIG. 1 , the distribution of the deviation of the monitoring current Icm from 0 when the voltage V5 deviates from the voltage VOUT is shown by the dotted line.

[0070] like Figure 3As shown, when the voltage V5 is offset to the positive side compared with the voltage VOUT, the monitoring current Icm output from the current monitoring terminal T5 is distributed on the positive side of 0. When the voltage V5 is offset to the negative side compared with the voltage VOUT, the monitoring current Icm output from the current monitoring terminal T5 is not distributed on the negative side of 0, but distributed at 0.

[0071] Thus, when the operational amplifier AMP has an input bias voltage and there is no load, the monitoring current Icm may not be 0 due to the influence of the input bias voltage. In other words, an error (a positive shift from 0 or a negative shift from 0) of the monitoring current Icm may occur.

[0072] When the load LD is driven, a relatively large current Idrv flows through the load LD. When the load current Idrv is relatively large, the error of the monitoring current Icm is smaller than the load current Idrv. In this case, the possibility of deterioration of the measurement accuracy of the monitoring current Icm is low. However, when the load current Idrv is 0, the error of the monitoring current Icm is larger than 0. In this case, the measurement accuracy of the monitoring current Icm may deteriorate.

[0073] The current regulating circuit 6 is a circuit that regulates the monitoring current Icm to be close to 0 when there is no load. More specifically, the current regulating circuit 6 is Figure 3 The monitoring current Icm is adjusted in such a way that the distribution of deviations from 0 of the monitoring current Icm shown by the dotted line converges to 0. Figure 1 As shown, the current adjustment circuit 6 includes switches SW3 and SW4 , a resistor Rm, a comparator CMP, and a trimming control circuit 61 .

[0074] The switch SW3 is an element for switching between connection and disconnection between the node ND7 and the current monitoring terminal T5. One end of the switch SW3 is connected to the node ND7. The other end of the switch SW3 is connected to the node ND12.

[0075] The switch SW4 is an element that switches between connection and disconnection between the node ND7 and the resistance element Rm. One end of the switch SW4 is connected to the node ND7, and the other end of the switch SW4 is connected to the node ND10.

[0076] One end of the resistance element Rm is connected to the node ND10. The other end of the resistance element Rm is connected to the ground voltage terminal T3. The resistance value of the resistance element Rm is set in consideration of a trimming amount described later, for example.

[0077] The comparator CMP has a first input terminal, a second input terminal, and an output terminal. The first input terminal of the comparator CMP is an inverting input terminal. The second input terminal of the comparator CMP is a non-inverting input terminal. The first input terminal of the comparator CMP is connected to the node ND10. That is, the voltage Vm of the node ND10 is applied to the first input terminal of the comparator CMP. The reference voltage Vref is applied to the second input terminal of the comparator CMP. The comparator CMP compares the voltage Vm and the voltage Vref, and outputs the result of the comparison from the output terminal. Hereinafter, the result of the comparison is recorded as "comparison result RES". When the voltage Vm is greater than the voltage Vref, the comparator CMP outputs a signal of "L" level as the comparison result RES. On the other hand, when the voltage Vm is less than the voltage Vref, the comparator CMP outputs a signal of "H" level as the comparison result RES. The output terminal of the comparator CMP is connected to the node ND11. The reference voltage Vref is set, for example, in consideration of the value obtained by converting the input bias voltage into a current and the resistance value of the resistor Rm. In addition, the reference voltage Vref is set to a voltage such that when the voltage Vm is equal to or higher than the voltage Vref, the monitoring current Icm flows through the node ND10, and when the voltage Vm is less than the voltage Vref, the monitoring current Icm does not flow through the node ND10. For example, assuming that the resistance element Rm is 200 kΩ and the trimming amount dI described later is 1 μA, the reference voltage Vref is set to 0.1 V.

[0078] The trimming control circuit 61 is a circuit that adjusts the monitoring current Icm based on the comparison result RES. More specifically, the trimming control circuit 61 adjusts the current value of the variable current source 41 or the current value of the variable current source 42 based on the comparison result RES, thereby adjusting the monitoring current Icm. Hereinafter, the adjustment of the current value of the variable current source 41 or the current value of the variable current source 42 will also be described as "trimming". In addition, the trimming control circuit 61 controls the switches SW1 to SW4. Figure 1 As shown, the trimming control circuit 61 includes a register 62 .

[0079] The register 62 is a circuit for storing the result of adjustment by the current adjustment circuit 6. The result of adjustment by the current adjustment circuit 6 includes, for example, the current value of the variable current source 41 and the current value of the variable current source 42.

[0080] As described above, the current regulating circuit 6 compares the voltage Vm obtained by converting the monitoring current Icm into a voltage with the reference voltage Vref, and regulates the monitoring current Icm to be close to zero based on the comparison result RES.

[0081] 1.2 Action

[0082] The semiconductor device 1 includes a load driving action, a current monitoring action, and a current regulating action. The load driving action is an action of driving the load LD by supplying a load current Idrv to the load LD. The current monitoring action is an action of monitoring a monitoring current Icm based on the load current Idrv. The current regulating action is an action of regulating the monitoring current Icm to be close to 0 when there is no load.

[0083] 1.2.1 Current adjustment action

[0084] The current adjustment operation is described. The current adjustment operation includes a determination operation, a first adjustment operation, and a second adjustment operation. First, the determination operation, the first adjustment operation, and the second adjustment operation are described below.

[0085] (Determine action)

[0086] The determination operation is an operation of determining whether the monitoring current Icm is shifted to the positive side or the negative side compared to the current value (=0) when the voltage V5 of the node ND5 and the voltage VOUT of the input / output terminal T4 are equal under no load.

[0087] Figure 4 1 is a circuit diagram showing the connection relationship of the semiconductor device 1 during the determination operation. Figure 4 As shown, when the determination operation starts, the trimming control circuit 61 turns the switches SW1 to SW3 to the disconnected (OFF) state and turns the switch SW4 to the conducting (ON) state. Furthermore, the trimming control circuit 61 determines whether the monitoring current Icm is offset to the positive side or the negative side compared to 0 based on the comparison result RES output from the comparator CMP. When there is no load and the monitoring current Icm flows through the node ND10, the voltage Vm of the node ND10 becomes greater than the reference voltage Vref. On the other hand, when there is no load and the monitoring current Icm does not flow through the node ND10, the voltage Vm of the node ND10 is less than the reference voltage Vref. Therefore, when the comparison result RES is at the "L" level, the trimming control circuit 61 determines that the monitoring current Icm is offset to the positive side compared to 0. On the other hand, when the comparison result RES is at the "H" level, the trimming control circuit 61 determines that the monitoring current Icm is offset to the negative side compared to 0.

[0088] (1st adjustment action)

[0089] The first adjustment operation is an operation to adjust the monitoring current Icm to be close to 0 when there is no load and the determination operation determines that the monitoring current Icm is deviated to the positive side compared to 0 (when the voltage Vm is equal to or higher than the reference voltage Vref).

[0090] Figure 5This is a circuit diagram showing the connection relationship during the first adjustment operation of the semiconductor device 1. Hereinafter, the current flowing through the node ND5 is described as "current Ind5". The current flowing through the node ND6 is described as "current Ind6".

[0091] like Figure 5 As shown in FIG. 1 , when the first adjustment operation starts, the trimming control circuit 61 turns on the switches SW1 and SW4 and turns off the switches SW2 and SW3. Furthermore, the trimming control circuit 61 increases the current In1 of the variable current source 41 and selects the value of the current In1 in the first cycle processing described later before the comparison result RES output from the comparator CMP changes from the "L" level to the "H" level.

[0092] use Figure 6 A method of selecting the value of the current In1 will be described. Figure 6 This is a diagram showing an example of the relationship between the transition of the value of the current In1 and the transition of the value of the comparison result RES when the first adjustment operation is executed.

[0093] When the first adjustment operation starts without load, the trimming control circuit 61 sets the value of the current In1 of the variable current source 41 to 0. At this time, without load, the monitoring current Icm flows through the node ND10. That is, the monitoring current Icm is shifted to the positive side compared to 0. As a result, the comparison result RES becomes "L" level.

[0094] The trimming control circuit 61 reduces the monitoring current Icm to bring the monitoring current Icm closer to 0. For example, the trimming control circuit 61 reduces the monitoring current Icm by a predetermined trimming amount dI (increases the current In1 by the trimming amount dI). The trimming amount dI is, for example, 10 μA. Furthermore, the trimming control circuit 61 determines whether the comparison result RES changes from the “L” level to the “H” level.

[0095] When the comparison result RES does not change to the "H" level, the monitoring current Icm flows through the node ND10. Therefore, the trimming control circuit 61 further reduces the monitoring current Icm by the trimming amount dI, and determines whether the comparison result RES changes from the "L" level to the "H" level. For example, the trimming control circuit 61 further reduces the monitoring current Icm by the trimming amount dI compared to when the monitoring current Icm is reduced by the trimming amount dI (the current In1 is further increased by the trimming amount dI compared to when the current In1 is increased by the trimming amount dI). That is, the trimming control circuit 61 makes the total reduction amount of the monitoring current Icm -2×dI (the value of the current In1 is 2×dI). In addition, the trimming control circuit 61 determines whether the comparison result RES changes from the "L" level to the "H" level. Thereafter, when the comparison result RES does not change to the "H" level, as described above, a combination of the process of reducing the monitoring current Icm by the trimming amount dI (the process of increasing the current In1 by the trimming amount dI) and the process of determining whether the logic level of the comparison result RES has changed is repeated (hereinafter, these processes are also collectively recorded as the "first cycle process").

[0096] On the other hand, when the comparison result RES changes to the "H" level, the monitoring current Icm does not flow through the node ND10. Therefore, the trimming control circuit 61 selects the value of the current In1 during the previous trimming (first cycle processing). Figure 6 In the example of , when the trimming control circuit 61 sets the value of the current In1 to 6×dI, the comparison result RES changes to the “H” level. Thus, the trimming control circuit 61 selects 6×dI as the value of the current In1.

[0097] Thus, the trimming control circuit 61 repeatedly executes the first cycle process to select the value of the current In1 in the previous first cycle process when the logic level of the comparison result RES changes as the current In1. Then, the trimming control circuit 61 adjusts the value of the current In1 to the selected value of the current In1.

[0098] use Figure 5 Further Figure 6 This is illustrated by an example. Figure 6 In the example, the error (shift from 0 to the positive side) of the monitoring current Icm is 6×dI.

[0099] like Figure 5 As shown, when the current In1 = 0, the current In1 does not flow through the node ND8. The current Ind5 = Imr1 = 6 × dI flows through the node ND5. The current Ind6 = Ind5 - In1 = 6 × dI flows through the node ND6. Thus, the monitoring current Icm = Ind6 = 6 × dI flows through the node ND10.

[0100] When the current In1 = dI, the current In1 = dI flows through the node ND8. The current Ind5 = 6 × dI flows through the node ND5. The current Ind6 = 5 × dI flows through the node ND6. Thus, the monitoring current Icm = 5 × dI flows through the node ND10.

[0101] When the current In1 = 2×dI, the current In1 = 2×dI flows through the node ND8 . The current Ind5 = 6×dI flows through the node ND5 . The current Ind6 = 4×dI flows through the node ND6 . Thus, the monitoring current Icm = 4×dI flows through the node ND10 .

[0102] When the current In1 = 3×dI, the current In1 = 3×dI flows through the node ND8 . The current Ind5 = 6×dI flows through the node ND5 . The current Ind6 = 3×dI flows through the node ND6 . Thus, the monitoring current Icm = 3×dI flows through the node ND10 .

[0103] When the current In1 = 4×dI, the current In1 = 4×dI flows through the node ND8 . The current Ind5 = 6×dI flows through the node ND5 . The current Ind6 = 2×dI flows through the node ND6 . Thus, the monitoring current Icm = 2×dI flows through the node ND10 .

[0104] When the current In1 = 5×dI, the current In1 = 5×dI flows through the node ND8 . The current Ind5 = 6×dI flows through the node ND5 . The current Ind6 = dI flows through the node ND6 . Thus, the monitoring current Icm = dI flows through the node ND10 .

[0105] When the current In1 = 6×dI, the current In1 = 6×dI flows through the node ND8. The current Ind5 = 6×dI flows through the node ND5. The current Ind6 does not flow through the node ND6 (Ind6 = 0). Therefore, the monitoring current Icm does not flow through the node ND10 (Icm = 0).

[0106] Based on the above, the trimming control circuit 61 selects 6×dI as the value of the current In1. By performing the first adjustment operation in this way, the monitoring current Icm is adjusted to be close to zero.

[0107] (Second adjustment action)

[0108] The second adjustment operation is an operation of adjusting the monitoring current Icm to be close to 0 when there is no load and the determination operation determines that the monitoring current Icm is deviated to the negative side compared to 0 (when the voltage Vm is lower than the reference voltage Vref).

[0109] Figure 7ND9 is a circuit diagram showing a connection relationship during the second adjustment operation of the semiconductor device 1. Hereinafter, the current flowing through the node ND9 is referred to as “current Ind9”.

[0110] like Figure 7 As shown in FIG. 1 , when the second adjustment operation starts, the trimming control circuit 61 turns on the switches SW2 and SW4 and turns off the switches SW1 and SW3. Furthermore, the trimming control circuit 61 increases the current Ip1 of the variable current source 42 and selects the value of the current Ip1 in the second cycle processing described later before the comparison result RES changes from the "H" level to the "L" level.

[0111] use Figure 8 A method of selecting the value of the current Ip1 will be described. Figure 8 1 is a diagram showing an example of the relationship between the transition of the value of the current Ip1 and the transition of the value of the comparison result RES when the second adjustment operation is executed.

[0112] When the second adjustment operation starts without load, the trimming control circuit 61 sets the value of the current Ip1 of the variable current source 42 to 0. At this time, there is no load, and the monitoring current Icm does not flow through the node ND10. That is, the monitoring current Icm is offset to the negative side compared to 0. As a result, the comparison result RES becomes "H" level.

[0113] The trimming control circuit 61 increases the monitoring current Icm to bring it closer to 0. For example, the trimming control circuit 61 increases the monitoring current Icm by the trimming amount dI (increases the current Ip1 by the trimming amount dI). The trimming control circuit 61 also determines whether the comparison result RES changes from the "H" level to the "L" level.

[0114] When the comparison result RES does not change to the "L" level, the monitoring current Icm does not flow through the node ND10. Therefore, the trimming control circuit 61 further increases the monitoring current Icm by the trimming amount dI, and determines whether the comparison result RES changes from the "H" level to the "L" level. For example, the trimming control circuit 61 increases the monitoring current Icm by the trimming amount dI compared to when the monitoring current Icm is increased by the trimming amount dI (the current Ip1 is further increased by the trimming amount dI compared to when the current Ip1 is increased by the trimming amount dI). That is, the trimming control circuit 61 makes the total increase of the monitoring current Icm +2×dI (the value of the current Ip1 is 2×dI). Furthermore, the trimming control circuit 61 determines whether the comparison result RES changes from the "H" level to the "L" level. Thereafter, when the comparison result RES does not change to the "L" level, as described above, a combination of the process of increasing the monitoring current Icm by the trimming amount dI (the process of increasing the current Ip1 by the trimming amount dI) and the process of determining whether the logic level of the comparison result RES has changed is repeated (hereinafter, these processes are also collectively recorded as the "second cycle process").

[0115] On the other hand, when the comparison result RES changes to the "L" level, the monitoring current Icm flows through the node ND10. Therefore, the trimming control circuit 61 selects the value of the current Ip1 during the previous trimming (second cycle processing). Figure 8 In the example of , when the trimming control circuit 61 sets the value of the current Ip1 to 7×dI, the comparison result RES changes to the “L” level. Thus, the trimming control circuit 61 selects 6×dI as the value of the current Ip1.

[0116] Thus, by repeatedly executing the second loop process, the trimming control circuit 61 selects the value of the current Ip1 in the previous second loop process when the logic level of the comparison result RES changes as the current Ip1. Then, the trimming control circuit 61 adjusts the value of the current Ip1 to the selected value of the current Ip1.

[0117] use Figure 7 Further Figure 8 This is illustrated by an example. Figure 8 In the example, the error of the monitoring current Icm (the offset from 0 to the negative side) is -6×dI.

[0118] like Figure 7As shown, when the current Ip1 = 0, the current Ip1 does not flow through the node ND9. The current Ind5 does not flow through the node ND5 (Ind5 = Imr1 = -6 × dI). The current Ind6 does not flow through the node ND6 (Ind6 = Ind5 + Ip1 = -6 × dI). The monitoring current Icm does not flow through the node ND10 (Icm = Ind6 = -6 × dI).

[0119] When current Ip1=dI, current Ip1=dI flows through node ND9. Current Ind5 does not flow through node ND5 (Ind5=-6×dI). Current Ind6 does not flow through node ND6 (Ind6=-5×dI). Monitoring current Icm does not flow through node ND10 (Icm=-5×dI).

[0120] When the current Ip1=2×dI, the current Ip1=2×dI flows through the node ND9. The current Ind5 does not flow through the node ND5 (Ind5=-6×dI). The current Ind6 does not flow through the node ND6 (Ind6=-4×dI). The monitoring current Icm does not flow through the node ND10 (Icm=-4×dI).

[0121] When current Ip1=3×dI, current Ip1=3×dI flows through node ND9. Current Ind5 does not flow through node ND5 (Ind5=-6×dI). Current Ind6 does not flow through node ND6 (Ind6=-3×dI). Monitoring current Icm does not flow through node ND10 (Icm=-3×dI).

[0122] When the current Ip1=4×dI, the current Ip1=4×dI flows through the node ND9. The current Ind5 does not flow through the node ND5 (Ind5=-6×dI). The current Ind6 does not flow through the node ND6 (Ind6=-2×dI). The monitoring current Icm does not flow through the node ND10 (Icm=-2×dI).

[0123] When the current Ip1=5×dI, the current Ip1=5×dI flows through the node ND9. The current Ind5 does not flow through the node ND5 (Ind5=-6×dI). The current Ind6 does not flow through the node ND6 (Ind6=-dI). The monitoring current Icm does not flow through the node ND10 (Icm=-dI).

[0124] When the current Ip1=6×dI, the current Ip1=6×dI flows through the node ND9. The current Ind5 does not flow through the node ND5 (Ind5=-6×dI). The current Ind6 does not flow through the node ND6 (Ind6=0). The monitoring current Icm does not flow through the node ND10 (Icm=0).

[0125] When the current In1 = 7×dI, the current Ip1 = 7×dI flows through the node ND9. The current Ind5 does not flow through the node ND5 (Ind5 = -6×dI). The current Ind6 = dI flows through the node ND6. The monitoring current Icm = dI flows through the node ND10.

[0126] Based on the above, the trimming control circuit 61 selects 6×dI as the value of the current Ip1. By performing the second adjustment operation in this way, the monitoring current Icm is adjusted to be close to zero.

[0127] (flow chart)

[0128] Fig. 9 This is a flowchart showing an example of the current adjustment operation of the semiconductor device 1 .

[0129] When the semiconductor device 1 is powered on, or when the semiconductor device 1 receives a request signal from the outside requesting execution of a current adjustment operation (adjustment of the monitoring current Icm), the control circuit 2 generates an "L" level signal as the control signal CS3, and sends the generated "L" level control signal CS3 to the current monitoring circuit 4. The "L" level control signal CS3 is, for example, a signal instructing execution of a current adjustment operation.

[0130] When receiving the control signal CS3 of "L" level from the control circuit 2, steps S101 to S115 are executed. Steps S101 to S103 correspond to the determination operation. Steps S104 to S109 correspond to the first adjustment operation. Steps S110 to S115 correspond to the second adjustment operation.

[0131] First, the trimming control circuit 61 turns off the switches SW1 to SW3 and turns on the switch SW4 (S101). Next, the comparator CMP compares the voltage Vm of the node ND10 with the reference voltage Vref (S102). Next, the trimming control circuit 61 determines whether the comparison result RES of step S102 is at the "L" level (S103).

[0132] In step S103, when it is determined that the comparison result RES is at the "L" level (S103: Yes), the trimming control circuit 61 turns on the switch SW1 (S104). Next, the trimming control circuit 61 increases the value of the current In1 of the variable current source 41 by the trimming amount dI (S105). Next, the comparator CMP compares the voltage Vm and the voltage Vref (S106). Next, the trimming control circuit 61 determines whether the comparison result RES of step S106 has changed from the "L" level to the "H" level (S107).

[0133] In step S107 , when it is determined that the logic level of the comparison result RES has not changed ( S107 : No), the trimming control circuit 61 executes step S105 .

[0134] In step S107, when it is determined that the logic level of the comparison result RES has changed (S107: Yes), the trimming control circuit 61 stores "0" as the adjustment flag TFLG in the register 62 (S108). Next, the trimming control circuit 61 stores the value of the current In1 in the previous first cycle processing when the comparison result RES has changed in the register 62 as the set value In1s of the current In1 (S109).

[0135] On the other hand, in step S103, when it is determined that the comparison result RES is not at the "L" level (S103: No), the trimming control circuit 61 turns on the switch SW2 (S110). Next, the trimming control circuit 61 increases the value of the current Ip1 by the trimming amount dI (S111). Next, the comparator CMP compares the voltage Vm and the voltage Vref (S112). Next, the trimming control circuit 61 determines whether the comparison result RES of step S112 has changed from the "H" level to the "L" level (S113).

[0136] In step S113 , when it is determined that the logic level of the comparison result RES has not changed ( S113 : No), the trimming control circuit 61 executes step S111 .

[0137] In step S113, when it is determined that the logic level of the comparison result RES has changed (S113: Yes), the trimming control circuit 61 stores "1" as the adjustment flag TFLG in the register 62 (S114). Next, the trimming control circuit 61 stores the value of the current Ip1 in the second cycle processing before the comparison result RES has changed in the register 62 as the set value Ip1s of the current Ip1 (S115).

[0138] 1.2.2 Current monitoring action

[0139] The current monitoring operation is described. The current monitoring operation includes a setting operation and a monitoring execution operation. The setting operation is an operation of setting the current value of the variable current source 41 or the current value of the variable current source 42 to the current value adjusted by the current adjustment operation. The monitoring execution operation is an operation of monitoring the monitoring current Icm.

[0140] (flow chart)

[0141] Fig.10 This is a flowchart showing an example of the current monitoring operation of the semiconductor device 1 .

[0142] When the current adjustment operation is completed, the control circuit 2 generates an "H" level signal as the control signal CS3, and sends the generated "H" level control signal CS3 to the current monitoring circuit 4. The "H" level control signal CS3 is, for example, a signal instructing execution of the current monitoring operation.

[0143] When the control signal CS3 of "H" level is received from the control circuit 2, steps S201 to S208 are executed. Steps S201 to S205 and S207 and S208 correspond to the setting operation.

[0144] First, the trimming control circuit 61 turns off the switches SW1, SW2, and SW4, and turns on the switch SW3 (S201). Next, the trimming control circuit 61 obtains the adjustment flag TFLG, the set value In1s, and the set value Ip1s from the register 62 (S202). Next, the trimming control circuit 61 determines whether the adjustment flag TFLG is "0" (S203).

[0145] When the adjustment flag TFLG is "0" (S203: Yes), the trimming control circuit 61 sets the value of the current In1 of the variable current source 41 to the set value In1s (S204). Next, the trimming control circuit 61 turns on the switch SW1 (S205). Fig.11 The connection relationship of the semiconductor device 1 at this time is shown. Fig.11 This is a circuit diagram showing the connection relationship of the semiconductor device 1 during the current monitoring operation when the value of the current In1 of the variable current source 41 is adjusted to the set value In1s by the current adjustment operation.

[0146] On the other hand, when the adjustment flag TFLG is not "0" (S203: No), the trimming control circuit 61 sets the value of the current Ip1 of the variable current source 42 to the set value Ip1s (S207). Next, the trimming control circuit 61 turns on the switch SW2 (S208). Fig.12 The connection relationship of the semiconductor device 1 at this time is shown. Fig.12 This is a circuit diagram showing the connection relationship of the semiconductor device 1 during the current monitoring operation when the value of the current Ip1 of the variable current source 42 is adjusted to the set value Ip1s by the current adjustment operation.

[0147] When step S205 or step S208 is completed, the current monitoring circuit 4 starts the monitoring execution action (S206). The current monitoring circuit 4 can monitor the monitoring current Icm in a state where the current In1 is set to the current value In1s adjusted by the current adjustment action, or in a state where the current Ip1 is set to the current value Ip1s adjusted by the current adjustment action. That is, the current monitoring circuit 4 can monitor the monitoring current Icm in a state where the monitoring current Icm is adjusted. Therefore, the current monitoring circuit 4 can detect the monitoring current Icm having a value relatively close to 0 in the absence of load.

[0148] 1.3 Effects of this Implementation

[0149] In a semiconductor device including a drive circuit for driving an external load and a current monitoring circuit for monitoring a current flowing through the load, as described above, when the operational amplifier AMP has an input bias voltage and there is no load, the measurement accuracy of the monitoring current Icm may deteriorate.

[0150] The semiconductor device 1 involved in this embodiment includes a drive circuit 3 and a current monitoring circuit 4. The drive circuit 3 drives the load LD by supplying a load current Idrv to the load LD that can be connected to the input / output terminal T4. The current monitoring circuit 4 includes a mirror circuit 5 that copies the load current Idrv based on the voltage VOUT of the input / output terminal T4 and outputs the copied current Imr1, and monitors the monitoring current Icm based on the current Imr1. In addition, the current monitoring circuit 4 includes a current adjustment circuit 6 that adjusts the monitoring current Icm when there is no load. The current adjustment action is performed by the current adjustment circuit 6, and the current monitoring circuit 4 can monitor the monitoring current Icm in a state adjusted by the current adjustment action. The adjustment performed by the current adjustment circuit 6 takes into account the adjustment of the input bias voltage. Therefore, the current monitoring circuit 4 can detect the monitoring current Icm having a value relatively close to 0 when there is no load. Therefore, according to this embodiment, the current measurement accuracy of the monitoring current Icm can be improved.

[0151] 2. Second Implementation Method

[0152] A semiconductor device according to a second embodiment will be described. In a semiconductor device 1A according to the second embodiment, the configuration of a current monitoring circuit 4 is different from that of the first embodiment. In the following description, differences from the first embodiment will be described.

[0153] 2.1 Circuit Configuration of Semiconductor Devices

[0154] use Fig.13 A circuit configuration of a semiconductor device 1A according to the present embodiment will be described. Fig.13 This is a circuit diagram showing an example of the configuration of the semiconductor device 1A.

[0155] As Fig.13 shown, the semiconductor device 1A includes a first power supply voltage terminal T1, a second power supply voltage terminal T2, a ground voltage terminal T3, an input / output terminal T4, a current monitoring terminal T5, a control circuit 2, a drive circuit 3, and a current monitoring circuit 4A. The configuration other than the current monitoring circuit 4A is the same as that shown in the first embodiment Figure 1 . In Fig.13 , a case where the load current Idrv flows from the second power supply voltage terminal T2 through the NMOS transistor N1 and the input / output terminal T4 to the load LD is shown.

[0156] 2.2 Configuration of the Current Monitoring Circuit

[0157] The circuit configuration of the current monitoring circuit 4A will be described. The semiconductor device 1A according to the present embodiment monitors the load current Idrv when the load LD is driven by the NMOS transistor N1 of the drive circuit 3. That is, the current monitoring circuit 4A is a current monitoring circuit for high-side driving.

[0158] As Fig.13 shown, the current monitoring circuit 4A includes a mirror circuit 5A, PMOS transistors P1 and P2, NMOS transistors N6 and N7, switches SW1 and SW2, variable current sources 41 and 42, and a current adjustment circuit 6. The configuration other than the mirror circuit 5A and the NMOS transistors N6 and N7 is the same as that shown in the first embodiment Figure 1 .

[0159] The mirror circuit 5A includes an NMOS transistor N5, a PMOS transistor P3, and an operational amplifier AMP. The configuration of the operational amplifier AMP is the same as that shown in the first embodiment Figure 1 .

[0160] The NMOS transistor N5 has, for example, a gate width w1 (w1 < W1). The gate of the NMOS transistor N5 is connected to the node ND1. That is, a control signal CS1 is input to the gate of the NMOS transistor N5. One end of the NMOS transistor N5 is connected to the node ND21. The other end of the NMOS transistor N5 is connected to the second power supply voltage terminal T2.

[0161] The first input terminal of the operational amplifier AMP is connected to the node ND3. That is, the voltage VOUT of the input-output terminal T4 is applied to the first input terminal of the operational amplifier AMP. The second input terminal of the operational amplifier AMP is connected to the node ND21. That is, the voltage V21 of the node ND21 is applied to the second input-output terminal of the operational amplifier AMP. The operational amplifier AMP outputs a voltage Va from an output terminal based on the voltage VOUT and the voltage V21. The output terminal of the operational amplifier AMP is connected to the node ND4.

[0162] The gate of the PMOS transistor P3 is connected to the node ND4. That is, the voltage Va is applied to the gate of the PMOS transistor P3. One end of the PMOS transistor P3 is connected to the node ND22. The other end of the PMOS transistor P3 is connected to the node ND21.

[0163] The gate of the NMOS transistor N6 is connected to the node ND22. One end of the NMOS transistor N6 is connected to the node ND22. The other end of the NMOS transistor N6 is connected to the ground voltage terminal T3.

[0164] The gate of the NMOS transistor N7 is connected to the node ND22. One end of the NMOS transistor N7 is connected to the node ND6. The other end of the NMOS transistor N7 is connected to the ground voltage terminal T3.

[0165] The switch SW1 is an element that switches between connection and disconnection between the node ND22 and the variable current source 41. One end of the switch SW1 is connected to the node ND22, and the other end of the switch SW1 is connected to the node ND23.

[0166] The switch SW2 is an element that switches between connection and disconnection between the node ND6 and the variable current source 42. One end of the switch SW2 is connected to the node ND6, and the other end of the switch SW2 is connected to the node ND24.

[0167] The variable current source 41 supplies the current In1 from the node ND22 to the ground voltage terminal T3. One end of the variable current source 41 is connected to the node ND23. The other end of the variable current source 41 is connected to the ground voltage terminal T3.

[0168] The variable current source 42 supplies the current Ip1 from the node ND6 to the ground voltage terminal T3. One end of the variable current source 42 is connected to the node ND24. The other end of the variable current source 42 is connected to the ground voltage terminal T3.

[0169] The operational amplifier AMP outputs a voltage Va that makes the voltage VOUT equal to the voltage V21 through the operational amplifier AMP and the PMOS transistor P3. That is, the voltage V21 is controlled to be equal to the voltage VOUT. Therefore, when the load LD is driven by the NMOS transistor N1 and the load current Idrv flows through the load LD, the replica current Imr1=Idrv×(w1 / W1) flows from the second power supply voltage terminal T2 to the ground voltage terminal T3 via the NMOS transistor N5, the PMOS transistor P3, and the NMOS transistor N6. Since the NMOS transistor N6 and the NMOS transistor N7 form a current mirror, a current of the same magnitude as the current Imr1 also flows from the first power supply voltage terminal T1 to the ground voltage terminal T3 via the PMOS transistor P1 and the NMOS transistor N7. Hereinafter, this current is recorded as "replica current Imr1'". Furthermore, since the PMOS transistor P1 and the PMOS transistor P2 form a current mirror, the monitor current Icm having the same magnitude as the current Imr1 also flows from the first power supply voltage terminal T1 to the node ND7 via the PMOS transistor P2 .

[0170] 2.3 Action

[0171] The load driving operation, current monitoring operation, and current regulating operation of the semiconductor device 1A are the same as those of the first embodiment. Hereinafter, the first regulating operation and the second regulating operation will be described.

[0172] (1st adjustment action)

[0173] Fig.14 This is a circuit diagram showing the connection relationship during the first adjustment operation of the semiconductor device 1A. Hereinafter, the current flowing through the node ND21 is recorded as "current Ind21". The current flowing through the node ND22 is recorded as "current Ind22". The current flowing through the node ND6 is recorded as "current Ind6".

[0174] As shown in the first embodiment Figure 6 As in the example, use Fig.14 A case where the error (deviation from 0 to the positive side) of the monitoring current Icm is 6×dI will be described.

[0175] like Fig.14 As shown, when the current In1 = 0, the current In1 does not flow through the node ND23. The current Ind21 = Imr1 = 6 × dI flows through the node ND21. The current Ind22 = Ind21 - In1 = 6 × dI flows through the node ND22. As a result, the current Imr1 '= Ind22 = 6 × dI flows through the node ND6, and the monitoring current Icm = Ind6 = 6 × dI flows through the node ND10.

[0176] When current In1 = dI, current In1 = dI flows through node ND23. Current Ind21 = 6 × dI flows through node ND21. Current Ind22 = 5 × dI flows through node ND22. Thus, current Imr1 ′ = 5 × dI flows through node ND6, and monitoring current Icm = 5 × dI flows through node ND10.

[0177] When current In1 = 2×dI, current In1 = 2×dI flows through node ND23. Current Ind21 = 6×dI flows through node ND21. Current Ind22 = 4×dI flows through node ND22. Thus, current Imr1 ′ = 4×dI flows through node ND6, and monitoring current Icm = 4×dI flows through node ND10.

[0178] When current In1 = 3×dI, current In1 = 3×dI flows through node ND23. Current Ind21 = 6×dI flows through node ND21. Current Ind22 = 3×dI flows through node ND22. Thus, current Imr1 ′ = 3×dI flows through node ND6, and monitoring current Icm = 3×dI flows through node ND10.

[0179] When current In1 = 4×dI, current In1 = 4×dI flows through node ND23. Current Ind21 = 6×dI flows through node ND21. Current Ind22 = 2×dI flows through node ND22. Thus, current Imr1 ′ = 2×dI flows through node ND6, and monitoring current Icm = 2×dI flows through node ND10.

[0180] When current In1 = 5×dI, current In1 = 5×dI flows through node ND23. Current Ind21 = 6×dI flows through node ND21. Current Ind22 = dI flows through node ND22. Thus, current Imr1 ′ = dI flows through node ND6, and monitoring current Icm = dI flows through node ND10.

[0181] When current In1 = 6 × dI, current In1 = 6 × dI flows through node ND23. Current Ind21 = 6 × dI flows through node ND21. Current Ind22 does not flow through node ND22 (Ind22 = 0). As a result, current Imr1 ′ does not flow through node ND6 (Imr1 ′ = 0), and monitoring current Icm does not flow through node ND10 (Icm = 0).

[0182] Based on the above, the trimming control circuit 61 selects 6×dI as the value of the current In1. By performing the first adjustment operation in this way, the monitoring current Icm is adjusted to be close to zero.

[0183] (Second adjustment action)

[0184] Fig.15 1 is a circuit diagram showing the connection relationship of the semiconductor device 1A during the second adjustment operation.

[0185] like Fig.15 As shown in FIG. 1 , a replica current Imr1′ having the same magnitude as the replica current Imr1 flows through the node ND6. Therefore, similarly to the first embodiment, by adjusting the value of the current Ip1 of the variable current source 42 connected to the node ND6, the monitoring current Icm is adjusted to be close to 0. Therefore, as shown in the first embodiment, Figure 8 As in the example of , when the error (shift from 0 to the negative side) of the monitoring current Icm is 6×dI, the monitoring current Icm is adjusted to be close to 0 by performing the second adjustment operation as in the first embodiment.

[0186] 2.4 Effects of this Implementation

[0187] According to this embodiment, the same effects as those of the first embodiment are achieved.

[0188] 3. Third Implementation Method

[0189] A semiconductor device according to a third embodiment will be described. A semiconductor device 1B according to the third embodiment differs from the first embodiment in that it includes a current detection circuit and eliminates the ground voltage terminal T3 and the current monitoring terminal T5. In the following description, differences from the first embodiment will be described.

[0190] 3.1 Circuit Configuration of Semiconductor Devices

[0191] use Fig.16 A circuit configuration of a semiconductor device 1B according to the present embodiment will be described. Fig.16 It is a circuit diagram showing an example of the configuration of the semiconductor device 1B.

[0192] like Fig.16 As shown, the semiconductor device 1B includes a first power supply voltage terminal T1, a second power supply voltage terminal T2, an input / output terminal T4, a control circuit 2, a drive circuit 3, a current monitoring circuit 4, and a current detection circuit 7. The configuration other than the current detection circuit 7 is the same as that shown in the first embodiment. Figure 1 The composition is the same. Fig.16 2 shows a state in which the switches SW1 and SW3 are turned on and the switches SW2 and SW4 are turned off during the current monitoring operation.

[0193] The current detection circuit 7 is a circuit for detecting the monitoring current Icm. The current detection circuit 7 is connected to the node ND12. One end of the resistance element RL is connected to the node ND12.

[0194] The load driving operation, current monitoring operation, and current regulating operation of the semiconductor device 1B are the same as those of the first embodiment. The current detection circuit 7 can detect the monitoring current Icm by detecting the voltage of the node ND12.

[0195] 3.2 Effects of this Implementation

[0196] According to this embodiment, the same effects as those of the first embodiment are achieved. Of course, this embodiment can also be applied to the semiconductor device 1A according to the second embodiment.

[0197] 3.3 Variations

[0198] A semiconductor device according to a modification of the third embodiment will be described. A semiconductor device 1C according to the modification of the third embodiment is different from the third embodiment in that the current detection circuit 7 is replaced by an A / D converter 8. In the following description, differences from the third embodiment will be described.

[0199] 3.3.1 Circuit Configuration of Semiconductor Devices

[0200] use Fig.17 A circuit configuration of a semiconductor device 1C according to this modification example will be described. Fig.17 It is a circuit diagram showing an example of the configuration of the semiconductor device 1C.

[0201] like Fig.17 As shown, the semiconductor device 1C includes a first power supply voltage terminal T1, a second power supply voltage terminal T2, an input / output terminal T4, a control circuit 2, a drive circuit 3, a current monitoring circuit 4, and an A / D converter 8. The configuration other than the A / D converter 8 is the same as that shown in the third embodiment. Fig.16 The composition is the same. Fig.17 2 shows a state in which the switches SW1 and SW3 are turned on and the switches SW2 and SW4 are turned off during the current monitoring operation.

[0202] The A / D converter 8 is a circuit that converts the voltage V12 (analog value) of the node ND12 into a digital value (hereinafter referred to as "voltage V12'"). The A / D converter 8 is connected to the node ND12. One end of the resistor RL is connected to the node ND12.

[0203] The load driving operation, current monitoring operation, and current regulating operation of the semiconductor device 1C are the same as those of the first embodiment. Since the voltage V12 is converted into the voltage V12' by the A / D converter 8, the monitoring current Icm can be detected by detecting the converted voltage V12'.

[0204] 3.3.2 Effects of this modification

[0205] According to this modification, the same effects as those of the first embodiment are achieved. Of course, this modification can also be applied to the semiconductor device 1A according to the second embodiment.

[0206] 4. Modifications, etc.

[0207] As described above, the semiconductor device (1) according to the embodiment includes: a first circuit (3) for driving a load (LD) by supplying a load current (Idrv) to the load (LD) connectable to the first terminal (T4); and a third circuit (4) including a second circuit (5) for replicating the load current (Idrv) based on a first voltage (VOUT) of the first terminal (T4) and outputting the replicated first current (Imr1), and monitoring a second current (Icm) based on the first current. The third circuit (4) further includes a fourth circuit (6) for adjusting the second current (Icm) when the load current (Idrv) is not supplied to the load (LD).

[0208] In addition, the embodiment is not limited to the above-described embodiment, and various modifications are possible.

[0209] In addition, the flowcharts described in the above embodiments can replace the order of the processes as much as possible.

[0210] Several embodiments of the present invention have been described, but these embodiments are provided as examples and are not intended to limit the scope of the invention. These embodiments can be implemented in various other ways, and various omissions, substitutions, and changes can be made without departing from the scope of the purpose of the invention. These embodiments and / or their variations are included in the scope and purpose of the invention, and are also included in the invention described in the claims and their equivalents.

Claims

1. A semiconductor device comprising: a first circuit for driving a load connectable to the first terminal by supplying a load current to the load; and The third circuit includes a second circuit that copies the load current based on the first voltage of the first terminal and outputs the copied first current, and monitors a second current based on the first current. The third circuit further includes a fourth circuit that adjusts the second current when the load current is not supplied to the load.

2. The semiconductor device according to claim 1, The fourth circuit compares a second voltage obtained by converting the second current into a voltage with a reference voltage, and adjusts the second current to be close to zero based on a result of the comparison.

3. The semiconductor device according to claim 1, The fourth circuit adjusts the second current when the semiconductor device is powered on.

4. The semiconductor device according to claim 1, The fourth circuit adjusts the second current when the semiconductor device receives a signal requesting adjustment of the second current from the outside.

5. The semiconductor device according to claim 1, The fourth circuit monitors the second current in a state where the second current is adjusted.

6. The semiconductor device according to claim 1, The second circuit comprises: A first transistor, a gate to which a control signal is input, one end of which is connected to the first node, and the other end of which is connected to the second terminal; an operational amplifier having the first voltage applied to a first input terminal, having a third voltage at the first node applied to a second input terminal, and outputting a fourth voltage from an output terminal based on the first voltage and the third voltage; as well as a second transistor having the fourth voltage applied to the gate, one end of which is connected to the second node and the other end of which is connected to the first node; The third circuit further includes: a third transistor, a gate of which is connected to the second node, one end of which is connected to the third terminal, and the other end of which is connected to the second node; a fourth transistor, a gate of which is connected to the second node, one end of which is connected to the third terminal, and the other end of which is connected to the third node; a first switch, one end of which is connected to the third terminal, and the other end of which is connected to the fourth node; a second switch, one end of which is connected to the second node, and the other end of which is connected to the fifth node; a first variable current source having one end connected to the fourth node and the other end connected to the second node, and a second variable current source, one end of which is connected to the fifth node and the other end of which is connected to the second terminal; The fourth circuit comprises: a third switch, one end of which is connected to the third node, and the other end of which is connected to the sixth node; a fourth switch, one end of which is connected to the third node, and the other end of which is connected to the seventh node; a resistor element, one end of which is connected to the seventh node and the other end of which is connected to the second terminal; a comparator, which compares the fifth voltage of the seventh node with a reference voltage and outputs a comparison result; and The control circuit adjusts the second current to be close to zero based on the result.

7. The semiconductor device according to claim 6, When the fifth voltage is equal to or higher than the reference voltage, The control circuit turns the first switch on and turns the second switch off to increase the current of the first variable current source. When the fifth voltage is lower than the reference voltage, The control circuit turns the first switch into an OFF state and turns the second switch into an ON state, thereby increasing the current of the second variable current source.

8. The semiconductor device according to claim 6, When the fifth voltage is equal to or higher than the reference voltage, The control circuit Repeatedly executing the first cycle process, the first cycle process comprising: The first switch is turned on, the second switch is turned off, and the current of the first variable current source is increased by a first trimming amount; and determining whether a transition has occurred in the logic level of the result, adjusting the current value of the first variable current source to a first current value in the previous first cycle of processing when the logic level of the result has changed, When the fifth voltage is lower than the reference voltage, The control circuit Repeating a second loop process, the second loop process comprising: turning the first switch off, turning the second switch on, and increasing the current of the second variable current source by a second trimming amount; and determining whether a transition has occurred in the logic level of the result, The value of the current of the second variable current source is adjusted to a second current value in the second cycle processing before the transition of the logic level of the result.

9. The semiconductor device according to claim 1, The fourth circuit includes a register storing a result of adjustment performed by the fourth circuit.

10. The semiconductor device according to claim 1, The second circuit comprises: A fifth transistor, a gate to which a control signal is input, one end of which is connected to the eighth node, and the other end of which is connected to the fourth terminal; an operational amplifier having the first voltage applied to a first input terminal, having the sixth voltage at the eighth node applied to a second input terminal, and outputting a seventh voltage from an output terminal based on the first voltage and the sixth voltage; as well as a sixth transistor having the seventh voltage applied to the gate, one end of which is connected to the ninth node and the other end of which is connected to the eighth node; The third circuit further includes: a seventh transistor, a gate connected to the ninth node, one end connected to the ninth node, and the other end connected to the fifth terminal; an eighth transistor, a gate of which is connected to the ninth node, one end of which is connected to the tenth node, and the other end of which is connected to the fifth terminal; a ninth transistor, having a gate connected to the tenth node, one end connected to the sixth terminal, and the other end connected to the tenth node; a tenth transistor, having a gate connected to the tenth node, one end connected to the sixth terminal, and the other end connected to the eleventh node; a fifth switch, one end of which is connected to the ninth node, and the other end of which is connected to the twelfth node; a sixth switch, one end of which is connected to the tenth node, and the other end of which is connected to the thirteenth node; a third variable current source, one end of which is connected to the twelfth node and the other end of which is connected to the fifth terminal; and a fourth variable current source, one end of which is connected to the 13th node and the other end of which is connected to the fifth terminal; The fourth circuit comprises: a seventh switch, one end of which is connected to the eleventh node, and the other end of which is connected to the fourteenth node; an eighth switch, one end of which is connected to the eleventh node, and the other end of which is connected to the fifteenth node; a resistor element, one end of which is connected to the 15th node and the other end of which is connected to the 5th terminal; a comparator, comparing the eighth voltage of the fifteenth node with a reference voltage, and outputting a comparison result; and The control circuit adjusts the second current to be close to zero based on the result.

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