NOR type memory and reading method thereof

Abstract

The invention relates to a NOR type memory and a reading method thereof. The reading method comprises the following steps: continuously receiving at least two random access addresses in a random reading mode; and continuously outputting data read in response to the received access address. By adopting the reading method, the speed of reading the data of the plurality of random addresses in the NOR type memory can be increased.

Description

Technical Field

[0001] The present disclosure relates to the field of storage, and in particular to a NOR type memory and a reading method thereof. Background Art

[0002] Currently, flash memory is widely used in various electronic devices, among which NOR flash memory is used in more and more devices.

[0003] Therefore, it is hoped that the data transmission speed of the NOR flash memory can be improved. Summary of the invention

[0004] A technical problem to be solved by the present disclosure is to provide a NOR type memory and a reading method thereof, which can improve the data transmission speed.

[0005] According to a first aspect of the present disclosure, a method for reading a NOR type memory is provided, comprising:

[0006] At least two random access addresses are continuously received in a random read mode; and data read in response to the received access addresses are continuously output.

[0007] Optionally, the random read mode is initiated by receiving a predetermined instruction value.

[0008] Optionally, the transmission format of the random read mode is expressed as: cmd+address_1+…+address_n+dummy clk+address_1_data+…+address_n_data, wherein cmd represents a predetermined instruction value, address_1+…+address_n represents n consecutively received random access addresses, wherein n is an integer greater than 1, dummy clk represents a predetermined number of dummy clock cycles, wherein the predetermined number is a number greater than or equal to 0, and address_1_data+…+address_n_data represents data read in response to the n random access addresses respectively, which is output continuously in the order in which the access addresses are received.

[0009] Optionally, the random read mode is enabled by presetting a designated register in the NOR memory.

[0010] Optionally, the transmission format of the random read mode is expressed as: address_1+…+address_n+dummy clk+address_1_data+…+address_n_data, wherein address_1+…+address_n represents n consecutively received random access addresses, wherein n is an integer greater than 1, dummy clk represents a predetermined number of dummy clock cycles, wherein the predetermined number is a number greater than or equal to 0, and address_1_data+…+address_n_data represents data read in response to the n random access addresses respectively, which are output continuously in the order in which the access addresses are received.

[0011] Optionally, the random read mode is a continuous read mode, the continuous read mode includes at least two continuous read transfers, and each read transfer includes continuously receiving at least two random access addresses; and continuously outputting data read in response to the received access addresses.

[0012] Optionally, the transmission format of the first read transmission of the two consecutive read transmissions is expressed as: cmd+address_1+…+address_n+dummy clk+address_1_data+…+address_n_data; and the transmission format of the second read transmission of the two consecutive read transmissions is expressed as: address_1+…+address_n+dummy clk+address_1_data+…+address_n_data; wherein, address_1+…+address_n represents n random access addresses received continuously, wherein n is an integer greater than 1; dummy clk represents a predetermined number of dummy clock cycles, wherein the predetermined number is a number greater than or equal to 0; address_1_data+…+address_n_data represents data read in response to the n random access addresses respectively, which are output continuously in the order in which the access addresses are received.

[0013] Optionally, the number of n or the number of dummy clock cycles is pre-agreed, or is determined by the predetermined instruction value or the preset value of a designated register in the NOR memory.

[0014] Optionally, the read operation performed in response to at least one of the received access addresses is a burst read operation, and the burst length or default burst length for reading each access address is pre-agreed or determined by a pre-set value of a designated register in the NOR-type memory.

[0015] Optionally, at least two of the received access addresses correspond to at least two different bare chips, respectively, wherein at least one bit of information in each access address is used to indicate the bare chip corresponding to the access address.

[0016] Optionally, the NOR memory has an access interface using an SPI protocol.

[0017] Optionally, the NOR memory has a single-port, dual-port, quad-port or octal-port access interface.

[0018] Optionally, the NOR memory uses SDR timing to receive an access address and output read data.

[0019] Optionally, the time length for reading data of the access address address_1 is shorter than the time length for transmitting the address_2+...+address_n instruction, the time length of the dummy clk is 0 or the transmission format of the random read mode does not include the dummy clk.

[0020] According to a second aspect of the present disclosure, a NOR-type memory is provided, comprising: one or more NOR-type memory arrays fabricated on one or more bare chips; an access interface for transmitting information to the outside; and a control module configured to control a read operation on the NOR-type memory array according to information received from the access interface, thereby implementing the method described in the first aspect of the present disclosure.

[0021] Therefore, the present disclosure proposes a novel read mode of a NOR type memory, which can reduce the time required to obtain read data of multiple random addresses and improve the data transmission speed. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] The above and other objects, features and advantages of the present disclosure will become more apparent through a more detailed description of exemplary embodiments of the present disclosure in conjunction with the accompanying drawings, wherein like reference numerals generally represent like components in the exemplary embodiments of the present disclosure.

[0023] Figure 1 An exemplary composition diagram of a NOR memory according to an embodiment of the present disclosure is shown.

[0024] Figure 2 An exemplary timing diagram of a random read mode according to an embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0025] The exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although the exemplary embodiments of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the embodiments set forth herein. On the contrary, these embodiments are provided to make the present disclosure more thorough and complete, and to fully convey the scope of the present disclosure to those skilled in the art.

[0026] The continuous transmission speed of the current NOR type memory is very fast, that is, the speed of continuously reading data from an address is very fast. However, the present disclosure finds that for the situation where multiple random addresses need to be read, the current random read speed is limited by the transmission process of the read instruction. For example, the transmission format of the existing conventional read instruction is: cmd+address+dummy clk+data, wherein "cmd" represents the instruction sent by the host to the memory (for example, it can be a read instruction value), "address" represents the access address sent by the host to the memory, "dummy clk" represents a number of dummy clock cycles (i.e., idle waiting time), and "data" represents the data read out in response to the received access address sent by the memory to the host. In other words, the entire transmission process of the existing read instruction is: the host continuously sends the read instruction value (cmd) and the access address (address) to the memory, and then after a certain idle waiting time (dummy clk), the memory sends the data (data) read out from the received access address to the host. Therefore, when the host uses the existing read command to continuously read data from multiple random addresses, it needs to send multiple read commands, where each read command must include the read command value sent at the beginning and the idle waiting time between the address and the read data. For example, when the host wants to burst read N bytes starting from address A and then burst read M bytes starting from address B, it needs to go through the complete transmission process of the above read command twice. In this article, the so-called "random" address or access address means an address that can be arbitrarily specified by the user (it can be a continuous address in some scenarios).

[0027] In addition, the related art also proposes another read instruction for the case of performing read operations of multiple random addresses continuously. The continuous read instruction can start a series (multiple) read instructions of the same type through an instruction value, that is, only one instruction value is transmitted during the first read operation, eliminating the transmission of the instruction value at the beginning of the subsequent read instruction. In other words, the transmission format of the subsequent read instruction can be changed to: address+dummy clk+data. However, similar to the conventional read instruction mentioned above, the subsequent read operation must wait for the entire transmission process of the previous read operation to be completed before it can start, that is, it is necessary to wait until all the read data of the previous time is output before starting to transmit the access address corresponding to the next read and perform the corresponding read processing.

[0028] It should be noted that in all embodiments of the present application, "+" does not have any specific meaning, but is only used to indicate the format of the instruction; for example, in address+dummy clk+data, address can be a string (i.e. one or more) of continuous characters used to indicate the address; dummy clk can be a placeholder for a certain time interval or preset length (i.e. any character without a specific meaning, also known as a useless character) or left blank in any other way; data can be a string (i.e. one or more) of continuous characters (typically binary characters) used to indicate data. Exemplarily, address+dummy clk+data can be 111100001010, where the first four characters 1111 represent the address, the middle four characters 0000 represent dummy clk, and the last four characters 1010 represent data; in actual use, there is no need to actually use "+" in the transmission format. This will not be repeated below.

[0029] The present disclosure believes that the aforementioned existing setting of the read instruction affects the reading speed of multiple random addresses.

[0030] Therefore, the present disclosure proposes a new reading mode for NOR type memory, which can reduce unnecessary information transmission and idle waiting time when performing read operations on multiple random addresses continuously, thereby improving the transmission speed of read data.

[0031] In some embodiments, the present disclosure proposes a new random read mode. After starting the random read mode, at least two random access addresses can be continuously received, and then the data read in response to the received access addresses can be continuously output. Thus, in some cases, the time for subsequent repeated sending of the corresponding read instruction value can be saved. In addition, in some cases, the memory can receive the subsequent access address during the read delay (the time from receiving the first access address to starting to output the data read from the address) required for the first read operation (i.e., the read operation performed for the first received access address), so compared with the related art, the data transmission time of multiple random read operations can be further saved. In addition, in some cases, since the subsequent access address is pre-stored, the subsequent read operation does not need to wait until the previous read operation is completely completed before starting, but a part of the consecutive read operations can be processed in parallel, similar to a pipeline operation, for example, the corresponding word line (WordLine, WL) and bit line (BitLine, BL) can be opened according to the subsequent access address during the transmission of the data read from the previous access address; therefore, the idle waiting time of multiple random read operations can be reduced, and the data transmission speed can be further improved.

[0032] As will be described in detail later, in some embodiments, the random read mode of the present disclosure may be initiated by receiving a predetermined instruction value; the transmission format of the random read mode is expressed as:

[0033] cmd+address_1+……+address_n+dummy clk+address_1_data+……+address_n_data,

[0034] Among them, cmd represents a predetermined instruction value; address_1+…+address_n represents n random access addresses received continuously, where n is an integer greater than 1; dummy clk represents a predetermined number of dummy clock cycles, where the predetermined number is a number greater than or equal to 0; address_1_data+…+address_n_data represents the data read in response to the n random access addresses respectively, which are continuously output in the order of receiving the access addresses.

[0035] Wherein, in some cases, after receiving a read transmission indicating a random read mode, the transmission in the random read mode can be performed continuously, and the predetermined instruction value cmd is omitted in the subsequent transmission format. That is, two or more consecutive read transmissions are performed continuously; wherein the transmission format of the first read transmission in the two consecutive read transmissions is expressed as: cmd+address_1+…+address_n+dummy clk+address_1_data+…+address_n_data; and the transmission format of the second read transmission in the two consecutive read transmissions is expressed as: address_1+…+address_n+dummy clk+address_1_data+…+address_n_data. In this way, after the read transmission is started by the cmd command during the first read transmission, multiple read transmissions can be performed continuously, and the cmd command in the transmission format of the subsequent read transmissions is omitted.

[0036] Alternatively, in some embodiments, the random read mode may be started by presetting a specified register in a NOR memory (this eliminates the need to transmit the initial read instruction value). That is, the transmission format of the random read mode is expressed as:

[0037] address_1+……+address_n+dummy clk+address_1_data+……+address_n_data,

[0038] Among them, address_1+…+address_n represents n random access addresses received continuously, where n is an integer greater than 1; dummy clk represents a predetermined number of dummy clock cycles, where the predetermined number is a number greater than or equal to 0; address_1_data+…+address_n_data represents the data read in response to the n random access addresses respectively, which are continuously output in the order of receiving the access addresses.

[0039] In some embodiments, the number of access addresses continuously received in the random read mode of the present disclosure may be pre-agreed, or determined by a command value (cmd) transmitted at the beginning or a value of a predetermined register in a NOR memory.

[0040] In some embodiments, the data read from each access address may be output continuously according to the order in which the access addresses are received, that is, the order of the continuously output read data is consistent with the order of the previously continuously received access addresses.

[0041] In some embodiments, the received access address may be a logical address or a physical address. The access address may include a row address and a column address. In some embodiments, when multiple dies share an access interface as described below, each access address may also include at least one bit to indicate which die it belongs to. For example, at least one bit may be added to the highest bit of the access address within each chip to indicate the die information, so that when the access address is decoded, the corresponding chip select information is generated according to the added highest bit information to select the die to which it belongs.

[0042] In some embodiments, in the random read mode of the present disclosure, the read data can be continuously output after waiting for a period of idle time after continuously receiving all access addresses, or the read data can be seamlessly switched to outputting the read data after receiving all access addresses without waiting for any clock cycle. For example, the time length for reading the data of the address_1 access address is less than the time length for transmitting the address_2+...+address_n instruction, and the time length of the dummy clk is 0 or the dummy clk is not included in the transmission format of the random read mode. That is, if the time used to transmit multiple subsequent transmission addresses can meet the time required for reading the data corresponding to the first address, no dummy clk is required; conversely, if the time used to transmit multiple subsequent transmission addresses cannot meet the time required for reading the data corresponding to the first address, a dummy clk is required to ensure that there is enough time to read the data corresponding to the first address. For the mth random access address, "subsequent multiple transmission addresses" refer to the m+1th random access address to the last (nth) random access address in the transmission format; for example, for the first random access address, "subsequent multiple transmission addresses" refer to the second random access address to the last random access address in the transmission format.

[0043] In some implementations, the length of the idle time can be preconfigured (a length of 0 is considered as no idle time), or the length of the idle time can be determined by an instruction value transmitted at the beginning or a value of a specified register in a pre-set NOR memory.

[0044] In some embodiments, the read operation is usually performed in a burst mode. For example, after starting a read operation for an access address, a preset burst length of bytes must be read continuously, that is, burst length bytes are automatically and continuously read starting from the access address. The read operation performed in response to at least one of the received access addresses can be a burst read operation. The burst length or the default burst length for reading each access address can be pre-configured or determined by the value of a specified register in a pre-set NOR memory.

[0045] In some cases, the various designated registers in the aforementioned NOR memory may be the same set of registers, in which different bit values ​​may determine different parameter quantities (such as the startup mode, the number of consecutively received access addresses, the length of idle time, the burst length, etc.); or may belong to multiple different registers. The host may write each setting value in advance in the corresponding register at one time or in batches multiple times before starting the random read mode as needed.

[0046] The technical solution of the present disclosure will be described in detail below by taking a NOR type memory with an SPI interface as an example. However, those skilled in the art will appreciate that the present disclosure is not limited thereto but can also be applied to a NOR type memory with other serial access interfaces or parallel access interfaces.

[0047] Figure 1 An exemplary composition diagram of a NOR memory according to an embodiment of the present disclosure is shown.

[0048] like Figure 1 As shown, the NOR memory 100 includes a storage array 110, an access interface 120 and a control module 130, wherein the access interface 120 is used to transmit information to the outside, and the control module 130 can be configured to control the read operation of the storage array 110 according to the information received from the access interface 120, so as to realize the new random read mode proposed in the present disclosure.

[0049] In some implementations, memory array 110 may include one or more NOR-type memory arrays.

[0050] In some embodiments, the storage array 110 and a portion or even the entirety of the control module 130 may be fabricated on a single die.

[0051] In some embodiments, although Figure 1 Although not shown, the NOR memory 100 may include more than one die, each of which is provided with a storage array 110; in some embodiments, each die may also include a portion or even all of a corresponding control module 130. Each storage array 110 may include one or more NOR storage arrays, and the more than one die may share one access interface 120.

[0052] In some embodiments, Figure 1 As shown, the access interface 120 can use the SPI (Serial Peripheral Interface) protocol to communicate with an external host. The access interface 120 may include at least a clock signal line CLK, a chip enable line CE#, and a group (M) of data / address multiplexing lines DQ for implementing the SPI protocol. <m-1:0>. When the host performs a read operation on the memory 100, the host can output a clock signal CLK to the memory to control the signal transmission timing (that is, the desired signal transmission can be performed at each rising edge and / or falling edge of CLK), pull down the CE# signal to select the memory, and use the DQ line to exchange instructions, addresses and / or data related to the read operation with the memory. The SPI protocol in the present disclosure may include various versions thereof, such as a single-port, dual-port, 4-port or 8-port SPI protocol. In this article, "single-port, dual-port, 4-port or 8-port" means that the bit width of the parallel transmission data is 1 bit, 2 bits, 4 bits or 8 bits, and accordingly, the single-port, dual-port, 4-port or 8-port SPI protocol means that the number M of the data / address multiplexing lines DQ is 1, 2, 4 or 8. The following will take an 8-port SPI (M=8, the DQ line transmits 1 byte in parallel each time, i.e. 8 bits) as an example to describe the embodiments of the present disclosure, but those skilled in the art can understand that the technical solution of the present disclosure does not limit the number of bits. In addition, in some embodiments, in addition to the data / address multiplexing line DQ, the access interface 120 may also include other transmission lines to separately transmit part of the data or address; for example, the access interface 120 may also include a separate address line to transmit the address in parallel with the data / address multiplexing line DQ.

[0053] In addition, those skilled in the art should understand that since the present disclosure does not limit the specific implementation of the memory internal control circuit for implementing the random read mode proposed in the present disclosure, Figure 1 Only a simplified block diagram is used to represent the control module 130 in the NOR memory 100. The control module 130 may include various circuit components and various arrangements involved in performing a desired read operation on the memory array 110, for example, a command decoder, a row / column decoder, a sense amplifier (SA), a page buffer, and / or various latches or registers (such as an address latch / register, a data latch / register, a configuration register, etc.) as required.

[0054] The following will be combined Figure 2 The timing diagram shown is similar to Figure 1 The structural block diagram of the random read mode of the present disclosure is used to describe in detail an example. Those skilled in the art will understand that many of the following details are only exemplified for the sake of completeness of the solution and are not intended to limit the technical solution of the present disclosure. For example, although Figure 2 The timing diagram shown is using Figure 1 However, it can also be adaptively modified to be suitable for NOR type memories adopting other kinds of serial or parallel access interfaces.

[0055] Figure 2 An exemplary timing diagram of a random read mode according to an embodiment of the present disclosure is shown.

[0056] like Figure 2 As shown, the host sends a clock signal CLK to the memory, pulls the chip enable signal CE# low, and sends a predetermined instruction value at the beginning, thereby starting a random read mode specified by the instruction value.

[0057] In this example, the data transmission on the DQ line adopts the SDR (Single Data Rate) timing, that is, data is transmitted only once in one clock cycle. Data with a bit width can be transmitted once at the rising edge or falling edge of the clock signal CLK. For example, when the SPI interface with a bit width of 8 bits (M=8) is used to transmit data, one byte of data is transmitted in one clock cycle. Those skilled in the art should understand that Figure 2 The number of clock cycles taken to transmit each instruction, address and read data on the DQ line shown is only exemplary, and the present disclosure is not limited thereto, but the number of clock cycles taken for each transmission should be set according to the interface bit width and the length of each instruction, address and read data in actual application. Those skilled in the art will understand that the present disclosure is not limited to SDR timing, and DDR (Double Data Rate) timing may also be used, that is, data can be transmitted at both the rising and falling edges of CLK, and data is transmitted twice in one clock cycle.

[0058] After sending the command value, such as Figure 2 As shown, the host continuously sends n random access addresses A1-An on the DQ line, where n>1. As mentioned above, n can be pre-agreed, or determined by the instruction value transmitted at the beginning, or by the value of a specified register in a pre-set NOR memory. Figure 2 In the embodiment, the instructions and the addresses are transmitted seamlessly, but those skilled in the art should understand that the present disclosure is not limited thereto. For example, in some other embodiments, an idle waiting time (dummy clock cycle (dummy clk)) may be inserted between the instruction and the first address A1 and / or between the addresses as needed. Figure 2 What is shown is a timing diagram with a dummy clock cycle (dummy clk); of course, those skilled in the art will understand that Figure 2 There may be no dummy clock cycle (dummy clk).

[0059] Then, if Figure 2 As shown, after a predetermined number (which can be 0) of dummy clock cycles (dummy clk), the host starts to receive data from A1 (i.e., data burst read from A1); at this time, the burst length is set to 2 bytes, so two clock cycles are used to continuously transmit 2 bytes of read data. As mentioned above, the number of dummy clock cycles and / or the burst length for reading each access address (or the default burst length for all addresses) can be pre-agreed, or determined by the instruction value transmitted at the beginning or the value of a specified register in a pre-set NOR type memory. For example, in some cases, there must be a read delay (i.e., the time that a read operation must take) between the memory receiving the first address A1 and outputting the corresponding read data, which is mainly affected by the time-consuming operation of SA; therefore, the number of dummy clock cycles can be calculated based on the read delay and the time required to transmit n access addresses. If n is large enough, the first read operation is also completed after the access address transmission is completed, and the data from A1 can be seamlessly output, that is, the number of dummy clock cycles can be set to 0. That is, the transmission format of the read instruction can be expressed as: cmd+address_1+…+address_n+address_1_data+…+address_n_data, excluding dummy clk; or, the transmission format of the read instruction can be expressed as: address_1+…+address_n+address_1_data+…+address_n_data, excluding dummy clk. If the first read operation is not completed after the transmission of n access addresses is completed, the number of dummy clock cycles is set as needed. In this example using the SPI serial port, since the transmission directions of the address and the read data on the DQ line are different, the transmission direction must be switched between the last address An and the first data read out; in some cases, this IO switch only takes half a cycle, and because Figure 2 The example uses SDR timing, that is, data is transmitted only once in one clock cycle, so there is a clock cycle between every two transmissions. This interval is sufficient for IO switching, and there is no need to provide additional dummy clock cycles.

[0060] Then, if Figure 2 As shown, the host seamlessly and continuously receives data from subsequent access addresses until it has received all the data read in response to all previously sent access addresses. The host then pulls CE# high to end this random read mode. Figure 2 In the example, since the memory pre-stores all access addresses, the read operations corresponding to the access addresses can be pipelined, thereby shortening the interval time between the read operations and outputting the read data seamlessly. However, the present disclosure is not limited thereto, and in some other embodiments, a suitable dummy clock cycle can be set between the read data as needed. Figure 2 The entire transmission process on the DQ line shown can be pre-set or pre-agreed by the host, so the host can receive each read data on time and accurately according to the pre-setting / agreed.

[0061] In addition, in some other embodiments, if the host does not need the read data from the address received later, CE# can be pulled high in advance to end the random read mode in advance. For example, when CE# is pulled high, the read data that has not been output by the memory can be discarded, and all subsequent read processing can be stopped; or the read operation in progress when CE# is pulled high can be completed before ending. The processing method for the received address and its corresponding read data after CE# is pulled high can be agreed or set in advance. In this way, the host can flexibly implement any number of continuous random read operations as needed.

[0062] From the above, it can be concluded that Figure 2 An exemplary transmission format of a read instruction in a random read mode represented by the timing diagram can be expressed as:

[0063] cmd+address_1+……+address_n+dummy clk+address_1_data+……+address_n_data,

[0064] Among them, cmd represents the predetermined command value,

[0065] address_1+…+address_n represents n random access addresses received consecutively, where n is an integer greater than 1.

[0066] dummy clk represents a predetermined number of dummy clock cycles, wherein the predetermined number is an integer greater than or equal to 0,

[0067] address_1_data+ . . . +address_n_data represents data read in response to the n random access addresses, respectively, and is output continuously in the order in which the access addresses are received.

[0068] In another possible implementation, the random read mode of the present disclosure may be started by receiving a predetermined command value cmd; and after starting to enter the random read mode by cmd, the predetermined command value cmd may be omitted in the subsequent transmission format. That is, the transmission format used for the first time is: cmd+address_1+…+address_n+dummyclk+address_1_data+…+address_n_data; and in subsequent transmissions, the transmission format used is: address_1+…+address_n+dummy clk+address_1_data+…+address_n_data.

[0069] In a possible implementation, the CE# signal will be changed after entering the random read mode; and before the CE# signal is changed (eg, pulled high), cmd is not required.

[0070] In addition, as mentioned above, in other implementations, the random read mode can also be started by presetting a specific register in the memory, thereby eliminating the need for Figure 2 The transmission of the read instruction value at the beginning further saves transmission time.

[0071] At this time, the transmission format of the random read mode can be transformed accordingly:

[0072] address_1+……+address_n+dummy clk+address_1_data+……+address_n_data,

[0073] Wherein, address_1+…+address_n represents n random access addresses received consecutively, where n is an integer greater than 1.

[0074] dummy clk represents a predetermined number of dummy clock cycles, wherein the predetermined number is an integer greater than or equal to 0,

[0075] address_1_data+ . . . +address_n_data represents data read in response to the n random access addresses, respectively, and is output continuously in the order in which the access addresses are received.

[0076] In the embodiment of the present disclosure, the random read mode can be started by presetting a specific register in the memory, and after starting to enter the random read mode, the same transmission format is also used. That is, the transmission format used for the first time is: address_1+...+address_n+dummy clk+address_1_data+...+address_n_data; and in subsequent transmissions, the transmission format used is: address_1+...+address_n+dummy clk+address_1_data+...+address_n_data.

[0077] This variant implementation can be implemented by using various details discussed above or any combination thereof, which will not be described in detail here.

[0078] In the description of the embodiments of the present application, unless otherwise specified, the meaning of "multiple" refers to a quantity of two or more. For example, multiple bare chips refer to two or more bare chips. In the embodiments of the present application, words such as "in one possible implementation", "in some embodiments", or "for example" are used to indicate examples, illustrations, or descriptions. Any embodiment or design scheme described as "in one possible implementation", "in some embodiments", or "for example" in the embodiments of the present application should not be interpreted as being more preferred or more advantageous than other embodiments or design schemes. Specifically, the use of words such as "in one possible implementation", "in some embodiments", or "for example" is intended to present related concepts in a concrete way.

[0079] The embodiments of the present disclosure have been described above, and the above description is exemplary, not exhaustive, and is not limited to the disclosed embodiments. Many modifications and changes will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The selection of terms used herein is intended to best explain the principles of the embodiments, practical applications, or improvements to the technology in the market, or to enable other persons of ordinary skill in the art to understand the embodiments disclosed herein.

Claims

1. A method for reading a NOR memory, comprising: receiving at least two random access addresses in succession in a random read mode; as well as The data read in response to the received access address is continuously output.

2. The method according to claim 1, wherein: The random read mode is initiated by receiving a predetermined command value.

3. The method according to claim 1 or 2, wherein: The transmission format of the random read mode is expressed as: cmd+address_1+……+address_n+dummy clk+address_1_data+……+address_n_data, Among them, cmd represents the predetermined command value, address_1+…+address_n represents n random access addresses received consecutively, where n is an integer greater than 1. dummy clk represents a predetermined number of dummy clock cycles, wherein the predetermined number is a number greater than or equal to 0, address_1_data+ . . . +address_n_data represents data read in response to the n random access addresses, respectively, and is output continuously in the order in which the access addresses are received.

4. The method according to claim 1, wherein: The random read mode is activated by presetting a designated register in the NOR type memory.

5. The method according to claim 4, wherein: The transmission format of the random read mode is expressed as: address_1+……+address_n+dummy clk+address_1_data+……+address_n_data, Wherein, address_1+…+address_n represents n random access addresses received consecutively, where n is an integer greater than 1. dummy clk represents a predetermined number of dummy clock cycles, wherein the predetermined number is a number greater than or equal to 0, address_1_data+ . . . +address_n_data represents data read in response to the n random access addresses, respectively, and is output continuously in the order in which the access addresses are received.

6. The method according to claim 2, wherein the random read mode is a continuous read mode, the continuous read mode includes at least two continuous read transfers, and each read transfer includes continuously receiving at least two random access addresses and continuously outputting data read in response to the received access addresses.

7. The method according to claim 6, wherein: The transmission format of the first read transmission of the two consecutive read transmissions is expressed as: cmd+address_1+……+address_n+dummy clk+address_1_data+……+address_n_data; And the transmission format of the second read transmission in the two consecutive read transmissions is expressed as: address_1+……+address_n+dummy clk+address_1_data+……+address_n_data, Wherein, address_1+…+address_n represents n random access addresses received consecutively, where n is an integer greater than 1. dummy clk represents a predetermined number of dummy clock cycles, wherein the predetermined number is a number greater than or equal to 0, address_1_data+ . . . +address_n_data represents data read in response to the n random access addresses, respectively, and is output continuously in the order in which the access addresses are received.

8. The method according to claim 3, 5 or 7, wherein: The number of n or the number of dummy clock cycles is pre-agreed, or is determined by the predetermined instruction value or the preset value of a designated register in the NOR memory.

9. The method according to any one of claims 1 to 8, wherein: the read operation performed in response to at least one of the received access addresses is a burst read operation, The burst length or default burst length for reading each access address is pre-agreed, or is determined by a preset value of a designated register in the NOR memory.

10. The method according to any one of claims 1 to 9, wherein: At least two of the received access addresses correspond to at least two different dies, respectively, wherein at least one bit of information in each access address is used to indicate the die corresponding to the access address.

11. The method according to any one of claims 1 to 10, wherein: The NOR memory has an access interface using the SPI protocol; and / or The NOR memory has a single-port, dual-port, quad-port or octal-port access interface; and / or The NOR type memory uses SDR timing to receive an access address and output read data.

12. The method according to claim 3, 5 or 7, wherein: The time length for reading data of the access address address_1 is shorter than the time length for transmitting the address_2+...+address_n instruction, the time length of the dummy clk is 0 or the transmission format of the random read mode does not include the dummy clk.

13. A NOR memory, comprising: One or more NOR-type memory arrays are fabricated on one or more dies; Access interface, used to transmit information to the outside; as well as A control module is configured to control a read operation on the NOR storage array according to information received from the access interface, thereby implementing the method according to any one of claims 1-10.

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