Addition compressor for additive operation and bit data processing method

Abstract

The invention discloses an addition compressor for addition operation and a bit data processing method, which are used for solving the technical problem of low resource efficiency of a lookup table caused by the existing addition compressor. The compressor comprises a first five-input lookup table and a second five-input lookup table which is spliced and connected with the first five-input lookup table; the first five input lookup table is used for calculating input first bit data, second bit data, third bit data, fourth bit data and fifth bit data, outputting operation low bit data, operation middle bit data and operation high bit data, and removing the operation high bit data; and the second five input lookup table is used for calculating the input operation low bit data, the operation middle bit data, the first bit data, the second bit data and the sixth bit data based on a preset operation truth table to generate a compressor target result.

Description

Technical Field

[0001] The present invention relates to the technical field of data processing, and in particular to an adder compressor for addition operation and a method for processing bit data. Background Art

[0002] In digital circuit systems, adder compressors are an indispensable computing unit. When using digital circuit systems for signal processing, various adder compressors are often used. The performance and power consumption of different adder compressors depend on the designed circuit structure.

[0003] The use of adder compressors has a long history in the design of arithmetic units in microcomputers. The basic idea is to avoid slow carry propagation by passing (saving) the carry to the next compressor stage, rather than propagating it within the same stage.

[0004] Existing additive compressors mainly include 3-2 compressors, 2-2 compressors, approximate 4:2 compressors, etc., but these compressors only focus on reducing latency and do not consider the resource consumption of the lookup table (LUT). The lack of overall planning of LUT resources leads to low resource efficiency of the lookup table. Summary of the invention

[0005] The present invention provides an adder compressor for addition operation and a method for processing bit data, which are used to solve the technical problem that the existing adder compressor leads to low resource efficiency of the lookup table.

[0006] A first aspect of the present invention provides an additive compressor for addition operation, the compressor comprising a first five-input lookup table and a second five-input lookup table spliced ​​and connected to the first five-input lookup table;

[0007] The first five-input lookup table is used to calculate the input first bit data, second bit data, third bit data, fourth bit data and fifth bit data, output calculation low-order bit data, calculation middle-order bit data and calculation high-order bit data, and remove the calculation high-order bit data;

[0008] The second fifth input lookup table is used to calculate the input low-order bit data, the middle-order bit data, the first bit data, the second bit data, and the sixth bit data based on a preset operation truth table to generate a compressor target result.

[0009] Optionally, the second fifth input lookup table is specifically used for:

[0010] Generate restored high-order bit data according to the calculated low-order bit data, the calculated middle-order bit data, the first bit data, and the second bit data using a preset calculation truth table;

[0011] Determine target high-order bit data based on the restored high-order bit data, the calculated middle-order bit data and the sixth bit data;

[0012] The target high-order bit data and the calculated low-order bit data are concatenated to output a compressor target result.

[0013] Optionally, the calculation process of the first five-input lookup table is specifically as follows:

[0014] a1+a2+a3+a4+a5=(s3,s2,s1);

[0015] Among them, a1 is the first bit data; a2 is the second bit data; a3 is the third bit data; a4 is the fourth bit data; a5 is the fifth bit data; s3 is the high-order bit data for calculation; s2 is the middle-order bit data for calculation; s1 is the low-order bit data for calculation.

[0016] Optionally, the target high-order bit data includes first target high-order bit data and second target high-order bit data; the calculation process of the target high-order bit data is specifically as follows:

[0017] (s5,s4)=(s3',s2)+b1;

[0018] Among them, s5 is the second target high-order bit data; s4 is the first target high-order bit data; s3' is the restored high-order bit data; s2 is the calculated middle bit data; b1 is the sixth bit data; (,) is concatenation; + is addition.

[0019] A second aspect of the present invention provides a method for processing bit data, which is applied to the above-mentioned additive compressor for addition operation, comprising:

[0020] Obtaining first bit data, second bit data, third bit data, fourth bit data, fifth bit data and sixth bit data;

[0021] Calculate the first bit data, the second bit data, the third bit data, the fourth bit data and the fifth bit data, output calculated low-order bit data, calculated middle-order bit data and calculated high-order bit data, and remove the calculated high-order bit data;

[0022] Based on a preset operation truth table, the input operation low-order bit data, the operation middle-order bit data, the first bit data, the second bit data, and the sixth bit data are calculated to generate a compressor target result.

[0023] Optionally, the step of calculating the input low-order bit data, the middle-order bit data, the first bit data, the second bit data, and the sixth bit data based on a preset operation truth table to generate a compressor target result includes:

[0024] Generate restored high-order bit data according to the calculated low-order bit data, the calculated middle-order bit data, the first bit data, and the second bit data using a preset calculation truth table;

[0025] Determine target high-order bit data based on the restored high-order bit data, the calculated middle-order bit data and the sixth bit data;

[0026] The target high-order bit data and the calculated low-order bit data are concatenated to output a compressor target result.

[0027] Optionally, the target high-order bit data includes first target high-order bit data and second target high-order bit data; the calculation process of the target high-order bit data is specifically as follows:

[0028] (s5,s4)=(s3',s2)+b1;

[0029] Among them, s5 is the second target high-order bit data; s4 is the first target high-order bit data; s3' is the restored high-order bit data; s2 is the calculated middle bit data; b1 is the sixth bit data; (,) is concatenation; + is addition.

[0030] A third aspect of the present invention provides a computer device, comprising a memory and a processor, wherein the memory stores a computer program, and when the computer program is executed by the processor, the processor executes the steps of the bit data processing method as described in any one of the above items.

[0031] A fourth aspect of the present invention provides a computer-readable storage medium having a computer program stored thereon, and when the computer program is executed, the steps of the bit data processing method as described in any one of the above items are implemented.

[0032] A fifth aspect of the present invention provides a computer program product, which includes a computer program stored on a non-transitory computer-readable storage medium, and the computer program includes program instructions, wherein when the program instructions are executed by a computer, the computer executes the steps of the bit data processing method as described in any one of the above items.

[0033] It can be seen from the above technical solutions that the present invention has the following advantages:

[0034] The first aspect of the above technical scheme of the present invention provides an additive compressor for addition operation, the compressor comprising a first five-input lookup table and a second five-input lookup table spliced ​​and connected to the first five-input lookup table; the first five-input lookup table is used to calculate the input first bit data, second bit data, third bit data, fourth bit data and fifth bit data, output the operation low-order bit data, operation middle-order bit data and operation high-order bit data, and eliminate the operation high-order bit data; the second five-input lookup table is used to calculate the input operation low-order bit data, operation middle-order bit data, first bit data, second bit data and sixth bit data based on a preset operation truth table to generate a compressor target result; based on the above scheme, each bit data is processed by the first five-input lookup table and the second five-input lookup table spliced ​​and connected to the first five-input lookup table, and the process of outputting the compressor target result, compared with the existing additive compressor that only focuses on reducing delay, the present invention can reduce the resource consumption of the lookup table, thereby improving the resource efficiency of the lookup table.

[0035] The second aspect of the above technical solution of the present invention provides a method for processing bit data, which is applied to the additive compressor for addition operation proposed in the present invention. First, the first bit data, the second bit data, the third bit data, the fourth bit data, the fifth bit data and the sixth bit data are obtained; the first bit data, the second bit data, the third bit data, the fourth bit data and the fifth bit data are calculated, and the operation low-order bit data, the operation middle-order bit data and the operation high-order bit data are output, and the operation high-order bit data is eliminated; based on the preset operation truth table, the input operation low-order bit data, the operation middle-order bit data, the first bit data, the second bit data and the sixth bit data are calculated to generate a compressor target result; based on the above scheme, each bit data obtained is processed and the compressor target result is output. Compared with the existing additive compressor that only focuses on reducing delays, the present invention can reduce the resource consumption of the lookup table, thereby improving the resource efficiency of the lookup table. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative labor.

[0037] Figure 1 A schematic diagram of the structure of an adder compressor for addition operation provided in the first embodiment of the present invention;

[0038] Figure 2 A schematic diagram of a compression process of an additive compressor for addition operation provided in Embodiment 1 of the present invention;

[0039] Figure 3 A schematic diagram of the compression process of the 3-2 compressor provided in Embodiment 1 of the present invention;

[0040] Figure 4 A schematic diagram of the compression process of the 2-2 compressor provided in Embodiment 1 of the present invention;

[0041] Figure 5 A schematic diagram of the compression process of the 6-3 compressor and the 5-3 compressor provided in the first embodiment of the present invention;

[0042] Figure 6 A flowchart of a method for processing bit data provided in Embodiment 2 of the present invention. DETAILED DESCRIPTION

[0043] The embodiments of the present invention provide an adder compressor for addition operation and a method for processing bit data, which are used to solve the technical problem that the existing adder compressor leads to low resource efficiency of the lookup table.

[0044] In order to make the purpose, features and advantages of the present invention more obvious and easy to understand, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the embodiments described below are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0045] See also Figure 1 , Figure 1 A schematic diagram of the structure of an adder compressor for addition operation provided in Embodiment 1 of the present invention.

[0046] The present invention provides an additive compressor for addition operation, the compressor comprising a first five-input lookup table and a second five-input lookup table spliced ​​and connected to the first five-input lookup table;

[0047] A first five-input lookup table is used to calculate the input first bit data, second bit data, third bit data, fourth bit data and fifth bit data, output the calculated low-order bit data, the calculated middle-order bit data and the calculated high-order bit data, and remove the calculated high-order bit data;

[0048] The second five-input lookup table is used to calculate the input low-order bit data, middle-order bit data, first bit data, second bit data, and sixth bit data based on a preset operation truth table to generate a compressor target result.

[0049] Please note that Figure 2 The invention uses two LUT5 (5 inputs and 2 outputs), namely the first five-input lookup table and the second five-input lookup table connected by the first five-input lookup table, to compress six 1-bit data into three 1-bit data, so that the resource efficiency of compression is 1.5; wherein, Figure 2 The five black spheres on the right are 1-bit data to be compressed, namely the first bit data a1, the second bit data a2, the third bit data a3, the fourth bit data a4 and the fifth bit data a5. The 1-bit data of the black sphere on the left is the sixth bit data b1. The three black spheres at the bottom are the target results of the compressor (s5, s4, s1).

[0050] Furthermore, the calculation idea for the first five-input lookup table is as follows: use the first five-input lookup table (LUT5) to calculate: a1+a2+a3+a4+a5=(s3,s2,s1), discard s3, and only output s1 and s2, where a1 is the first bit data; a2 is the second bit data; a3 is the third bit data; a4 is the fourth bit data; a5 is the fifth bit data; s3 is the high-order bit data for operation; s2 is the middle-order bit data for operation; s1 is the low-order bit data for operation, representing the low-bit data of the complete compression result.

[0051] It is worth mentioning that the adder compressor for addition operation proposed in the present invention is widely used in various occasions that require high-speed and efficient addition operation. Carry-save adders play an important role in digital signal processing, microprocessor chips, high-speed multipliers, and computing tasks that require processing large amounts of data. For example, the adder compressor for addition operation proposed in the present invention can be used for adding multiple inputs, which belongs to a carry-save adder (CSA, Carry-SaveAdder), which is more commonly used in the compression step of the multiplier. Through the adder compressor proposed in the present invention, the addition of multiple partial products can be effectively processed and quickly compressed into fewer partial sums, thereby significantly improving the operation speed and efficiency.

[0052] As a further improvement, the second five-input lookup table is specifically used for:

[0053] Generate restored high-order bit data according to the low-order bit data, the middle-order bit data, the first bit data, and the second bit data using a preset operation truth table;

[0054] Determine target high-order bit data based on the restored high-order bit data, the calculated middle-order bit data and the sixth-order bit data;

[0055] The target high-order bit data and the calculated low-order bit data are concatenated to output the compressor target result.

[0056] The target upper bit data includes first target upper bit data and second target upper bit data.

[0057] It should be noted that, based on the preset operation truth table, a1, a2, s1, s2 and b1 are input into the second five-input lookup table to obtain the high 2-bit data s5 and s4 of the compression result, which are then concatenated with s1 output by the first LUT5 (the first five-input lookup table), and it is calculated that (s5, s4, s1) is the final result of the compressor. Two LUT5s are used to eliminate three 1-bit data, and the resource efficiency is 1.5.

[0058] The processing of s5 and s4 can be expressed as:

[0059] (s5,s4)=(s3',s2)+b1;

[0060] Among them, s5 is the second target high-order bit data; s4 is the first target high-order bit data; s3' is the restored high-order bit data; s2 is the calculated middle bit data; b1 is the sixth bit data; (,) is concatenation; + is addition.

[0061] Further, based on the numerical value corresponding to the low-order bit data, the numerical value corresponding to the middle-order bit data, the numerical value corresponding to the first bit data, and the numerical value corresponding to the second bit data, the high-order bit data s3' is determined to be restored in the preset operation truth table; wherein the preset operation truth table is shown in Table 1-Table 4:

[0062] Table 1 Preset operation truth table

[0063]

[0064] Table 2 Preset operation truth table

[0065]

[0066] Table 3 Preset operation truth table

[0067]

[0068] Table 4 Preset operation truth table

[0069]

[0070] Furthermore, the calculation idea for the second five-input lookup table can be summarized as follows: divide s1 and s2 into 4 categories: 00, 01, 10 and 11; when (s2, s1) = 00, the possible combinations of a1, a2, a3, a4 and a5 are 5 0s, or 4 1s and 1 0, and the result of a1+a2+a3+a4+a5 can be restored through the additional 2 inputs a1 and a2; when (s2, s1) = 01, the possible combinations of a1, a2, a3, a4 and a5 are 1 1 and 4 0s , or 5 1s, the result of a1+a2+a3+a4+a5 can be recovered through the additional 2 inputs a1 and a2; when (s2,s1)=10, the possible combinations of a1, a2, a3, a4 and a5 are 2 1s and 3 0s, and the result of a1+a2+a3+a4+a5 can be directly recovered; when (s2,s1)=11, the possible combinations of a1, a2, a3, a4 and a5 are 3 1s and 2 0s, and the result of a1+a2+a3+a4+a5 can be directly recovered.

[0071] As a comparison of the technical effect, it can be referenced in conjunction with the prior art that almost any arithmetic operation uses the addition of several variables. Existing additive compressors provide a fast and compact implementation for ordinary adder trees by using a carry-and-store algorithm. The most prominent example is multiplication, where several partial products must be added. However, there are many more applications besides multiplication. In a network of multiply-add operations, many operations can be merged into a single compressor tree according to the well-known concept of merged arithmetic. This includes basic operations such as square, multiply-add, and complex multiplication, but also function calculations using polynomials, as well as signal processing applications such as digital filters and linear transforms, to name just a few.

[0072] Existing additive compressors, while promising substantial speedups for application-specific integrated circuits (ASICs) or custom integrated circuits, have long been considered unsuitable for use with carry-save algorithms on field-programmable gate arrays (FPGAs) (e.g., the classic additive compressor structures such as the Wallace tree and Dadda tree, 3-2 compressors and 2-2 compressors). The reason for this is that the specialized carry chains found in modern FPGAs are much faster than the general-purpose wires mapped to the FPGA routing structure. For example, Figure 3-Figure 4 As shown, the compression process of the 3-2 compressor and the 2-2 compressor is as follows:

[0073] The 3-2 compressor can be equivalent to the addition of 3 1-bit data, and the 2-2 compressor is equivalent to the addition of 2 1-bit data. Both compressors consume 1 lookup table resource and the delay is 1 lookup table. The number of levels of the multi-bit compression tree changes from 3 to 2. The 3-2 compressor consumes 1 bit of data, and 3 1-bit data are converted into 2 data through 1 lookup table. The 2-2 compressor consumes 1 lookup table, and there is no reduction in the amount of data.

[0074] The classic 3-2 compressor and 2-2 compressor can be regarded as full adder and half adder respectively. Since the basic unit structure of the popular FPGA is a lookup table (LUT6, 6 inputs and 1 output, or LUT5, 5 inputs and 2 outputs), the 3-2 and 2-2 compressors cannot be effectively mapped to the lookup table, resulting in a waste of some resources.

[0075] Therefore, an additive compressor designed for the lookup table is needed, which can effectively utilize the lookup table resources. Figure 5 As shown, the scheme based on the lookup table includes a 6-3 compressor and a 5-3 compressor, and the compression process is as follows:

[0076] The 6-3 compressor is equivalent to the addition of 6 1-bit data, and the 5-3 compressor is equivalent to the addition of 5 1-bit data. These two compressors consume 3 and 2 lookup table resources respectively, and the delay is 1 lookup table. The number of levels of the multi-bit compression tree changes to 6-->3 or 5-->3. The 6-3 compressor consumes 3 bits of data, and 6 1-bit data are converted into 3 data through 3 lookup tables. The 5-3 compressor consumes 2 bits of data, and 5 1-bit data are converted into 3 data through 2 lookup tables. The compression efficiency of the lookup table is 1 (that is, one lookup table resource consumes 1 bit of data).

[0077] Through the compression scheme based on the lookup table, it can be found that the compression efficiency of the 6-3 compressor and the 5-3 compressor is the same as that of the 3-2 compressor, that is, one lookup table can eliminate one bit of data.

[0078] The hardware delay characteristics of the 6-3 compressor and the 5-3 compressor are better than those of the 3-2 compressor. In multi-bit addition compression, for example, 6 multi-bit data are added together, and the target is compressed into 3 rows of data. The 3-2 adder needs to be compressed in parallel. The first round of compression compresses 6 addends into 4 addends, and the second round uses a multi-bit 3-2 adder to compress into 3 rows. The hardware delay is 2 lookup tables, and the delay efficiency is 1 / 3. The 6-3 compressor directly compresses 6 rows of data into 3 rows, and the hardware delay is 1 lookup table, and the delay efficiency is 1 / 2. Their compression process consumes the same lookup table resources, and the compression resource efficiency is 1.

[0079] In summary, the existing compressor solutions based on lookup tables focus on reducing delays and improving the hardware delay efficiency of the compression tree. However, the resource efficiency of the lookup table is still 1. Therefore, the existing technology does not reduce the resource consumption of the LUT. In order to improve the resource efficiency of the lookup table in the compression tree, the present invention proposes an additive compressor for addition operations. The resource efficiency of the FPGA compressor (additive compressor for addition operations) based on the lookup table (excluding the addition carry chain logic in the slice) is improved to 1.5 compared with the existing solution.

[0080] In an embodiment of the present invention, the present invention provides an additive compressor for addition operation, the compressor comprising a first five-input lookup table and a second five-input lookup table spliced ​​and connected to the first five-input lookup table; the first five-input lookup table is used to calculate the input first bit data, second bit data, third bit data, fourth bit data and fifth bit data, output the operation low-order bit data, operation middle bit data and operation high-order bit data, and eliminate the operation high-order bit data; the second five-input lookup table is used to calculate the input operation low-order bit data, operation middle bit data, first bit data, second bit data, and sixth bit data based on a preset operation truth table to generate a compressor target result; based on the above scheme, each bit data is processed by the first five-input lookup table and the second five-input lookup table spliced ​​and connected to the first five-input lookup table, and the process of outputting the compressor target result, compared with the existing additive compressor that only focuses on reducing delay, the present invention can reduce the resource consumption of the lookup table, thereby improving the resource efficiency of the lookup table.

[0081] See also Figure 6 , Figure 6 A flowchart of a method for processing bit data provided in Embodiment 2 of the present invention.

[0082] A method for processing bit data provided by the present invention is applied to the above-mentioned additive compressor for addition operation, comprising:

[0083] Step 601: Obtain first bit data, second bit data, third bit data, fourth bit data, fifth bit data and sixth bit data.

[0084] In the embodiment of the present invention, first bit data, second bit data, third bit data, fourth bit data, fifth bit data and sixth bit data are acquired.

[0085] Step 602: Calculate the first bit data, the second bit data, the third bit data, the fourth bit data and the fifth bit data, output the calculated low-order bit data, the calculated middle-order bit data and the calculated high-order bit data, and remove the calculated high-order bit data.

[0086] In an embodiment of the present invention, the first bit data, the second bit data, the third bit data, the fourth bit data and the fifth bit data are calculated, and the calculated low-order bit data, the calculated middle-order bit data and the calculated high-order bit data are output, and the calculated high-order bit data is discarded.

[0087] Step 603: Based on the preset operation truth table, the input operation low-order bit data, operation middle-order bit data, first bit data, second bit data, and sixth bit data are calculated to generate a compressor target result.

[0088] Further, step 603 may include the following sub-steps:

[0089] S31, using a preset operation truth table to generate restored high-order bit data according to the operation low-order bit data, the operation middle-order bit data, the first bit data, and the second bit data;

[0090] S32, determining target high-order bit data based on the restored high-order bit data, the calculated middle-order bit data and the sixth bit data;

[0091] S33, concatenate the target high-order bit data and the calculated low-order bit data, and output the compressor target result.

[0092] The target high-order bit data includes first target high-order bit data and second target high-order bit data; the calculation process of the target high-order bit data is specifically as follows:

[0093] (s5,s4)=(s3',s2)+b1;

[0094] Among them, s5 is the second target high-order bit data; s4 is the first target high-order bit data; s3' is the restored high-order bit data; s2 is the calculated middle bit data; b1 is the sixth bit data; (,) is concatenation; + is addition.

[0095] In the embodiment of the present invention, based on a preset operation truth table, the input operation low-order bit data, operation middle-order bit data, first bit data, second bit data, and sixth bit data are calculated to generate a compressor target result.

[0096] In an embodiment of the present invention, the present invention provides a method for processing bit data, which is applied to the additive compressor for addition operation proposed in the present invention. First, the first bit data, the second bit data, the third bit data, the fourth bit data, the fifth bit data and the sixth bit data are obtained; the first bit data, the second bit data, the third bit data, the fourth bit data and the fifth bit data are calculated, and the operation low-order bit data, the operation middle-order bit data and the operation high-order bit data are output, and the operation high-order bit data is eliminated; based on a preset operation truth table, the input operation low-order bit data, the operation middle-order bit data, the first bit data, the second bit data and the sixth bit data are calculated to generate a compressor target result; based on the above scheme, each bit data obtained is processed and the compressor target result is output. Compared with the existing additive compressor that only focuses on reducing delays, the present invention can reduce the resource consumption of the lookup table, thereby improving the resource efficiency of the lookup table.

[0097] An embodiment of the present invention further provides a computer device, including a memory and a processor, wherein a computer program is stored in the memory; when the computer program is executed by the processor, the processor executes the steps of the bit data processing method of the second embodiment.

[0098] An embodiment of the present invention further provides a computer-readable storage medium on which a computer program / instruction is stored. When the computer program / instruction is executed by a processor, the steps of the bit data processing method of the above-mentioned embodiment 2 are implemented.

[0099] An embodiment of the present invention further provides a computer program product, including a computer program / instruction, which implements the steps of the bit data processing method of the above-mentioned embodiment 2 when the computer program / instruction is executed by a processor.

[0100] In the several embodiments provided in the present application, it should be understood that the disclosed adder compressor and method for addition operation can be implemented in other ways. For example, the device embodiments described above are only schematic. For example, the division of units is only a logical function division. There may be other division methods in actual implementation. For example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0101] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0102] As described above, the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit the same. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that the technical solutions described in the aforementioned embodiments may still be modified, or some of the technical features thereof may be replaced by equivalents. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. An additive compressor for addition operation, characterized in that The compressor includes a first five-input lookup table and a second five-input lookup table spliced ​​and connected to the first five-input lookup table; The first five-input lookup table is used to calculate the input first bit data, second bit data, third bit data, fourth bit data and fifth bit data, output calculation low-order bit data, calculation middle-order bit data and calculation high-order bit data, and remove the calculation high-order bit data; The second fifth input lookup table is used to calculate the input low-order bit data, the middle-order bit data, the first bit data, the second bit data, and the sixth bit data based on a preset operation truth table to generate a compressor target result.

2. The additive compressor for addition operation according to claim 1, characterized in that The second fifth input lookup table is specifically used for: Generate restored high-order bit data according to the calculated low-order bit data, the calculated middle-order bit data, the first bit data, and the second bit data using a preset calculation truth table; Determine target high-order bit data based on the restored high-order bit data, the calculated middle-order bit data and the sixth bit data; The target high-order bit data and the calculated low-order bit data are concatenated to output a compressor target result.

3. The additive compressor for addition operation according to claim 1, characterized in that The calculation process of the first five input lookup tables is specifically as follows: a1+a2+a3+a4+a5=(s3,s2,s1); Among them, a1 is the first bit data; a2 is the second bit data; a3 is the third bit data; a4 is the fourth bit data; a5 is the fifth bit data; s3 is the high-order bit data for calculation; s2 is the middle-order bit data for calculation; s1 is the low-order bit data for calculation.

4. The additive compressor for addition operation according to claim 2, characterized in that: The target high-order bit data includes first target high-order bit data and second target high-order bit data; the calculation process of the target high-order bit data is specifically as follows: (s5,s4)=(s3',s2)+b1; Among them, s5 is the second target high-order bit data; s4 is the first target high-order bit data; s3' is the restored high-order bit data; s2 is the calculated middle bit data; b1 is the sixth bit data; (,) is concatenation; + is addition.

5. A method for processing bit data, characterized in that: Applied to the additive compressor for addition operation as claimed in claim 1, the method comprising: Obtaining first bit data, second bit data, third bit data, fourth bit data, fifth bit data and sixth bit data; Calculate the first bit data, the second bit data, the third bit data, the fourth bit data and the fifth bit data, output calculated low-order bit data, calculated middle-order bit data and calculated high-order bit data, and remove the calculated high-order bit data; Based on a preset operation truth table, the input operation low-order bit data, the operation middle-order bit data, the first bit data, the second bit data, and the sixth bit data are calculated to generate a compressor target result.

6. The method for processing bit data according to claim 5, characterized in that: The step of calculating the input low-order bit data, the middle-order bit data, the first bit data, the second bit data, and the sixth bit data based on the preset operation truth table to generate a compressor target result includes: Generate restored high-order bit data according to the calculated low-order bit data, the calculated middle-order bit data, the first bit data, and the second bit data using a preset calculation truth table; Determine target high-order bit data based on the restored high-order bit data, the calculated middle-order bit data and the sixth bit data; The target high-order bit data and the calculated low-order bit data are concatenated to output a compressor target result.

7. The method for processing bit data according to claim 6, characterized in that: The target high-order bit data includes first target high-order bit data and second target high-order bit data; the calculation process of the target high-order bit data is specifically as follows: (s5,s4)=(s3',s2)+b1; Among them, s5 is the second target high-order bit data; s4 is the first target high-order bit data; s3' is the restored high-order bit data; s2 is the calculated middle bit data; b1 is the sixth bit data; (,) is concatenation; + is addition.

8. A computer device, characterized in that: It comprises a memory and a processor, wherein the memory stores a computer program, and when the computer program is executed by the processor, the processor executes the steps of the bit data processing method as described in any one of claims 5-7.

9. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed, the method for processing bit data as described in any one of claims 5 to 7 is implemented.

10. A computer program product, characterized in that The computer program product comprises a computer program stored on a non-transitory computer-readable storage medium, wherein the computer program comprises program instructions, wherein when the program instructions are executed by a computer, the computer is caused to execute the method for processing bit data as described in any one of claims 5-7.

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