Single-precision chip data processing method and system, chip, equipment and storage medium
By using multiple single-precision floating point numbers on a single-precision chip to represent double-precision floating point numbers and perform reduction and reconstruction processing, the poor performance problem caused by the lack of 64-bit double-precision floating point computing hardware units is solved, and efficient double-precision floating point calculation is achieved.
Patent Information
- Application Number
- CN202411855691.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-17
- Publication Date
- 2025-03-25
AI Technical Summary
The prior art lacks 64-bit double-precision floating-point calculation hardware units when performing double-precision floating-point calculations, resulting in poor performance, especially on chips such as GPUs that have a large number of 32-bit single-precision computing components.
By using at least three single-precision floating point numbers on a single-precision chip, and reducing and reconstructing the calculation of the double-precision floating point number, the calculation of the double-precision floating point number is performed using the single-precision operation unit to perform calculation of the double-precision transcendence function.
It realizes efficient double-precision floating-point number calculation in the absence of 64-bit double-precision floating-point computing hardware units, fully utilizes the potential of single-precision floating-point computing power, and improves computing performance.
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Figure CN119690381A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of chip data processing technology, and in particular, to a single-precision chip data processing method, system, chip, device and storage medium. Background Art
[0002] The double-precision floating point number type used in C and C++ is defined in the IEEE Standard for Binary Floating-Point Arithmetic (ANSI / IEEE Std 754-1985). Double-precision floating point numbers (Double) are used to represent real numbers with decimal parts. They are generally used to define variables in computer programming. They occupy 8 bytes of storage space and have a value range of -1.7E-308 to 1.7E+308. Double-precision floating point numbers have a maximum of 15 or 16 decimal digits.
[0003] 64-bit double-precision floating-point operations require more computing resources. Some GPUs or embedded chips do not have such hardware units, and are even more powerless for complex calculations such as trigonometric functions and transcendental functions. In this case, software that only uses integer operation instructions is often used for calculations.
[0004] However, these floating-point arithmetic software libraries use integers to represent the encoding of double-precision floating-point numbers and only use integer arithmetic instructions to perform calculations according to corresponding algorithms. Although high precision can be achieved, the performance is very low. Summary of the invention
[0005] In order to solve one of the above-mentioned technical defects, a single-precision chip data processing method, system, chip, device and storage medium are provided in the embodiments of the present application.
[0006] According to a first aspect of an embodiment of the present application, a single-precision chip data processing method is provided, the method comprising:
[0007] For single-precision chips, double-precision floating points are represented by at least three single-precision floating points;
[0008] Perform reduction processing on the calculation of double-precision floating-point numbers in single-precision chips;
[0009] The calculation of double-precision floating-point numbers is reconstructed through a reduction equation to complete the processing of double-precision floating-point data in a single-precision chip.
[0010] In an optional embodiment of the present application, the step of reducing the calculation of double-precision floating-point numbers in the single-precision chip further includes:
[0011] The function value calculation of the first double-precision floating-point number is reduced and converted into the function value calculation of the second double-precision floating-point number within a limited range, and the function value of the second double-precision floating-point number that meets the target precision requirement is obtained.
[0012] In an optional embodiment of the present application, the step of reducing the calculation of double-precision floating-point numbers in the single-precision chip further includes:
[0013] Get the function value of the second double-precision floating-point number that meets the target precision requirement through an approximation algorithm.
[0014] In an optional embodiment of the present application, the step of reducing the calculation of double-precision floating-point numbers in the single-precision chip further includes:
[0015] The approximation algorithm includes any one of a piecewise optimal approximation algorithm and an optimal polynomial approximation algorithm.
[0016] In an optional embodiment of the present application, the step of reconstructing the calculation of the double-precision floating-point number by reducing the equation to complete the processing of the double-precision floating-point data in the single-precision chip also includes:
[0017] The function value of the first double-precision floating-point number is calculated using the function value of the second double-precision floating-point number according to the characteristic of the function value of the first double-precision floating-point number.
[0018] According to a second aspect of an embodiment of the present application, a single-precision chip data processing system is provided, the system comprising a precision representation module, a reduction processing module and a reconstruction processing module; wherein,
[0019] A precision representation module, used for representing a double precision floating point through at least three single precision floating points in a single precision chip;
[0020] A reduction processing module, used for performing reduction processing on the calculation of double-precision floating-point numbers in a single-precision chip;
[0021] The reconstruction processing module is used to perform reconstruction calculation on the calculation of double-precision floating-point numbers through a reduction equation to complete the processing of double-precision floating-point data in a single-precision chip.
[0022] In an optional embodiment of the present application, the reduction processing module further includes:
[0023] The function value calculation of the first double-precision floating-point number is reduced and converted into the function value calculation of the second double-precision floating-point number within a limited range, and the function value of the second double-precision floating-point number that meets the target precision requirement is obtained.
[0024] According to a third aspect of an embodiment of the present application, a chip is provided, the chip comprising a processor and a memory, a computer program is stored in the memory, and when the computer program is executed by the processor, a single-precision chip data processing method as described in any one of the first aspects of the embodiment of the present application is implemented.
[0025] According to a fourth aspect of the embodiments of the present application, there is provided a computer device, including: a memory;
[0026] A processor; and a computer program; wherein the computer program is stored in a memory and is configured to be executed by the processor to implement a single-precision chip data processing method as described in any one of the first aspects of the embodiments of the present application.
[0027] According to a fourth aspect of an embodiment of the present application, a computer-readable storage medium is provided, on which a computer program is stored; the computer program is executed by a processor to implement a single-precision chip data processing method as described in any one of the first aspects of the embodiments of the present application.
[0028] The single-precision chip data processing method provided in the embodiment of the present application has the following beneficial effects:
[0029] The present application uses a method of expressing double-precision floating-point numbers by using multiple single-precision floating-point numbers, and uses a single-precision arithmetic unit to calculate a double-precision transcendental function. The single-precision floating-point arithmetic unit can be used to perform double-precision transcendental function calculations. The application is suitable for chips such as GPUs that have a large number of 32-bit single-precision arithmetic components but lack 64-bit double-precision floating-point arithmetic components, and can give full play to the computing power of the chip. BRIEF DESCRIPTION OF THE DRAWINGS
[0030] The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:
[0031] Figure 1 A flowchart of a single-precision chip data processing method provided in an embodiment of the present application;
[0032] Figure 2 A structural diagram of a single-precision chip data processing system provided in an embodiment of the present application;
[0033] Figure 3 A schematic diagram of the structure of a chip provided in an embodiment of the present application;
[0034] Figure 4 A schematic diagram of the computer device structure provided in an embodiment of the present application. DETAILED DESCRIPTION
[0035] In order to make the technical solutions and advantages in the embodiments of the present application more clearly understood, the exemplary embodiments of the present application are further described in detail below in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present application, rather than an exhaustive list of all the embodiments. It should be noted that the embodiments in the present application and the features in the embodiments can be combined with each other without conflict.
[0036] 64-bit double-precision floating-point operations usually require more complex computing resources due to their high precision requirements. However, not all graphics processing units (GPUs) or embedded chips are equipped with such hardware units, especially when faced with complex calculations of transcendental functions such as trigonometric functions. Such functions are particularly demanding in terms of computing resources due to their nonlinear characteristics and high mathematical complexity.
[0037] In the case of limited hardware resources, a common solution is to use pure software, that is, to rely only on integer operation instructions to complete the calculation task. This method uses a specific algorithm to convert double-precision floating-point numbers into integer encoding, and then uses the integer operation unit to perform the corresponding calculation steps. Although this method can achieve higher calculation accuracy in theory, due to the essential differences between integer operations and floating-point operations, as well as the limitations of the integer operation unit in processing complex mathematical functions, the overall performance is often very low.
[0038] This performance bottleneck is particularly evident on chips with a large number of 32-bit single-precision floating-point units, such as modern GPUs. Although these chips are good at processing single-precision floating-point operations, they cannot fully realize their computing potential when performing double-precision transcendental function calculations due to the lack of hardware units that directly support double-precision floating-point operations and the conversion overhead between integer operations and floating-point operations. This not only leads to low computing efficiency, but also limits the application scope of these high-performance computing resources in fields that require high-precision calculations.
[0039] Some background concepts are explained in the embodiments of this application:
[0040] IEEE single-precision floating point number: Single-precision floating point number encoding 32 bits, each with 1 sign bit S = b 31 , 8 exponent bits E = b 30 …b 23 , 23 mantissa digits F = b 22 ...b0, the value represented is Where m x =1+2 -23 ·F,e x =E-127, with a precision of 24 significant digits.
[0041] IEEE double-precision floating point number: Double-precision floating point number encoding 64 bits, each with 1 sign bit S = b 63 , 11 exponent bits E = b 62 …b 52 , 52 mantissa digits F = b 51 ...b0, the value represented is Where m x =1+2 -52 ·F,e x =E-1023, with a precision of 53 significant digits.
[0042] Transcendental function: The transcendental function here refers to the functions that cannot be directly calculated by the multiplication and addition unit, such as square root, reciprocal square root, trigonometric function, exponential function, logarithmic function, etc.
[0043] The present application provides a data processing method suitable for a single-precision chip, which can utilize a single-precision floating-point arithmetic unit to perform double-precision transcendental function calculations, thereby giving full play to the computing power of the chip. Figure 1 For a flowchart of the single-precision chip data processing method provided in the embodiment of the present application, please refer to Figure 1 :
[0044] S1: For single-precision chips, double-precision floating points are represented by at least three single-precision floating points.
[0045] In a specific implementation, the effective number of a single-precision floating point (float) is 24 bits, and the effective number of a double-precision floating point (double) is 53 bits. In this embodiment, three floats are used to represent a double, namely
[0046] x=x h +x m +x l
[0047] Where x is a double-precision floating point number, h , X m , x1 are all single-precision floating point numbers.
[0048] In this way, the number of significant digits of this representation method can reach 72, which fully meets the accuracy requirements of double-precision floating-point numbers. The only limitation is the exponent range, which is limited to the standard range of the float type, from -126 to 127. Although the exponent range is somewhat limited, it is still sufficient for most common applications.
[0049] S2: Reduce the calculation of double-precision floating-point numbers in the single-precision chip.
[0050] In some embodiments of the present application, the function value calculation of the first double-precision floating-point number is reduced to the function value calculation of the second double-precision floating-point number within a limited range, and the function value of the second double-precision floating-point number that meets the target precision requirement is obtained.
[0051] Specifically, the function value of the second double-precision floating-point number that meets the target precision requirement is obtained through an approximation algorithm. Optionally, the approximation algorithm includes any one of a piecewise optimal approximation algorithm and an optimal polynomial approximation algorithm.
[0052] In the specific implementation, the characteristics of the target function f(x) are used to convert the function value calculation of any floating point number x into the calculation of the function value f(y) of the floating point number y within a certain limited range. For example, the calculation of the square root of a floating point number can be reduced to the calculation within the interval [1, 2):
[0053] In the specific implementation, a piecewise optimal approximation algorithm is used to calculate f(y) that meets the target accuracy requirements.
[0054] Specifically, a piecewise optimal approximation algorithm is used to calculate the function value that meets the target accuracy requirements. Based on the characteristics of the target function, this algorithm divides its domain into several smaller subintervals and searches for an optimal approximation function for each subinterval. These approximation functions can be polynomials, rational functions, or other types of simple functions, which can approximate the original function with extremely high accuracy in their respective subintervals.
[0055] In the process of segmentation, the smoothness, monotonicity or other known characteristics of the objective function are used to ensure that the sub-intervals are neither too fragmented, thereby avoiding unnecessary increase in the amount of calculation, nor too broad, thereby avoiding loss of approximation accuracy. The approximation function in each sub-interval is determined by minimizing the approximation error to find the optimal approximation function coefficients.
[0056] After all the approximation functions of the subintervals are determined, these approximation functions can be used to quickly and accurately calculate the function value of the original function at any given point, as long as the point is within a subinterval. Since each approximation function is carefully designed within its corresponding subinterval, they can provide function value calculations that match the target accuracy requirements.
[0057] This piecewise optimal approximation algorithm not only significantly improves the accuracy and efficiency of function value calculation, but also makes the algorithm adaptable and flexible to different types of objective functions and accuracy requirements.
[0058] S3: Reconstruct the calculation of the double-precision floating-point number through the reduction equation to complete the processing of the double-precision floating-point data in the single-precision chip.
[0059] In some embodiments of the present application, the function value of the first double-precision floating-point number is calculated using the function value of the second double-precision floating-point number according to the characteristics of the function value of the first double-precision floating-point number.
[0060] In a specific implementation, f(x) is calculated using the value of f(y) according to the characteristics of the objective function, such as the square root reduction equation mentioned above.
[0061] Based on this, the embodiment of the present application maps the input floating-point number to a limited range through a certain transformation (such as scaling, translation or modulo operation), further calculates the function value based on the reduced value, and restores the result to the original scale through another inverse transformation.
[0062] Furthermore, the embodiment of the present application provides a specific example, taking the calculation of the double-precision trigonometric function sin(x) as an example to further illustrate the above technical solution:
[0063] Take the double-precision trigonometric function sin(x) calculation as an example. The input is
[0064] m x =1.b1…b 52 ,e x ∈[-126,127]
[0065] The calculation process is as follows:
[0066] Reduction: Reduce x to
[0067]
[0068]
[0069] The constant is recorded as The integer k has at most 127 significant digits. If the precision of the reduction parameter y is p, the precision of C needs to reach 189+p digits after the decimal point. In order to ensure that the intermediate calculation results do not lose precision, a few more digits can be added. k and y are calculated according to equation (i). The above x and y are both expressed in 3 floats.
[0070] Approximation: After the parameter reduction process in the previous step, the problem is transformed into calculation The sin and cos function values at . According to the best polynomial approximation algorithm, calculate the sin and cos in the interval The best approximation polynomials of degree 9 and degree 8 are
[0071] sin(y)=y+A3·y 3 +A5·y 5+A7·y 7 +A9·y 9
[0072] cos(y)=1+B2·y 2 +B4·y 4 +B6·y 6 +B8·y 8
[0073] The coefficients are limited to double-precision floating point numbers, and their encodings are
[0074] A3 = 0xbfc55555555554c0 B2 = 0xbfdffffffffffce0 A5 = 0x3f81111111082c60 B4 = 0x3fa55555553d3780 A7 = 0xbf2a019f6f02cda0 B6 = 0xbf56c16b2d54d240 A9 = 0x3ec718cb47813bc0 B8 = 0x3ef9faa3e99c2b60
[0075] Reconstruction: Substitute sin(y) and cos(y) calculated in the previous step into the reduction equation Just recalculate and The integer k is split into k = 16m + 4r + u, then Where 0≤u≤3,0≤r≤3.
[0076] S0=0, S1=sin(π / 8), S2=sin(2π / 8), S3=sin(3π / 8),
[0077] S4=1
[0078] It can be calculated according to the following table and
[0079]
[0080] In summary, the embodiment of the present application uses a single-precision computing unit to calculate a double-precision transcendental function, which is suitable for chips such as GPUs that have a large number of 32-bit single-precision computing components but lack 64-bit double-precision floating-point computing components. The method proposed in the embodiment of the present application can give full play to the single-precision floating-point computing power, and proposes a unified calculation method for transcendental function calculation.
[0081] It should be understood that, although the various steps in the flow chart are displayed in sequence according to the indication of the arrows, these steps are not necessarily executed in sequence according to the order indicated by the arrows. Unless there is a clear description in this article, the execution of these steps is not strictly limited in order, and these steps can be executed in other orders. Moreover, at least a portion of the steps in the figure may include multiple sub-steps or multiple stages, and these sub-steps or stages are not necessarily executed at the same time, but can be executed at different times, and the execution order of these sub-steps or stages is not necessarily to be carried out in sequence, but can be executed in turn or alternately with other steps or at least a portion of the sub-steps or stages of other steps.
[0082] See also Figure 2 An embodiment of the present application provides a single-precision chip data processing system, which includes a precision representation module 10, a reduction processing module 20 and a reconstruction processing module 30; wherein,
[0083] A precision representation module 10, used for representing a double precision floating point through at least three single precision floating points in a single precision chip;
[0084] A reduction processing module 20, used for performing reduction processing on the calculation of double-precision floating-point numbers in a single-precision chip;
[0085] The reconstruction processing module 30 is used to perform reconstruction calculation on the calculation of double-precision floating-point numbers through a reduction equation to complete the processing of double-precision floating-point data in a single-precision chip.
[0086] In some embodiments of the present application, the reduction processing module 20 further includes: reducing the function value calculation of the first double-precision floating-point number to convert the function value calculation of the second double-precision floating-point number within a limited range, and obtaining the function value of the second double-precision floating-point number that meets the target precision requirement.
[0087] For the specific definition of the above-mentioned single-precision chip data processing system, please refer to the definition of the single-precision chip data processing method above, which will not be repeated here. Each module in the above-mentioned single-precision chip data processing system can be implemented in whole or in part by software, hardware and a combination thereof. The above-mentioned modules can be embedded in or independent of the processor in the computer device in the form of hardware, or can be stored in the memory in the computer device in the form of software, so that the processor can call and execute the operations corresponding to the above modules.
[0088] The present application also provides a chip, see Figure 3 As shown, the chip includes a processor and a memory, in which a computer program is stored. When the computer program is executed by the processor, the single-precision chip data processing method in the above-mentioned embodiments is implemented.
[0089] In one embodiment, a computer device is provided, the internal structure diagram of which can be as follows: Figure 4As shown. The computer device includes a processor, a memory, a network interface and a database connected through a system bus. Among them, the processor of the computer device is used to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system, a computer program and a database. The internal memory provides an environment for the operation of the operating system and the computer program in the non-volatile storage medium. The database of the computer device is used to store data. The network interface of the computer device is used to communicate with an external terminal through a network connection. When the computer program is executed by the processor, the single-precision chip data processing method as above is implemented. It includes: a memory and a processor, the memory stores a computer program, and the processor implements the single-precision chip data processing method as above when executing the computer program.
[0090] In one embodiment, a computer-readable storage medium is provided, on which a computer program is stored. When the computer program is executed by a processor, the single-precision chip data processing method as described above can be implemented.
[0091] Those skilled in the art will appreciate that the embodiments of the present application can be provided as methods, systems, or computer program products. Therefore, the present application can adopt the form of complete hardware embodiments, complete software embodiments, or embodiments in combination with software and hardware. Moreover, the present application can adopt the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) that contain computer-usable program code. The scheme in the embodiments of the present application can be implemented in various computer languages, for example, C language, VHDL language, Verilog language, object-oriented programming language Java and literal scripting language JavaScript, etc.
[0092] The present application is described with reference to the flowcharts and / or block diagrams of the systems and computer program products according to the embodiments of the present application. It should be understood that each process and / or block in the flowchart and / or block diagram, as well as the combination of the processes and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.
[0093] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.
[0094] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.
[0095] Although the preferred embodiments of the present application have been described, those skilled in the art may make other changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications falling within the scope of the present application.
[0096] Obviously, those skilled in the art can make various changes and modifications to the present application without departing from the spirit and scope of the present application. Thus, if these modifications and variations of the present application fall within the scope of the claims of the present application and their equivalents, the present application is also intended to include these modifications and variations.
Claims
1. A single-precision chip data processing method, characterized in that: include: For single-precision chips, double-precision floating points are represented by at least three single-precision floating points; Performing reduction processing on the calculation of double-precision floating-point numbers in the single-precision chip; The calculation of the double-precision floating-point number is reconstructed by a reduction equation to complete the processing of the double-precision floating-point data in the single-precision chip.
2. The single-precision chip data processing method according to claim 1, characterized in that: The step of reducing the calculation of the double-precision floating point number in the single-precision chip also includes: The function value calculation of the first double-precision floating-point number is reduced and converted into the function value calculation of the second double-precision floating-point number within a limited range, and the function value of the second double-precision floating-point number that meets the target precision requirement is obtained.
3. The single-precision chip data processing method according to claim 2, characterized in that: The step of reducing the calculation of the double-precision floating point number in the single-precision chip also includes: The function value of the second double-precision floating-point number that meets the target precision requirement is obtained through an approximation algorithm.
4. The single-precision chip data processing method according to claim 3, characterized in that: The step of reducing the calculation of the double-precision floating point number in the single-precision chip also includes: The approximation algorithm includes any one of a piecewise optimal approximation algorithm and an optimal polynomial approximation algorithm.
5. The single-precision chip data processing method according to any one of claims 1 to 4, characterized in that: The step of reconstructing the calculation of the double-precision floating-point number by reducing the equation to complete the processing of the double-precision floating-point data in the single-precision chip also includes: The function value of the first double-precision floating-point number is calculated using the function value of the second double-precision floating-point number according to the characteristic of the function value of the first double-precision floating-point number.
6. A single-precision chip data processing system, characterized in that: include: Precision representation module, reduction processing module and reconstruction processing module; among them, A precision representation module, used for representing a double precision floating point through at least three single precision floating points in a single precision chip; A reduction processing module, used for performing reduction processing on the calculation of double-precision floating-point numbers in the single-precision chip; The reconstruction processing module is used to reconstruct the calculation of the double-precision floating point number through a reduction equation to complete the processing of the double-precision floating point data in the single-precision chip.
7. The single-precision chip data processing system according to claim 6, characterized in that: The reduction processing module also includes: The function value calculation of the first double-precision floating-point number is reduced and converted into the function value calculation of the second double-precision floating-point number within a limited range, and the function value of the second double-precision floating-point number that meets the target precision requirement is obtained.
8. A chip, characterized in that: The chip includes a processor and a memory, wherein a computer program is stored in the memory, and when the computer program is executed by the processor, the single-precision chip data processing method according to any one of claims 1 to 5 is implemented.
9. A computer device, characterized in that: include: Memory; processor; as well as Computer programs; The computer program is stored in the memory and is configured to be executed by the processor to implement the single-precision chip data processing method according to any one of claims 1 to 5.
10. A computer-readable storage medium, characterized in that: A computer program is stored thereon; the computer program is executed by a processor to implement a single-precision chip data processing method as claimed in any one of claims 1 to 5.