Memory fault processing method and device, medium and server

Abstract

The invention discloses a memory fault management method and device, a medium and a server, relates to the field of servers, and is used for solving the problems of system instability and reliability caused by memory faults. After the processor receives the fault alarm information of the target memory, the processor firstly analyzes the alarm information and verifies the validity of the alarm information, and if the fault information is valid, a target physical address and a target power supply corresponding to the target memory are determined according to the fault alarm information; and isolating the target memory according to the target physical address, and sending a power-off instruction to the target power supply so as to power off the target memory. The fault memory is allowed to be isolated and replaced when the server runs, the maintainability of the memory is improved, the service interruption caused by the memory fault can be reduced, the maintenance cost is reduced, and the downtime is shortened.

Description

Technical Field

[0001] The present invention relates to the field of servers, and in particular to a memory fault management method, device, medium and server. Background Art

[0002] The rapid development of information technology and the continuous advancement of server technology have made servers play a core role in key areas such as cloud computing, big data, artificial intelligence and the Internet of Things, and have put forward unprecedented high requirements for server performance, stability and scalability. In the complex architecture of servers, memory is a high-speed bridge between the CPU and storage devices, responsible for temporarily storing data and accelerating program execution. Its importance is self-evident.

[0003] However, as server workloads increase, memory capacity expands, and speed increases, memory failures have become a key factor affecting system stability and reliability, which may lead to data loss, service interruptions, and even chain reactions that affect the normal operation of the entire system. Traditional methods of handling memory failures usually require shutting down the server power supply and then switching the memory, which will cause business interruptions and affect service continuity and stability. Summary of the invention

[0004] The purpose of the present invention is to provide a memory fault management method, device, medium and server, which allow the isolation and replacement of faulty memory while the server is running, improve the maintainability of the memory, reduce business interruptions caused by memory failures, reduce maintenance costs and reduce downtime.

[0005] In a first aspect, the present application provides a memory fault management method, which is applied to a processor in a server, wherein the server further comprises a plurality of memories and a plurality of power supplies corresponding to the plurality of memories one by one, each of the memories being connected to a power supply through the power supply, and the memory fault management method comprises:

[0006] When receiving the fault warning information of the target memory, parsing the fault warning information;

[0007] Determine whether the fault warning information is valid according to the analysis result, and if the fault warning information is valid, determine the target physical address and the target power supply corresponding to the target memory according to the fault warning information;

[0008] The target memory is isolated according to the target physical address, and a power-off instruction is sent to the target power supply to power off the target memory.

[0009] Optionally, the fault alarm information includes an identifier of a target central processor to which the target memory belongs, a serial number under the target central processor, and a value of a target register corresponding to the target memory, wherein the value in the target register is used to indicate whether a fault occurs to the target memory;

[0010] When the fault warning information of the target memory is received, the fault warning information is parsed, including:

[0011] When receiving the fault warning information of the target memory, parsing the identifier of the target central processor to which the target memory belongs, the serial number under the target central processor and the value of the target register from the fault warning information;

[0012] Determining whether the fault warning information is valid according to the analysis result includes:

[0013] Determining whether the resolved identifier of the target CPU is within a first preset range;

[0014] Determine whether the sequence number of the target CPU in the target memory is within a second preset range;

[0015] Determining whether the parsed value of the target register is a preset value;

[0016] If the identifier of the target CPU is within the first preset range, and the serial number of the target CPU in the target memory is within the second preset range, and the value of the target register is the preset value, then it is determined that the fault warning information is valid;

[0017] If the identifier of the target CPU is outside the first preset range, or the serial number of the target CPU in the target memory is outside the second preset range, or the value of the target register is not the preset value, it is determined that the fault alarm information is invalid.

[0018] Optionally, the fault warning information includes a value of a target register corresponding to the target memory, and the value in the target register is used to indicate whether the target memory fails; after determining a target physical address and a target power supply corresponding to the target memory according to the fault warning information, the method further includes:

[0019] determining a register address of a target register corresponding to the target memory;

[0020] Isolating the target memory according to the target physical address includes:

[0021] The target physical address and the register address of the target register are written into a memory management register, so that a basic input and output system isolates the target memory based on information in the memory management register.

[0022] Optionally, the server further includes a plurality of fault indication devices corresponding to the plurality of memories one by one, each of the fault indication devices being arranged on a memory slot of the memory corresponding to itself, and after determining a target physical address and a target power supply corresponding to the target memory according to the fault alarm information, further including:

[0023] Determine the target memory slot where the target memory is located and the fault type of the target memory according to the fault alarm information;

[0024] After isolating the target memory according to the target physical address and sending a power-off instruction to the target power supply to power off the target memory, the method further includes:

[0025] Calling a preset correspondence relationship according to the fault type to determine a target state of a target fault indication device corresponding to the target memory; the preset correspondence relationship is a one-to-one correspondence between a fault type and a state of a fault indication device;

[0026] A control signal is sent to the target fault indication device to update the state of the target fault indication device to the target state.

[0027] Optionally, after isolating the target memory according to the target physical address and sending a power-off instruction to the target power supply to power off the target memory, the method further includes:

[0028] Load the backup memory, and send a power-on instruction to the backup power supply corresponding to the backup memory, so that the backup power supply drives the internal charge pump inverter and negative linear regulator to start working, and when the negative voltage output by the negative linear regulator reaches a preset percentage of the set value, the backup power supply turns on the path between the power supply and the backup memory.

[0029] Optionally, the fault alarm information includes a value of a register corresponding to the memory, and the value in the register is used to indicate whether the memory fails; after the backup power supply conducts the path between the power supply and the backup memory, the backup power supply further includes:

[0030] Performing a hardware self-test on the backup memory, the hardware self-test at least comprising detecting a physical connection state between the backup memory and a corresponding central processing unit, detecting a data transmission rate of the backup memory, and detecting an error rate of the backup memory;

[0031] When the detection result of the hardware self-test meets the preset requirement, the value of the register corresponding to the backup memory is reset to a second value, and the basic input and output system is triggered to load the backup memory, and the second value indicates that the memory is not faulty.

[0032] Optionally, the server further includes a plurality of fault recording modules corresponding to the plurality of memories one by one, each of the fault recording modules being used to record the operating status and fault information of the memory; after triggering the basic input and output system to load the backup memory, the server further includes:

[0033] updating a fault recording module corresponding to the target memory according to the fault alarm information, recording the time when the target memory fault occurs, the fault type, the target physical address, and the loading status of the backup memory;

[0034] Log information including the fault handling process of the target memory is generated according to the updated fault record data in the fault record module, and a fault prompt is sent through a management console or a remote interface.

[0035] In a second aspect, the present application provides a memory fault management device, comprising:

[0036] Memory for storing computer programs;

[0037] The processor is used to implement the steps of the memory fault management method as described above when executing a computer program.

[0038] In a third aspect, the present application provides a non-volatile storage medium having a computer program stored thereon, and when the computer program is executed by a processor, the steps of the memory fault management method as described above are implemented.

[0039] In a fourth aspect, the present application provides a server, comprising a memory fault management device as described above, and also comprising a plurality of memories and a plurality of power supplies corresponding one-to-one to the plurality of memories, each of the memories being connected to a power supply through the power supply, and the memory fault management device being connected to each of the memories and each of the power supplies respectively.

[0040] The present application provides a memory fault management method, device, medium and server for solving system instability and reliability problems caused by memory faults. After receiving the fault alarm information of the target memory, the processor first parses the alarm information and verifies its validity. If the fault information is valid, the target physical address and target power supply corresponding to the target memory are determined according to the fault alarm information; the target memory is isolated according to the target physical address, and a power-off instruction is sent to the target power supply to power off the target memory. It allows the isolation and replacement of faulty memory while the server is running, which improves the maintainability of the memory, can reduce business interruptions caused by memory failures, reduce maintenance costs and reduce downtime. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] In order to more clearly illustrate the embodiments of the present invention, the following briefly introduces the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0042] Figure 1 A flow chart of a memory fault management method provided by the present invention;

[0043] Figure 2 A schematic diagram of a power supply provided by the present invention;

[0044] Figure 3 A schematic diagram of a memory fault management device provided by the present invention;

[0045] Figure 4 A schematic diagram of a non-volatile storage medium provided by the present invention. DETAILED DESCRIPTION

[0046] The core of the present invention is to provide a memory fault management method, device, medium and server, which allow the isolation and replacement of faulty memory while the server is running, improve the maintainability of the memory, reduce business interruptions caused by memory failures, reduce maintenance costs and reduce downtime.

[0047] In order to make the purpose, technical solution and advantages of the embodiments of the present invention clearer, the technical solution in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0048] In a first aspect, the present application provides a memory fault management method, which is applied to a processor in a server, wherein the server further includes a plurality of memories and a plurality of power supplies corresponding to the plurality of memories one by one, each memory being connected to a power supply through a power supply, and the memory fault management method includes:

[0049] S11: when receiving the fault warning information of the target memory, analyzing the fault warning information;

[0050] In this step, when the fault alarm information of the target memory is received, the fault information parsing process is first triggered to accurately identify the key data fields contained in the alarm information and their corresponding meanings. The fault alarm information may include, but is not limited to, a hardware monitoring module (such as an ECC check unit or a memory controller), and may include information such as the identifier of the target CPU to which the target memory belongs, the specific serial number of the target memory under the CPU, and the value of the register corresponding to the target memory. The first step of the analysis is to extract and separate these core fields from the received alarm information to ensure the integrity and identifiability of the data in each field. Subsequently, the extracted fields are semantically checked, such as checking whether the target CPU identifier belongs to the CPU range supported by the current server to ensure that the identifier is valid and matches the actual hardware configuration; checking whether the serial number of the target memory under the target CPU is within the legal range to avoid misoperation caused by the wrong number; checking whether the value of the register is equal to the preset fault identification value (such as the abnormal flag of a specific bit) to further confirm the authenticity of the memory fault.

[0051] Through the multi-level analysis and verification mechanism, false alarms caused by hardware noise or other interference factors can be effectively filtered out, ensuring the accuracy and reliability of the analysis results, and providing precise input basis for subsequent troubleshooting steps.

[0052] S12: determining whether the fault alarm information is valid according to the analysis result, and if the fault alarm information is valid, determining a target physical address and a target power supply corresponding to the target memory according to the fault alarm information;

[0053] In this step, the validity of the fault alarm information obtained from the analysis is further verified to ensure that subsequent processing is only for real and accurate memory faults, thereby avoiding misoperation. For example, a comparison is made with the server's memory address mapping table to confirm whether the target memory pointed to by the alarm exists and has been assigned to the current task or process. By checking the real-time status data of the memory (such as temperature, supply voltage, current fluctuations, or ECC error counts), it is evaluated whether there are abnormal phenomena consistent with the alarm description, and false alarms that may be caused by short-term interference or false alarms are eliminated. In addition, the processor will also combine the timestamp and system log of the alarm to analyze whether the fault is related to recent operations (such as frequent reading and writing or power fluctuations), thereby improving the credibility of the alarm.

[0054] If the fault warning information is confirmed to be valid, the processor further extracts the physical address of the target memory from the memory address mapping table, and searches for the connection information between the target memory and the power supply, thereby locating the target power supply corresponding to the memory.

[0055] This process ensures that subsequent isolation and power-off operations can be performed accurately on the target memory and related power supplies without affecting other normally functioning memory modules.

[0056] S13: Isolating the target memory according to the target physical address, and sending a power-off instruction to the target power supply to power off the target memory.

[0057] In this step, the target memory is isolated according to the target physical address, and a power-off command is sent to the target power supply to cut off the power. The principle is to ensure that the impact of the faulty memory is limited to the minimum scope through precise hardware control and system resource management.

[0058] Specifically, the processor uses the memory address mapping table and the control authority of the system bus to remove the physical address of the target memory from the system address space to prevent any process or task from further accessing the memory, thereby preventing the fault from spreading or data corruption from spreading to other modules. Next, the processor sends a power-off instruction to the target power supply, locates the target power supply and performs a shutdown operation to disconnect the power supply circuit related to the faulty memory to completely cut off the electrical connection and prevent current shock, overheating or other secondary faults caused by continuous power supply.

[0059] In addition, the power-off operation is strictly prioritized and checked to ensure that other normally running memory modules are not affected. At the same time, the triggering of the power-off signal is coordinated with the memory isolation step to avoid system abnormalities caused by power-off without isolation. During the entire process, detailed information on isolation and power-off is recorded and notified to the operation and maintenance management system to provide a basis for subsequent fault analysis and processing.

[0060] Based on the above embodiments:

[0061] As an optional embodiment, the fault warning information includes an identifier of a target central processor to which the target memory belongs, a serial number under the target central processor, and a value of a target register corresponding to the target memory, wherein the value in the target register is used to indicate whether a fault occurs in the target memory; upon receiving the fault warning information of the target memory, parsing the fault warning information, including: upon receiving the fault warning information of the target memory, parsing the identifier of the target central processor to which the target memory belongs, the serial number under the target central processor, and the value of the target register from the fault warning information; determining whether the fault warning information is valid according to the parsing result, including: determining the parsed target Whether the identifier of the target CPU is within the first preset range; whether the serial number of the target CPU in the target memory is within the second preset range; whether the value of the target register parsed is the preset value; if the identifier of the target CPU is within the first preset range, and the serial number of the target CPU in the target memory is within the second preset range, and the value of the target register is the preset value, then the fault alarm information is determined to be valid; if the identifier of the target CPU is outside the first preset range, or the serial number of the target CPU in the target memory is outside the second preset range, or the value of the target register is not the preset value, then the fault alarm information is determined to be invalid.

[0062] In this embodiment, by performing multi-level verification on key fields of the fault alarm information, the validity of the alarm information is accurately determined, thereby avoiding interference of false alarms on system operation.

[0063] Specifically, when a fault alarm message is received, the target central processing unit (CPU) to which the target memory belongs, the serial number of the target memory under the target CPU, and the value of the target register are first extracted. This information is the core data used to identify the memory module and characterize the fault status.

[0064] The resolved target CPU identifier is compared with the first preset range to ensure that the CPU pointed to by the alarm information belongs to the range of the processor cluster actually deployed in the system, thereby filtering out irrelevant or falsely reported processor identifiers.

[0065] At the same time, the serial number of the target memory is checked to ensure that it is within the valid address space of the target CPU (the second preset range), thereby verifying the legitimacy of the memory location and avoiding erroneous operations caused by address out-of-bounds or false data.

[0066] At the same time, the value of the target register is determined by comparing it with the preset value to determine whether the state recorded in the register indicates that the memory has indeed failed (such as ECC error exceeding the limit, temperature abnormality, etc.).

[0067] Only when the above three conditions are met at the same time, that is, the target CPU identifier is within the valid range, the memory serial number is legal, and the register value is as expected, the alarm information is considered valid, thereby initiating subsequent isolation and power-off operations; otherwise, the alarm information is considered invalid and discarded.

[0068] This multi-layer verification mechanism uses specific information at the hardware level, combined with the system's preset operating rules, to effectively improve the accuracy and reliability of alarm judgments, while avoiding incorrect isolation or power-off operations on non-faulty memory, ensuring the overall stability and security of the system.

[0069] As an optional embodiment, the fault warning information includes a value of a target register corresponding to the target memory, and the value in the target register is used to indicate whether the target memory fails; after determining the target physical address and the target power supply corresponding to the target memory according to the fault warning information, it also includes:

[0070] determining a register address of a target register corresponding to the target memory;

[0071] Isolate target memory based on target physical address, including:

[0072] The target physical address and the register address of the target register are written into the memory management register so that the basic input and output system isolates the target memory based on the information in the memory management register.

[0073] In this embodiment, the faulty memory is safely and efficiently isolated from the system through accurate positioning of register addresses and effective configuration of memory management registers combined with the isolation mechanism of the basic input and output system (BIOS).

[0074] Specifically, after determining the target physical address and target power supply corresponding to the target memory according to the fault alarm information, it is necessary to further obtain the register address of the target register associated with the target memory. This address is an important control entry for accessing and operating the target memory state. Then, in order to isolate the target memory, the processor will write the physical address of the target memory and the register address of the target register into the memory management register at the same time. This step plays the role of marking the faulty memory in the system hardware and BIOS. As a key component for the interaction between BIOS and hardware resources, the memory management register can pass the stored physical address and register address to the BIOS so that it can identify the specific faulty memory module. Based on this information, the BIOS updates the memory access policy, and by removing the target memory from the system's address space or marking it as unavailable, it prevents the processor, operating system or application from continuing to access the faulty memory area, thereby effectively avoiding system instability or data corruption caused by faulty memory.

[0075] This isolation mechanism based on the collaborative work of registers and memory management fully utilizes the capabilities of hardware resources and the underlying logic of the system, ensuring the accuracy and real-time nature of fault handling while providing a stable environment for subsequent system operations.

[0076] As an optional embodiment, the server further includes a plurality of fault indication devices corresponding to the plurality of memories one by one, each fault indication device is arranged on a memory slot of the memory corresponding to itself, and after determining the target physical address and the target power supply corresponding to the target memory according to the fault alarm information, further includes:

[0077] Determine the target memory slot where the target memory is located and the target memory fault type according to the fault alarm information;

[0078] After isolating the target memory according to the target physical address and sending a power-off instruction to the target power supply to power off the target memory, the method further includes:

[0079] Calling a preset corresponding relationship according to the fault type to determine the target state of the target fault indication device corresponding to the target memory; the preset corresponding relationship is a one-to-one correspondence between the fault type and the state of the fault indication device;

[0080] A control signal is sent to the target fault indicating device to update the state of the target fault indicating device to a target state.

[0081] In this embodiment, the fault information in the target memory is transmitted to the maintenance personnel in an intuitive physical form through the status update of the fault indication device, thereby achieving more efficient fault location and processing.

[0082] Specifically, after the fault alarm information is parsed, the physical slot where the target memory is located and its corresponding fault type will be further determined. This information is crucial for achieving accurate isolation and alarm status management. After isolating and powering off the target memory, the target state that the corresponding target fault indication device needs to display will be determined based on the parsed fault type and the one-to-one correspondence between the preset fault type and the state of the fault indication device. For example, different fault types such as memory overheating, data verification failure, or power supply abnormality may correspond to different states of the indication device, such as changes in light color (red, yellow, green) or changes in flashing frequency. Subsequently, the processor sends a control signal to the target fault indication device, triggering the state of the indication device to be updated to the target state, thereby intuitively displaying the specific fault information of the memory at the physical location of the memory slot.

[0083] In this way, maintenance personnel can quickly locate faulty memory and its cause without the need for additional complex diagnostic tools, improving maintenance efficiency and reducing system downtime. This dynamic update method combined with hardware indicator devices not only enhances the visualization and automation capabilities of fault management, but also further optimizes the system's maintenance experience and operational reliability.

[0084] As an optional embodiment, after isolating the target memory according to the target physical address and sending a power-off instruction to the target power supply to power off the target memory, the method further includes:

[0085] Load the backup memory and send a power-on command to the backup power supply corresponding to the backup memory, so that the backup power supply drives the internal charge pump inverter and negative linear regulator to start working, and when the negative voltage output by the negative linear regulator reaches a preset percentage of the set value, the backup power supply turns on the path between the power supply and the backup memory.

[0086] In this embodiment, by introducing a backup memory and a backup power supply, after a target memory fails and loses power, it is ensured that the system can seamlessly switch to the backup memory to ensure continuous operation of the system.

[0087] Specifically, after the target memory is isolated and powered off, the processor or system control unit will start the loading process of the backup memory. This process first activates the backup power supply by controlling the backup power supply and sending a power-on command to it. The backup power supply contains an internal charge pump inverter and a negative linear regulator. The charge pump inverter is responsible for converting the input voltage into the required stable voltage, and then generating a negative voltage supply through the negative linear regulator. The negative linear regulator ensures that the output value of the negative voltage gradually increases during the power supply process, and when the negative voltage output reaches the preset set value, the backup power supply will output power to the backup memory through its own output terminal, establishing a power supply path between the backup power supply and the backup memory.

[0088] This process ensures that the backup memory starts working only when the power supply is stable and the voltage reaches the required level, thus avoiding the problem that the backup memory cannot start normally due to unstable or insufficient voltage. Through this sophisticated power management and memory switching mechanism, the load can be smoothly switched to the backup memory after the target memory fails, ensuring that the system will not be interrupted or data lost, and improving the reliability and fault tolerance of the system.

[0089] like Figure 2As shown in the figure, the principle of the power supply is as follows: During the startup phase, the input voltage (Vin) of the power supply is connected to the input pin of the power supply, and the input voltage should be in the range of 2.5V to 5.5V. When the input voltage is stable and reaches the startup threshold of the power supply, the power supply starts to perform the internal initialization process. At this time, the internal charge pump inverter of the power supply starts to work and generates the required negative voltage output through the negative linear regulator. When the negative voltage output is stable and maintained within ±7.5% of the set value, the power supply's power normal (POK) output pin sends a signal and delivers current to the corresponding memory slot to start the memory and enable the server to start normally. Similarly, when loading the backup memory, a low-level signal is sent to the shutdown pin (SHDN) of the power supply of the faulty memory through an I2C command. When the SHDN pin receives a low-level signal, the power supply starts to perform the shutdown process. The charge pump inverter stops working, and the charge pump inverter inside the power supply will no longer generate a negative voltage output, and the output voltage gradually decreases. As the charge pump inverter stops, the output voltage (NEGOUT) of the power supply will gradually decrease to ensure that the GaAsFET power amplifier is not damaged during the shutdown process. When the output voltage drops to a safe level (close to 0V), the power supply will completely disconnect from the GaAsFET power amplifier. At this point, after confirming that the output voltage has been completely disconnected, the input voltage (Vin) can be safely disconnected. The power-off operation of the faulty memory is completed, and the operation and maintenance personnel can replace the equipment.

[0090] As an optional embodiment, the fault alarm information includes a value of a register corresponding to the memory, and the value in the register is used to indicate whether the memory fails; after the backup power supply conducts the path between the power supply and the backup memory, it also includes:

[0091] Performing a hardware self-test on the backup memory, the hardware self-test at least including the detection of the physical connection status between the backup memory and the corresponding central processing unit, the detection of the data transmission rate of the backup memory, and the detection of the error rate of the backup memory;

[0092] When the detection result of the hardware self-test meets the preset requirement, the value of the register corresponding to the backup memory is reset to a second value, and the basic input and output system is triggered to load the backup memory. The second value indicates that the memory is not faulty.

[0093] In this embodiment, the backup memory is ensured to pass a series of hardware self-checking programs to verify its health status before being put into use, and after confirming that the backup memory is normal, it is officially connected to the system.

[0094] Specifically, after the backup power supply is successfully turned on and provides stable power to the backup memory, the system will perform a series of hardware self-test operations on the backup memory. The hardware self-test first checks the physical connection status between the backup memory and the central processing unit (CPU) to ensure that there is no signal loss or transmission interruption due to hardware failure or loose connection. Next, the data transmission rate of the backup memory is tested to verify whether the data transmission capacity between the memory and the CPU meets the performance requirements of the system to avoid affecting the overall operation efficiency of the system due to too slow transmission speed. Finally, the error rate of the backup memory is also tested to ensure that the read and write operations of the memory will not cause data errors or loss. These tests are performed according to preset standards to ensure that the working status of the backup memory reaches a normal level.

[0095] Once the result of the hardware self-test meets the preset standard, that is, the backup memory has been fully tested and is operating normally, the value in the register corresponding to the backup memory will be reset to a second value, which indicates that the memory is not faulty. At this time, the basic input and output system (BIOS) is triggered to load the backup memory, connect it to the system and replace the faulty target memory, ensuring that the system can continue to operate and will not be affected by the faulty memory.

[0096] Through this verification process, the reliability and stability of the backup memory can be effectively guaranteed, while avoiding the erroneous enabling of unqualified backup memory in the event of a failure, thereby further improving the fault tolerance and stability of the system.

[0097] As an optional embodiment, the server further includes a plurality of fault recording modules corresponding to the plurality of memories, each fault recording module being used to record the operation status and fault information of the memory; after triggering the basic input and output system to load the backup memory, it further includes:

[0098] Update the fault recording module corresponding to the target memory according to the fault alarm information, record the time when the target memory fault occurs, the fault type, the target physical address and the loading status of the backup memory;

[0099] Generate log information including the fault handling process of the target memory according to the updated fault record data in the fault record module, and send the fault prompt through the management console or the remote interface.

[0100] In this embodiment, the fault recording module is used to systematically record and track memory fault events, and detailed fault handling log information is generated to provide a transparent and traceable fault management process.

[0101] Specifically, after the basic input and output system (BIOS) is triggered to load the backup memory, the fault recording module associated with the target memory is updated according to the received fault alarm information. The fault recording module is responsible for recording various information about the target memory fault, including the specific time of the fault, the fault type (such as read and write errors, timeouts, etc.), the physical address of the target memory, and the status of the backup memory loading (such as whether the backup memory is successfully loaded, whether it has passed the self-test, etc.). This information helps administrators understand the detailed background of the fault and provides valuable data support for subsequent fault analysis and processing.

[0102] At the same time, according to the updated fault record data, log information including the target memory fault handling process will be generated. This log information not only records the time and type of fault, but also describes the specific fault handling measures taken by the system, such as memory isolation, backup memory loading and hardware self-test. The generation of log information not only facilitates the analysis and tracking of faults in the future, but also provides clues for system maintenance personnel to diagnose and repair faults.

[0103] Finally, fault notifications are sent through the management console or remote interface to ensure that system administrators can obtain fault information in a timely manner. This notification usually includes the fault type, affected memory, spare memory loading status and other relevant data, which helps administrators respond quickly and perform effective maintenance operations.

[0104] Through such fault recording and log management, the system realizes comprehensive monitoring, recording and transparent management of memory faults, further improving fault handling efficiency and system reliability.

[0105] As a preferred embodiment, after the backup power supply outputs power to the backup memory and performs a hardware self-test on the backup memory, it also includes: after the backup memory passes the hardware self-test and is loaded, dynamically migrating high-priority tasks associated with the target memory to the backup memory according to task priority and memory load; after completing the migration of high-priority tasks, reallocating low-priority tasks to the remaining valid memory according to a preset task migration strategy to balance the utilization of memory resources; after completing the migration of all tasks, updating the memory allocation table in the task scheduler, and sending a memory status update notification to the operating system to ensure that the system can schedule tasks based on the latest memory status.

[0106] In this embodiment, after the backup memory is loaded and verified to be normal through hardware self-test, tasks are intelligently and dynamically migrated according to the priority of the task and the current memory load to maximize resource utilization and ensure stable operation of the system. When the backup memory passes the hardware self-test and is successfully loaded, the system will first identify the high-priority tasks associated with the target memory according to the priority of the task. Since the backup memory is ready, the system will migrate these high-priority tasks to the backup memory to ensure that these tasks are processed in a timely manner and will not be affected by the failure of the target memory.

[0107] After the high-priority task migration is completed, the low-priority tasks are reasonably reallocated according to the preset task migration strategy. Low-priority tasks usually do not need to be executed immediately, so they are migrated to the remaining valid memory to free up spare memory space for more important tasks. This process ensures that memory resources are evenly distributed, avoids memory overload or idleness, and improves the utilization efficiency of system resources.

[0108] Once all tasks have completed migration, the memory allocation table in the task scheduler is updated. This memory allocation table records the current relationship between each task and memory, including the target memory location after the task is migrated. The updated memory allocation table will be passed to the operating system so that the operating system can schedule tasks based on the latest memory status. After receiving the memory status update notification, the operating system will re-evaluate the availability of memory resources and adjust the task scheduling strategy accordingly to ensure that the system can still run efficiently after the memory load changes.

[0109] This dynamic task migration and memory management strategy enhances the flexibility and reliability of the system in the event of memory failure or load fluctuation, improving the timeliness of task processing and the overall performance of the system.

[0110] Second, as Figure 3 As shown, the present application provides a memory fault management device, comprising:

[0111] A memory 31, used for storing computer programs;

[0112] The processor 32 is used to implement the steps of the above-mentioned memory fault management method when executing the computer program. For other introductions of the memory fault management device, please refer to the above-mentioned embodiments, and this application will not repeat them here.

[0113] Thirdly, Figure 4As shown, the present application provides a non-volatile storage medium 41, on which a computer program 42 is stored, and when the computer program 42 is executed by a processor, the steps of the memory fault management method described above are implemented. For other introductions to the non-volatile storage medium 41, please refer to the above embodiments, and the present application will not repeat them here.

[0114] In a fourth aspect, the present application provides a server, including the memory fault management device as described above, and also including a plurality of memories and a plurality of power supplies corresponding to the plurality of memories, each memory being connected to a power supply through a power supply, and the memory fault management device being connected to each memory and each power supply respectively. For other introductions to the server, please refer to the above embodiments, and the present application will not repeat them here.

[0115] In a fifth aspect, the present application provides a computer program product, including a computer program / instruction, which implements the steps of the memory fault management method as described above when the computer program / instruction is executed by a processor. For other introductions to the computer program product, please refer to the above embodiments, and the present application will not repeat them here.

[0116] It should also be noted that, in this specification, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "comprises", "comprising" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the statement "comprising a ..." does not exclude the presence of other identical elements in the process, method, article or device including the element.

[0117] The above description of the disclosed embodiments enables those skilled in the art to implement or use the present invention. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention will not be limited to the embodiments shown herein, but rather to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A memory fault management method, characterized in that: A processor applied to a server, the server further comprising a plurality of memories and a plurality of power supplies corresponding to the plurality of memories one by one, each of the memories being connected to a power supply via the power supply, the memory fault management method comprising: When receiving the fault warning information of the target memory, parsing the fault warning information; Determine whether the fault warning information is valid according to the analysis result, and if the fault warning information is valid, determine the target physical address and the target power supply corresponding to the target memory according to the fault warning information; The target memory is isolated according to the target physical address, and a power-off instruction is sent to the target power supply to power off the target memory.

2. The memory fault management method according to claim 1, characterized in that: The fault alarm information includes an identifier of a target CPU to which the target memory belongs, a serial number under the target CPU, and a value of a target register corresponding to the target memory, wherein the value in the target register is used to indicate whether a fault occurs to the target memory; When the fault warning information of the target memory is received, the fault warning information is parsed, including: When receiving the fault warning information of the target memory, parsing the identifier of the target central processor to which the target memory belongs, the serial number under the target central processor and the value of the target register from the fault warning information; Determining whether the fault warning information is valid according to the analysis result includes: Determining whether the resolved identifier of the target CPU is within a first preset range; Determine whether the sequence number of the target CPU in the target memory is within a second preset range; Determining whether the parsed value of the target register is a preset value; If the identifier of the target CPU is within the first preset range, and the serial number of the target CPU in the target memory is within the second preset range, and the value of the target register is the preset value, then it is determined that the fault warning information is valid; If the identifier of the target CPU is outside the first preset range, or the serial number of the target CPU in the target memory is outside the second preset range, or the value of the target register is not the preset value, it is determined that the fault alarm information is invalid.

3. The memory fault management method according to claim 1, characterized in that: The fault warning information includes a value of a target register corresponding to the target memory, and the value in the target register is used to indicate whether the target memory fails; after determining a target physical address and a target power supply corresponding to the target memory according to the fault warning information, the method further includes: determining a register address of a target register corresponding to the target memory; Isolating the target memory according to the target physical address includes: The target physical address and the register address of the target register are written into a memory management register, so that a basic input and output system isolates the target memory based on information in the memory management register.

4. The memory fault management method according to claim 1, characterized in that: The server further includes a plurality of fault indication devices corresponding to the plurality of memories one by one, each of the fault indication devices being arranged on a memory slot of the memory corresponding to itself, and after determining a target physical address and a target power supply corresponding to the target memory according to the fault alarm information, further including: Determine the target memory slot where the target memory is located and the fault type of the target memory according to the fault alarm information; After isolating the target memory according to the target physical address and sending a power-off instruction to the target power supply to power off the target memory, the method further includes: Calling a preset correspondence relationship according to the fault type to determine a target state of a target fault indication device corresponding to the target memory; the preset correspondence relationship is a one-to-one correspondence between a fault type and a state of a fault indication device; A control signal is sent to the target fault indication device to update the state of the target fault indication device to the target state.

5. The memory fault management method according to any one of claims 1 to 4, characterized in that: After isolating the target memory according to the target physical address and sending a power-off instruction to the target power supply to power off the target memory, the method further includes: Load the backup memory, and send a power-on instruction to the backup power supply corresponding to the backup memory, so that the backup power supply drives the internal charge pump inverter and negative linear regulator to start working, and when the negative voltage output by the negative linear regulator reaches a preset percentage of the set value, the backup power supply turns on the path between the power supply and the backup memory.

6. The memory fault management method according to claim 5, characterized in that: The fault alarm information includes a value of a register corresponding to the memory, and the value in the register is used to indicate whether the memory fails; After the backup power supply conducts the path between the power supply and the backup memory, the backup power supply further includes: Performing a hardware self-test on the backup memory, the hardware self-test at least comprising detecting a physical connection state between the backup memory and a corresponding central processing unit, detecting a data transmission rate of the backup memory, and detecting an error rate of the backup memory; When the detection result of the hardware self-test meets the preset requirement, the value of the register corresponding to the backup memory is reset to a second value, and the basic input and output system is triggered to load the backup memory, and the second value indicates that the memory is not faulty.

7. The memory fault management method according to claim 6, characterized in that: The server further includes a plurality of fault recording modules corresponding to the plurality of memories one by one, each of the fault recording modules being used to record the operating status and fault information of the memory; After triggering the basic input and output system to load the backup memory, the method further includes: updating a fault recording module corresponding to the target memory according to the fault alarm information, recording the time when the target memory fault occurs, the fault type, the target physical address, and the loading status of the backup memory; Log information including the fault handling process of the target memory is generated according to the updated fault record data in the fault record module, and a fault prompt is sent through a management console or a remote interface.

8. A memory fault management device, characterized in that: include: Memory for storing computer programs; A processor, used to implement the steps of the memory fault management method as described in any one of claims 1 to 7 when executing a computer program.

9. A non-volatile storage medium, characterized in that: The non-volatile storage medium stores a computer program, and when the computer program is executed by the processor, the steps of the memory fault management method according to any one of claims 1 to 7 are implemented.

10. A server, characterized in that: It includes the memory fault management device as described in claim 8, and also includes multiple memories and multiple power supplies corresponding to the multiple memories one by one, each of the memories is connected to the power supply through the power supply, and the memory fault management device is respectively connected to each of the memories and each of the power supplies.

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