ATPG test vector debugging method, electronic equipment and storage medium

Abstract

The invention relates to the field of chips, in particular to an ATPG test vector debugging method, electronic equipment and a storage medium, ATPG analyzes and loads a first-class simulation database generated by a verilog simulator, the ATPG performs simulation according to a test vector to generate a second-class simulation database, and the first-class simulation database and the second-class simulation database are connected with the first-class simulation database and the second-class simulation database. Obtaining an unmatched test vector set, an instance corresponding to each unmatched test vector and an unmatched output pin, wherein the test vector in the unmatched test vector set is a test vector which observes that a first type of output response data signal output by the output pin of the chip model is not matched with an expected response in the test vector; and when the user specifies the test vector in the unmatched test vector set as the target test vector, the unmatched source of the target test vector is obtained, and the traceability efficiency is high.

Description

Technical Field

[0001] The present invention relates to the field of chips, and in particular to an ATPG test vector debugging method, electronic equipment and storage medium. Background Art

[0002] Automatic Test Pattern Generation (ATPG) is a method for generating test vectors that can detect digital circuit faults. The test of a chip is to apply a certain input stimulus to a chip under test in a known state, and compare the output response obtained with the "ideal" expected response, and judge whether the DUT has a fault based on whether the comparison results are consistent. The input stimulus applied to the chip under test and the "ideal" expected response constitute a test vector, which is automatically generated by the ATPG algorithm program. However, if the test vector generated by ATPG does not meet expectations, the real fault in the DUT cannot be tested, and the test vector cannot be used to test the DUT.

[0003] In order to verify the correctness of the test vector, a Verilog simulation tool is usually used for verification. The stimulus in the test vector is applied to the chip model for simulation, and the output result is recalculated based on the input stimulus. The output result obtained by the Verilog simulation tool is compared with the "ideal" expected response in the test vector. If the comparison results are consistent, the test vector generated by ATPG is considered correct; otherwise, the test vector generated by ATPG is incorrect, which is also called test vector mismatch.

[0004] Usually, the debugger in the Verilog simulation tool is used to debug and find the root cause of the test vector mismatch. However, the main disadvantage of Verilog is that it only has waveform data signals from the Verilog simulation database, that is, it only has a Verilog simulation view, but no ATPG simulation view. Users need to open the Verilog simulation view and the ATPG simulation view through two different tools respectively. When tracing through each tool, they need to manually add the selected signal to the waveform viewer to view its value, and find the source of the mismatch by comparing the values ​​in the waveform viewers of the two tools. For hundreds of millions of modern large-scale designs, this method is very difficult. Not only is the operation complicated, but it is also prone to errors and has low traceability efficiency. Therefore, how to efficiently debug and trace the mismatched test vectors has become a technical problem that needs to be solved urgently. Summary of the invention

[0005] In view of the above technical problems, the technical solution adopted by the present invention is:

[0006] In a first aspect, an embodiment of the present invention provides a debugging method for ATPG test vector mismatch, the method comprising the following steps:

[0007] S100, ATPG parses and loads the first type of simulation database generated by the Verilog simulator, wherein the first type of simulation database stores the first type of simulation data signals obtained by simulating the input of the chip model by applying stimulus according to the test vector, wherein the first type of simulation data signals includes the test vector and the first type of output response data signal; the test vector includes stimulus and expected response.

[0008] S200, ATPG generates a second type of simulation database by simulation according to the test vector, wherein the second type of simulation database stores a second type of simulation data signal, wherein the second type of simulation data signal includes the test vector and a second type of output response data signal output by an output pin.

[0009] S300, obtain a set of unmatched test vectors and the instances and unmatched output pins corresponding to each unmatched test vector, wherein the test vectors in the unmatched test vector set are test vectors in which the first type of output response data signal output by the output pin of the chip model is observed to be mismatched with the expected response in the test vector.

[0010] S400, when the user specifies a test vector in the unmatched test vector set as a target test vector, obtaining a source of the unmatched target test vector includes:

[0011] S410 , adding an instance of the test vector in which a mismatch is observed, and taking the added instance of the test vector in which a mismatch is observed as a target instance.

[0012] S420, extracting first-type simulation data signals of all pins of all instances from a first-type simulation database.

[0013] S430, extracting second-type simulation data signals of all pins in all instances from the second-type simulation database.

[0014] S440, when the first type of simulation data signal and the second type of simulation data signal of the same pin are compared to obtain the same result, a data signal is displayed on the corresponding pin in the example circuit diagram of the visualization window; otherwise, two types of unmatched data signals are displayed according to the specified display format.

[0015] S450, tracing back according to the unmatched output pins of the target instance to obtain the unmatched source.

[0016] The present invention has at least the following beneficial effects:

[0017] The method provided by the present invention can combine Verilog simulation data signals and ATPG simulation data signals into one tool, and display the two types of simulation signals in the same visualization window. The mismatch between the two types of simulation signals can be displayed in the visualization window according to the specified format, and the root instance of the mismatch can be found by tracing the highlighted signal path. The method significantly improves the traceability efficiency and realizes efficient positioning. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0019] Figure 1 A flowchart of a debugging method for ATPG test vector mismatch provided by an embodiment of the present invention;

[0020] Figure 2 The present invention is a schematic diagram of realizing circuit display in a visualization window by using the method provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0021] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present invention.

[0022] See also Figure 1 , which shows a flow chart of a debugging method for ATPG test vector mismatch, the method comprising the following steps:

[0023] S100, ATPG parses and loads the first type of simulation database generated by the Verilog simulator, wherein the first type of simulation database stores the first type of simulation data signals obtained by simulating the input of the chip model by applying stimulus according to the test vector, wherein the first type of simulation data signals includes the test vector and the first type of output response data signal; the test vector includes stimulus and expected response.

[0024] Among them, the stimulus in the test vector is the input signal applied to the input pin of the chip model, the expected response is the ideal output signal generated according to the ATPG algorithm, and the first type of output response data signal is the output signal actually generated after the stimulus is applied and observed at the output pin of the chip model. The test vector is automatically generated according to the ATPG algorithm. After the stimulus of the test vector is applied to the chip model, the chip model generates an actual output response signal. By comparing the output response signal with the expected response signal, it is possible to detect whether the chip is faulty, so that the output response signals of the faulty circuit module and the correct circuit module are different. Among them, the ATPG algorithm generates corresponding test vectors according to various fault models. However, if there is a problem with the test vector itself, it is impossible to correctly verify whether the chip is faulty. Therefore, before the test vector is used for chip verification, it is necessary to verify the correctness of the test vector through simulation.

[0025] Among them, the Verilog simulator is used to verify the correctness of the test vector. The first type of simulation database generated by the Verilog simulator also includes the input signals of the input pins and the data signals on each port inside the chip model. It should be noted that since the data signals on the input pins and output pins of the chip model correspond to the stimulus and expected response in the test vector respectively, the data signals on each port inside the chip model have no corresponding stimulus and response in the test vector.

[0026] Among them, ATPG parses the data in the first type simulation database into simulation data signals that can be recognized by ATPG. The methods in the prior art that can parse the first type simulation database generated by Verilog simulation into simulation data signals that can be recognized by ATPG all fall within the protection scope of the present invention.

[0027] It should be noted that, for ease of understanding, the first category and the second category in the present invention are only used to distinguish between Verilog simulation data signals and ATPG simulation data signals, and do not represent the importance or order of data signals.

[0028] S200, ATPG generates a second type of simulation database by simulation according to the test vector, wherein the second type of simulation database stores a second type of simulation data signal, wherein the second type of simulation data signal includes the test vector and a second type of output response data signal output by an output pin.

[0029] It should be noted that ATPG can not only generate test vectors, but also perform simulation debugging based on the test vectors to verify the correctness of the test vectors. The data signals generated by simulation are stored in the memory, that is, the second type of simulation database refers to the memory that stores the simulation data signals.

[0030] The second type of simulation data signals also include input signals of chip model input pins and data signals on various ports inside the chip model.

[0031] Among them, the test vectors simulated in ATPG are the same as the test vectors simulated in Verilog in S100.

[0032] S300, obtain a set of unmatched test vectors and the instances and unmatched output pins corresponding to each unmatched test vector, wherein the test vectors in the unmatched test vector set are test vectors in which the first type of output response data signal output by the output pin of the chip model is observed to be mismatched with the expected response in the test vector.

[0033] Optionally, the unmatched test vectors, the instances corresponding to the unmatched test vectors, and the unmatched output pins are generated by a Verilog simulator, or are generated after ATPG parses the first type of simulation database.

[0034] Preferably, the unmatched test vectors, the instances corresponding to the unmatched test vectors and the unmatched output pins are generated by a Verilog simulator.

[0035] It should be noted that the mismatch test vector is obtained based on the mismatch between the first type of output response data signal output by the output pin and the expected response in the test vector, and does not include the data signals of each port inside the chip model, nor does it include the second type of output response data signal. Among them, mismatch means inequality.

[0036] The instance is a device obtained after instantiation of a standard cell library, such as an AND gate circuit model, a buffer, etc.

[0037] S400, when a user specifies a test vector in a mismatched test vector set as a target test vector, a source of mismatch of the target test vector is obtained.

[0038] Among them, S400 includes:

[0039] S410 , adding an instance of the test vector in which a mismatch is observed, and taking the added instance of the test vector in which a mismatch is observed as a target instance.

[0040] It should be noted that the correspondence between the unmatched target test vector and the instance has been obtained in S300, so when the user specifies the unmatched test vector, the corresponding instance can be obtained. In order to find the root cause of the unmatched test vector, it is necessary to trace back, so the instance of the unmatched test vector is added to ATPG. Adding the instance to ATPG can display all unmatched data signals in the entire chip model in the specified format in the visualization window, and the implementation process is as shown in S420-S440.

[0041] S420, extracting first-type simulation data signals of all pins of all instances from a first-type simulation database.

[0042] It should be noted that the chip model includes a large number of instances, each of which has input and output pins, and the Verilog simulator can monitor the data signal on each input and output pin.

[0043] S430, extracting second-type simulation data signals of all pins in all instances from the second-type simulation database.

[0044] S440, when the first type of simulation data signal and the second type of simulation data signal of the same pin are compared to obtain the same result, a data signal is displayed on the corresponding pin in the example circuit diagram of the visualization window; otherwise, two types of unmatched data signals are displayed according to the specified display format.

[0045] As a preferred embodiment, when comparing the first type of simulation data signal and the second type of simulation data signal of the same pin, the compared data signals include the input signal of the input pin of the chip model, the output signal of the output pin and the data signals of each port inside the chip model.

[0046] It should be noted that if there is a match, one data signal is displayed, and if there is no match, they are displayed in a specified format and different data signals are displayed for easy viewing.

[0047] Optionally, the specified display format is a red font, a highlighted background color or a bold highlighted font. Other specified formats in the prior art for distinguishing between matching and unmatching data formats all fall within the protection scope of the present invention.

[0048] S450, tracing back to obtain the mismatched source according to the unmatched output pin of the target instance. The unmatched source is an instance where all input signals are matched. It should be noted that the purpose of debugging is to find the mismatched source.

[0049] The method provided by the present invention can combine Verilog simulation data signals and ATPG simulation data signals into one tool, and display the two types of simulation signals in the same visualization window. The mismatch between the two types of simulation signals can be displayed in the visualization window according to the specified format, and the root instance of the mismatch can be found by tracing the highlighted signal path. The method significantly improves the traceability efficiency and realizes efficient positioning.

[0050] As a preferred embodiment, S450 further includes:

[0051] S451, by double-clicking the input pin with two types of mismatched data signals in the instance, trace back to obtain the driver instance connected to the input pin, and the mismatched input pin of the driver instance is displayed in a specified format; double-click the mismatched input pin in the driver instance again, and so on, until a root instance with all input signals matching is obtained, and the root instance is the source of the mismatch. This method can clearly display all mismatched instances and their pins, and the user can trace the source by double-clicking the mismatched input pin, which can achieve rapid tracing. Compared with the method of cross-comparison of two software in the prior art, it is more convenient and faster, with high tracing efficiency and less prone to errors.

[0052] See also Figure 2 , which shows the circuit displayed in the visualization window, in which a part of the circuit structure is omitted. In the circuit, instance C4 is an instance of the added unmatched test vector. Two types of values ​​of all unmatched pins are displayed and highlighted in the visualization window, one of which is a first type of simulation data signal generated by the Verilog simulator, and the other signal value is a second type of simulation data signal generated by ATPG simulation. In C4, two types of values ​​S100 / S110 of the input pins and two types of values ​​S111 / S101 of the output pins are highlighted. By tracing back through S451, when tracing back to instance C3, when double-clicking the first highlighted input S011 / S111 of C3, the driver instance of C3 is C1, and all inputs of C1 are matched, and there are no unmatched input pins. At this time, C1 is obtained as the source of the mismatch.

[0053] As a preferred embodiment, S451 is a step of manual tracing by a user. In order to improve the efficiency of tracing, the embodiment of the present invention also provides an automatic tracing step. S450 also includes the following steps:

[0054] S452, add all observed unmatched test vector instances to a queue, and pop out the first instance in the queue as a tracking instance. Pop out the instances in the queue in order, and process each unmatched test vector instance in the queue to obtain the source of each unmatched test vector.

[0055] S453, executing steps S410-S440 for the tracking instance, when the first type of simulation data signal and the second type of simulation data signal of the input pin of the tracking instance are different, if the driver instance of the tracking instance is not in the unmatched tracking list, the driver instance is put into the queue.

[0056] The tracking list stores all driver instances on the traceback path when the tracking instance is traced back. It should be noted that the driver instance is the instance connected to the input pin of the current instance.

[0057] Among them, S453 also includes:

[0058] S4531, mark the instance added to the queue as a tracked instance and add it to the unmatched tracking list.

[0059] S4532, if the i-th driver instance is tracked i If all input first-type simulation data signals and second-type simulation data signals are the same and one output data signal is different, then instance i Mark as a mismatch source and add it to the mismatch source list.

[0060] S454, repeat steps S450-S451 until the queue is empty.

[0061] S455, marking all instances in the mismatch source list in the visualization window.

[0062] According to the steps provided in S452-455, automatic tracing can be achieved to obtain the source instances of all instances that do not match the test vectors, thereby improving the efficiency of tracing.

[0063] As a preferred embodiment, based on steps S452-455, the paths between all instances in the unmatched tracking list are marked in the visualization window, so that each unmatched path can be visualized for the user to view.

[0064] An embodiment of the present invention also provides a non-transitory computer-readable storage medium, which can be set in an electronic device to store at least one instruction or at least one program related to implementing a method in a method embodiment. The at least one instruction or the at least one program is loaded and executed by the processor to implement the method provided in the above embodiment.

[0065] An embodiment of the present invention further provides an electronic device, comprising a processor and the aforementioned non-transitory computer-readable storage medium.

[0066] An embodiment of the present invention further provides a computer program product, which includes program code. When the program product is run on an electronic device, the program code is used to enable the electronic device to execute the steps of the method according to various exemplary embodiments of the present invention described above in this specification.

[0067] Although some specific embodiments of the present invention have been described in detail by way of example, it will be appreciated by those skilled in the art that the above examples are for illustration only and are not intended to limit the scope of the present invention. It will also be appreciated by those skilled in the art that various modifications may be made to the embodiments without departing from the scope and spirit of the present invention. The scope of the present invention is defined by the appended claims.

Claims

1. A debugging method for ATPG test vector mismatch, characterized in that: The method comprises the following steps: S100, ATPG parses and loads a first type of simulation database generated by a Verilog simulator, wherein the first type of simulation database stores a first type of simulation data signal obtained by simulating the input of a chip model by applying stimulus to the input of the chip model according to a test vector, wherein the first type of simulation data signal includes a test vector and a first type of output response data signal; the test vector includes a stimulus and an expected response; S200, ATPG generates a second type of simulation database by simulation according to the test vector, wherein the second type of simulation database stores a second type of simulation data signal, wherein the second type of simulation data signal includes the test vector and a second type of output response data signal output by an output pin; S300, obtaining an unmatched test vector set and an instance and an unmatched output pin corresponding to each unmatched test vector, wherein the test vectors in the unmatched test vector set are test vectors in which a first type of output response data signal output by an output pin of a chip model is observed to be mismatched with an expected response in the test vector; S400, when the user specifies a test vector in the unmatched test vector set as a target test vector, obtaining a source of the unmatched target test vector includes: S410, adding an instance of the observed mismatched test vector, and using the added instance of the mismatched test vector as a target instance; S420, extracting first-type simulation data signals of all pins of all instances from the first-type simulation database; S430, extracting second-type simulation data signals of all pins in all instances from the second-type simulation database; S440, when the first type of simulation data signal and the second type of simulation data signal of the same pin are compared to obtain the same result, display a data signal on the corresponding pin in the example circuit diagram of the visualization window; otherwise, display the two types of unmatched data signals according to the specified display format; S450, tracing back according to the unmatched output pins of the target instance to obtain the unmatched source.

2. The method according to claim 1, characterized in that The S450 also includes: S451, double-click the input pin with two types of unmatched data signals in the instance to trace back to obtain the driver instance connected to the input pin, and the unmatched input pin of the driver instance is displayed in a specified format; double-click the unmatched input pin in the driver instance again, and so on, until a root instance in which all input signals are matched is obtained, and the root instance is the source of the mismatch.

3. The method according to claim 1, characterized in that The S450 also includes: S452, adding all observed instances of unmatched test vectors to a queue, and popping out the first instance in the queue as a tracking instance; S453, executing steps S410-S440 for the tracking instance, when the first type of simulation data signal and the second type of simulation data signal of the input pin of the tracking instance are different, if the driver instance of the tracking instance is not in the unmatched tracking list, then putting the driver instance into a queue, including: S4531, mark the instance added to the queue as a tracked instance and add it to the unmatched tracking list; S4532, if the i-th instance instance i If all input first-type simulation data signals and second-type simulation data signals are the same and one output data signal is different, then instance i Mark as mismatch source and add to the mismatch source list; S454, repeat steps S450-S451 until the queue is empty; S455, marking all instances in the mismatch source list in the visualization window.

4. The method according to claim 3, characterized in that Marks paths between all instances in the trace list that do not match in the visualization window.

5. The method according to claim 1, characterized in that The first type of simulation database also includes input signals of input pins and data signals on various ports inside the chip model; The second type of simulation data signals also includes input signals of chip model input pins and data signals on various ports inside the chip model; In S440, when comparing the first type of simulation data signal and the second type of simulation data signal of the same pin, the compared data signals include input signals of input pins of the chip model, output signals of output pins, and data signals of various ports inside the chip model.

6. The method according to claim 1, characterized in that The unmatched test vectors, the instances corresponding to the unmatched test vectors and the unmatched output pins in S300 are generated by the Verilog simulator.

7. The method according to claim 1, characterized in that The source of mismatch in S450 is the instance where all input signals are matched.

8. The method according to claim 1, characterized in that The display format specified in S440 is red font, highlighted background color or bold highlighted font.

9. A non-transitory computer-readable storage medium, wherein at least one instruction or at least one program is stored in the storage medium, and the at least one instruction or the at least one program is loaded and executed by a processor to implement the method as claimed in any one of claims 1 to 8.

10. An electronic device, characterized in that: The invention comprises a processor and the non-transitory computer-readable storage medium as claimed in claim 9.

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