A memory system

Abstract

The present invention relates to the field of computer technologies, and particularly relates to a memory system. Among them, a memory controller and a physical layer are interconnected through a memory physical interface; the memory controller sends a controller handshake request to the physical layer through a message interface every first preset number of cycles, and the memory controller implements data reading and writing operations through an interface for implementing data reading and writing; the physical layer obtains delay chain calibration data once every second preset number of cycles. When receiving the controller handshake request, it determines whether the change in the delay chain caused by the current temperature and voltage drift exceeds a preset delay chain change threshold. If it exceeds, it returns an acknowledgement signal to the memory controller through the message interface; after receiving the acknowledgement signal, the memory controller controls to start the physical layer to calibrate the delay chain based on the current delay chain calibration data. During the process of calibrating the delay chain, the operation of the interface for implementing data reading and writing is paused. The present invention improves the access efficiency of the memory.

Description

Technical Field

[0001] The present invention relates to the field of computer technology, and in particular, to a memory system. Background Art

[0002] The access efficiency of memory is a key indicator affecting the performance of the memory system. In common methods, scheduling strategies are mostly adopted to reduce the extra overhead between commands, such as the operation overhead of closing the current row and opening a new row caused by command line breaks, and an interleaving mechanism is adopted to increase the opportunity of overlap operations, so as to shorten the command interval as much as possible. However, during the operation of the memory system, due to temperature and voltage changes, certain drifts will occur. The memory system must calibrate these drifts in a timely manner, and these calibration operations will inevitably affect normal read and write accesses, and often become an unignorable impact on the access efficiency of the memory.

[0003] In traditional methods, the memory controller generally sends calibration update requests at fixed intervals. However, if the requests are sent too frequently, and the drifts caused by temperature and voltage changes are still within the safe range and there is no need to update, then although the memory controller sending update requests frequently will avoid read and write conflicts as much as possible, it will still inevitably affect the normal read and write bandwidth. If the memory controller does not send update requests to save bandwidth, then when the drifts caused by temperature and voltage exceed the safe range, it will cause the physical layer (PHY) connecting the memory controller and the storage unit to initiate a forced update request. This forced update must be responded to as soon as possible and takes longer, which will have a greater impact on the access efficiency. It can be seen that how to improve the access efficiency of the memory while reducing the impact on the normal read and write bandwidth and ensuring timely updates at necessary moments has become a technical problem to be solved urgently. Summary of the Invention

[0004] The object of the present invention is to provide a memory system, which improves the access efficiency of the memory while reducing the impact on the normal read and write bandwidth and ensuring timely updates at necessary moments.

[0005] According to a first aspect of the present invention, there is provided a memory system, including a memory controller, a physical layer, and a storage unit. The memory controller is connected to the storage unit through the physical layer, and the memory controller performs read and write data operations on the storage unit through the physical layer;

[0006] The memory controller and the physical layer are interconnected through a memory physical interface, and the memory physical interface includes a message interface and an interface for implementing read and write data;

[0007] The memory controller is used to send a controller handshake request to the physical layer through the message interface every first preset number of cycles. The memory controller implements data read and write operations through an interface for implementing data read and write. The message interface is independent of the interface for implementing data read and write.

[0008] The physical layer obtains delay chain calibration data once every second preset number of cycles. When receiving a controller handshake request, it determines whether the change in the delay chain caused by the current temperature and voltage drift exceeds a preset delay chain change threshold. If it exceeds, it returns an acknowledgment signal to the memory controller through the message interface.

[0009] The memory controller is further used to control the physical layer to calibrate the delay chain based on the current delay chain calibration data after receiving the acknowledgment signal. During the process of calibrating the delay chain, the operation of the interface for implementing data read and write is paused.

[0010] Compared with the prior art, the present invention has obvious advantages and beneficial effects. By means of the above technical solution, a memory system provided by the present invention can achieve considerable technical progressiveness and practicality, and has wide industrial utilization value. It has at least the following beneficial effects:

[0011] The present invention sends a handshake signal between the memory controller and the physical layer through the message interface. Only when the temperature and voltage drift exceeds the preset delay chain change threshold, the update of the delay chain is triggered. The periodic handshake will not affect data read and write and will not occupy the normal read and write bandwidth. On the premise of reducing the impact on the normal read and write bandwidth and ensuring timely update at necessary moments, the present invention improves the memory access efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0013] Figure 1 It is a schematic structural diagram of the memory system provided by the embodiment of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0014] The following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the drawings in the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, rather than all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts belong to the scope of protection of the present invention.

[0015] According to a first aspect of the present invention, there is provided a memory system, as Figure 1 shown, comprising a memory controller (Memory controller, abbreviated as MC), a physical layer (Physical Layer, abbreviated as PHY), and a storage unit. The memory controller is connected to the storage unit through the physical layer, and the memory controller performs read and write data operations on the storage unit through the physical layer. It should be noted that the memory controller receives data read and write instructions from a central processing unit (Central Processing Unit, abbreviated as CPU), generates read and write control instructions based on the data read and write instructions, and executes data read and write operations in the storage unit through the physical layer. The storage unit is a static random access memory (SRAM), a double data rate synchronous dynamic random access memory (DDR), or the like.

[0016] The memory controller and the physical layer are interconnected through a memory physical interface (DDR Physical Interface, abbreviated as DFI). The memory physical interface includes a message interface and an interface for implementing read and write data; the interface for implementing read and write data includes a command interface (Commond Interface), a data interface (Data Interface), a clock interface (Clock Interface), a response interface (Response Interface), etc. The memory physical interface further includes an update interface (Update Interface).

[0017] The memory controller is configured to send a controller handshake request to the physical layer through the message interface every first preset number of cycles. The memory controller implements data read and write operations through the interface for implementing read and write data, and the message interface and the interface for implementing read and write data are independent of each other. It should be noted that the memory controller sending a controller handshake request to the physical layer through the message interface does not affect normal data read and write operations. And the handshake requests are all actively initiated by the memory controller. Specifically, it can be achieved by setting a periodic counter and a handshake request generator to send a controller handshake request to the physical layer through the message interface every other cycle.

[0018] The physical layer obtains delay chain calibration data every second preset number of cycles. When a handshake request from the memory controller is received, it determines whether the change in the delay chain caused by the current temperature and voltage drift exceeds a preset delay chain change threshold. If it exceeds, an acknowledgement signal (ACK) is returned to the memory controller through the message interface. It should be noted that the first preset number of cycles and the second preset number of cycles can be equal or unequal. As an embodiment, both the first preset number of cycles and the second preset number of cycles are one cycle. The delay chain is a digital delay chain, and its function is to adjust the delay of data or command signal lines. The delay chain is located in the physical layer, and the delay chain is instantiated on both the data path and the command path of the physical layer.

[0019] The memory controller is further configured to, after receiving the acknowledgement signal, control the physical layer to calibrate the delay chain based on the current delay chain calibration data. During the process of calibrating the delay chain, the operations of the interfaces for implementing read and write data are paused. It should be noted that if no ACK is received within the Ack time required by the DFI protocol, it is considered that no update is needed, and the system can continue to perform normal read and write operations. If an ACK is received within the ACK time required by the DFI protocol, the memory controller can initiate the preparation for the delay chain update operation. After the current allowed consecutive page-hit commands are sent, an update request is sent to the physical layer to enable the physical layer to perform a delay chain update operation.

[0020] It should be noted that in the prior art, the memory controller updates the interface to periodically send update requests to the physical layer and perform update operations. When performing the update operation, it will occupy interfaces such as the command interface, data interface, clock interface, and response interface, thus affecting normal read and write operations. If the memory controller does not actively send updates and only monitors the temperature and voltage drift situation through the physical layer, it requires the physical layer to passively and forcibly initiate updates, and usually initiates after the temperature and voltage drift has reached the maximum value Max of the delay chain change. At this time, the current delay chain calibration data updated by the physical layer is no longer accurate. On the one hand, it takes a lot of time for the physical layer to passively initiate updates. On the other hand, the physical layer needs to re-obtain accurate delay chain calibration data, which also takes a lot of time. During this period, the read and write operations cannot be carried out normally, thus affecting the memory access efficiency.

[0021] In this application, a periodic handshake is established through the message interface and the physical layer, which will not affect the normal read and write operations. The delay chain change threshold is R, and R = Max - a, where Max is the maximum value of the delay chain change. When the temperature and voltage drift exceeds Max, the physical layer will sample the data incorrectly. a is the delay chain change buffer value. Setting a can ensure the safety of the system, so that generally, there will be no large temperature and voltage drift in the second preset number of cycles. And when the delay chain change caused by the current temperature and voltage drift exceeds the preset delay chain change threshold, an update operation is actively initiated by the memory controller by returning an acknowledgment signal through the message interface. At this time, the current delay chain calibration data of the physical layer can be directly used.

[0022] As an embodiment, the message interface includes a dfi_ctrlmsg_data data segment and a dfi_ctrlmsg_ack data segment. Among them, the dfi_ctrlmsg_data data segment is used to implement the transmission of message data from the memory controller to the physical layer. The dfi_ctrlmsg_data data segment includes reserved items, and one of the reserved items is selected and set to be used to send a handshake request code. The memory controller sends a handshake request code to the physical layer through the selected reserved item in the dfi_ctrlmsg_data data segment to implement the transmission of a handshake request from the memory controller to the physical layer. The dfi_ctrlmsg_ack data segment is used to implement the transmission of an acknowledgment signal from the physical layer to the memory controller. The message interface also includes a dfi_ctrlmsg data segment and a dfi_ctrlmsg_req data segment. Among them, the dfi_ctrlmsg data segment is used to implement the transmission of message instructions from the memory controller to the physical layer; and the dfi_ctrlmsg_req data segment is used to implement the transmission of requests from the memory controller to the physical layer.

[0023] It should be noted that in the embodiment of the present invention, the update operation can be directly initiated by the memory controller based on the acknowledgment signal received by the memory controller, or the update interface and the message interface can be used in combination to implement the active initiation of the update operation by the memory controller. As an embodiment, the memory physical interface further includes an update interface. The system further includes a selection logic unit (MCU). One end of the selection logic unit is connected to the memory controller, and the other end is connected to the message interface and the update interface. The message interface and the update interface are connected to the physical layer. In the initial state, the selection logic gates the message interface. When the memory controller receives the acknowledgment signal returned by the physical layer, the selection logic gates the update interface, and the memory controller starts the physical layer to calibrate the delay chain based on the current delay chain calibration data through the update interface.

[0024] It should be noted that under normal circumstances, data and commands should be aligned. However, as the system runs, changes in temperature and voltage will occur. These changes will affect the movement of carriers at the microscopic level, thereby changing the characteristics of the device (such as switching speed, etc.). Before the maximum value MAX of the delay chain change is exceeded, it will not affect the system sampling data. However, when the maximum value MAX of the delay chain change is exceeded, it will affect the system sampling data. Therefore, it is necessary to calibrate the sampling data in a timely manner before the delay chain change caused by temperature and voltage drift reaches the maximum value MAX. The physical layer periodically obtains the delay chain calibration data to quickly and accurately calibrate the sampling data before the delay chain change caused by temperature and voltage drift reaches the maximum value MAX, so that the data and commands are realigned. As an embodiment, the delay chain calibration data includes data window calibration data and command window calibration data, and the delay chain calibration data is stored in a preset storage area. The physical layer obtains the delay chain calibration data every second preset number of cycles and overwrites the data stored in the preset storage area.

[0025] In the system according to the embodiment of the present invention, a handshake signal is sent between the memory controller and the physical layer through a message interface. The update of the delay chain is only triggered when the temperature and voltage drift exceeds a preset delay chain change threshold. The periodic handshake will not affect data reading and writing and will not occupy the normal reading and writing bandwidth. The present invention improves the memory access efficiency while reducing the impact on the normal reading and writing bandwidth and ensuring timely update at a necessary moment.

[0026] The above are only preferred embodiments of the present invention and do not impose any form of limitation on the present invention. Although the present invention has been disclosed above with preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make some changes or modifications to the above-disclosed technical content to obtain equivalent embodiments with equivalent changes. However, as long as the content does not depart from the technical solution of the present invention, any simple modification, equivalent change, and modification made to the above embodiments based on the technical essence of the present invention still fall within the scope of the technical solution of the present invention.

Claims

1. A memory system, characterized in that, It includes a memory controller, a physical layer, and a storage unit. The memory controller is connected to the storage unit through the physical layer, and the memory controller performs read and write data operations on the storage unit through the physical layer. The memory controller and the physical layer are interconnected through a memory physical interface, and the memory physical interface includes a message interface and an interface for implementing read and write data. The memory controller is used to send a controller handshake request to the physical layer through the message interface every first preset number of cycles. The memory controller implements data read and write operations through the interface for implementing read and write data, and the message interface and the interface for implementing read and write data are independent of each other. The physical layer acquires delay chain calibration data once every second preset number of cycles. When receiving a controller handshake request, it determines whether the change in the delay chain caused by the current temperature and voltage drift exceeds a preset delay chain change threshold. If it exceeds, it returns an acknowledgment signal to the memory controller through the message interface. The memory controller is further used to control the physical layer to calibrate the delay chain based on the current delay chain calibration data after receiving the acknowledgment signal. During the process of calibrating the delay chain, the operation of the interface for implementing read and write data is paused.

2. The system according to claim 1, wherein The message interface includes a dfi_ctrlmsg_data data segment and a dfi_ctrlmsg_ack data segment. Among them, the dfi_ctrlmsg_data data segment is used to implement sending message data from the memory controller to the physical layer. The dfi_ctrlmsg_data data segment includes reserved items, and one of the reserved items is set as the code for sending a handshake request. The memory controller sends the handshake request code to the physical layer through the selected reserved item in the dfi_ctrlmsg_data data segment. The dfi_ctrlmsg_ack data segment is used to implement sending an acknowledgment signal from the physical layer to the memory controller.

3. The system according to claim 1, wherein The memory physical interface further includes an update interface. The system further includes a selection logic unit. One end of the selection logic unit is connected to the memory controller, and the other end is connected to the message interface and the update interface. The message interface and the update interface are connected to the physical layer. In the initial state, the selection logic gates the message interface. When the memory controller receives the acknowledgment signal returned by the physical layer, the selection logic gates the update interface, and the memory controller starts the physical layer to calibrate the delay chain based on the current delay chain calibration data through the update interface.

4. The system according to claim 1, wherein The delay chain change threshold is R, and R = Max - a, where Max is the maximum value of the delay chain change. When the temperature and voltage drift exceed Max, the physical layer will sample data incorrectly, and a is the delay chain change buffer value.

5. The system according to claim 1, wherein The delay chain calibration data includes data window calibration data and command window calibration data, and the delay chain calibration data is stored in a preset storage area; The physical layer obtains the delay chain calibration data once every second preset number of cycles and overwrites and stores it in the preset storage area.

6. The system according to claim 1, wherein The storage unit is a dynamic random access memory.

7. The system according to claim 1, wherein The storage unit is a double data rate synchronous dynamic random access memory.

8. The system according to claim 1, wherein The interface for realizing reading and writing data includes a command interface, a data interface, a clock interface, and a response interface.

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