Mode aware enhanced crosstalk cancellation (PEXTC) scheme

Abstract

The invention relates to a mode aware enhanced crosstalk cancellation (PEXTC) scheme. An apparatus includes a signal pattern sensing circuit and a crosstalk cancellation (XTC) circuit. The signal pattern sensing circuit includes a plurality of logic gates. The signal pattern sensing circuit receives a first signal and a second signal. The signal pattern sensing circuit generates an enable signal at an output of one of the plurality of logic gates based on a switching pattern of the first signal and the second signal. The XTC circuit includes a buffer coupled with a capacitor. The capacitor receives a second signal via the buffer. The XTC circuit dynamically couples an output of the capacitor to a communication channel of the first signal based on the enable signal.

Description

Technical Field

[0001] The present application relates generally to the field of circuits, and more particularly to a pattern-aware enhanced crosstalk cancellation method. Background Art

[0002] The performance of high-speed parallel buses is limited by channel crosstalk interference. Routing dense parallel buses can be challenging with limited available board / package area. While achieving low-cost packaging and platforms, channel design is affected by higher crosstalk in the transmission lines due to limited stacking options. In order to solve the channel crosstalk problem and improve interface performance, cross-talk cancellation (XTC) technology can be used. However, existing XTC technology is associated with limited solution space and increased power dissipation. Summary of the invention

[0003] According to one aspect of the present application, a device is provided, comprising: a signal pattern sensing circuit including a plurality of logic gates, the signal pattern sensing circuit receiving a first signal and a second signal, and generating an enable signal at an output of one of the plurality of logic gates based on a switching pattern of the first signal and the second signal; and a crosstalk cancellation (XTC) circuit, the XTC circuit comprising a buffer coupled to a capacitor, the capacitor receiving the second signal via the buffer, and the XTC circuit dynamically coupling the output of the capacitor to a communication channel of the first signal based on the enable signal.

[0004] According to another aspect of the present application, a system is provided, comprising: a memory; and at least one processor coupled to the memory, the at least one processor being used to: decode a first signal comprising a first even signal and a first odd signal; decode a second signal comprising a second even signal and a second odd signal; determine a switching pattern of the first signal and the second signal based on a switching state of each of the first even signal, the first odd signal, the second even signal, and the second odd signal at multiple time instances; generate an enable signal based on the switching pattern of the first signal and the second signal; and dynamically couple an output of a capacitor to a communication channel of the first signal based on the enable signal, the capacitor being used to receive the second signal via a buffer.

[0005] According to another aspect of the present application, a method is provided, comprising: decoding a first signal comprising a first even signal and a first odd signal; decoding a second signal comprising a second even signal and a second odd signal; determining a switching pattern of the first signal and the second signal based on a switching state of each of the first even signal, the first odd signal, the second even signal and the second odd signal at multiple time instances; generating an enable signal based on the switching pattern of the first signal and the second signal; and dynamically coupling an output of a capacitor to a communication channel of the first signal based on the enable signal, the capacitor receiving the second signal via a buffer. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] In the accompanying drawings, like reference numerals may describe the same or similar components or features in different views. Like reference numerals with different letter suffixes may represent different instances of similar components. Some embodiments are illustrated by way of example and not limitation in the accompanying drawings, in which:

[0007] Figure 1 illustrates a high-level block diagram of a transmit (Tx) side XTC architecture according to some embodiments;

[0008] Figure 2 illustrates a high-level block diagram of a Tx-side XTC architecture using pattern-aware (PAW) logic according to some embodiments;

[0009] Figure 3 illustrates a high-level block diagram of a Tx-side mode-aware enhanced XTC (PeXTC) architecture according to some embodiments;

[0010] Figure 4 It is illustrated that according to some embodiments, Figure 3 The truth table that can be used by the PeXTC architecture is:

[0011] Figure 5 illustrates a graph showing improvement of margin with XTC gain in conventional XTC and PeXTC for a memory channel according to some embodiments;

[0012] Figure 6 illustrates a table showing improvements of conventional XTC and PeXTC for a memory channel according to some embodiments;

[0013] Figure 7 illustrates a table showing improvements of conventional XTC and PeXTC for another memory channel according to some embodiments;

[0014] Figure 8illustrates a graph of victim line modulation due to crosstalk aggressor pattern dependency according to some embodiments;

[0015] Fig. 9 The diagram illustrates that according to some embodiments, an attacker may influence (e.g., from Figure 8 A plot of the victim mode of the high side slice of FIG.

[0016] Fig.10 illustrates a table with XTC gain delay sweeps according to some embodiments (eg, current XTC techniques versus disclosed PeXTC techniques);

[0017] Fig.11 illustrates a table with a summary of best case margin comparison and circuit effectiveness according to some embodiments;

[0018] Fig.12 illustrates a graph of two sequential bursts of a random even mode and an odd mode victim-aggressor mode according to some embodiments;

[0019] Fig.13 illustrates a table with conventional XTC circuit parameter scans and the effects of odd-mode and even-mode attacks according to some embodiments;

[0020] Fig.14 is a flow chart of an example method for crosstalk cancellation (XTC) according to some embodiments; and

[0021] Fig.15 Illustrated is a block diagram of an example machine upon which any one or more of the operations / techniques (eg, methodologies) discussed herein may be performed. DETAILED DESCRIPTION

[0022] The following detailed description refers to the accompanying drawings. The same reference numerals may be used to identify the same or similar elements in different drawings. In the following description, specific details such as specific structures, architectures, interfaces, technologies, etc. are recorded for illustration, not limitation, to provide a thorough understanding of various aspects of various embodiments. However, it will be clear to those skilled in the art who benefit from this disclosure that various aspects of various embodiments may be implemented in other examples that are separated from these specific details. In some cases, descriptions of well-known devices, circuits, and methods are omitted to avoid obscuring the description of various embodiments with unnecessary details.

[0023] The following description and the accompanying drawings sufficiently illustrate the specific embodiments to enable those skilled in the art to implement them. Other embodiments may contain structural, logical, electrical, process and other changes. Portions and features of some embodiments may be included in other embodiments, or replace portions and features of other embodiments. The embodiments outlined in the claims cover all available equivalents of these claims.

[0024] As used herein, the term "chip" (or die) refers to a piece of material, such as semiconductor material, that includes a circuit such as an integrated circuit or a portion of an integrated circuit. The term "memory IP" refers to memory intellectual property. The terms "memory IP," "memory device," "memory chip," and "memory" are interchangeable.

[0025] The term "processor" configured to perform a particular operation includes both a single processor configured to perform all functions (e.g., the operations or methods disclosed herein), and multiple processors that are individually configured to perform some or all operations (which may overlap), such that a combination of the processors performs all operations.

[0026] As used herein, the term "odd-way mode" means that two signals (e.g., a first signal (also referred to as a victim signal) and a second signal (also referred to as an aggressor signal) switch periods in different directions at a given time. As used herein, the term "even-way mode" means that two signals switch periods in the same direction at a given time.

[0027] In some aspects, to solve the channel crosstalk problem and improve interface performance, passive XTC techniques and active crosstalk cancellation circuits can be utilized. Passive crosstalk cancellation provides a fixed solution that requires careful design and may result in a limited solution space. Passive XTC solutions (e.g., stubby transmission lines, coupled via solutions, fuzzy via solutions, etc.) are fixed solutions that cannot be scaled.

[0028] Active XTC provides a scalable solution, but at the expense of additional power dissipation in the circuit and the overload associated with the circuit addition. In addition, active XTC circuits (which can be implemented on the transmitter side or the receiver side) may have limitations in terms of power and performance.

[0029] Current active and passive XTC technologies are associated with the following disadvantages:

[0030] (a) As described in detail below, both passive and currently implemented active XTC circuits are limited / constrained by a unified XTC scheme over all attacker modes (the disclosed PeXTC technique overcomes these shortcomings).

[0031] (b) Crosstalk from a particular mode is destructive, but crosstalk from the opposite mode is constructive. If the channels are inductively coupled, even-mode modes are destructive, while odd-mode modes are constructive.

[0032] (c) Currently, conventional XTC is applied uniformly regardless of the aggressor mode, and the goal is to compensate for the crosstalk from the destructive mode.

[0033] (d) When conventional XTC is uniformly applied without mode awareness, the constructive mode gain is invalidated.

[0034] (e) Conventional XTC implementations without mode awareness restrict circuit optimization for destructive modes, since the reduction of constructive modes becomes the limiting factor. Due to this feature, the effectiveness of conventional XTC is significantly affected.

[0035] (f) Conventional XTC is always on and consumes power continuously.

[0036] The disclosed pattern-aware enhanced cross-talk cancellation (PeXTC) technology overcomes the limitations of conventional crosstalk cancellation (XTC) circuits to improve the effectiveness of active crosstalk cancellation circuits. The proposed scheme can save about 40% to 50% of the power dissipated by current active cancellation circuits.

[0037] According to the disclosed PeXTC technology, the XTC circuit will be dynamically turned on and off based on the aggressor signal pattern relative to the victim signal pattern. The disclosed PeXTC scheme significantly enhances the effectiveness of XTC in suppressing noise, enhancing signal and improving SNR.

[0038] Assuming a random pattern, the probability of shutting down the XTC may be greater than 80% of the attacker pattern, which can also save up to 80% of the XTC circuit power consumption. The disclosed PeXTC technology brings higher performance to high-speed interfaces (e.g., DDRx, LPx, and GDDRx technologies) and can be applied on single-ended switching and dense parallel buses.

[0039] Crosstalk has been one of the significant limiting factors in dense parallel buses (e.g., memory interfaces) while allowing higher data rates to be achieved. Crosstalk from the aggressor bit can be destructive or constructive. Destructive crosstalk reduces the victim signal margin, while constructive crosstalk improves the victim signal margin. Figure 8 and Fig. 9 This is further shown in . Figure 1-Figure 3An example XTC architecture is illustrated in which the disclosed techniques may be used.

[0040] Figure 1 FIG. 1 illustrates a high-level block diagram of a transmit (Tx) side XTC architecture according to some embodiments. Figure 1 , the XTC architecture 100 includes a transmit buffer 120 (also referred to as a Tx buffer) receiving a first signal 120, a channel resistor 122, a communication channel 124 for the first signal, and a receive buffer 126 (also referred to as an Rx buffer).

[0041] The XTC architecture 100 also includes a Tx buffer 128 that receives the second signal 104 , a channel resistor 130 , a communication channel 132 for the second signal, and an Rx buffer 134 .

[0042] The XTC architecture 100 may be associated with far-end cross-talk (FEXT) 136 between the communication channels 124 and 132. In some aspects, the active XTC circuit 106 may be used to mitigate the FEXT 136.

[0043] In some aspects, the active XTC circuit 106 includes a buffer 114, a channel resistor 116, and a capacitor 118 to couple the second signal 104 to a communication channel 124 of the first signal 102. The active XTC circuit 106 also includes a buffer 108, a channel resistor 110, and a capacitor 112 to couple the first signal 102 to a communication channel 132 of the second signal 104.

[0044] In some embodiments, an XTC circuit (eg, active XTC circuit 106) may be configured as a PeXTC circuit (eg, as described in connection with the disclosed techniques) using the disclosed techniques. Figure 2 and Figure 3 described above).

[0045] Figure 2 FIG. 2 illustrates a high-level block diagram of a Tx-side XTC architecture 200 using PAW logic according to some embodiments. Figure 2 , the XTC architecture 200 includes a Tx buffer 220 receiving a first signal 202 , a channel resistor 222 , a communication channel 224 for the first signal, and an Rx buffer 226 .

[0046] The XTC architecture 200 also includes a Tx buffer 228 that receives the second signal 204 , a channel resistor 230 , a communication channel 232 for the second signal, and an Rx buffer 234 .

[0047] XTC architecture 200 may be associated with FEXT 236 between communication channels 224 and 232. In some aspects, PeXTC circuit 206 may be used to mitigate FEXT 236.

[0048] In some aspects, the PeXTC circuit 206 includes a buffer 214, a channel resistor 216, a capacitor 218, and a transistor 242 to couple the second signal 204 to the communication channel 224 of the first signal 202. The PeXTC circuit 206 also includes a buffer 208, a channel resistor 210, a capacitor 212, and a transistor 240 to couple the first signal 202 to the communication channel 232 of the second signal 204.

[0049] In some aspects, the PeXTC circuit 206 also includes a mode sensor 238 (also referred to as mode sensing logic or XTCPAW logic). The mode sensor 238 receives the first signal 202 and the second signal 204 and determines a switching mode for each of the first signal 202 and the second signal 204. The PeXTC circuit 206 generates an enable signal 244 based on the determined switching mode. For example, when the first signal 202 and the second signal 204 are switching in the same direction (e.g., both signals are associated with an even-way switching mode, e.g., Figure 8 ), the PeXTC circuit 206 generates an enable signal 244. In some aspects, the enable signal 244 is used to enable (or turn on) transistors 242 and / or 240 (which act as switches) to allow the signal communication output from capacitors 218 and 212 to be injected into the corresponding communication channels 224 and / or 232, thereby performing XTC and mitigating FEXT 236.

[0050] Will contact Figure 3 A more detailed schematic diagram of the PeXTC circuit used in the XTC architecture is discussed below.

[0051] Figure 3 Illustrated is a high-level block diagram of a Tx-side mode-aware enhanced XTC (PeXTC) architecture according to some embodiments.

[0052] Figure 4 It is illustrated that according to some embodiments, Figure 3 The PeXTC architecture may use truth table 400 .

[0053] refer to Figure 3, the XTC architecture 300 includes a Tx driver 308 that receives a first signal 366 (also referred to as a victim signal), which may be a serialized signal. More specifically, the flip-flop circuit 302 outputs an even signal 362, and the flip-flop circuit 304 outputs an odd signal 364. The even signal 362 and the odd signal 364 are serialized by the serializer 306 to generate a serialized signal (e.g., the first signal 366).

[0054] The XTC architecture 300 also includes a Tx driver 316 that receives a second signal 360 (also referred to as an aggressor signal), which may be a serialized signal. More specifically, the flip-flop circuit 310 outputs an even signal 356, and the flip-flop circuit 312 outputs an odd signal 358. The even signal 356 and the odd signal 358 are serialized by the serializer 314 to generate a serialized signal (e.g., the second signal 360).

[0055] In some aspects, FEXT may exist between the communication channels of the first signal 366 and the second signal 360. The PeXTC circuit 301 may use the XTC PAW logic 318 and the XTC circuits 326, ..., 328 to mitigate FEXT.

[0056] XTC PAW logic 318 includes logic AND gates 320 and 322 coupled to logic OR gate 324. Logic AND gates 320 and 322 receive signal sets 368 and 370 as inputs, respectively, which may indicate the switching states of even signal 362 (or vic_even), odd signal 364 (or vic_odd), even signal 356 (or agg_even), odd signal 358 (or agg_odd), and corresponding opposite (or opposing) signals (i.e., vic_oddb, agg_oddb, vic_evenb, and agg_evenb). In some aspects, signal sets 368 and 370 are configured in a truth table, such as Figure 4 . In some aspects, the truth table may be stored in the PeXTC circuit 301.

[0057] The outputs of the logic AND gates 320 and 322 are communicated as inputs to the logic OR gate 324, which generates an enable signal 372 (also referred to as a dynamic enable signal) that is communicated as inputs to the XTC circuits 326, ..., 328. In some aspects, the enable signal 372 is generated when the first signal 366 and the second signal 360 are toggled in the same direction (e.g., Figure 4In this regard, the enable signal 372 may indicate the presence of an even-way switching pattern between the victim and aggressor signals, which may activate one or more of the XTC circuits 326 , . . . , 328 .

[0058] The XTC circuit 326 includes a logic AND gate 330, an inverter 332, serially coupled buffers 334 and 344, and a driving capacitor 354. The output of the capacitor 354 is coupled to the signal path of the first signal 366. In some aspects, the buffers 334 and 344 are configured as tri-state inverters. For example, the buffer 334 includes p-channel metal-oxide-semiconductor (PMOS) transistors 336 and 338 and n-channel metal-oxide-semiconductor (NMOS) transistors 340 and 342. Similarly, the buffer 344 includes PMOS transistors 346 and 348 and NMOS transistors 350 and 352. The buffers 334 and 344 receive the aggressor signal (e.g., the second signal 360) as input.

[0059] In operation, the XTC PAW logic 318 receives the signal sets 368 and 370 and generates an enable signal 372 when an even-mode switching pattern between the victim and aggressor signals is detected. The enable signal 372 is communicated as an input to a logic AND gate 330, which also receives an XTC gain signal 374 as a second input. The XTC gain signal 374 can be used to adjust the amount of gain required for the XTC by activating (or selecting) one or more of the XTC circuits 326, ..., 328. The output signal 331 from the logic AND gate 330 is used to activate the buffers 334 and 344 to inject the output signal 374 generated by the capacitor 354 into the communication channel of the first signal 366, thereby implementing XTC during the even-mode switching pattern between the victim and aggressor signals.

[0060] Although in Figure 3 301 is illustrated as including XTC PAW logic 318 and XTC circuits 326, ..., 328, but the present disclosure is not limited thereto, and different levels of circuit integration may be used. For example, Figure 3 One or more of the circuits illustrated in the drawings may be separate circuits, or two or more of the illustrated circuits may be implemented together (eg, as a single circuit (eg, a single processor)).

[0061] Figure 5Illustrated are graphs 502 and 504 showing improvement of margin with XTC gain in conventional XTC and PeXTC for a memory channel, according to some embodiments. Figure 5 The circuit simulation data disclosed in illustrates the XTC gain using the disclosed techniques. The analysis was performed using a DDR5 channel model. Figure 5 It is shown that as the XTC gain of the XTC circuit increases, there is no significant gain for the conventional XTC, while a significant improvement in eye height is observed for the disclosed PeXTC circuit.

[0062] Figure 6 FIG. 6 shows a table 600 showing the improvement of conventional XTC and PeXTC for a memory channel according to some embodiments. More specifically, table 600 shows the margin for the case of XTC gain = 6. Table 600 shows that the XTC power consumption is reduced by about 10% relative to conventional XTC. In addition, from Figure 6 It can be seen that the eye area is improved by 18% using the disclosed PeXTC circuit compared to 10% in conventional XTC.

[0063] In some aspects, a pattern detector (e.g., XTC PAW logic 318) may be located upstream (before serializers 306 and 314) to provide more processing time. Zero-delay processing may not be a requirement. In some aspects, buffers may be used to provide additional delay to the XTC or signal path if desired. In some aspects, programmable delay elements may be added to the XTC path to further optimize the XTC.

[0064] Figure 7 Illustrated is a table 700 showing improvements of conventional XTC and PeXTC for another memory channel, according to some embodiments.

[0065] Channel transient simulation can be performed for the disclosed technology using LPDDR5 channels. In this case, transmitter XTC analysis can be performed. The circuit used may not be created in ADS, but can be used with Figure 3 Table 700 shows the margin of the XTC. The delays of the XTC aggressor input and the XTC enable input can be optimized to obtain optimized results. From Table 700, it can be seen that the eye area is improved by 17% when PeXTC is used compared to 2% in the conventional XTC.

[0066] Figure 8 Illustrated are graphs 802 and 804 of victim line modulation due to crosstalk aggressor pattern dependency, according to some embodiments.

[0067] Fig. 9The diagram illustrates that according to some embodiments, an attacker may influence (e.g., from Figure 8 Graph 900 of the victim mode of the high side slice).

[0068] Crosstalk can be a significant limiting factor in densely parallel buses (e.g., memory interfaces) while achieving higher data rates. Crosstalk from the aggressor bit can be destructive or constructive. Destructive crosstalk reduces the victim margin, while constructive crosstalk improves the victim margin. This is particularly true in Figure 8 Graph 802 shows the victim and aggressor input patterns, and graph 804 shows the victim output signal modulated by crosstalk. Fig. 9 The graph 900 in FIG. 1 also shows a zoomed-in version of the victim line. Most memory channels are dominated by inductively coupled crosstalk, and such channels are also considered for the research results disclosed below. On platforms with higher inductive crosstalk, even-numbered victim-aggressor patterns will result in destructive crosstalk, while odd-numbered victim-aggressor patterns will result in constructive patterns.

[0069] (A)PoC: Case Study 1.

[0070] The analysis is performed using two networks, one is the victim and the other is the aggressor. The channel is stimulated with the worst case ISI crosstalk pattern derived from the PDA analysis using a random stream of odd and even pattern combinations. The focus is on examining the impact of the conventional XTC circuit and comparing it with the disclosed pattern-aware enhanced XTC circuit. The LPDDR5x 2nd order channel and a simple Rx side XTC circuit are used for the analysis.

[0071] Fig.10 Illustrated is a table 1000 with XTC gain delay sweeps according to some embodiments (eg, current XTC techniques versus disclosed PeXTC techniques).

[0072] Fig.11 Illustrated is a table 1100 with a summary of best case margin comparison and circuit effectiveness, according to some embodiments.

[0073] Table 1000 shows the effect of adjusting the parameters of the conventional XTC circuit and the mode-aware XTC circuit. The parameters gx and cx are the gain and delay of the XTC circuit that are swept to simulate possible training scenarios. gx=0 means that the XTC circuit is disabled. Table 1000 summarizes the best case for all adjustment ranges. From Table 1000, it can be seen that there is a 1mV / 5.9ps improvement using the current cancellation circuit, while using the mode-aware XTC circuit, the margin is improved by 8mV / 4.1ps.

[0074] The best case margins are summarized in Table 1100. Here, No Crosstalk represents the ISI-only scenario—the channel is not stressed by crosstalk. The With Crosstalk but Crosstalk Disabled scenario represents crosstalk present in the channel, but the XTC circuit is turned off via the gain control. The XTC circuit is still present, but may overload the victim signal path. The XTC Enabled case is after turning on the regular XTC circuit. The PeXTC Enabled case represents the introduction of the proposed pattern-aware enhanced crosstalk cancellation circuit. The Eye Area Impact Percent is an excellent matrix for comparing the effectiveness of the circuits.

[0075] (B)POC case study 2.

[0076] Fig.12 Illustrated is a graph 1200 of two sequential bursts of random even-way and odd-way victim-aggressor patterns, according to some embodiments.

[0077] The analysis is performed using two networks, considering one as the victim and the other as the aggressor. The channel is stimulated with random pattern bursts to examine the impact of the XTC circuit, and then the impact of implementing a pattern-aware XTC circuit is examined. In the transmission burst, the aggressor has the same transitions as the victim (even-way stimulation). In contrast, in the second burst, the aggressor has the opposite transitions to the victim (odd-way stimulation). This is shown in Figure 2. Fig.12 LPDDR5x channels are used, and a simplified Rx-side crosstalk cancellation circuit is used for analysis.

[0078] Fig.13 Illustrated is table 1300 with conventional XTC circuit parameter scans and the effects of odd-way and even-way attacks, according to some embodiments.

[0079] Table 1300 shows the effect of the XTC circuit on even and odd aggressor modes. Parameters gx and cx are the gain and delay of the XTC circuit. gx=0 means that the XTC circuit is disabled. The following observations can be made from this analysis:

[0080] (a) Comparison of [Case #2 and Case #1] shows that even-mode aggressors will hurt the ISI margin, but odd-mode crosstalk may increase the margin if the channel is dominated by inductive coupling.

[0081] (b) The comparison of [Case #2 vs. Case #3] and [Case #6 vs. Case #7] shows that the conventional XTC scheme partially recovers the margin loss from even-numbered attackers, while the circuit kills the crosstalk gain from odd-numbered attackers.

[0082] (c) The comparison of [Case #3 vs. Case #4] and [Case #7 vs. Case #8] shows that the mode-aware enhanced XTC scheme actually recovers the margin loss from the even-way attacker while preserving the crosstalk gain from the odd-way attacker.

[0083] (d) Case #3 and Case #7 show that the margin of the odd-way aggressor mode becomes a limiting factor in the overall margin calculation and needs to be improved. Case #7 specifically shows that in the inductively coupled channel, the effectiveness of the conventional XTC circuit is greatly constrained due to the odd-way effects.

[0084] (e) Case #4 and Case #8 show that the margin of utilizing mode-aware XTC is superior to the current XTC circuit. Case #8 clearly shows that the mode-aware XTC scheme unlocks the opportunity to improve the crosstalk cancellation gain with a more comprehensive gx / cx range compared to conventional XTC.

[0085] Fig.14 is a flow chart of an example method 1400 for XTC according to some embodiments. Fig.14 , method 1400 includes operations 1402, 1404, 1406, 1408, and 1410, which can be performed by a PeXTC circuit (e.g., Figure 3 PeXTC circuit 301) or another processor of a computing device (e.g., Fig.15 The machine 1500 is shown as a hardware processor 1502, which may include Figure 3 In some embodiments, Figure 3 One or more of the circuits shown in Fig.14 and the features discussed in the examples listed below.

[0086] In operation 1402 , a first signal (eg, first signal 366 ) is decoded, wherein the first signal includes a first even signal (eg, even signal 362 ) and a first odd signal (eg, odd signal 364 ).

[0087] At operation 1404 , a second signal (eg, the second signal 360 ) is decoded, wherein the second signal includes a second even signal (eg, the even signal 356 ) and a second odd signal (eg, the odd signal 358 ).

[0088] At operation 1406, a switching pattern of the first signal and the second signal is determined based on the switching state of each of the first even signal, the first odd signal, the second even signal, and the second odd signal at a plurality of time instances. Figure 4 The truth table 400 determines the switching state of each signal set 368 and 370.

[0089] At operation 1408 , an enable signal (eg, the enable signal 372 ) is generated based on the switching pattern of the first signal and the second signal (eg, when an even-numbered switching pattern is detected).

[0090] At operation 1410, an output of a capacitor (e.g., capacitor 354) can be dynamically coupled to a communication channel of a first signal based on an enable signal (e.g., the capacitor can be dynamically activated or switched). The capacitor (e.g., capacitor 354) receives a second signal (e.g., second signal 360) via buffers (e.g., buffers 334 and 344).

[0091] Fig.15 A block diagram of an example machine 1500 on which any one or more techniques (e.g., methods) discussed herein may be executed is illustrated. In alternative embodiments, the machine 1500 may operate as a standalone device or may be connected (e.g., networked) to other machines. In a networked deployment, the machine 1500 may operate as a server machine, a client machine, or both in a server-client network environment. In an example, the machine 1500 may act as a peer machine in a peer-to-peer (P2P) (or other distributed) network environment. The machine 1500 may be a personal computer (PC), a tablet PC, a set-top box (STB), a personal digital assistant (PDA), a portable communication device, a mobile phone, a smart phone, a web appliance, a network router, a switch or a bridge, or any other computing device capable of executing instructions (sequential or otherwise) specifying the actions to be taken by the machine. In addition, although only a single machine is illustrated, the term "machine" should also be understood to include any collection of machines that individually or jointly execute a set (or multiple sets) of instructions to perform any one or more of the methodologies discussed herein, such as cloud computing, software as a service (SaaS), and other computer cluster configurations. The terms "machine," "computing device," and "computer system" are used interchangeably.

[0092] The machine (e.g., computer system) 1500 may include a hardware processor 1502 (e.g., a central processing unit (CPU), a graphics processing unit (GPU), a hardware processor core, or any combination thereof), a main memory 1504, and a static memory 1506, some or all of which may communicate with each other via an interconnection link 1508 (e.g., a bus). In some aspects, the main memory 1504, the static memory 1506, or any other type of memory (including cache memory) used by the machine 1500 may be configured based on the disclosed techniques, or may implement the disclosed memory devices.

[0093] Specific examples of main memory 1504 include random access memory (RAM), and semiconductor memory devices, which in some embodiments may include storage locations in a semiconductor, such as registers. Specific examples of static memory 1506 include non-volatile memory, such as semiconductor memory devices (e.g., electrically programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM)), and flash memory devices; magnetic disks, such as internal hard disks and removable disks; magneto-optical disks; RAM; and CD-ROM and DVD-ROM disks.

[0094] The machine 1500 may also include a display device 1510, an input device 1512 (e.g., a keyboard), and a user interface (UI) navigation device 1514 (e.g., a mouse). In one example, the display device 1510, the input device 1512, and the UI navigation device 1514 may be a touch screen display. The machine 1500 may also include a storage device (e.g., a drive unit or another large storage device) 1516, a signal generating device 1518 (e.g., a speaker), a network interface device 1520, and one or more sensors 1521, such as a global positioning system (GPS) sensor, a compass, an accelerometer, or other sensors. The machine 1500 may include an output controller 1528, such as a serial (e.g., universal serial bus (USB)), parallel or other wired or wireless (e.g., infrared (IR), near field communication (NFC), etc.) connection to communicate with one or more peripheral devices (e.g., printers, card readers, etc.) or control one or more peripheral devices. In some embodiments, hardware processor 1502 and / or instructions 1524 may include processing circuitry and / or transceiver circuitry.

[0095] The storage device 1516 may include a machine-readable medium 1522 on which may be stored one or more sets of data structures or instructions 1524 (e.g., software) embodying or utilized by any one or more of the techniques or functionality described herein. The instructions 1524 may also reside, completely or at least partially, within the main memory 1504, within the static memory 1506, or within the hardware processor 1502 during execution thereof by the machine 1500. In an example, one or any combination of the hardware processor 1502, the main memory 1504, the static memory 1506, or the storage device 1516 may constitute a machine-readable medium.

[0096] Specific examples of machine-readable media may include nonvolatile memory, such as semiconductor memory devices (e.g., EPROM or EEPROM) and flash memory devices; magnetic disks, such as internal hard disks and removable disks; magneto-optical disks; RAM; and CD-ROM and DVD-ROM disks.

[0097] Although the machine-readable medium 1522 is illustrated as a single medium, the term “machine-readable medium” may include a single medium or multiple media (eg, a centralized or distributed database, and / or associated caches and servers) configured to store the instructions 1524 .

[0098] The apparatus of the machine 1500 may be one or more of the following: a hardware processor 1502 (e.g., a central processing unit (CPU), a graphics processing unit (GPU), a hardware processor core, or any combination thereof), a main memory 1504 and a static memory 1506, one or more sensors 1521, a network interface device 1520, one or more antennas 1560, a display device 1510, an input device 1512, a UI navigation device 1514, a storage device 1516, instructions 1524, a signal generation device 1518, and an output controller 1528. The apparatus may be configured to perform one or more methods and / or operations disclosed herein. The apparatus may be used as a component of the machine 1500 to perform one or more methods and / or operations disclosed herein, and / or a portion of performing one or more methods and / or operations disclosed herein. In some embodiments, the apparatus may include a pin or other device to receive power. In some embodiments, the apparatus may include power regulation hardware.

[0099] The term "machine-readable medium" may include any medium that is capable of storing, encoding or carrying instructions for execution by the machine 1500 and causing the machine 1500 to perform any one or more techniques of the present disclosure, or capable of storing, encoding or carrying data structures used by or associated with such instructions. Non-limiting examples of machine-readable media may include solid-state memory, as well as optical and magnetic media. Specific examples of machine-readable media may include non-volatile memory, such as semiconductor memory devices (e.g., electrically programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), and flash memory devices; disks, such as internal hard disks and removable disks; magneto-optical disks; random access memory (RAM); and CD-ROM and DVD-ROM disks. In some examples, the machine-readable medium may include non-transitory machine-readable media. In some examples, the machine-readable medium may include machine-readable media that is not a transient propagation signal.

[0100] The instructions 1524 may also be sent or received over a communication network 1526 using a transmission medium via the network interface device 1520 using any of a number of transmission protocols (e.g., frame relay, internet protocol (IP), transmission control protocol (TCP), user datagram protocol (UDP), hypertext transfer protocol (HTTP), etc.). Example communication networks may include a local area network (LAN), a wide area network (WAN), a packet data network (e.g., the Internet), a mobile phone network (e.g., a cellular network), a Plain Old Telephone (POTS) network, and a wireless data network (e.g., a wireless network known as a WLAN). The IEEE 802.11 series of standards is known as ), IEEE 802.16 series of standards), IEEE 802.15.4 series of standards, Long Term Evolution (LTE) series of standards, Universal Mobile Telecommunications System (UMTS) series of standards, peer-to-peer (P2P) networks, and so on.

[0101] In one example, the network interface device 1520 may include one or more physical jacks (e.g., Ethernet, coaxial or telephone jacks) or one or more antennas to connect to the communication network 1526. In one example, the network interface device 1520 may include one or more antennas 1560 to communicate wirelessly using at least one single-input multiple-output (SIMO), multiple-input multiple-output (MIMO) or multiple-input single-output (MISO) technology. In some examples, the network interface device 1520 may communicate wirelessly using multi-user MIMO technology. The term "transmission medium" should be understood to include any intangible medium that can store, encode or carry instructions for execution by the machine 1500, and includes digital or analog communication signals or other intangible media to facilitate the communication of such software.

[0102] Examples as described herein may include logic or several components, modules or mechanisms, or may operate on logic or several components, modules or mechanisms. A module is a tangible entity (e.g., hardware) that can perform specified operations and can be configured or arranged in a particular manner. In one example, a circuit may be arranged as a module in a specified manner (e.g., internally or with respect to an external entity, such as other circuits). In one example, all or part of one or more computer systems (e.g., stand-alone, client or server computer systems) or one or more hardware processors may be configured as a module by firmware or software (e.g., instructions, application parts or applications), and the module operates to perform specified operations. In one example, the software may reside on a machine-readable medium. In one example, the software, when executed by the underlying hardware of the module, causes the hardware to perform specified operations.

[0103] Thus, the term "module" is understood to encompass a tangible entity, whether the entity is physically constructed, specifically configured (e.g., hardwired), or temporarily (e.g., temporarily) configured (e.g., programmed) to operate in a specified manner or to perform part, all, or any of the operations described herein. Considering the example of temporarily configured modules, each module need not be instantiated at any one time. For example, where a module includes a general-purpose hardware processor configured using software, the general-purpose hardware processor may be configured as various different modules at different times. The software may accordingly configure the hardware processor to, for example, constitute a particular module at one time and constitute different modules at different times.

[0104] Some embodiments may be implemented in whole or in part in software and / or firmware. This software and / or firmware may take the form of instructions contained in or on a non-transitory computer-readable storage medium. These instructions may then be read and executed by one or more processors to enable the operations described herein to be performed. The instructions may take any appropriate form, such as but not limited to source code, compiled code, interpreted code, executable code, static code, dynamic code, and the like. Such a computer-readable medium may include any tangible non-transitory medium for storing information in one or more computer-readable forms, such as but not limited to read-only memory (ROM), random access memory (RAM), magnetic disk storage medium, optical storage medium, flash memory, and the like.

[0105] The above detailed description includes reference to the accompanying drawings, which form a part of the detailed description. The accompanying drawings illustrate specific embodiments that can be implemented. These embodiments are also referred to as "examples" in this article. Such examples may include additional elements other than those shown or described. However, examples including the elements shown or described are also contemplated. In addition, examples (or one or more aspects thereof) using any combination or arrangement of these elements shown or described are also contemplated, whether for a specific example (or one or more aspects thereof), or for other examples (or one or more aspects thereof) shown or described herein.

[0106] Publications, patents, and patent documents cited in this document are hereby incorporated by reference in their entirety, as if each were incorporated by reference. In the event of inconsistent usages between this document and those documents so incorporated by reference, the usage in the incorporated reference(s) supplements that of this document; for irreconcilable inconsistencies, the usage in this document controls.

[0107] In this document, the terms "a" and "an" are used to include one or more than one, as is common in patent documents, independent of any other instances or uses of "at least one" or "one or more." In this document, the term "or" is used to refer to a non-exclusive or, so that "A or B" includes "A but not B," "B but not A," and "A and B," unless otherwise indicated. In the appended claims, the terms "including" and "in which" are used as the plain English equivalents of the respective terms "comprising" and "wherein." In addition, in the appended claims, the terms "including" and "comprising" are open-ended; that is, systems, devices, articles, or processes that include other elements in addition to those listed after such terms in the claim are still considered to fall within the scope of the claim. Moreover, in the appended claims, the terms "first," "second," and "third," etc., are used merely as labels and are not intended to imply a numerical order to their objects.

[0108] The embodiments described above may be implemented in various hardware configurations, which may include a processor for executing instructions that perform the described techniques. Such instructions may be included in a machine-readable medium, such as a suitable storage medium or memory or other processor-executable medium.

[0109] The embodiments as described herein may be implemented in a number of environments, such as as part of a system on a chip, a group of functional blocks communicating with each other, or the like. However, the scope of the present disclosure is not limited in this regard.

[0110] Implementations of the described subject matter may include one or more of the features, alone or in combination, as described below by way of example.

[0111] Example 1 is a device comprising: a signal pattern sensing circuit including a plurality of logic gates, the signal pattern sensing circuit receiving a first signal and a second signal and generating an enable signal at an output of one of the plurality of logic gates based on a switching pattern of the first signal and the second signal; and a crosstalk cancellation (XTC) circuit comprising a buffer coupled to a capacitor, the capacitor receiving the second signal via the buffer, and the XTC circuit dynamically coupling the output of the capacitor to a communication channel of the first signal based on the enable signal.

[0112] In Example 2, the subject matter of Example 1 includes the following subject matter: wherein the plurality of logic gates include a first logic AND gate and a second logic AND gate to receive a plurality of input signals based on the first signal and the second signal.

[0113] In Example 3, the subject matter as in Example 2 includes the following subject matter: wherein the first signal includes a first even signal and a first odd signal, and wherein the second signal includes a second even signal and a second odd signal.

[0114] In Example 4, the subject matter as described in Example 3 includes the following subject matter: wherein the signal pattern sensing circuit generates the multiple input signals based on switching states of the first even signal, the first odd signal, the second even signal, and the second odd signal at multiple time instances.

[0115] In Example 5, the subject matter of Examples 2-4 includes the following subject matter: wherein the one logic gate of the plurality of logic gates comprises a logical OR gate.

[0116] In Example 6, the subject matter of Example 5 includes the following subject matter: wherein the output of the first logical AND gate and the output of the second logical AND gate are coupled to the input of the logical OR gate.

[0117] In Example 7, the subject matter of Example 6 includes the following subject matter: wherein the logical OR gate generates the enable signal based on an output of the first logical AND gate and an output of the second logical AND gate.

[0118] In Example 8, the subject matter of Examples 1-7 includes the following subject matter: wherein the signal mode sensing circuit generates the enable signal when the first signal and the second signal switch in the same direction.

[0119] In Example 9, the subject matter of Examples 1-8 includes the following subject matter: wherein the XTC circuit includes a logic AND gate that receives the enable signal and a gain control signal.

[0120] In Example 10, the subject matter of Example 9 includes one or more additional XTC circuits coupled in parallel with the XTC circuit, wherein the gain control signal is used to enable or disable the one or more additional XTC circuits.

[0121] In Example 11, the subject matter of Example 10 includes each of the one or more additional XTC circuits including an additional buffer coupled to an additional capacitor, wherein the additional capacitor receives the second signal via the additional buffer.

[0122] In Example 12, the subject matter of Example 11 includes the subject matter wherein the one or more additional XTC circuits dynamically couple an output of the additional capacitor to a communication channel of the first signal based on the enable signal and the gain control signal.

[0123] In Example 13, the subject matter of Examples 9-12 includes the following subject matter: wherein the buffer includes at least two tri-state inverters coupled in parallel with each other, and wherein the at least two tri-state inverters drive the capacitor.

[0124] In Example 14, the subject matter of Example 13 includes an inverter, wherein the output of the logic AND gate is coupled to an input of the inverter and to n-channel metal-oxide-semiconductor (NMOS) transistors of the at least two tri-state inverters.

[0125] In Example 15, the subject matter of Example 14 includes the following subject matter: wherein the output of the inverter is coupled to p-channel metal-oxide-semiconductor (PMOS) transistors of the at least two tri-state inverters.

[0126] In Example 16, the subject matter of Example 15 includes the following subject matter: wherein the second signal includes an even signal and an odd signal, and wherein the device further includes a serializer to generate a serialized signal using the even signal and the odd signal.

[0127] In Example 17, the subject matter of Example 16 includes the subject matter wherein an output of the serializer is coupled to an input of one of the at least two tri-state inverters.

[0128] In Example 18, the subject matter of Example 17 includes the subject matter wherein the serialization signal is communicated to a gate terminal of an NMOS-PMOS transistor pair of one of the at least two tri-state inverters.

[0129] In Example 19, the subject matter of Examples 1-18 includes one or more interconnects coupled to the signal pattern sensing circuit and the XTC circuit.

[0130] In Example 20, the subject matter of Examples 1-19 includes the following subject matter: wherein the apparatus includes a processor, and wherein the processor includes the signal pattern sensing circuit and the XTC circuit.

[0131] In Example 21, the subject matter of Example 20 includes one or more interconnects coupling the signal pattern sensing circuit and the XTC circuit.

[0132] Example 22 is a system comprising a memory and at least one processor coupled to the memory, the at least one processor decoding a first signal comprising a first even signal and a first odd signal; decoding a second signal comprising a second even signal and a second odd signal; determining a switching pattern of the first signal and the second signal based on a switching state of each of the first even signal, the first odd signal, the second even signal, and the second odd signal at multiple time instances; generating an enable signal based on the switching pattern of the first signal and the second signal; and dynamically coupling an output of a capacitor to a communication channel of the first signal based on the enable signal, the capacitor receiving the second signal via a buffer.

[0133] In Example 23, the subject matter as described in Example 22 includes the following subject matter: wherein the at least one processor generates the enable signal at the output of a logic OR gate, the logic OR gate is coupled to the outputs of a first logic AND gate and a second logic AND gate, and the first logic AND gate and the second logic AND gate receive multiple input signals based on the first signal and the second signal.

[0134] In Example 24, the subject matter as described in Example 23 includes the following subject matter: wherein the at least one processor generates the multiple input signals based on the switching states of the first even signal, the first odd signal, the second even signal and the second odd signal at the multiple time instances.

[0135] In Example 25, the subject matter of Examples 22-24 includes subject matter wherein the at least one processor generates the enable signal when the switching pattern indicates that the first signal and the second signal switch in the same direction.

[0136] Example 26 is a method comprising: decoding a first signal comprising a first even signal and a first odd signal; decoding a second signal comprising a second even signal and a second odd signal; determining a switching pattern of the first signal and the second signal based on a switching state of each of the first even signal, the first odd signal, the second even signal, and the second odd signal at multiple time instances; generating an enable signal based on the switching pattern of the first signal and the second signal; and dynamically coupling an output of a capacitor to a communication channel of the first signal based on the enable signal, the capacitor receiving the second signal via a buffer.

[0137] In Example 27, the subject matter as described in Example 26 includes generating the enable signal at the output of a logic OR gate, the logic OR gate being coupled to the outputs of a first logic AND gate and a second logic AND gate, the first logic AND gate and the second logic AND gate receiving multiple input signals based on the first signal and the second signal.

[0138] In Example 28, the subject matter of Example 27 includes generating the plurality of input signals based on switching states of the first even signal, the first odd signal, the second even signal, and the second odd signal at the plurality of time instances.

[0139] In Example 29, the subject matter of Examples 26-28 includes generating the enable signal when the switching pattern indicates that the first signal and the second signal are switching in the same direction.

[0140] Example 30 is a device comprising: a first transmit (Tx) driver comprising an input terminal and an output terminal; a first three-state inverter coupled in series with a second three-state inverter; a first capacitor, wherein the input of the first capacitor is coupled to the output of the second three-state inverter and the output of the first capacitor is coupled to the output terminal of the first Tx driver; and a logic AND gate, wherein the output of the logic AND gate is coupled to the input of the first three-state inverter.

[0141] In Example 31, the subject matter of Example 30 includes: a second Tx driver including an input terminal and an output terminal, wherein the input terminal of the second Tx driver is coupled to the input of the first tri-state inverter.

[0142] In Example 32, the subject matter as described in Examples 30-31 includes a third three-state inverter coupled in series with a fourth three-state inverter and a second capacitor, wherein an input of the second capacitor is coupled to an output of the fourth three-state inverter and an output of the second capacitor is coupled to an output terminal of the first Tx driver.

[0143] In Example 33, the subject matter of Examples 30-32 includes mode-aware logic comprising a plurality of logic gates, wherein an output of the mode-aware logic is coupled to an input of the first tri-state inverter.

[0144] In Example 34, the subject matter as described in Example 33 includes the following subject matter: wherein the plurality of logic gates includes at least two logic AND gates coupled to a logic OR gate, and wherein the output of the logic OR gate is the output of the mode-aware logic.

[0145] Example 35 is an apparatus comprising means for performing a method as illustrated in any of the preceding claims.

[0146] Example 36 is a machine-readable storage device comprising machine-readable instructions which, when executed, cause a transceiver to implement a method as set forth in any preceding claim.

[0147] Example 37 is a machine-readable storage device comprising machine-readable instructions which, when executed, cause an equalization circuit to implement a method as set forth in any preceding claim.

[0148] Example 38 is a computer program comprising instructions which, when executed by a computer, cause the computer to perform a method as exemplified in any of the preceding claims.

[0149] Example 39 is at least one machine-readable medium comprising instructions that, when executed by a processing circuit, cause the processing circuit to perform operations to implement any of Examples 1-38.

[0150] Example 40 is an apparatus comprising means for implementing any of Examples 1-38.

[0151] Example 41 is a system for implementing any of Examples 1-38.

[0152] Example 42 is a method for implementing any of Examples 1-38.

[0153] The above description is intended to be illustrative, not restrictive. For example, the above examples (or one or more aspects thereof) may be used in combination with other examples. Other embodiments may be used, for example, by a person of ordinary skill in the art after viewing the above description. The abstract is used to allow the reader to quickly determine the nature of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. In addition, in the above detailed description, various features may be grouped to simplify the present disclosure. However, the claims may not record every feature disclosed herein, because the embodiments may be characterized by a subset of the features. In addition, the embodiments may include fewer features than those disclosed in a particular example. Thus, the attached claims are now incorporated into the detailed description, and a claim is independent as a separate embodiment. The scope of the embodiments disclosed herein should be determined with respect to the attached claims and the full range of equivalents to which such claims are entitled.

Claims

1. A device comprising: a signal pattern sensing circuit comprising a plurality of logic gates, the signal pattern sensing circuit receiving a first signal and a second signal and generating an enable signal at an output of one of the plurality of logic gates based on a switching pattern of the first signal and the second signal; as well as A crosstalk cancellation (XTC) circuit includes a buffer coupled to a capacitor, the capacitor receiving the second signal via the buffer, and the XTC circuit dynamically couples an output of the capacitor to a communication channel of the first signal based on the enable signal.

2. The device according to claim 1, wherein: The plurality of logic gates include a first logic AND gate and a second logic AND gate to receive a plurality of input signals based on the first signal and the second signal.

3. The device as claimed in claim 2, wherein: The first signal includes a first even signal and a first odd signal, and wherein the second signal includes a second even signal and a second odd signal.

4. The device as claimed in claim 3, wherein: The signal pattern sensing circuit is used to generate the plurality of input signals based on switching states of the first even signal, the first odd signal, the second even signal, and the second odd signal at a plurality of time instances.

5. The device according to claim 2, wherein: The one logic gate of the plurality of logic gates comprises a logical OR gate.

6. The device according to claim 5, wherein: An output of the first logical AND gate and an output of the second logical AND gate are coupled to an input of the logical OR gate.

7. The device according to claim 6, wherein: The logic OR gate generates the enable signal based on an output of the first logic AND gate and an output of the second logic AND gate.

8. The device according to any one of claims 1 to 7, wherein: The signal mode sensing circuit generates the enable signal when the first signal and the second signal switch in the same direction.

9. The device according to any one of claims 1 to 7, wherein: The XTC circuit includes a logic AND gate that receives the enable signal and a gain control signal.

10. The apparatus of claim 9, further comprising one or more additional XTC circuits coupled in parallel with the XTC circuit, wherein: The gain control signal is used to enable or disable the one or more additional XTC circuits.

11. The device of claim 10, wherein: Each of the one or more additional XTC circuits includes an additional buffer coupled to an additional capacitor, and wherein the additional capacitor receives the second signal via the additional buffer.

12. The device of claim 11, wherein: The one or more additional XTC circuits dynamically couple an output of the additional capacitor to a communication channel of the first signal based on the enable signal and the gain control signal.

13. The device of claim 9, wherein: The buffer includes at least two tri-state inverters coupled in parallel to each other, and wherein the at least two tri-state inverters drive the capacitor.

14. The device of claim 13, further comprising an inverter, wherein: The output of the logic AND gate is coupled to the input of the inverter and to n-channel metal-oxide-semiconductor (NMOS) transistors of the at least two tri-state inverters.

15. The device of claim 14, wherein: An output of the inverter is coupled to p-channel metal-oxide-semiconductor (PMOS) transistors of the at least two tri-state inverters.

16. The device of claim 15, wherein: The second signal includes an even signal and an odd signal, and wherein the apparatus further includes a serializer for generating a serialized signal using the even signal and the odd signal.

17. The device of claim 16, wherein: The output of the serializer is coupled to the input of one of the at least two tri-state inverters.

18. A system comprising: Memory; as well as at least one processor coupled to the memory, the at least one processor configured to: decoding a first signal including a first even signal and a first odd signal; decoding a second signal including a second even signal and a second odd signal; determining a switching pattern of the first signal and the second signal based on a switching state of each of the first even signal, the first odd signal, the second even signal, and the second odd signal at a plurality of time instances; generating an enable signal based on a switching pattern of the first signal and the second signal; and An output of a capacitor is dynamically coupled to a communication channel of the first signal based on the enable signal, the capacitor being configured to receive the second signal via a buffer.

19. The system of claim 18, wherein: The at least one processor is configured to: The enable signal is generated at an output of a logic OR gate coupled to outputs of a first logic AND gate and a second logic AND gate that receive a plurality of input signals based on the first signal and the second signal.

20. The system of claim 19, wherein: The at least one processor is configured to: The plurality of input signals are generated based on switching states of the first even signal, the first odd signal, the second even signal, and the second odd signal at the plurality of time instances.

21. The system of any one of claims 18 to 20, wherein: The at least one processor is configured to: The enable signal is generated when the switching pattern indicates that the first signal and the second signal are switching in the same direction.

22. A method comprising: decoding a first signal including a first even signal and a first odd signal; decoding a second signal including a second even signal and a second odd signal; determining a switching pattern of the first signal and the second signal based on a switching state of each of the first even signal, the first odd signal, the second even signal, and the second odd signal at a plurality of time instances; generating an enable signal based on a switching pattern of the first signal and the second signal; and An output of a capacitor is dynamically coupled to a communication channel of the first signal based on the enable signal, the capacitor receiving the second signal via a buffer.

23. The method of claim 22, further comprising: The enable signal is generated at an output of a logic OR gate coupled to outputs of a first logic AND gate and a second logic AND gate that receive a plurality of input signals based on the first signal and the second signal.

24. The method of claim 23, further comprising: The plurality of input signals are generated based on switching states of the first even signal, the first odd signal, the second even signal, and the second odd signal at the plurality of time instances.

25. The method of any one of claims 22 to 24, further comprising: The enable signal is generated when the switching pattern indicates that the first signal and the second signal are switching in the same direction.

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