Inter-chip communication system and inter-chip communication method thereof
By introducing inter-core communication units into the integrated circuit, inter-chip communication is allowed between processors, the problem of inter-chip communication in cascaded multiple integrated circuits is solved, efficient communication is achieved and the hardware structure remains unchanged.
Patent Information
- Application Number
- CN202411744925.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-11-29
- Publication Date
- 2025-03-25
AI Technical Summary
In the field of intelligent driving, when multiple integrated circuits are cascaded, how to achieve inter-chip communication between integrated circuits is an urgent problem to be solved.
By introducing an inter-core communication unit into each integrated circuit, direct inter-chip communication between processors is allowed. The specific steps include the first processor determining the second processor communicating with it, and transmitting data through the inter-core communication unit in the second integrated circuit, the second processor reading data from the inter-core communication unit, and sending a response message through the inter-core communication unit in the first integrated circuit.
Interchip communication between processors in different integrated circuits is realized, communication efficiency between multiple integrated circuits is improved, and communication can be achieved only by changing the communication protocol without changing the cascade chip hardware structure.
Smart Images
Figure CN119690900A_ABST
Abstract
Description
Technical Field
[0001] The present disclosure relates to the technical field of integrated circuits, and in particular to an inter-chip communication system and an inter-chip communication method thereof. Background Art
[0002] In the field of intelligent driving, if the computing power of a single integrated circuit does not meet the demand, multiple integrated circuits can be cascaded to increase the computing power. However, when multiple integrated circuits are cascaded, how to communicate between multiple integrated circuits is an urgent problem to be solved. Summary of the invention
[0003] In order to solve the above technical problems, the present disclosure provides an inter-chip communication system and an inter-chip communication method thereof to solve the problem of inter-chip communication between multiple integrated circuits.
[0004] A first aspect of the present disclosure provides an inter-chip communication method for an integrated circuit, comprising: a first processor in a first integrated circuit determines a second processor in a second integrated circuit for inter-chip communication with the first processor; the first processor transmits inter-chip communication data to the second processor based on a first inter-core communication unit in the second integrated circuit; the second processor reads the inter-chip communication data from the first inter-core communication unit; the second processor transmits a response message to the first processor based on the second inter-core communication unit in the first integrated circuit; the response message is used to indicate that the second processor has read the inter-chip communication data.
[0005] According to a second aspect of the present disclosure, there is provided an inter-chip communication system, comprising: a first integrated circuit and a second integrated circuit cascaded with the first integrated circuit, the first integrated circuit comprising a first processor and a second inter-core communication unit, the second integrated circuit comprising a second processor and the first inter-core communication unit; wherein the first processor is used to determine the second processor for inter-chip communication with the first processor; transmit inter-chip communication data to the second processor based on the first inter-core communication unit; the second processor is used to read the inter-chip communication data from the first inter-core communication unit; transmit a response message to the first processor based on the second inter-core communication unit; the response message is used to indicate that the second processor has read the inter-chip communication data.
[0006] In a third aspect of the present disclosure, an embodiment proposes an electronic device, comprising: a processor; a memory for storing executable instructions of the processor; the processor is configured to read the executable instructions from the memory and execute the instructions to implement the inter-chip communication method of the integrated circuit described in the first aspect above; or, the electronic device comprises the inter-chip communication system described in the second aspect above.
[0007] In a fourth aspect of the present disclosure, an embodiment provides a computer-readable storage medium, wherein the storage medium stores a computer program, and the computer program is used to execute the inter-chip communication method of the integrated circuit described in the first aspect.
[0008] In a fifth aspect of the present disclosure, an embodiment proposes a computer program product. When an instruction processor in the computer program product executes, the inter-chip communication method proposed in the embodiment of the first aspect of the present disclosure is executed.
[0009] In the inter-chip communication method of the integrated circuit provided by the embodiment of the present disclosure, when inter-chip communication is performed between two processors in different integrated circuits, since the first processor in the first integrated circuit can transmit inter-chip communication data to the second processor in the second integrated circuit based on the inter-core communication unit in the second integrated circuit, the second processor can read the inter-chip communication data from the inter-core communication unit in the second integrated circuit, and transmit a response message to the first processor based on the inter-core communication unit in the first integrated circuit. That is, the two processors in different integrated circuits in the present disclosure can respectively perform inter-chip communication through the inter-core communication units in the two integrated circuits. In other words, the present disclosure can realize inter-chip communication between two integrated circuits by utilizing the inter-core communication unit in the integrated circuit, without changing the hardware structure of the cascade chip, only by changing the communication protocol of the inter-chip communication. BRIEF DESCRIPTION OF THE DRAWINGS
[0010] Figure 1A It is a structural diagram of an inter-chip communication system provided by an exemplary embodiment of the present disclosure.
[0011] Figure 1B It is a structural diagram of an inter-chip communication system provided by another exemplary embodiment of the present disclosure.
[0012] Figure 2 The figure is a flow chart of an inter-chip communication method of an integrated circuit provided by an exemplary embodiment of the present disclosure.
[0013] Figure 3 It is a flowchart of an inter-chip communication method of an integrated circuit provided by another exemplary embodiment of the present disclosure.
[0014] Figure 4 It is a flowchart of an inter-chip communication method of an integrated circuit provided by yet another exemplary embodiment of the present disclosure.
[0015] Figure 5 It is a flowchart of an inter-chip communication method of an integrated circuit provided by yet another exemplary embodiment of the present disclosure.
[0016] Figure 6It is a flowchart of an inter-chip communication method of an integrated circuit provided by yet another exemplary embodiment of the present disclosure.
[0017] Figure 7 is a structural diagram of an electronic device provided by an exemplary embodiment of the present disclosure. DETAILED DESCRIPTION
[0018] To explain the present disclosure, example embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present disclosure, rather than all of the embodiments. It should be understood that the present disclosure is not limited to the example embodiments.
[0019] It should be noted that the relative arrangement of components and steps, the numerical expressions and numerical values set forth in these embodiments do not limit the scope of the present disclosure unless specifically stated otherwise.
[0020] Application Overview
[0021] In the field of intelligent driving, environmental information around the vehicle can be collected through sensors installed in the vehicle, and the driving of the vehicle can be planned and controlled based on the collected environmental information. Usually, in intelligent driving scenarios, the amount of data that needs to be processed is large, and the computing power of the chip is required to be high. If the computing power of a single integrated circuit does not meet the usage requirements, then multiple integrated circuits can be cascaded to increase the computing power.
[0022] Generally, processors in an integrated circuit can communicate with each other through an inter-processor communications module (IPCM). However, when two integrated circuits are cascaded, how to communicate between processors in the two integrated circuits becomes an urgent problem to be solved.
[0023] Based on the above technical problems, an embodiment of the present disclosure provides an inter-chip communication method of an integrated circuit. When inter-chip communication is performed between two processors in different integrated circuits, since the first processor in the first integrated circuit can transmit inter-chip communication data to the second processor in the second integrated circuit based on the inter-core communication unit in the second integrated circuit, the second processor can read the inter-chip communication data from the inter-core communication unit of the second integrated circuit, and transmit a response message to the first processor based on the inter-core communication unit in the first integrated circuit. That is, the two processors in different integrated circuits in the present disclosure can respectively perform inter-chip communication through the inter-core communication units in the two integrated circuits. In other words, the present disclosure can realize inter-chip communication between two integrated circuits by utilizing the inter-core communication unit in the integrated circuit, without changing the hardware structure of the cascade chip, only by changing the communication protocol of the inter-chip communication.
[0024] Exemplary Systems
[0025] Figure 1A FIG. 1 is a schematic diagram of the structure of an inter-chip communication system provided by an exemplary embodiment of the present disclosure. Figure 1A As shown, the inter-chip communication system 100 may include: a first integrated circuit 101, and a second integrated circuit 102 cascaded with the first integrated circuit 101. Exemplarily, the first integrated circuit 101 and the second integrated circuit 102 may be two different chips, such as the first integrated circuit 101 and the second integrated circuit 102 may be two cascaded system-on-chips (System on Chip, SOC).
[0026] Among them, Figure 1A As shown, the first integrated circuit 101 includes a first processor 1011 and a second inter-core communication unit 1012 , and the second integrated circuit 102 includes a second processor 1021 and a first inter-core communication unit 1022 .
[0027] The first processor 1011 is configured to determine a second processor 1021 that performs inter-chip communication with the first processor 1011 ; and transmit inter-chip communication data to the second processor 1021 based on the first inter-core communication unit 1022 .
[0028] The second processor 1021 is used to read the inter-chip communication data from the first inter-core communication unit 1022; and transmit a response message to the first processor 1011 based on the second inter-core communication unit 1012; wherein the response message is used to indicate that the second processor 1021 has read the inter-chip communication data.
[0029] In some examples, the inter-chip communication system 100 may further include more integrated circuits cascaded with the first integrated circuit 101 and the second integrated circuit 102, such as a third integrated circuit, a fourth integrated circuit, etc., which is not limited in the embodiments of the present disclosure. Figure 1A An example is given for the inter-chip communication system 100 including two integrated circuits. When the inter-chip communication system 100 includes more integrated circuits, the inter-chip communication between any two integrated circuits in the inter-chip communication system 100 is similar to the inter-chip communication between the first integrated circuit 101 and the second integrated circuit 102, and the present disclosure does not limit this.
[0030] In some embodiments, the first integrated circuit may further include a first communication interface, and the second integrated circuit may further include a second communication interface, and the first communication interface of the first integrated circuit and the second communication interface of the second integrated circuit may be connected via a communication bus. It should be noted that the first communication interface and the second communication interface may be hardware interfaces (Hardware Software Interface, HSI).
[0031] For example, Figure 1B As shown, the first integrated circuit 101 further includes a first communication interface 1013, and the second integrated circuit 102 further includes a second communication interface 1023. The first communication interface 1013 and the second communication interface 1023 are connected via a communication bus, so that the first integrated circuit 101 and the second integrated circuit 102 are cascaded.
[0032] Exemplarily, the first communication interface and the second communication interface may be an Ethernet communication interface (Ethernet, Eth), a high-speed serial computer expansion bus interface or other high-speed peripheral communication interface (Peripheral Component Interconnect Express, PCIe), etc. It is understandable that the first communication interface and the second communication interface are communication interfaces of the same interface type, and the communication bus is related to the interface type of the first communication interface and the second communication interface.
[0033] Exemplarily, when the first communication interface and the second communication interface are Ethernet communication interfaces, the communication bus is an Ethernet bus, that is, the first integrated circuit and the second integrated circuit are connected to the first communication interface and the second communication interface through the Ethernet bus; when the first communication interface and the second communication interface are high-speed serial computer expansion bus interfaces, the communication bus is a high-speed serial computer expansion bus, that is, the first integrated circuit and the second integrated circuit are connected to the first communication interface and the second communication interface through the high-speed serial computer expansion bus.
[0034] In some embodiments, the first integrated circuit may further include a first system bus, and the first processor, the first communication interface, and the second inter-core communication unit in the first integrated circuit may be connected together through the first system bus.
[0035] For example, Figure 1B As shown, the first processor 1011 and the second inter-core communication unit 1012 are connected via the first system bus 1014, the first processor 1011 and the first communication interface 1013 are connected via the first system bus 1014, and the second inter-core communication unit 1012 and the first communication interface 1013 are connected via the first system bus 1014. In this way, the first processor, the first communication interface, and the second inter-core communication unit can transmit data via the first system bus.
[0036] In some embodiments, the second integrated circuit may further include a second system bus, and the second processor, the second communication interface and the first inter-core communication unit in the second integrated circuit may also be connected together through the second system bus.
[0037] For example, Figure 1BAs shown, the second integrated circuit 102 also includes a second system bus 1024 as an example. The second processor 1021 and the first inter-core communication unit 1022 are connected via the second system bus 1024, the second processor 1021 and the second communication interface 1023 are connected via the second system bus 1024, and the first inter-core communication unit 1022 and the second communication interface 1023 are connected via the second system bus 1024. In this way, the second processor, the second communication interface and the first inter-core communication unit can transmit data via the second system bus.
[0038] In some embodiments, Figure 1A As shown, the first processor 1011 is specifically used to transmit inter-chip communication data to the first inter-core communication unit 1022, and send a first interrupt signal to the second processor 1021 through the first inter-core communication unit 1022; the second processor 1021 is specifically used to read the inter-chip communication data from the first inter-core communication unit 1022 in response to receiving the first interrupt signal.
[0039] In some embodiments, the first processor 1011 is specifically used to write inter-chip communication data in the first register of the first inter-core communication unit 1022, and based on the identification information of the second processor 1021, configure the parameters of multiple second registers in the first inter-core communication unit 1022 to trigger the first inter-core communication unit to generate a first interrupt signal; the first inter-core communication unit 1022 can be used to send the first interrupt signal to the second processor 1021 through the first communication channel.
[0040] Exemplarily, the first register is a register for storing inter-chip communication data; the plurality of second registers may include: a register for configuring a sender of the inter-chip communication data, a register for configuring a receiver of the inter-chip communication data, a register for triggering a first interrupt signal, and a register for configuring a first communication channel. By configuring the parameters of the plurality of second registers in the first inter-core communication unit, the first inter-core communication unit may generate a first interrupt signal and send the first interrupt signal to the second processor through the first communication channel.
[0041] The first inter-core communication unit may include multiple communication channels, and the first communication channel is a communication channel pre-allocated to the first processor among the multiple communication channels of the first inter-core communication unit. In some examples, the communication channel may be a mailbox channel. When the first processor communicates with the second processor between chips, the first processor configures multiple second registers so that the first inter-core communication unit can generate a first interrupt signal, and sends the first interrupt signal to the second processor through the first communication channel.
[0042] In some examples, the multiple second registers in the first inter-core communication unit 1022 include registers 1 to 3 as an example, wherein register 1 is a register for configuring the sender of inter-chip communication data, register 2 is a register for configuring the receiver of inter-chip communication data, and register 3 is a register for triggering a first interrupt signal. When the first processor communicates with the second processor, it can configure the sender of the inter-chip communication data through register 1, configure the receiver of the inter-chip communication data through register 2, and trigger the first interrupt signal through register 3.
[0043] For example, Figure 1A As shown, the first processor 1011 can write the identification information "1" of the first processor 1011 in register 1 to indicate that the inter-chip communication data is sent by the first processor 1011; the first processor 1011 can write the identification information "2" of the second processor 1021 in register 2 to indicate that the inter-chip communication data is received by the second processor 1021; the first processor 1011 can write the configuration information "0" for triggering the first interrupt signal in register 3 to trigger the first interrupt signal.
[0044] In some embodiments, Figure 1B As shown, take the example that the first integrated circuit 101 includes the first communication interface 1013 and the second integrated circuit 102 includes the second communication interface 1023. The first processor 1011 can write inter-chip communication data in the first register of the first inter-core communication unit 1022 through the first communication interface 1013 and the second communication interface 1023, and configure the parameters of multiple second registers in the first inter-core communication unit 1022 through the first communication interface 1013 and the second communication interface 1023 based on the identification information of the second processor 1021, so as to trigger the first inter-core communication unit to generate a first interrupt signal; the first inter-core communication unit 1022 sends the first interrupt signal to the second processor 1021 through the first communication channel.
[0045] In some embodiments, Figure 1B As shown, the second processor 1021 may also write configuration information for clearing the first interrupt signal into the first interrupt register in the first inter-core communication unit 1022 to clear the first interrupt signal.
[0046] In some embodiments, the second processor is specifically used to configure the parameters of multiple third registers in the second inter-core communication unit 1012 based on the identification information of the first processor to trigger the second inter-core communication unit to generate a second interrupt signal; the second inter-core communication unit 1012 is used to send a second interrupt signal to the first processor 1011 through a second communication channel; wherein the response message includes the second interrupt signal; the first processor 1011 is also used to determine, based on the second interrupt signal, that the second processor 1021 has read the inter-chip communication data.
[0047] Exemplarily, the plurality of third registers may include: a register for configuring a recipient of the second interrupt signal, and a register for triggering the second interrupt signal. By configuring the parameters of the plurality of third registers in the second inter-core communication unit, the second inter-core communication unit may generate a second interrupt signal and send the second interrupt signal to the first processor through the second communication channel.
[0048] The second inter-core communication unit may include multiple communication channels, and the second communication channel is a communication channel pre-allocated to the second processor among the multiple communication channels. When the second processor performs inter-chip communication with the first processor, the second processor configures multiple third registers so that the second inter-core communication unit can generate a second interrupt signal, and sends the second interrupt signal to the first processor through the second communication channel.
[0049] In some examples, the multiple second registers in the second inter-core communication unit include register A and register B as an example; wherein register A is a register for configuring the recipient of the second interrupt signal, and register B is a register for triggering the second interrupt signal. When the second processor communicates with the first processor, the second processor can configure the recipient of the second interrupt signal through register A and trigger the second interrupt signal through register B.
[0050] For example, Figure 1B As shown, the second processor 1021 can write the identification information "1" of the first processor 1011 in register A to indicate that the second interrupt signal is sent to the first processor 1011; the second processor 1021 can write the configuration information "0" for triggering the second interrupt signal in register B to trigger the second interrupt signal.
[0051] In some embodiments, Figure 1BAs shown, take the example that the first integrated circuit 101 includes the first communication interface 1013 and the second integrated circuit 102 includes the second communication interface 1023. The second processor 1021 can configure the parameters of the multiple third registers in the second inter-core communication unit 1012 through the first communication interface 1013 and the second communication interface 1023 based on the identification information of the first processor 1011 to trigger the second inter-core communication unit to generate a second interrupt signal; the second inter-core communication unit 1012 can send the second interrupt signal to the first processor 1011 through the second communication channel; the first processor 1011 can also determine that the second processor 1021 has read the inter-chip communication data based on the second interrupt signal.
[0052] In some embodiments, Figure 1B As shown, the first processor 1011 may also write configuration information for clearing the second interrupt signal into the second interrupt register in the second inter-core communication unit 1012 to clear the second interrupt signal.
[0053] In the inter-chip communication system provided by the embodiment of the present disclosure, the first processor in the first integrated circuit can transmit inter-chip communication data to the second processor in the second integrated circuit through the inter-core communication unit in the second integrated circuit, and the second processor in the second integrated circuit can also transmit a response message to the first processor in the first integrated circuit through the inter-core communication unit in the first integrated circuit. That is, when two processors in different integrated circuits in the present disclosure perform inter-chip communication, the processor in one integrated circuit can perform inter-chip communication with the processor in the other integrated circuit through the inter-core communication unit in the other integrated circuit. Therefore, the present disclosure can realize inter-chip communication between two integrated circuits by utilizing the inter-core communication unit in the integrated circuit without changing the hardware structure of the cascade chip, only by changing the communication protocol of the inter-chip communication. Moreover, the present disclosure can quickly read the inter-chip communication data by sending an interrupt signal, thereby improving the efficiency of inter-chip communication between the two integrated circuits.
[0054] Furthermore, when processors of different integrated circuits in the present disclosure communicate with each other, inter-chip communication is achieved through different communication channels in the first inter-core communication unit and the second inter-core communication unit. Since the first inter-core communication unit and the second inter-core communication unit are inter-core communication units in different integrated circuits, it is possible to ensure that different communications are not affected by each other and to improve the efficiency of inter-chip communication.
[0055] In addition, since the present disclosure directly reuses the inter-core communication unit used for inter-core communication between two processors on a chip in the inter-chip communication between two integrated circuits, and no other hardware units are added to the integrated circuit, the chip area overhead is not increased and the chip production cost is saved.
[0056] Exemplary Methods
[0057] Figure 2 FIG. 1 is a flow chart of an integrated circuit inter-chip communication method provided by an exemplary embodiment of the present disclosure. Figure 1A or Figure 1B The inter-chip communication system shown in FIG. 1 , or applied to the above-mentioned Figure 1A or Figure 1B The inter-chip communication system shown in the electronic device, such as Figure 2 As shown, the method may include the following steps:
[0058] Step 201: A first processor in a first integrated circuit determines a second processor in a second integrated circuit that performs inter-chip communication with the first processor.
[0059] In some embodiments, the first integrated circuit and the second integrated circuit may be two cascaded system-on-chips (System on Chip, SOC). The first integrated circuit may include at least one processor, and the at least one processor may include a first processor; the second integrated circuit may include at least one processor, and the at least one processor may include a second processor. The embodiment of the present disclosure does not limit the number of processors included in the first integrated circuit and the second integrated circuit.
[0060] In some embodiments, the first processor and the second processor may be any of the following: a central processing unit, an image processor, a neural network processor, etc. The disclosed embodiment does not limit the types of the first processor and the second processor. For example, the types of the first processor and the second processor may be the same or different.
[0061] Exemplarily, the first processor is a central processing unit, and the second processor is an image processor; or, the first processor is a central processing unit, and the second processor is also a central processing unit.
[0062] In some embodiments, a first processor in a first integrated circuit may determine information of a processor that performs inter-chip communication with the first processor. When the first processor determines that it needs to communicate with a second processor in a second integrated circuit, the first processor may serve as a sender of inter-chip communication data, and the second processor may serve as a receiver of inter-chip communication data.
[0063] Step 202: The first processor transmits inter-chip communication data to the second processor based on a first inter-core communication unit in a second integrated circuit.
[0064] In some embodiments, the second integrated circuit may include one inter-core communication unit or multiple inter-core communication units. The embodiment of the present disclosure does not limit the number of inter-core communication units included in the second integrated circuit. When the second integrated circuit includes only one inter-core communication unit, the inter-core communication unit is the first inter-core communication unit; when the second integrated circuit includes multiple inter-core communication units, the first inter-core communication unit is the inter-core communication unit corresponding to the second processor among the multiple inter-core communication units.
[0065] For example, the second integrated circuit includes processor 1, processor 2, processor 3, IPCM1, IPCM2 and IPCM3, where processor 1 corresponds to IPCM1, processor 2 corresponds to IPCM2, and processor 3 corresponds to IPCM3. When the second processor is processor 1, the first inter-core communication unit is IPCM1; when the second processor is processor 2, the first inter-core communication unit is IPCM2; when the second processor is processor 3, the first inter-core communication unit is IPCM3.
[0066] In some embodiments, the inter-chip communication data can be data obtained by the first processor from a sensor, register or external device, or it can be data processed by the first processor. The embodiments of the present disclosure are not limited to this. The inter-chip communication data can be any type of data that needs to be transmitted to the second processor.
[0067] In some embodiments, the first processor may process the data collected by the sensor, use the processed data as inter-chip communication data, and transmit the inter-chip communication data to the second processor based on the first inter-core communication unit in the second integrated circuit.
[0068] In some examples, the first processor transmits inter-chip communication data to the second processor based on the first inter-core communication unit in the second integrated circuit. The first processor can transmit the inter-chip communication data to the first inter-core communication unit through a first communication interface in the first integrated circuit and a second communication interface in the second integrated circuit, so that the second processor can read the inter-chip communication data from the first inter-core communication unit.
[0069] For example, Figure 1B As shown, the first processor 1011 can transmit the inter-chip communication data to the first inter-core communication unit 1022 through the first communication interface 1013 and the second communication interface 1023 , so that the second processor 1021 reads the inter-chip communication data from the first inter-core communication unit 1022 .
[0070] Step 203: The second processor reads inter-chip communication data from the first inter-core communication unit.
[0071] In some embodiments, when the first processor writes inter-chip communication data into the first inter-core communication unit, the first inter-core communication unit may notify the second processor, and in response to the notification the second processor may read the inter-chip communication data in the first inter-core communication unit.
[0072] In some embodiments, the first inter-core communication unit may include a register for storing inter-chip communication data, and the second processor may read the inter-chip communication data from the register for storing inter-chip communication data in the first inter-core communication unit.
[0073] Step 204: The second processor transmits a response message to the first processor based on the second inter-core communication unit in the first integrated circuit.
[0074] The response message is used to indicate that the second processor has read the inter-chip communication data.
[0075] In some embodiments, the first integrated circuit may include only one inter-core communication unit or multiple inter-core communication units. The embodiment of the present disclosure does not limit the number of inter-core communication units included in the first integrated circuit. When the first integrated circuit includes only one inter-core communication unit, the inter-core communication unit is the second inter-core communication unit; when the second integrated circuit includes multiple inter-core communication units, the second inter-core communication unit is the inter-core communication unit corresponding to the first processor among the multiple inter-core communication units.
[0076] Exemplarily, the first integrated circuit includes processor A, processor B, processor C, IPCMA, and IPCMB, where processor A and processor B correspond to IPCMA, and processor C corresponds to IPCMB. When the first processor is processor A, the second inter-core communication unit is IPCMA; when the first processor is processor B, the second inter-core communication unit is IPCMA; when the first processor is processor C, the second inter-core communication unit is IPCMB.
[0077] In some embodiments, the second processor may configure the second inter-core communication unit through the second communication interface in the second integrated circuit and the first communication interface in the first integrated circuit to transmit the response message to the first processor.
[0078] For example, Figure 1B As shown, the second integrated circuit includes the second communication interface 1023 and the first integrated circuit includes the first communication interface 1013. The second processor 1021 can configure the second inter-core communication unit 1012 through the second communication interface 1023 and the first communication interface 1013, so that the second inter-core communication unit 1012 transmits a response message to the first processor 1011.
[0079] In the inter-chip communication method of the integrated circuit provided by the embodiment of the present disclosure, when inter-chip communication is performed between two processors in different integrated circuits, since the first processor in the first integrated circuit can transmit inter-chip communication data to the second processor in the second integrated circuit based on the inter-core communication unit in the second integrated circuit, the second processor can read the inter-chip communication data from the inter-core communication unit of the second integrated circuit, and transmit a response message to the first processor based on the inter-core communication unit in the first integrated circuit. That is, in the present disclosure, when two processors in different integrated circuits perform inter-chip communication, the processor in one integrated circuit can perform inter-chip communication with the processor in the other integrated circuit through the inter-core communication unit in the other integrated circuit. Therefore, inter-chip communication between two integrated circuits can be achieved by only changing the communication protocol of inter-chip communication without changing the hardware structure of the cascade chip.
[0080] like Figure 3 As shown in the above Figure 2 Based on the illustrated embodiment, step 202 may include the following steps; accordingly, step 203 may include the following step 2031:
[0081] Step 2021: The first processor transmits inter-chip communication data to the first inter-core communication unit, and sends a first interrupt signal to the second processor through the first inter-core communication unit.
[0082] In some embodiments, the first processor first transmits inter-chip communication data to the first inter-core communication unit, and after the inter-chip communication data transmission is completed (for example, the last frame of inter-chip communication data transmission is completed), sends a first interrupt signal to the second processor through the first inter-core communication unit.
[0083] In some embodiments, the first interrupt signal is used to notify the second processor to read the inter-chip communication data from the first inter-core communication unit.
[0084] For example, Figure 1A As shown, the cascade connection of the first integrated circuit 101 and the second integrated circuit 102 is taken as an example. After the first processor 1011 transmits inter-chip communication data to the first inter-core communication unit 1022 , the first interrupt signal may be sent to the second processor 1021 through the first inter-core communication unit 1022 .
[0085] In some embodiments, the first processor can transmit inter-chip communication data to the first inter-core communication unit through the first communication interface in the first integrated circuit and the second communication interface in the second integrated circuit, and configure the first inter-core communication unit through the first communication interface and the second communication interface so that the first inter-core communication unit sends a first interrupt signal to the second processor.
[0086] For example, Figure 1BAs shown, the first processor 1011 transmits inter-chip communication data to the first inter-core communication unit 1022 through the first communication interface 1013 and the second communication interface 1023, and configures the first inter-core communication unit 1022 through the first communication interface 1013 and the second communication interface 1023 so that the first inter-core communication unit 1022 sends a first interrupt signal to the second processor 1021.
[0087] In some embodiments, the above step 2021 includes: the first processor writes inter-chip communication data in the first register of the first inter-core communication unit; the first processor configures the parameters of multiple second registers in the first inter-core communication unit based on the identification information of the second processor to trigger the first inter-core communication unit to generate a first interrupt signal; the first inter-core communication unit sends the first interrupt signal to the second processor through the first communication channel.
[0088] For example, Figure 1B As shown, the first processor 1011 can write inter-chip communication data in the first register of the first inter-core communication unit 1022 through the first communication interface 1013 in the first integrated circuit 101 and the second communication interface 1023 in the second integrated circuit 102; and based on the identification information of the second processor 1021, configure the parameters of multiple second registers in the first inter-core communication unit 1022 through the first communication interface 1013 and the second communication interface 1023 to trigger the first inter-core communication unit to generate a first interrupt signal; the first inter-core communication unit 1022 can send the first interrupt signal to the second processor 1021 through the first communication channel.
[0089] Exemplarily, the identification information of the second processor is information used to identify the second processor; the identification information may be a device name, number or serial number of the second processor or other information that can uniquely identify the second processor.
[0090] Exemplarily, the first register is a register for storing inter-chip communication data; the plurality of second registers may include: a register for configuring a sender of the inter-chip communication data, a register for configuring a receiver of the inter-chip communication data, and a register for triggering a first interrupt signal. By configuring the parameters of the plurality of second registers in the first inter-core communication unit, the first inter-core communication unit may generate a first interrupt signal and send the first interrupt signal to the second processor through the first communication channel.
[0091] The first inter-core communication unit may include multiple communication channels, and the first communication channel is a communication channel pre-allocated to the first processor among the multiple communication channels. When the first processor communicates with the second processor between chips, the first processor configures multiple second registers so that the first inter-core communication unit can generate a first interrupt signal, and sends the first interrupt signal to the second processor through the first communication channel.
[0092] In some examples, taking the multiple second registers in the first inter-core communication unit 1022 including registers 1 to 3 as an example, when the first processor communicates with the second processor, it can configure the sender of the inter-chip communication data through register 1, configure the receiver of the inter-chip communication data through register 2, and trigger the first interrupt signal by configuring register 3.
[0093] For example, Figure 1A As shown, the first processor 1011 can write the identification information "1" of the first processor 1011 in register 1 to indicate that the inter-chip communication data is sent by the first processor 1011; the first processor 1011 can write the identification information "2" of the second processor 1021 in register 2 to indicate that the inter-chip communication data is received by the second processor 1021; the first processor 1011 can write the configuration information "0" for triggering the first interrupt signal in register 3 to trigger the first interrupt signal.
[0094] Step 2031: In response to receiving the first interrupt signal, the second processor reads inter-chip communication data from the first inter-core communication unit.
[0095] In some examples, in response to receiving the first interrupt signal, the second processor may read the inter-chip communication data from the first register in the first inter-core communication unit.
[0096] In some embodiments, since the multiple second registers include a register for configuring the sender of inter-chip communication data, when the second processor reads the inter-chip communication data from the first register in the first inter-core communication unit, the second processor can determine that the inter-chip communication data is sent by the first processor.
[0097] In the inter-chip communication method provided by the embodiment of the present application, since the first processor can transmit inter-chip communication data to the first inter-core communication unit and send a first interrupt signal to the second processor through the first inter-core communication unit, the second processor can respond to the received first interrupt signal and quickly read the inter-chip communication data from the first inter-core communication unit, thereby improving the efficiency of inter-chip communication between the first integrated circuit and the second integrated circuit. In addition, the first processor can configure the parameters of multiple second registers in the first inter-core communication unit to send the first interrupt signal to the second processor through the first communication channel.
[0098] like Figure 4 As shown in the above Figure 3 Based on the embodiment shown, the following steps may also be included:
[0099] Step 205: The second processor writes configuration information for clearing the first interrupt signal into the first interrupt register in the first inter-core communication unit to clear the first interrupt signal.
[0100] In some embodiments, the first interrupt register is a register used to trigger the first interrupt signal among the plurality of second registers in the above embodiments. The purpose of clearing the first interrupt signal can be achieved by writing configuration information used to clear the first interrupt signal in the first interrupt register.
[0101] In some examples, the second processor can clear the first interrupt signal by writing preset information in the first interrupt register. For example, the second processor can write configuration information "1" for clearing the first interrupt signal in the first interrupt register to clear the first interrupt signal.
[0102] In some embodiments, after the second processor reads the inter-chip communication data from the first inter-core communication unit, if the first interrupt signal needs to be cleared, the second processor can write configuration information for clearing the first interrupt signal in the first interrupt register in the first inter-core communication unit to clear the first interrupt signal.
[0103] For example, Figure 1B As shown, the second processor 1021 writes “1” in the first interrupt register in the first inter-core communication unit 1022 to clear the first interrupt signal, so that the first inter-core communication unit 1022 will no longer send the first interrupt signal to the second processor 1021.
[0104] In the inter-chip communication method provided by the embodiment of the present application, the second processor in the second integrated circuit can write configuration information for clearing the first interrupt signal in the first interrupt register in the first inter-core communication unit to clear the first interrupt signal. By clearing the first interrupt signal by the second processor, it is possible to avoid the first inter-core communication unit sending interrupt signals to the second processor multiple times, and avoid the second integrated circuit from crashing or abnormal problems due to being unable to handle too many interrupts, thereby improving the stability of the second integrated circuit.
[0105] like Figure 5 As shown in the above Figure 2 Based on the illustrated embodiment, step 204 may include the following steps:
[0106] Step 2041: The second processor configures parameters of a plurality of third registers in the second inter-core communication unit based on the identification information of the first processor to trigger the second inter-core communication unit to generate a second interrupt signal.
[0107] Exemplarily, the identification information of the first processor is information used to identify the first processor; the identification information may be a device name, number or serial number of the first processor or other information that uniquely identifies the first processor.
[0108] Exemplarily, the plurality of third registers in the second inter-core communication unit may include: a register for configuring a recipient of the second interrupt signal and a register for triggering the second interrupt signal. By configuring the parameters of the plurality of third registers in the second inter-core communication unit, the second inter-core communication unit may generate a second interrupt signal and send the second interrupt signal to the first processor through the second communication channel.
[0109] The second inter-core communication unit may include multiple communication channels, and the second communication channel is a communication channel pre-allocated to the second processor among the multiple communication channels. When the second processor performs inter-chip communication with the first processor, the second processor configures multiple third registers so that the second inter-core communication unit can generate a second interrupt signal, and sends the second interrupt signal to the first processor through the second communication channel.
[0110] In some examples, the multiple second registers in the second inter-core communication unit include register A and register B as an example; wherein register A is a register for configuring the recipient of the second interrupt signal, and register B is a register for triggering the second interrupt signal. When the second processor communicates with the first processor, the second processor can configure the recipient of the second interrupt signal through register A and trigger the second interrupt signal by configuring register B.
[0111] For example, Figure 1B As shown, the second processor 1021 can write the identification information "1" of the first processor 1011 in register A to indicate that the second interrupt signal is sent to the first processor 1011; the second processor 1021 can write the configuration information "0" for triggering the second interrupt signal in register B to trigger the second interrupt signal.
[0112] Step 2042: The second inter-core communication unit sends a second interrupt signal to the first processor through the second communication channel.
[0113] The response message includes a second interrupt signal.
[0114] In some embodiments, the first processor may determine, based on the second interrupt signal, that the second processor has read the inter-chip communication data.
[0115] For example, Figure 1BAs shown, the second processor 1021 can configure the parameters of multiple third registers in the second inter-core communication unit 1012 through the first communication interface 1013 and the second communication interface 1023 based on the identification information of the first processor 1011 to trigger the second inter-core communication unit to generate a second interrupt signal; the second inter-core communication unit 1012 can send a second interrupt signal to the first processor 1011 through the second communication channel; the first processor 1011 can also determine, based on the second interrupt signal, that the second processor 1021 has read the inter-chip communication data.
[0116] It should be noted that after the first processor receives the second interrupt signal, the first processor may determine that the second processor has read the inter-chip communication data. At this time, the inter-chip communication between the first processor and the second processor ends.
[0117] The inter-chip communication method provided in the embodiment of the present application is that after the second processor reads the inter-chip communication data from the first inter-core communication unit, the second processor can configure the parameters of multiple third registers in the second inter-core communication unit so that the second inter-core communication unit sends a second interrupt signal to the first processor through the second communication channel. Therefore, the first processor can determine that the second processor has read the inter-chip communication data based on the second interrupt signal, thereby ensuring that the inter-chip communication process between the first integrated circuit and the second integrated circuit is fully executed until the end. Moreover, when the processors of different integrated circuits in the present disclosure communicate, they respectively realize inter-chip communication through different communication channels in the first inter-core communication unit and the second inter-core communication unit, thereby ensuring that different communications are not affected by each other and improving the efficiency of inter-chip communication.
[0118] like Figure 6 As shown in the above Figure 5 Based on the embodiment shown, the following steps may also be included:
[0119] Step 206: The first processor writes configuration information for clearing the second interrupt signal into the second interrupt register in the second inter-core communication unit to clear the second interrupt signal.
[0120] In some embodiments, the second interrupt register is a register used to trigger the second interrupt signal among the plurality of third registers in the above embodiments. The purpose of clearing the second interrupt signal can be achieved by writing configuration information used to clear the second interrupt signal into the second interrupt register.
[0121] In some examples, the first processor can clear the first interrupt signal by writing preset information in the second interrupt register. For example, the first processor can write configuration information "1" for clearing the second interrupt signal in the second interrupt register to clear the second interrupt signal.
[0122] In some embodiments, after the first processor receives the second interrupt signal, if the second interrupt signal needs to be cleared, the first processor may write configuration information for clearing the second interrupt signal in the second interrupt register in the second inter-core communication unit to clear the second interrupt signal.
[0123] For example, Figure 1B As shown, the first processor 1011 writes “1” into the second interrupt register in the second inter-core communication unit 1012 to clear the second interrupt signal, so that the second inter-core communication unit 1012 will no longer send the second interrupt signal to the first processor 1011.
[0124] In the inter-chip communication method provided by the embodiment of the present application, the first processor in the first integrated circuit can write configuration information for clearing the second interrupt signal in the second interrupt register in the second inter-core communication unit to clear the second interrupt signal. Since the second interrupt signal is cleared by the first processor, the second inter-core communication unit can be prevented from sending the interrupt signal to the first processor again, so the first integrated circuit can be prevented from crashing or abnormal problems due to being unable to handle too many interrupts, thereby improving the stability of the first integrated circuit.
[0125] Exemplary Electronic Devices
[0126] Figure 7 A structural diagram of an electronic device 11 provided in an embodiment of the present disclosure includes at least one processor 111 and a memory 112 .
[0127] The processor 111 may be a central processing unit (CPU) or other forms of processing units having data processing capabilities and / or instruction execution capabilities, and may control other components in the electronic device 110 to perform desired functions.
[0128] The memory 112 may include one or more computer program products, which may include various forms of computer-readable storage media, such as volatile memory and / or non-volatile memory. Volatile memory may include, for example, random access memory (RAM) and / or cache memory, etc. Non-volatile memory may include, for example, read-only memory (ROM), hard disk, flash memory, etc. One or more computer program instructions may be stored on the computer-readable storage medium, and the processor 111 may execute one or more computer program instructions to implement the inter-chip communication method and / or other desired functions of the various embodiments of the present disclosure described above.
[0129] In one example, the electronic device 11 may further include: an input device 113 and an output device 114 , and these components are interconnected via a bus system and / or other forms of connection mechanisms (not shown).
[0130] The input device 113 may include various sensors, including but not limited to: a distance sensor for detecting the distance between the target object and the vehicle; an image sensor for collecting information about the vehicle's surrounding environment. In some examples, the input device may also include a pressure sensor for detecting seat pressure, determining whether there is a passenger, and the position of the passenger; a temperature sensor for monitoring the temperature in the cabin; a humidity sensor for monitoring the humidity in the cabin to assist in adjusting the interior environment; an air quality sensor for monitoring the air quality in the vehicle, such as carbon dioxide, volatile organic compounds (VOCs), etc.; a light sensor for detecting the light intensity inside and outside the vehicle; an acceleration sensor for detecting changes in the acceleration of the vehicle; a distance sensor for detecting the distance between the vehicle and other objects; a touch screen sensor for interaction with the vehicle's infotainment system; a biometric sensor, such as fingerprint recognition, facial recognition, etc.; a heart rate monitor for monitoring the driver's heart rate; a sound sensor for voice recognition and interaction to achieve voice control functions; a seat sensor for monitoring the use of the seat, such as whether the seat is occupied and the body shape of the passenger; a wireless communication sensor, such as Bluetooth, Wi-Fi, etc., for connecting with smart devices to achieve data transmission and remote control. In addition to the examples given above, the input device may also include more or fewer sensors, which will not be described in detail here.
[0131] The output device 114 can output various information or signals to other hardware or devices, which may include displays, vehicle audio, seats, windows, steering wheels, etc., as well as communication networks and remote output devices connected thereto, etc. The displays may include a plurality of different display screens such as a driver's display screen, a co-driver's display screen, and a rear display screen, and the vehicle audio may include a plurality of speakers arranged at different positions in the vehicle cabin, and different display screens or speakers may work independently.
[0132] Of course, to simplify, Figure 7 Only some of the components related to the present disclosure in the electronic device 11 are shown, and components such as a bus, an input / output interface, etc. are omitted. In addition, according to specific application situations, the electronic device 11 may also include any other appropriate components.
[0133] Exemplary computer program products and computer-readable storage media
[0134] In addition to the above-mentioned methods and devices, embodiments of the present disclosure may also provide a computer program product, including computer program instructions, which, when executed by a processor, enable the processor to execute the steps of the inter-chip communication method of various embodiments of the present disclosure described in the above-mentioned "Exemplary Method" section.
[0135] The computer program product may be written in any combination of one or more programming languages to write program code for performing the operations of the disclosed embodiments, including object-oriented programming languages such as Java, C++, etc., and conventional procedural programming languages such as "C" or similar programming languages. The program code may be executed entirely on the user computing device, partially on the user device, as a separate software package, partially on the user computing device and partially on a remote computing device, or entirely on a remote computing device or server.
[0136] In addition, an embodiment of the present disclosure may also be a computer-readable storage medium having computer program instructions stored thereon. When the computer program instructions are executed by a processor, the processor executes the steps of the inter-chip communication method of various embodiments of the present disclosure described in the above “Exemplary Method” section.
[0137] Computer readable storage media can adopt any combination of one or more readable media. The readable medium can be a readable signal medium or a readable storage medium. The readable storage medium is, for example, but not limited to, a system, device or device including electricity, magnetism, light, electromagnetic, infrared, or semiconductor, or any combination of the above. More specific examples (non-exhaustive list) of readable storage media include: an electrical connection with one or more wires, a portable disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the above.
[0138] The basic principles of the present disclosure are described above in conjunction with specific embodiments. However, the advantages, strengths, effects, etc. mentioned in the present disclosure are only examples and not limitations, and cannot be considered as necessary for each embodiment of the present disclosure. In addition, the specific details disclosed above are only for the purpose of illustration and ease of understanding, rather than limitation, and the above details do not limit the present disclosure to being implemented by adopting the above specific details.
[0139] Those skilled in the art may make various changes and modifications to the present disclosure without departing from the spirit and scope of the present application. Thus, if these modifications and variations of the present application fall within the scope of the present disclosure claims and their equivalents, the present disclosure is also intended to include these modifications and variations.
Claims
1. An inter-chip communication method of an integrated circuit, comprising: A first processor in a first integrated circuit determines a second processor in a second integrated circuit that performs inter-chip communication with the first processor; The first processor transmits inter-chip communication data to the second processor based on a first inter-core communication unit in the second integrated circuit; The second processor reads the inter-chip communication data from the first inter-core communication unit; The second processor transmits a response message to the first processor based on a second inter-core communication unit in the first integrated circuit; the response message is used to indicate that the second processor has read the inter-chip communication data.
2. The method according to claim 1, wherein: The first processor transmits inter-chip communication data to the second processor based on a first inter-core communication unit in the second integrated circuit, including: The first processor transmits the inter-chip communication data to the first inter-core communication unit, and sends a first interrupt signal to the second processor through the first inter-core communication unit; The second processor reads the inter-chip communication data from the first inter-core communication unit, including: the second processor reads the inter-chip communication data from the first inter-core communication unit in response to receiving the first interrupt signal.
3. The method according to claim 2, wherein: The first processor transmits the inter-chip communication data to the first inter-core communication unit, and sends a first interrupt signal to the second processor through the first inter-core communication unit, including: The first processor writes the inter-chip communication data into a first register of the first inter-core communication unit; The first processor configures parameters of a plurality of second registers in the first inter-core communication unit based on the identification information of the second processor, so as to trigger the first inter-core communication unit to generate a first interrupt signal; The first inter-core communication unit sends the first interrupt signal to the second processor through a first communication channel.
4. The method according to any one of claims 1 to 3, further comprising: The second processor writes configuration information for clearing the first interrupt signal into a first interrupt register in the first inter-core communication unit to clear the first interrupt signal.
5. The method according to claim 1, wherein: The second processor transmits a response message to the first processor based on a second inter-core communication unit in the first integrated circuit, including: The second processor configures parameters of a plurality of third registers in the second inter-core communication unit based on the identification information of the first processor, so as to trigger the second inter-core communication unit to generate a second interrupt signal; The second inter-core communication unit sends the second interrupt signal to the first processor through a second communication channel; wherein the response message includes the second interrupt signal.
6. The method according to claim 5, further comprising: The first processor determines, based on the second interrupt signal, that the second processor has read the inter-chip communication data.
7. The method according to claim 5, further comprising: The first processor writes configuration information for clearing the second interrupt signal into a second interrupt register in the second inter-core communication unit to clear the second interrupt signal.
8. An inter-chip communication system, comprising: a first integrated circuit and a second integrated circuit cascaded with the first integrated circuit, the first integrated circuit comprising a first processor and a second inter-core communication unit, the second integrated circuit comprising a second processor and the first inter-core communication unit; wherein The first processor is used to determine the second processor that performs inter-chip communication with the first processor; and transmit inter-chip communication data to the second processor based on the first inter-core communication unit; The second processor is used to read the inter-chip communication data from the first inter-core communication unit; transmit a response message to the first processor based on the second inter-core communication unit; the response message is used to indicate that the second processor has read the inter-chip communication data.
9. The inter-chip communication system according to claim 8, wherein: The first processor is specifically configured to transmit the inter-chip communication data to the first inter-core communication unit, and send a first interrupt signal to the second processor through the first inter-core communication unit; The second processor is specifically configured to read the inter-chip communication data from the first inter-core communication unit in response to receiving the first interrupt signal.
10. The inter-chip communication system according to claim 9, wherein: The first processor is specifically configured to write the inter-chip communication data into a first register of the first inter-core communication unit, and configure parameters of a plurality of second registers in the first inter-core communication unit based on identification information of the second processor, so as to trigger the first inter-core communication unit to generate a first interrupt signal; The first inter-core communication unit is used to send the first interrupt signal to the second processor through a first communication channel.
11. The inter-chip communication system according to claim 8, wherein: The second processor is specifically configured to configure parameters of a plurality of third registers in the second inter-core communication unit based on the identification information of the first processor, so as to trigger the second inter-core communication unit to generate a second interrupt signal; The second inter-core communication unit is used to send the second interrupt signal to the first processor through a second communication channel; wherein the response message includes the second interrupt signal; The first processor is further configured to determine, based on the second interrupt signal, that the second processor has read the inter-chip communication data.
12. A computer-readable storage medium storing a computer program, wherein the computer program is used to execute the inter-chip communication method of an integrated circuit according to any one of claims 1 to 7.
13. An electronic device, comprising: processor; a memory for storing instructions executable by the processor; The processor is used to read the executable instructions from the memory and execute the instructions to implement the inter-chip communication method of the integrated circuit according to any one of claims 1 to 7; Alternatively, the electronic device includes the inter-chip communication system according to claims 8 to 11.