Circuit parameter calculation method and system, storage medium and electronic equipment

Abstract

The invention provides a circuit parameter calculation method and system, a storage medium and electronic equipment. The circuit parameter calculation method comprises the following steps: acquiring a first peak resonant frequency and a second peak resonant frequency; then, parasitic inductance and parasitic capacitance are obtained through calculation based on the first peak resonant frequency and the second peak resonant frequency; and obtaining optimal circuit parameters according to the parasitic inductance and the parasitic capacitance. The method can solve the problem that the parasitic capacitance and the parasitic inductance have no entity and cannot determine the specific numerical value, meanwhile, the calculation of subsequent circuit parameters is accurate, and the circuit peak processing is more efficient.

Description

Technical Field

[0001] The present application relates to the field of circuit optimization technology, and in particular to a circuit parameter calculation method, system, storage medium and electronic device. Background Art

[0002] In switching power supplies and power electronic systems, overcurrent or overvoltage spikes may occur when switching elements rapidly. Such spikes are usually caused by parasitic parameters or rapid voltage changes in the circuit. The parasitic capacitance and inductance effects of MOS tubes are the main causes of the spikes.

[0003] In actual DC-DC circuits, the components, wires, and transformer coils on the circuit will show some capacitance and inductance characteristics due to the influence of magnetic fields or PCB routing, which will form parasitic capacitance and parasitic inductance. When acting on the MOS tube, this capacitance will be charged / discharged during the switching process. When the MOS tube switches between the off state and the on state, the drain potential drops rapidly, causing the parasitic capacitance to discharge rapidly, thereby generating a spike voltage between the drain and the source. At this time, the current change rate is large, which will generate a large inductance voltage drop in the circuit. This voltage drop will be superimposed on the drain voltage of the MOS tube to form a spike.

[0004] In fact, parasitic capacitance and parasitic inductance do not really exist; therefore, how to calculate parasitic capacitance and parasitic inductance to select appropriate circuit parameters to limit the voltage or current spikes on the switch tube remains to be solved. Summary of the invention

[0005] In order to solve the above technical problems, the present application provides a circuit parameter calculation method, system, storage medium and electronic device.

[0006] Specifically, the present application provides a circuit parameter calculation method, comprising the following steps:

[0007] S100: Acquire a first peak resonance frequency and a second peak resonance frequency.

[0008] S200: Calculate and obtain parasitic inductance and parasitic capacitance based on the first peak resonant frequency and the second peak resonant frequency.

[0009] And S300: obtaining optimal circuit parameters according to the parasitic inductance and parasitic capacitance.

[0010] In the above technical solution, the problem that parasitic capacitance and parasitic inductance have no entity and cannot determine the specific value can be solved. At the same time, the calculation of subsequent circuit parameters is accurate, and the circuit peak processing is more efficient.

[0011] Furthermore, the S100 includes:

[0012] All buffer circuits are removed to detect the peak resonance frequency without the buffer circuit as the first peak resonance frequency.

[0013] A capacitor is added at a preset position of the current circuit, and the peak resonant frequency after the capacitor is added is detected as the second peak resonant frequency.

[0014] In the above technical solution, by removing the buffer circuit, a peak resonant frequency without the influence of other components can be obtained, ensuring the authenticity and reliability of the measurement results. At this time, the measured frequency data can better reflect the actual characteristics of the circuit and provide an accurate basis for subsequent calculations; by adding capacitance, the resonant frequency of the circuit is changed, providing a second key data point and improving the calculation accuracy; based on the actual measured resonant frequency, the parasitic parameters can be accurately calculated to avoid relying on empirical values.

[0015] Furthermore, the process of obtaining the second peak resonance frequency includes:

[0016] S101: After adding the capacitor, record the capacitance of the capacitor.

[0017] S102: Monitor the peak resonance frequency based on the capacitance in real time.

[0018] S103: Determine whether the peak resonant frequency based on the capacitance meets the detection standard. If yes, record the peak resonant frequency based on the capacitance as the second peak resonant frequency; otherwise, adjust the capacitance according to the monitoring result and return to S102.

[0019] In the above technical solution, the capacitance of the added capacitor is recorded to ensure that subsequent calculations are accurate; the peak resonant frequency is monitored in real time to instantly obtain circuit state changes, facilitating timely problem handling; the judgment standard ensures that the recorded peak resonant frequency meets the design requirements, thereby improving the reliability of the circuit design; the feedback mechanism allows engineers to adjust the capacitance value to ensure that the final recorded frequency is accurate, facilitating the optimization of the circuit design.

[0020] Furthermore, the S103 further includes:

[0021] If the peak resonance frequency based on the capacitance still does not meet the detection standard after adjusting the capacitance a preset number of times, an error message is returned to the user.

[0022] In the above technical solution, by setting a limit on the number of adjustments, users can be prevented from continuing to perform meaningless operations when they know that the adjustments are invalid, which helps to use development and debugging resources more rationally; error message prompts help engineers quickly identify the occurrence of problems and promptly conduct further investigations or adjust other design parameters according to the prompts.

[0023] Further, the S300 includes:

[0024] The characteristic impedance is calculated according to the parasitic inductance and the parasitic capacitance.

[0025] In the above technical solution, by calculating the characteristic impedance, it is possible to ensure that the impedance matching in the circuit design is more accurate; in the design of high-speed circuits and high-frequency circuits, impedance matching is a key factor in ensuring signal integrity and reducing reflection losses, and the calculation of characteristic impedance helps to design more stable and efficient circuits.

[0026] Furthermore, the optimal circuit parameters at least include an optimal resistance value and an optimal capacitance value; and S300 further includes:

[0027] An optimum resistance value is determined based on the characteristic impedance, and an optimum capacitance value is determined based on the parasitic capacitance.

[0028] In the above technical solution, by calculating the optimal resistance value based on the characteristic impedance, the optimal impedance matching of the circuit can be achieved, signal reflection can be reduced, and the effectiveness of signal transmission can be improved, which is particularly important in high-frequency or high-speed circuits and can prevent signal attenuation and distortion; ensuring the selection of the optimal resistance and capacitance values ​​makes the signal waveform more stable and improves signal integrity; optimizing the resistance value in circuit design can reduce power consumption, especially in high-frequency applications, by effectively matching the impedance, unnecessary energy loss can be reduced and the overall energy efficiency can be improved; optimizing the capacitance value according to the parasitic capacitance can improve the frequency response characteristics of the circuit and ensure that the circuit can maintain good performance at different frequencies.

[0029] In addition, with clear guidance on optimal parameters, the design and debugging time can be shortened, the need for repeated experiments can be reduced, and work efficiency can be improved; at the same time, designers can have a clear direction during the design stage.

[0030] Furthermore, the S300 further includes:

[0031] The optimal circuit parameters are connected to the actual circuit for verification, and the verification results are returned to the user.

[0032] In the above technical solution, the optimal circuit parameters obtained by calculation are applied to the actual circuit for verification to ensure that the theoretical calculation is consistent with the actual results, avoiding performance deviations caused by differences between theoretical models and real environments. Through verification feedback, deficiencies in the design can be discovered and corrected in a timely manner, reducing the number of repeated designs, accelerating the product development cycle, and saving development costs. If the verification results do not meet expectations, the feedback mechanism can quickly expose the problem, making it easier for the design team to adjust the design parameters or solutions in a timely manner and clarify the direction of improvement.

[0033] Based on the same concept, the present application also provides a circuit parameter calculation system, including:

[0034] Acquisition module: used to acquire the first peak resonance frequency and the second peak resonance frequency.

[0035] A first calculation module is configured to calculate and obtain parasitic inductance and parasitic capacitance based on the first peak resonant frequency and the second peak resonant frequency.

[0036] and a second calculation module: used for obtaining optimal circuit parameters according to the parasitic inductance and parasitic capacitance.

[0037] In electronic circuit design, parasitic capacitance and parasitic inductance are usually difficult to obtain exact values ​​through traditional measurement methods, which makes circuit optimization complicated and inefficient.

[0038] In the above technical solution, the specific values ​​of parasitic inductance and parasitic capacitance can be obtained more accurately, and the optimal parameters of the circuit can be further effectively calculated, thereby reducing signal reflection and loss and improving transmission efficiency.

[0039] Based on the same concept, the present application also provides a storage medium, in which a computer program is stored, wherein the computer program is configured to execute the circuit parameter calculation method when running.

[0040] Based on the same concept, the present application also provides an electronic device, which includes a processor and a memory, wherein the memory stores at least one instruction, at least one program, a code set or an instruction set, and the at least one instruction, the at least one program, the code set or the instruction set is loaded and executed by the processor to implement the circuit parameter calculation method.

[0041] Compared with the prior art, the beneficial effects of this application are:

[0042] The present application first obtains the first peak resonant frequency and the second peak resonant frequency; then calculates the parasitic inductance and the parasitic capacitance based on the first peak resonant frequency and the second peak resonant frequency; and further obtains the optimal circuit parameters according to the parasitic inductance and the parasitic capacitance. The present application can solve the problem that the parasitic capacitance and the parasitic inductance have no entity and the specific value cannot be determined, and at the same time, the calculation of the subsequent circuit parameters is accurate, and the circuit peak processing is more efficient. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] Figure 1 This is a flow chart of the circuit parameter calculation method described in this application.

[0044] Figure 2 This is a framework diagram of the circuit parameter calculation system described in this application. DETAILED DESCRIPTION

[0045] A circuit parameter calculation method, system, storage medium and electronic device of the present application are further described in detail below in conjunction with specific embodiments and drawings.

[0046] Embodiment 1:

[0047] See also Figure 1 , the present application provides a circuit parameter calculation method, comprising the following steps:

[0048] S100: Acquire a first peak resonance frequency and a second peak resonance frequency.

[0049] Furthermore, the S100 includes:

[0050] All buffer circuits are removed to detect the peak resonance frequency without the buffer circuit as the first peak resonance frequency.

[0051] In some embodiments, the circuit parameter calculation method is used for calculating the parasitic capacitance and parasitic inductance of the MOS tube in the DC-DC and further optimizing the parameters; it should be noted that the circuit parameter calculation method described in this embodiment can also be applied to circuits of various power switching elements, BUCK converters, etc., and is not limited to one type of MOS tube circuit in the DC-DC.

[0052] First, identify the buffer circuit part in the circuit, such as the driver and output stage buffer, which is used to isolate and not affect the signal transmission of the subsequent circuit; disconnect or remove all buffer circuit modules to ensure that the signal can be transmitted directly to the main circuit, thereby exposing parasitic capacitance and inductance.

[0053] Use a spectrum analyzer or other suitable testing equipment to perform a frequency response test on the circuit without the buffer circuit, record the detected peak resonance frequency, and use it as the first peak resonance frequency f0.

[0054] Furthermore, a capacitor is added at a preset position of the current circuit, and the peak resonance frequency after the capacitor is added is detected as the second peak resonance frequency.

[0055] In some embodiments, a capacitor C is connected in parallel between the drain (D) and the source (S) of the MOS tube. r (no resistance), the capacity is not fixed and can be in nF level.

[0056] Among them, the capacitor C r Connecting in parallel between the drain and source of the MOS tube is to improve the circuit's performance in terms of high frequency performance, switching characteristics and stability. Especially in the nF capacitor design, it can effectively meet the needs of high frequency fast switching and noise reduction.

[0057] Furthermore, the same spectrum analyzer or other testing equipment is used to perform a frequency response test on the circuit after adding the capacitor, and the detected peak resonance frequency is recorded and used as the second peak resonance frequency f1.

[0058] In the above technical solution, by removing the buffer circuit, a peak resonant frequency without the influence of other components can be obtained, ensuring the authenticity and reliability of the measurement results. At this time, the measured frequency data can better reflect the actual characteristics of the circuit and provide an accurate basis for subsequent calculations; by adding capacitance, the resonant frequency of the circuit is changed, providing a second key data point and improving the calculation accuracy; based on the actual measured resonant frequency, the parasitic parameters can be accurately calculated to avoid relying on empirical values.

[0059] Furthermore, the process of obtaining the second peak resonance frequency includes:

[0060] S101: After adding the capacitor, record the capacitance of the capacitor.

[0061] In some embodiments, a capacitor C is connected in parallel between the drain (D) and the source (S) of the MOS tube. r , use a capacitance measuring instrument or according to the mark on the capacitor, accurately record the capacitance value of the currently added capacitor, such as 1nF.

[0062] S102: Monitor the peak resonance frequency based on the capacitance in real time.

[0063] In some embodiments, a spectrum analyzer or other frequency response test equipment is used to start real-time monitoring of the frequency response of the circuit; the peak resonant frequency of the circuit at the current capacitance value is recorded by the spectrum analyzer; wherein, it is necessary to ensure that the recorded frequency is the main resonant frequency of the circuit.

[0064] S103: Determine whether the peak resonant frequency based on the capacitance meets the detection standard. If yes, record the peak resonant frequency based on the capacitance as the second peak resonant frequency; otherwise, adjust the capacitance according to the monitoring result and return to S102.

[0065] In some embodiments, detection criteria are set, for example, including frequency range, signal quality (such as signal-to-noise ratio), peak shape, etc.; the detection criteria can be set according to specific application scenarios.

[0066] If the currently monitored peak resonance frequency meets the preset detection standard, the current peak resonance frequency is recorded as the second peak resonance frequency f1, and the acquisition of the second peak resonance frequency is completed.

[0067] If the currently monitored peak resonance frequency does not meet the preset detection standard, the deviation of the peak resonance frequency is analyzed according to the monitoring results, and the capacitance value of the capacitor is adjusted; for example, if the peak frequency is too low, the capacitance may need to be reduced; if the frequency is too high, the capacitance may need to be increased.

[0068] After adjusting the capacitance value, return to S102 and continue to monitor the new peak resonance frequency in real time to find a frequency that meets the detection standard.

[0069] In the above technical solution, the capacitance of the added capacitor is recorded to ensure that subsequent calculations are accurate; the peak resonant frequency is monitored in real time to instantly obtain circuit state changes, facilitating timely problem handling; the judgment standard ensures that the recorded peak resonant frequency meets the design requirements, thereby improving the reliability of the circuit design; the feedback mechanism allows engineers to adjust the capacitance value to ensure that the final recorded frequency is accurate, facilitating the optimization of the circuit design.

[0070] Furthermore, the S103 further includes:

[0071] If the peak resonance frequency based on the capacitance still does not meet the detection standard after adjusting the capacitance a preset number of times, an error message is returned to the user.

[0072] In some embodiments, to prevent an infinite loop, a maximum number of adjustments is set (eg, 5 times), but those skilled in the art may also set it to other times, and the present invention is not limited thereto.

[0073] If the maximum number of adjustments is within the set value, based on the current capacitance C r If the peak resonance frequency still does not meet the detection criteria, an error message is generated and returned to the user. The content may include the specific error type (such as "the peak resonance frequency does not meet the standard"), suggested solutions (such as changing the capacitance range or checking the circuit design), etc.

[0074] In the above technical solution, by setting a limit on the number of adjustments, users can be prevented from continuing to perform meaningless operations when they know that the adjustments are invalid, which helps to use development and debugging resources more rationally; error message prompts help engineers quickly identify the occurrence of problems and promptly conduct further investigations or adjust other design parameters according to the prompts.

[0075] S200: Calculate and obtain parasitic inductance and parasitic capacitance based on the first peak resonant frequency and the second peak resonant frequency.

[0076] In some embodiments, the first peak resonant frequency f0 without buffering, the second peak resonant frequency f1 after the parallel capacitor, and the parallel capacitor C r Substitute into the following formula:

[0077] Peak frequency In the result:

[0078]

[0079] Among them, L1 is the parasitic inductance and C1 is the parasitic capacitance.

[0080] And S300: obtaining optimal circuit parameters according to the parasitic inductance and parasitic capacitance.

[0081] Further, the S300 includes:

[0082] The characteristic impedance is calculated according to the parasitic inductance and the parasitic capacitance.

[0083] In some embodiments, the parasitic inductance L1 and the parasitic capacitance C1 obtained above are substituted into the following formula to obtain the characteristic impedance Z0:

[0084]

[0085] In the above technical solution, by calculating the characteristic impedance, it is possible to ensure that the impedance matching in the circuit design is more accurate; in the design of high-speed circuits and high-frequency circuits, impedance matching is a key factor in ensuring signal integrity and reducing reflection losses, and the calculation of characteristic impedance helps to design more stable and efficient circuits.

[0086] Furthermore, the optimal circuit parameters at least include an optimal resistance value and an optimal capacitance value; and S300 further includes:

[0087] An optimum resistance value is determined based on the characteristic impedance, and an optimum capacitance value is determined based on the parasitic capacitance.

[0088] In some embodiments, the optimal resistance value needs to be close to the characteristic impedance Z0, and the optimal capacitance value C r It is between 4 and 10 times the parasitic capacitance C1; however, due to C r The value of is a range. If the capacitance is too small, it will reduce the effect of weakening the sword edge. If the value is too large, it will not enhance the absorption capacity and will increase the heat generated by the resistor R. Therefore, a relatively suitable specification should be found within this range.

[0089] Among them, according to the obtained characteristic impedance, the standard resistor closest to the impedance value is found; according to the circuit design requirements, a reasonable tolerance range can be set to allow for flexibility in selecting resistors. Then, when selecting resistors, it is necessary to consider, for example, power ratings, heating conditions, changes caused by temperature, etc.; further, for example, circuit simulation software is used to verify the selected resistors, analyze their performance under high-frequency conditions, especially the matching degree with the characteristic impedance, and finally obtain the optimal resistance value.

[0090] Further, several standard capacitance values ​​within the range of 4C1-10C1 are selected, such as 4C1, 5C1, 6C1, ..., 10C1. These capacitance values ​​are tested respectively in the actual circuit, and the peak resonance frequency, signal integrity, power consumption and other aspects are observed, and the performance data under each capacitance value is recorded. According to the test results, the capacitance value with the best performance is selected as the optimal capacitance value.

[0091] Alternatively, a circuit model is established using circuit simulation software, and the capacitance value is set to 4C1-10C1 for simulation; the simulation results provide data such as voltage, current, power, frequency, etc., and the optimal capacitance value is further selected based on the simulation data.

[0092] In the above technical solution, by calculating the optimal resistance value based on the characteristic impedance, the optimal impedance matching of the circuit can be achieved, signal reflection can be reduced, and the effectiveness of signal transmission can be improved, which is particularly important in high-frequency or high-speed circuits and can prevent signal attenuation and distortion; ensuring the selection of the optimal resistance and capacitance values ​​makes the signal waveform more stable and improves signal integrity; optimizing the resistance value in circuit design can reduce power consumption, especially in high-frequency applications, by effectively matching the impedance, unnecessary energy loss can be reduced and the overall energy efficiency can be improved; optimizing the capacitance value according to the parasitic capacitance can improve the frequency response characteristics of the circuit and ensure that the circuit can maintain good performance at different frequencies.

[0093] In addition, with clear guidance on optimal parameters, the design and debugging time can be shortened, the need for repeated experiments can be reduced, and work efficiency can be improved; at the same time, designers can have a clear direction during the design stage.

[0094] Furthermore, the S300 further includes:

[0095] The optimal circuit parameters are connected to the actual circuit for verification, and the verification results are returned to the user.

[0096] In some embodiments, a DC-DC converter circuit prototype is built, the optimal resistance value and the optimal capacitance value are integrated into the circuit, and the circuit is tested using an oscilloscope, a voltmeter, and an ammeter. The input voltage is set to the required value (such as 12V) and the output voltage and current are monitored. The output voltage, current, waveform, and frequency characteristics are recorded, and each parameter is compared with the corresponding set threshold value to obtain an analysis report and feedback to the user.

[0097] The analysis report may include, for example, comparative analysis diagrams, improvement suggestions, etc.

[0098] In the above technical solution, the optimal circuit parameters obtained by calculation are applied to the actual circuit for verification to ensure that the theoretical calculation is consistent with the actual results, avoiding performance deviations caused by differences between theoretical models and real environments. Through verification feedback, deficiencies in the design can be discovered and corrected in a timely manner, reducing the number of repeated designs, accelerating the product development cycle, and saving development costs. If the verification results do not meet expectations, the feedback mechanism can quickly expose the problem, making it easier for the design team to adjust the design parameters or solutions in a timely manner and clarify the direction of improvement.

[0099] Embodiment 2:

[0100] See also Figure 2 The present application also provides a system using the circuit parameter calculation method described in Embodiment 1, comprising:

[0101] Acquisition module: used to acquire the first peak resonance frequency and the second peak resonance frequency.

[0102] In some embodiments, all buffer circuits are removed to detect the peak resonant frequency without the buffer circuit as the first peak resonant frequency f0; a capacitor is connected in parallel between the drain (D) and the source (S) of the MOS tube, and the peak resonant frequency after adding the capacitor is detected as the second peak resonant frequency f1.

[0103] Furthermore, the process of obtaining the second peak resonance frequency includes:

[0104] After adding the capacitor, use a capacitance measuring instrument or record the capacitance of the capacitor according to the mark on the capacitor; use a spectrum analyzer or other frequency response test equipment to monitor the peak resonant frequency based on the capacitance in real time; determine whether the peak resonant frequency based on the capacitance meets the detection standard, if yes, record the peak resonant frequency based on the capacitance as the second peak resonant frequency f1; otherwise, analyze the deviation of the peak resonant frequency according to the monitoring result, adjust the capacitance of the capacitor, and continue to monitor the peak resonant frequency.

[0105] Furthermore, if the peak resonance frequency based on the capacitance still does not meet the detection standard after adjusting the capacitance a preset number of times, an error message is returned to the user.

[0106] In order to prevent an infinite loop, a maximum number of adjustments is set (for example, 5 times); if within the set maximum number of adjustments, the peak resonant frequency based on the current capacitor still does not meet the detection criteria, an error message is generated and returned to the user, and the content may include the specific error type, suggested solutions, etc.

[0107] A first calculation module is configured to calculate and obtain parasitic inductance and parasitic capacitance based on the first peak resonant frequency and the second peak resonant frequency.

[0108] In some embodiments, based on the first peak resonant frequency f0 without buffer, the second peak resonant frequency f1 after the parallel capacitor, and the parallel capacitor C r get:

[0109]

[0110] Among them, L1 is the parasitic inductance and C1 is the parasitic capacitance.

[0111] and a second calculation module: used for obtaining optimal circuit parameters according to the parasitic inductance and parasitic capacitance.

[0112] In some embodiments, the optimal circuit parameters include at least an optimal resistance value and an optimal capacitance value; the characteristic impedance is calculated based on the parasitic inductance and parasitic capacitance; the optimal resistance value is determined based on the characteristic impedance, and the optimal capacitance value is determined based on the parasitic capacitance.

[0113] In some embodiments, the parasitic inductance L1 and the parasitic capacitance C1 obtained above are substituted into the following formula to obtain the characteristic impedance Z0:

[0114]

[0115] The optimal resistance value needs to be close to the characteristic impedance Z0, and the optimal capacitance value C r It is between 4 and 10 times the parasitic capacitance C1.

[0116] Furthermore, the optimal circuit parameters are connected to the actual circuit for verification, and the verification result is returned to the user.

[0117] In some embodiments, a DC-DC converter circuit prototype is built, the optimal resistance value and the optimal capacitance value are integrated into the circuit, and data such as the output voltage, current, waveform and frequency characteristics are recorded, and each parameter is compared with the corresponding set threshold value to obtain an analysis report and feedback to the user.

[0118] The analysis report may include, for example, comparative analysis diagrams, improvement suggestions, etc.

[0119] In electronic circuit design, parasitic capacitance and parasitic inductance are usually difficult to obtain exact values ​​through traditional measurement methods, which makes circuit optimization complicated and inefficient.

[0120] In the above technical solution, the specific values ​​of parasitic inductance and parasitic capacitance can be obtained more accurately, and the optimal parameters of the circuit can be further effectively calculated, thereby reducing signal reflection and loss and improving transmission efficiency.

[0121] Embodiment three:

[0122] The present application also provides a storage medium, in which a computer program is stored, wherein the computer program is configured to execute the circuit parameter calculation method described in the first embodiment when running.

[0123] In some embodiments, the storage medium stores several computer programs for causing a device to execute all or part of the steps of the method described in various embodiments of the present application.

[0124] The medium may include a U disk, a mobile hard disk, a read-only memory, a random access memory, a magnetic disk or an optical disk, and other media that can store program codes.

[0125] Embodiment 4:

[0126] The present application also provides an electronic device, which includes a processor and a memory, wherein the memory stores at least one instruction, at least one program, a code set or an instruction set, and the at least one instruction, the at least one program, the code set or the instruction set is loaded and executed by the processor to implement the circuit parameter calculation method described in Example 1.

[0127] In some embodiments, the memory and the processor are interconnected; the processor may be one or more CPUs. When the processor is a CPU, the CPU may be a single-core CPU or a multi-core CPU. The processor is used to control various functional modules of the device and process signals.

[0128] The memory includes, but is not limited to, RAM (Random Access Memory), ROM (Read-Only Memory), EPROM (Erasable Programmable Read-Only Memory), and CD-ROM (Compact Disc Read-Only Memory). The memory is used to store computer programs, operating systems, various applications, and data, such as storing a computer program for implementing the circuit parameter calculation method described in Example 1.

[0129] In summary, the present application provides a circuit parameter calculation method, system, storage medium and electronic device; firstly, a first peak resonant frequency and a second peak resonant frequency are obtained; then, parasitic inductance and parasitic capacitance are calculated based on the first peak resonant frequency and the second peak resonant frequency; and then, the optimal circuit parameters are obtained according to the parasitic inductance and parasitic capacitance. The present application can solve the problem that parasitic capacitance and parasitic inductance have no entity and the specific value cannot be determined, and at the same time, the calculation of subsequent circuit parameters is accurate, and the circuit peak processing is more efficient.

[0130] Although example embodiments have been described herein with reference to the accompanying drawings, it should be understood that the above example embodiments are merely exemplary and are not intended to limit the scope of the present application to this. Those of ordinary skill in the art may make various changes and modifications therein without departing from the scope and spirit of the present application. All these changes and modifications are intended to be included within the scope of the present application as required by the appended claims.

[0131] Those of ordinary skill in the art will appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of this application.

[0132] In the several embodiments provided in this application, it should be understood that the disclosed devices and methods can be implemented in other ways. For example, the device embodiments described above are only schematic, for example, the division of the units is only a logical function division, and there may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another device, or some features can be ignored or not executed.

[0133] The various component embodiments of the present application can be implemented in hardware, or in software modules running on one or more processors, or in a combination thereof. It should be understood by those skilled in the art that a microprocessor or digital signal processor (DSP) can be used in practice to implement some or all functions of some modules according to the embodiments of the present application. The application can also be implemented as a device program (e.g., computer program and computer program product) for executing a part or all of the methods described herein. Such a program implementing the present application can be stored on a computer-readable medium, or can have the form of one or more signals. Such a signal can be downloaded from an Internet website, or provided on a carrier signal, or provided in any other form.

[0134] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or device including the elements.

[0135] Although the description of the present application is carried out in conjunction with the above specific embodiments, it is obvious that those skilled in the art can make many substitutions, modifications and changes based on the above content. Therefore, all such substitutions, improvements and changes are included in the spirit and scope of the appended claims.

Claims

1. A circuit parameter calculation method, characterized in that: The following steps are involved: S100: Acquire a first peak resonance frequency and a second peak resonance frequency; S200: Calculate and obtain parasitic inductance and parasitic capacitance based on the first peak resonant frequency and the second peak resonant frequency; And S300: obtaining optimal circuit parameters according to the parasitic inductance and parasitic capacitance.

2. The circuit parameter calculation method according to claim 1, characterized in that: The S100 includes: All buffer circuits are removed to detect the peak resonance frequency when there is no buffer circuit as the first peak resonance frequency; A capacitor is added at a preset position of the current circuit, and the peak resonant frequency after the capacitor is added is detected as the second peak resonant frequency.

3. The circuit parameter calculation method according to claim 2, characterized in that: The process of obtaining the second peak resonance frequency includes: S101: After adding the capacitor, recording the capacitance of the capacitor; S102: real-time monitoring of the peak resonant frequency based on the capacitance value; S103: Determine whether the peak resonant frequency based on the capacitance meets the detection standard. If yes, record the peak resonant frequency based on the capacitance as the second peak resonant frequency; otherwise, adjust the capacitance according to the monitoring result and return to S102.

4. The circuit parameter calculation method according to claim 3, characterized in that: The S103 further includes: If the peak resonance frequency based on the capacitance still does not meet the detection standard after adjusting the capacitance a preset number of times, an error message is returned to the user.

5. The circuit parameter calculation method according to claim 3, characterized in that: The S300 includes: The characteristic impedance is calculated according to the parasitic inductance and the parasitic capacitance.

6. The circuit parameter calculation method according to claim 4, characterized in that: The optimal circuit parameters at least include an optimal resistance value and an optimal capacitance value; S300 also includes: An optimum resistance value is determined based on the characteristic impedance, and an optimum capacitance value is determined based on the parasitic capacitance.

7. The circuit parameter calculation method according to claim 6, characterized in that: The S300 further includes: The optimal circuit parameters are connected to the actual circuit for verification, and the verification results are returned to the user.

8. A system using the circuit parameter calculation method according to any one of claims 1 to 7, characterized in that: include: An acquisition module: used to acquire a first peak resonance frequency and a second peak resonance frequency; A first calculation module: used for calculating and obtaining parasitic inductance and parasitic capacitance based on the first peak resonant frequency and the second peak resonant frequency; and a second calculation module: used for obtaining optimal circuit parameters according to the parasitic inductance and parasitic capacitance.

9. A storage medium, characterized in that: The storage medium stores a computer program, wherein the computer program is configured to execute the circuit parameter calculation method according to any one of claims 1 to 7 when running.

10. An electronic device, characterized in that: The electronic device includes a processor and a memory, wherein the memory stores at least one instruction, at least one program, a code set or an instruction set, and the at least one instruction, the at least one program, the code set or the instruction set is loaded and executed by the processor to implement the circuit parameter calculation method as described in any one of claims 1 to 7.

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