Pad graph drawing method and device for integrated circuit layout and storage medium

Abstract

The invention provides a bonding pad graph drawing method and device of an integrated circuit layout and a storage medium. The method comprises the steps that bonding pad information of a target chip is acquired; obtaining packaging information; checking the normalization of the packaging information; and after the inspection is passed, drawing a bonding pad pattern of the target chip on the integrated circuit layout by using the tool function according to the bonding pad information and the packaging information. Through the scheme, the drawing efficiency of the packaging layout can be greatly improved, errors possibly caused by manual drawing are avoided, the accuracy of an output result can be ensured, and extremely high compatibility is achieved.

Description

Technical Field

[0001] The present application relates to the technical field of integrated circuit layout design, and in particular to a method, device and storage medium for drawing pad graphics of an integrated circuit layout. Background Art

[0002] In the process of electronic component manufacturing, packaging is a vital step, and pad drawing is a key link. Packaging is the process of encapsulating electronic components in a shell to protect them from environmental influences and provide a way to connect to the circuit board. Pad drawing refers to the process of drawing pads on the circuit board, which are used to connect electronic components to the circuit board.

[0003] For example, when encapsulating multiple bare chips (dies), it is usually necessary to first draw the pads of the bare chips on a circuit board in order to evaluate the feasibility of the package.

[0004] For chip development projects in cooperation with external parties, information such as bare core schematics and pad coordinates are usually provided by external companies. When the pads of the bare core need to be drawn, existing solutions mostly rely on manual drawing of data drawings based on the coordinates, size, and shape name of each pad information. When the number of pads is large, a lot of manpower is required, and the accuracy cannot be guaranteed. In addition, there is a lack of inspection mechanism, and errors cannot be found. Once a mistake occurs, it will affect the project progress. Summary of the invention

[0005] In order to solve the above technical problems, the present application provides a method, device and storage medium for drawing pad graphics of an integrated circuit layout, aiming to simplify the pad drawing process, improve efficiency and avoid errors that may be caused by manual drawing.

[0006] According to a first aspect of the present application, a method for drawing a pad pattern of an integrated circuit layout is provided, comprising:

[0007] Get the pad information of the target chip;

[0008] Get packaging information;

[0009] Checking the standardization of the packaging information;

[0010] After the inspection is passed, a pad pattern of the target chip is drawn on an integrated circuit layout according to the pad information and the packaging information using a tool function.

[0011] Optionally, the pad information of the target chip is obtained, including:

[0012] The information file containing the pad information is processed using a pre-prepared script to obtain the pad information from the information file.

[0013] Optionally, the pad information of the target chip is obtained, including:

[0014] A configuration interface for pad information is provided, and the pad information is obtained according to the content input by the operator.

[0015] Optionally, obtain package information, including:

[0016] A configuration interface for packaging information is provided, and the packaging information is obtained according to the configuration content input by the operator.

[0017] Optionally, the pad information includes at least one of the following:

[0018] Pad name;

[0019] Pad size;

[0020] Number of pads; and

[0021] The pad coordinates of each pad.

[0022] Optionally, the packaging information includes at least one of the following:

[0023] Layout level information;

[0024] The size of the target chip;

[0025] the width of the scribe line; and

[0026] Pad shape.

[0027] Optionally, checking the standardization of the packaging information includes:

[0028] Checking whether the format of the layout layer information and various values ​​in the input packaging information conforms to the format specification under the predetermined process; and

[0029] Check whether the various values ​​in the input packaging information meet the value range specifications under the predetermined process.

[0030] According to a second aspect of the present application, a device for drawing a pad pattern of an integrated circuit layout is provided, comprising:

[0031] A pad information acquisition unit, used to acquire pad information of a target chip;

[0032] A packaging information acquisition unit, used to acquire packaging information;

[0033] An inspection unit, used for inspecting the standardization of the packaging information;

[0034] The pad pattern drawing unit is used to draw the pad pattern of the target chip on the integrated circuit layout according to the pad information and the packaging information by using a tool function after the inspection is passed.

[0035] According to a third aspect of the present application, a storage medium is provided, wherein a computer program or instructions are stored in the storage medium, and when the computer program or instructions are executed, the steps of the pad graphic drawing method as described in any embodiment of the present application are implemented.

[0036] According to a third aspect of the present application, an electronic device is provided, which includes: a memory, a processor, and a program stored in the memory and executable by the processor, wherein the program, when executed, implements the steps of the pad graphic drawing method as described in any embodiment of the present application.

[0037] The beneficial effects of this application include at least:

[0038] The embodiment of the present application provides a method for automatically drawing a pad graphic. The method first obtains the pad information and corresponding packaging information of the target chip, and then calls the corresponding tool function to process the obtained pad information and packaging information, so as to automatically complete the drawing of the pad graphic of the target chip, thereby realizing the operation of automatically importing the pad data into the integrated circuit layout. Compared with the manual drawing method, the present application scheme can greatly improve the drawing efficiency and evaluation efficiency of the integrated circuit package drawing, can avoid the errors that may be caused by manual drawing, and does not require learning costs. It has strong compatibility and is suitable for the drawing of pad graphics in the integrated circuit layout of any process and any packaging form. At the same time, the present application scheme also provides a checking mechanism in the automatic drawing process of the pad graphic, which can ensure the accuracy of the format and content of the input information, thereby ensuring the reliability of the drawing results.

[0039] It should be noted that the above general description and the following detailed description are merely exemplary and explanatory and do not limit the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] Figure 1 A schematic diagram showing an implementation flow of a pad pattern drawing method for an integrated circuit layout provided in accordance with an embodiment of the present application;

[0041] Figure 2 A schematic diagram showing an implementation of a configuration interface for packaging information provided in an embodiment of the present application is shown;

[0042] Figure 3 A schematic diagram showing a drawing of a pad pattern of a target chip provided according to an embodiment of the present application is shown;

[0043] Figure 4 A schematic diagram showing the structure of a pad pattern drawing device for an integrated circuit layout provided in an embodiment of the present application is shown;

[0044] Figure 5A schematic diagram of the structure of an electronic device provided according to an embodiment of the present application is shown. DETAILED DESCRIPTION

[0045] In order to facilitate the understanding of the present application, the present application will be described more comprehensively below with reference to the relevant drawings. The preferred embodiments of the present application are given in the drawings. However, the present application can be implemented in different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the understanding of the disclosure of the present application more thorough and comprehensive.

[0046] References to "one embodiment" or "some embodiments" etc. described in this specification mean that a particular feature, structure or characteristic described in conjunction with the embodiment is included in one or more embodiments of the present application. Thus, the phrases "in one embodiment", "in some embodiments", "in some other embodiments", "in some other embodiments", etc. that appear at different places in this specification do not necessarily refer to the same embodiment, but mean "one or more but not all embodiments", unless otherwise specifically emphasized in other ways. The terms "including", "comprising", "having" and their variations all mean "including but not limited to", unless otherwise specifically emphasized in other ways.

[0047] In the description of the present application, the words "exemplary" or "for example" are used to indicate examples, illustrations or explanations. Any embodiment described as "exemplary" or "for example" in the present application should not be interpreted as being more preferred or more advantageous than other embodiments. "And / or" herein is a description of the association relationship of associated objects, indicating that three relationships may exist, for example, A and / or B, which can represent: A exists alone, A and B exist at the same time, and B exists alone. "Multiple" refers to two or more than two. In addition, in order to facilitate the clear description of the technical solutions of the embodiments of the present application, the words "first", "second" and the like are used to distinguish between the same items or similar items with substantially the same functions and effects. Those skilled in the art will understand that the words "first", "second" and the like do not limit the quantity and execution order, and the words "first", "second" and the like do not limit them to be necessarily different.

[0048] In addition, the same figure marks in the figures represent the same or similar structures, and thus their repeated description will be omitted. That is, the various parts in this specification are described in a combination of parallel and progressive manners, and each part focuses on the differences from other parts. The same or similar parts between the various parts can be referenced to each other.

[0049] The embodiment of the present application provides a method for drawing a pad graphic of an integrated circuit layout, which can realize automatic drawing of a pad graphic according to an information file containing chip (herein referring to a bare chip before packaging) pad information. In particular, when multiple chips need to be packaged, for chip data information that is not recorded in a database (such as data information of a newly developed chip, or data information of a chip obtained from an external channel, etc.), the pad graphic drawing method provided by the embodiment of the present application can realize the operation of automatically importing the pad data into the integrated circuit layout. Compared with the manual drawing method, the drawing efficiency and evaluation efficiency of the integrated circuit package drawing can be greatly improved, and the errors that may be caused by manual drawing can be effectively avoided. There is no need for learning costs, and it has extremely strong compatibility. It is suitable for the drawing of pad graphics in integrated circuit layouts of any process and any packaging form, and the drawing results are highly accurate and reliable.

[0050] Figure 1 FIG. 1 shows a schematic diagram of an implementation process of a pad pattern drawing method for an integrated circuit layout provided by an embodiment of the present application, such as Figure 1 As shown, the pad graphic drawing method includes executing the following steps:

[0051] In step 110, pad information of a target chip is obtained.

[0052] In this step, the pad information of the target chip to be obtained may be the pad information of the chip recorded in the data of the newly developed chip or the data of the chip obtained from external channels, which has not yet been included in the relevant database. For example, in a chip cooperative development project, an information file containing chip schematics and pad information is provided by an external company or a third party.

[0053] In some embodiments, the specific implementation method of step 110 includes: using a pre-prepared script to process an information file containing pad information, and obtaining the pad information from the information file. Exemplarily, during the specific implementation, the script is run to determine the information file to be processed by automatically searching for a specific format file or by manually specifying the information file, and the script processes the information file to automatically extract the pad information data recorded in the information file. The whole process can be carried out automatically without human intervention.

[0054] In other embodiments, the specific implementation method of step 110 includes: providing a configuration interface for pad information, and obtaining pad information according to the content input by the operator. Exemplarily, during specific implementation, a configuration interface for pad information can be provided in response to a user operation or a pad information acquisition instruction, so as to obtain pad information according to the input configuration of pad information of the target chip by an operator such as a user in the configuration interface.

[0055] In this embodiment, the pad information of the aforementioned target chip includes but is not limited to at least one of the following: pad name, pad size, number of pads, and pad coordinates of each pad.

[0056] In step 120, packaging information is obtained.

[0057] In this step, the packaging information to be obtained may be packaging configuration information when the target chip is packaged alone, or may be relevant packaging configuration information when the target chip and other chips are packaged together. Optionally, the packaging information includes but is not limited to at least one of the following: layout layer information, size of the target chip, width of the scribe groove, and shape of the pad.

[0058] In some embodiments, the specific implementation method of step 110 includes: providing a configuration interface for packaging information, and obtaining packaging information according to the configuration content input by the operator. Exemplary, in specific implementation, the configuration interface 200 for packaging information can be provided in response to user operation or packaging information acquisition instructions, such as Figure 2 As shown, the packaging information is obtained according to the input configuration of the packaging information by the operator such as the user in the configuration interface 200.

[0059] refer to Figure 2 The configuration interface 200 of the encapsulation information includes, for example: a configuration item area 210 , a configuration input area 220 , and a command area 230 .

[0060] Configuration item area 210 provides at least one configuration item of packaging information. Figure 2 In the example shown, the configuration item area 210 provides multiple layout level information configuration items, target chip size configuration items (die size), scribe line width configuration items (scribe line width), and pad shape configuration items (pad type), wherein multiple layout level information configuration items include, for example: pad layer configuration items (pad layer), pin layer configuration items (pin layer), chip layer configuration items (chip layer) and scribe line layer configuration items (scribe line layer). Of course, in other embodiments of the present application, the packaging information configuration items provided by the configuration item area 210 can also be other combinations. Through the above configuration, it is possible to be compatible with the level selection requirements under different processes when drawing the pad graphics, which is conducive to improving the compatibility of the implementation of the solution.

[0061] The configuration input area 220 provides an input box for each configuration item so that the operator can configure each configuration item in the corresponding input box. Optionally, the input box provided in the configuration input area 220 can be a text box, a selection box (including a radio button, a check box, a drop-down box, etc.) type, or a combination of types. For example, the input box for the pad shape configuration item can be any type of selection box, and the options include rectangle and circle, etc.

[0062] Command area 230 provides command buttons for configuring interface 200. Figure 2 In the example shown, the command area 230 provides a confirmation button (ok) and a cancel / return button (cancel), etc., for configuring the interface 200 .

[0063] It should be noted that Figure 2 The configuration interface 200 of the packaging information shown displays content mainly in English, but the present application is not limited to this. The configuration interface 200 can also display content mainly in a commonly used single language or combination of languages ​​such as Chinese, French, Russian, Arabic, and Spanish.

[0064] In step 130, the packaging information is checked for compliance.

[0065] In this step, the specific implementation method of step 130 includes: checking whether the format of the layout hierarchy information and various numerical values ​​in the packaging information input in step 120 conforms to the format specification under the predetermined process; and checking whether the various numerical values ​​in the packaging information input in step 120 conform to the numerical range specification under the predetermined process.

[0066] Optionally, the compliance check of the package information can be performed synchronously while the operator is inputting the configuration items, so as to provide timely reminders when the format of the input content or the input numerical range does not meet the specifications; or, the compliance check of the package information can be performed after all the package information has been entered, and a unified error prompt can be given for the input items that are detected to be non-compliant with the specifications.

[0067] It can be understood that when the pad information of the target chip is obtained in step 110 by providing a pad information configuration interface, thereby obtaining the pad information according to the content input by the operator, the present application scheme may also include a step of checking the input pad information for compliance.

[0068] By setting up a checking mechanism for input content, it is possible to ensure that the format and content of manually input information are correct, thereby improving the reliability of the drawing result of the pad pattern.

[0069] In step 140, after the inspection is passed, a pad pattern of the target chip is drawn on the integrated circuit layout according to the pad information and the package information using a tool function.

[0070] In this step, the tool function refers to those functions used to perform specific tasks or functions. In some examples, the pad graph drawing scheme provided by the embodiment of the present application can be directly integrated into the EDA tool to realize the drawing and viewing results of the pad graph very easily. At this point, the aforementioned tool function refers to the function encapsulated in the EDA tool for performing specific tasks or functions. After the aforementioned content information of the input is checked, it is only necessary to call the corresponding tool function to draw the pad graph of the target chip on the integrated circuit layout according to the pad information and packaging information obtained, and realize the automatic drawing of the pad graph of the target chip without the need for learning cost.

[0071] Optionally, step 140 may be automatically executed in response to a corresponding instruction after the inspection is passed, or may be executed according to a confirmation action of an operator after the inspection is passed.

[0072] refer to Figure 3 , Figure 3 FIG. 1 shows a schematic diagram of an example of a pad pattern of a target chip after drawing. Figure 3 As shown, the pad pattern after drawing includes a chip area 320, a scribe groove area 310 located around the chip area 320, and a plurality of pads 330 located inside the chip area 320, and the name information of each pad 330 is also drawn inside or around the pad 330, so as to clearly distinguish the plurality of pads 330. It can be seen that the pad pattern drawing scheme provided in the embodiment of the present application can automatically complete the pad pattern drawing of the chip on the integrated circuit layout or other layout for different processes and different packaging forms, and the accuracy and reliability of the drawing result are higher than that of the manual drawing scheme.

[0073] The embodiment of the present invention also provides a device for drawing pad patterns of integrated circuit layouts. The device can be based on the above Figures 1 to 3 The pad pattern drawing method shown realizes the automatic drawing of the pad pattern of the target chip in the integrated circuit layout. Figure 4 As shown, the pad pattern drawing device includes: a pad information acquisition unit 410 , a package information acquisition unit 420 , an inspection unit 430 and a pad pattern drawing unit 440 .

[0074] The pad information acquisition unit 410 is used to acquire pad information of a target chip.

[0075] The packaging information acquiring unit 420 is used to acquire packaging information.

[0076] The checking unit 430 is used to check the input standardization of the packaging information.

[0077] The pad graphic drawing unit 440 is used to draw the pad graphic of the target chip on the integrated circuit layout using a tool function according to the pad information obtained by the pad information obtaining unit 410 and the packaging information obtained by the packaging information obtaining unit 420 after the inspection by the inspection unit 430 is passed.

[0078] The embodiment of the present invention further provides an electronic device, such as Figure 5 As shown, it includes a memory 510 and a processor 520. The memory 510 stores a program that can be run on the processor 520. When the program is executed by the processor 520, the various processes of the various embodiments of the pad graphic drawing method of the integrated circuit layout shown in the aforementioned embodiments can be implemented, and the same technical effect can be achieved. In order to avoid repetition, it will not be repeated here.

[0079] Those skilled in the art will appreciate that all or part of the steps in the various methods of the above embodiments can be completed by instructions, or by controlling related hardware through instructions. The instructions can be stored in a computer-readable storage medium and loaded and executed by a processor. To this end, an embodiment of the present invention further provides a storage medium on which a computer program or instruction is stored. When the computer program or instruction is executed by the processor, the above-mentioned Figures 1 to 3 The various processes of various embodiments of the method for drawing a pad pattern of an integrated circuit layout shown in the figure. Among them, the storage medium is, for example, a U disk, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a disk or an optical disk, and other media that can store program codes.

[0080] Since the instructions stored in the storage medium can execute the steps in the pad pattern drawing method of the integrated circuit layout provided by the embodiment of the present invention, the beneficial effects that can be achieved by the pad pattern drawing method of the integrated circuit layout provided by the embodiment of the present invention can be achieved. For details, please refer to the previous embodiment, which will not be repeated here. The specific implementation of each of the above operations can be referred to the previous embodiment, which will not be repeated here.

[0081] In summary, when drawing the pad graphic, the embodiment of the present application first obtains the pad information and corresponding packaging information of the target chip, and then calls the corresponding tool function to process the obtained pad information and packaging information. In this way, the drawing of the pad graphic of the target chip can be automatically completed, and the operation of automatically importing the pad data into the integrated circuit layout is realized. Compared with the manual drawing method, the present application scheme can greatly improve the drawing efficiency and evaluation efficiency of the integrated circuit package drawing, can avoid the errors that may be caused by manual drawing, and does not require learning costs. It has strong compatibility and is suitable for the drawing of pad graphics in the integrated circuit layout of any process and any packaging form. At the same time, the present application scheme also provides a checking mechanism in the automatic drawing process of the pad graphic, which can ensure the accuracy of the format and content of the input information, thereby ensuring the reliability of the drawing results.

[0082] Finally, it should be noted that: Obviously, the above embodiments are only examples for clearly explaining the present application, and are not intended to limit the implementation methods. For ordinary technicians in the relevant field, other different forms of changes or modifications can be made based on the above description. It is not necessary and impossible to list all the implementation methods here. The obvious changes or modifications derived from this are still within the scope of protection of the present application.

Claims

1. A method for drawing a pad pattern of an integrated circuit layout, comprising: Get the pad information of the target chip; Get packaging information; Checking the standardization of the packaging information; After the inspection is passed, a pad pattern of the target chip is drawn on an integrated circuit layout according to the pad information and the packaging information using a tool function.

2. The pad pattern drawing method according to claim 1, wherein: Get the pad information of the target chip, including: The information file containing the pad information is processed using a pre-prepared script to obtain the pad information from the information file.

3. The pad pattern drawing method according to claim 1, wherein: Get the pad information of the target chip, including: A configuration interface for pad information is provided, and the pad information is obtained according to the content input by the operator.

4. The pad pattern drawing method according to claim 1, wherein: Get package information, including: A configuration interface for packaging information is provided, and the packaging information is obtained according to the configuration content input by the operator.

5. The pad pattern drawing method according to any one of claims 1 to 3, wherein: The pad information includes at least one of the following: Pad name; Pad size; Number of pads; and The pad coordinates of each pad.

6. The pad pattern drawing method according to claim 1 or 4, wherein: The packaging information includes at least one of the following: Layout level information; The size of the target chip; the width of the scribe line; and Pad shape.

7. The pad pattern drawing method according to claim 6, wherein: Check the compliance of the packaging information, including: Checking whether the format of the layout layer information and various values ​​in the input packaging information conforms to the format specification under the predetermined process; and Check whether the various values ​​in the input packaging information meet the value range specifications under the predetermined process.

8. A device for drawing pad patterns of integrated circuit layouts, comprising: A pad information acquisition unit, used to acquire pad information of a target chip; A packaging information acquisition unit, used to acquire packaging information; An inspection unit, used for inspecting the standardization of the packaging information; The pad pattern drawing unit is used to draw the pad pattern of the target chip on the integrated circuit layout according to the pad information and the packaging information by using a tool function after the inspection is passed.

9. A storage medium, wherein: The storage medium stores a computer program or instructions, which, when executed, implement the steps of the method according to any one of claims 1 to 7.

10. An electronic device, wherein: include: A memory, a processor, and a program stored in the memory and executable by the processor, wherein the program implements the steps of the method according to any one of claims 1 to 7 when executed.

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