Layout checking method and device, electronic equipment and storage medium

Abstract

The embodiment of the invention discloses a layout inspection method and device, electronic equipment and a storage medium, relates to the technical field of integrated circuits, and can effectively improve the accuracy of three-dimensional interconnection inspection of a layout. The method comprises the following steps: acquiring a to-be-checked three-dimensional interconnection layout; the three-dimensional interconnection layout comprises an interconnection layout layer, and the interconnection layout layer comprises a first layout layer corresponding to a structure related to three-dimensional interconnection between the crystal grains in the first crystal grain and a second layout layer corresponding to a structure related to three-dimensional interconnection between the crystal grains in the second crystal grain; the first crystal grains and the second crystal grains are stacked with each other to form a three-dimensional chip; according to the pattern distribution information of each interconnection layout layer, determining a relative position relationship between adjacent layout layers and each layout pattern; and performing three-dimensional interconnection check on the three-dimensional interconnection layout according to whether the relative position relationship accords with a preset rule or not. The method is suitable for layout design of the three-dimensional chip.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuit technology, and in particular to a layout inspection method and device, electronic equipment, and a storage medium. Background Art

[0002] In three-dimensional chip design, interconnection verification between stacked grains has always been a top priority, but current EDA (Electronics Design Automation) tools mainly perform various verifications on two-dimensional chips. Verification of three-dimensional chips is not yet mature and has low verification accuracy. For example, many current EDA tools can only check whether two endpoints of the two grains stacked up and down in the layout are connected when checking the interconnection between the layouts of stacked grains. However, if there are multiple parallel paths between the two endpoints, it can only be determined that at least one of the multiple parallel paths is connected. If one or more of the parallel paths are defective and not connected, the existing EDA tools cannot reach the correct conclusion. Summary of the invention

[0003] In view of this, embodiments of the present invention provide a layout inspection method and device, electronic equipment, and storage medium, which can effectively improve the accuracy of three-dimensional interconnection inspection of the layout.

[0004] In a first aspect, an embodiment of the present invention provides a layout inspection method, comprising: obtaining a three-dimensional interconnection layout to be inspected; the three-dimensional interconnection layout comprises an interconnection layout layer, the interconnection layout layer comprises a first layout layer corresponding to a structure related to the three-dimensional interconnection between grains in a first grain, and a second layout layer corresponding to a structure related to the three-dimensional interconnection between grains in a second grain; the first grain and the second grain are used to be stacked with each other to form a three-dimensional chip; according to pattern distribution information of each interconnection layout layer, a relative position relationship between each layout pattern between adjacent layout layers is determined; wherein the adjacent layout layers are interconnection layout layers adjacent to each other in the grain stacking direction in the three-dimensional interconnection layout; and according to whether the relative position relationship meets a preset rule, a three-dimensional interconnection inspection is performed on the three-dimensional interconnection layout.

[0005] In one embodiment, determining the relative position relationship of each layout pattern between adjacent layout layers according to the pattern distribution information of each interconnected layout layer includes: according to the pattern distribution information of each interconnected layout layer, taking the target layer as the starting point, and determining the relative position relationship of each layout pattern between every two adjacent layout layers in sequence along the grain stacking direction, wherein the target layer is any one layer or any multiple layers in each interconnected layout layer.

[0006] In one embodiment, the target layer includes at least one of the following among the interconnection layout layers of the three-dimensional interconnection layout: a top layout layer, a bottom layout layer, and a middle layout layer.

[0007] In one embodiment, the target layer includes the top layout layer and / or the bottom layout layer; when the top layout layer is used as the target layer, the grain stacking direction includes a direction from the top layout layer to the bottom layout layer; when the bottom layer is used as the target layer, the grain stacking direction includes a direction from the bottom layout layer to the top layout layer.

[0008] In one embodiment, the target layer includes the intermediate layer; the grain stacking direction includes a direction from the intermediate layer to the bottom layer, and a direction from the intermediate layer to the top layer.

[0009] In one embodiment, the method of determining the relative position relationship of each layout pattern between every two adjacent layout layers in sequence along the grain stacking direction with the target layer as the starting point according to the pattern distribution information of each interconnected layout layer comprises: determining each target pattern in the target layer according to the pattern distribution information of the target layer, so that any two different target patterns are spaced apart from each other in the target layer; determining the target layer as a first iteration layer, and determining the target pattern as a first iteration pattern; respectively checking whether each of the first iteration patterns in the first iteration layer overlaps with the layout pattern in the second iteration layer; wherein the second iteration layer is overlapped with the first iteration pattern in the grain stacking direction; The interconnection layout layer adjacent to the first iteration layer; determining the layout pattern in the second iteration layer that overlaps with the first iteration pattern as the second iteration pattern, and determining the pattern formed by the overlapping part as the overlapping pattern; using the second iteration layer as the new first iteration layer, using the second iteration pattern as the new first iteration pattern, jumping to the step of respectively checking whether each of the first iteration patterns in the first iteration layer overlaps with the layout pattern in the second iteration layer, and iterating in a loop until the second iteration pattern is the preset termination layer in the grain stacking direction, wherein the termination layer is at least one of the interconnection layout layers in the three-dimensional interconnection layout.

[0010] In one embodiment, the three-dimensional interconnection inspection of the three-dimensional interconnection layout according to whether the relative position relationship conforms to a preset rule includes: determining a first overlapping pattern corresponding to a preset statistical layer, the first overlapping pattern being the overlapping pattern in the second iterative layer when the second iterative layer is the statistical layer, wherein the statistical layer is at least one of the interconnection layout layers from the target layer to the termination layer; determining first overlapping information of the statistical layer according to the first overlapping pattern, the first overlapping information including the number and / or position of the first overlapping pattern; comparing the first overlapping information with the second overlapping information preset in the statistical layer to obtain a comparison result; and performing a three-dimensional interconnection inspection on the three-dimensional interconnection layout according to the comparison result.

[0011] In one embodiment, the performing three-dimensional interconnection inspection on the three-dimensional interconnection layout according to the comparison result includes: when the first overlap information is consistent with the second overlap information, determining that the three-dimensional interconnection of the three-dimensional interconnection layout is qualified; or, when the first overlap information is inconsistent with the second overlap information, determining that the three-dimensional interconnection of the three-dimensional interconnection layout has defects and locating the defects.

[0012] In one embodiment, the second overlapping information includes the number and / or location of second overlapping patterns expected to exist between the layout pattern in the statistical layer and the layout pattern in the adjacent layout layer of the statistical layer.

[0013] In one embodiment, determining the relative position relationship of each layout pattern between adjacent layout layers according to the pattern distribution information of each interconnected layout layer includes: determining the relative position relationship of each layout pattern between adjacent layout layers according to the pattern distribution information of each interconnected layout layer, and determining the interconnection path between each interconnected layout layer according to the layout patterns overlapping each other in the relative position relationship; performing a three-dimensional interconnection check on the three-dimensional interconnected layout according to whether the relative position relationship conforms to a preset rule includes: performing a three-dimensional interconnection check on the three-dimensional interconnected layout according to whether the interconnection path conforms to a preset rule.

[0014] In one embodiment, after performing a three-dimensional interconnection inspection on the three-dimensional interconnection layout according to whether the relative position relationship conforms to a preset rule, the method further comprises: highlighting a layout portion with defects according to the inspection result.

[0015] In one embodiment, the first pattern layer includes: a pattern layer corresponding to the top metal of the first crystal grain, a pattern layer corresponding to the through silicon via of the first crystal grain, a pattern layer corresponding to the back metal of the first crystal grain, and a pattern layer corresponding to the bonding layer of the first crystal grain; the second pattern layer includes: a pattern layer corresponding to the bonding layer of the second crystal grain, and a pattern layer corresponding to the top metal of the second crystal grain; wherein the bonding layer of the first crystal grain is arranged on the back metal of the first crystal grain, and the bonding layer of the second crystal grain is arranged on the top metal of the second crystal grain, the bonding layer of the first crystal grain and the bonding layer of the second crystal grain correspond to each other, and are used to bond the first crystal grain to the second crystal grain; the top metal of the first crystal grain is electrically connected to the back metal of the first crystal grain through the through silicon via of the first crystal grain.

[0016] In a second aspect, an embodiment of the present invention further provides a layout inspection device, comprising: an acquisition unit, used to acquire a three-dimensional interconnection layout to be inspected; the three-dimensional interconnection layout includes an interconnection layout layer, the interconnection layout layer includes a first layout layer corresponding to a structure related to the three-dimensional interconnection between grains in a first grain, and a second layout layer corresponding to a structure related to the three-dimensional interconnection between grains in a second grain; the first grain and the second grain are used to be stacked on each other to form a three-dimensional chip; a determination unit, used to determine the relative position relationship of each layout pattern between adjacent layout layers according to pattern distribution information of each interconnection layout layer; wherein the adjacent layout layers are the interconnection layout layers adjacent to each other in the grain stacking direction in the three-dimensional interconnection layout; an inspection unit, used to perform a three-dimensional interconnection inspection on the three-dimensional interconnection layout according to whether the relative position relationship meets a preset rule.

[0017] In one embodiment, the determination unit is specifically used to determine the relative position relationship of each layout pattern between every two adjacent layout layers along the grain stacking direction based on the pattern distribution information of each interconnected layout layer, starting from the target layer, wherein the target layer is any one layer or any multiple layers in each of the interconnected layout layers.

[0018] In one embodiment, the target layer includes at least one of the following among the interconnection layout layers of the three-dimensional interconnection layout: a top layout layer, a bottom layout layer, and a middle layout layer.

[0019] In one embodiment, the target layer includes the top layout layer and / or the bottom layout layer; when the top layout layer is used as the target layer, the grain stacking direction includes a direction from the top layout layer to the bottom layout layer; when the bottom layer is used as the target layer, the grain stacking direction includes a direction from the bottom layout layer to the top layout layer.

[0020] In one embodiment, the target layer includes the intermediate layer; the grain stacking direction includes a direction from the intermediate layer to the bottom layer, and a direction from the intermediate layer to the top layer.

[0021] In one embodiment, the determination unit includes: a first determination module, which is used to determine each target pattern in the target layer according to pattern distribution information of the target layer, so that any two different target patterns are spaced from each other in the target layer; a second determination module, which is used to determine the target layer as a first iteration layer and the target pattern as a first iteration pattern; a first inspection module, which is used to respectively check whether each of the first iteration patterns in the first iteration layer overlaps with a layout pattern in a second iteration layer; wherein the second iteration layer is the interconnection layout layer adjacent to the first iteration layer in the grain stacking direction; a third determination module, which is used to determine a layout pattern in the second iteration layer that overlaps with the first iteration pattern as a second iteration pattern, and to determine a pattern formed by the overlapping part as an overlapping pattern; a trigger module, which is used to use the second iteration layer as a new first iteration layer and the second iteration pattern as a new first iteration pattern, and trigger the first inspection module to respectively check whether each of the first iteration patterns in the first iteration layer overlaps with a layout pattern in the second iteration layer, and iterate in a loop until the second iteration pattern is a preset termination layer in the grain stacking direction, wherein the termination layer is at least one of the interconnection layout layers in the three-dimensional interconnection layout.

[0022] In one embodiment, the inspection unit includes: a fourth determination module, used to determine a first overlapping pattern corresponding to a preset statistical layer, the first overlapping pattern being the overlapping pattern in the second iterative layer when the second iterative layer is the statistical layer, wherein the statistical layer is at least one of the interconnection layout layers from the target layer to the termination layer; a fifth determination module, used to determine first overlapping information of the statistical layer according to the first overlapping pattern, the first overlapping information including the number and / or position of the first overlapping pattern; a comparison module, used to compare the first overlapping information with second overlapping information preset in the statistical layer to obtain a comparison result; and a second inspection module, used to perform a three-dimensional interconnection inspection on the three-dimensional interconnection layout according to the comparison result.

[0023] In one embodiment, the second inspection module is specifically used to: determine that the three-dimensional interconnection of the three-dimensional interconnection layout is qualified when the first overlap information is consistent with the second overlap information; or determine that the three-dimensional interconnection of the three-dimensional interconnection layout has defects and locate the defects when the first overlap information is inconsistent with the second overlap information.

[0024] In one embodiment, the second overlapping information includes the number and / or location of second overlapping patterns expected to exist between the layout pattern in the statistical layer and the layout pattern in the adjacent layout layer of the statistical layer.

[0025] In one embodiment, the determination unit is specifically used to determine the relative position relationship of each layout pattern between the adjacent layout layers according to the pattern distribution information of each interconnected layout layer, and determine the interconnection path between each interconnected layout layer according to the layout patterns overlapping each other in the relative position relationship; the inspection unit is specifically used to: perform a three-dimensional interconnection inspection on the three-dimensional interconnected layout according to whether the interconnection path meets the preset rules.

[0026] In one embodiment, the device further includes a display unit for highlighting defective layout parts according to the inspection result after performing a three-dimensional interconnection inspection on the three-dimensional interconnection layout according to whether the relative position relationship conforms to a preset rule.

[0027] In one embodiment, the first pattern layer includes: a pattern layer corresponding to the top metal of the first crystal grain, a pattern layer corresponding to the through silicon via of the first crystal grain, a pattern layer corresponding to the back metal of the first crystal grain, and a pattern layer corresponding to the bonding layer of the first crystal grain; the second pattern layer includes: a pattern layer corresponding to the bonding layer of the second crystal grain, and a pattern layer corresponding to the top metal of the second crystal grain; wherein the bonding layer of the first crystal grain is arranged on the back metal of the first crystal grain, and the bonding layer of the second crystal grain is arranged on the top metal of the second crystal grain, the bonding layer of the first crystal grain and the bonding layer of the second crystal grain correspond to each other, and are used to bond the first crystal grain to the second crystal grain; the top metal of the first crystal grain is electrically connected to the back metal of the first crystal grain through the through silicon via of the first crystal grain.

[0028] In a third aspect, an embodiment of the present invention further provides an electronic device, comprising: a processor and a memory, wherein the processor is electrically connected to the memory; the memory is used to store executable program code; the processor runs a program corresponding to the executable program code by reading the executable program code stored in the memory, so as to implement any layout inspection method provided by the embodiments of the present invention.

[0029] In a fourth aspect, an embodiment of the present invention further provides a computer-readable storage medium, characterized in that the computer-readable storage medium stores one or more programs, and the one or more programs can be executed by one or more processors to implement any one of the layout inspection methods provided by the embodiments of the present invention.

[0030] The layout inspection method and device, electronic device, and storage medium provided by the embodiments of the present invention can obtain a three-dimensional interconnected layout to be inspected, determine the relative position relationship of each layout pattern between adjacent layout layers according to the pattern distribution information of each interconnected layout layer in the three-dimensional interconnected layout, and perform a three-dimensional interconnection inspection on the three-dimensional interconnected layout according to whether the relative position relationship conforms to a preset rule. Since the interconnected layout layer includes a first layout layer corresponding to a structure related to the three-dimensional interconnection between grains in the first crystal grain, and a second layout layer corresponding to a structure related to the three-dimensional interconnection between grains in the second crystal grain, and the adjacent layout layers are interconnected layout layers adjacent to each other in the grain stacking direction in the three-dimensional interconnected layout, the relative position relationship between each layout pattern between each adjacent interconnected layout layer can be used to inspect the interconnection between each interconnected layout layer layer by layer and layout pattern by layout pattern, so as to facilitate the discovery of detailed problems in the interconnection, rather than only checking whether the two endpoints in the three-dimensional interconnection are connected, so as to effectively improve the accuracy of the three-dimensional interconnection inspection of the layout. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0032] Figure 1 A flow chart of a layout inspection method provided by an embodiment of the present invention; Figure 2 A schematic diagram of a grain structure corresponding to a three-dimensional interconnection layout in an embodiment of the present invention; Figure 3 A schematic diagram of the positions of the target layer and the termination layer in an embodiment of the present invention; Figure 4 Another schematic diagram of the positions of the target layer and the termination layer in the embodiment of the present invention; Figure 5 It is another schematic diagram of the positions of the target layer and the termination layer in the embodiment of the present invention; Figure 6 It is another schematic diagram of the positions of the target layer and the termination layer in the embodiment of the present invention; Figure 7 A structural schematic diagram of the overlapping of layout patterns between adjacent layout layers in an embodiment of the present invention; Figure 8 A schematic diagram of a structure of a first overlapping pattern corresponding to a statistical layer in an embodiment of the present invention; Fig. 9A schematic diagram of a structure of overlapping patterns and interconnection paths between adjacent layout layers in an embodiment of the present invention; Fig.10 A detailed flow chart of a layout inspection method provided by an embodiment of the present invention; Fig.11 A schematic diagram of the structure of a layout inspection device provided by an embodiment of the present invention; Fig.12 A schematic structural diagram of an electronic device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0033] The embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0034] It should be clear that the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0035] In a first aspect, an embodiment of the present invention provides a layout inspection method, which can effectively improve the accuracy of three-dimensional interconnection inspection of the layout.

[0036] like Figure 1 As shown, an embodiment of the present invention provides a layout inspection method, comprising: S11, obtaining a three-dimensional interconnection layout to be inspected; the three-dimensional interconnection layout includes an interconnection layout layer, the interconnection layout layer includes a first layout layer corresponding to a structure related to the three-dimensional interconnection between grains in a first grain, and a second layout layer corresponding to a structure related to the three-dimensional interconnection between grains in a second grain; the first grain and the second grain are used to be stacked on each other to form a three-dimensional chip; In an embodiment of the present invention, a three-dimensional interconnection layout may refer to a set of layouts related to the three-dimensional interconnection between grains, and may include multiple interconnection layout layers. Here, the three-dimensional interconnection may refer to the electrical connection between grains, for example, the connection between the metal layer of one grain and the metal layer of another grain. In an embodiment of the present invention, the three-dimensional interconnection between grains is described by taking the first grain and the second grain stacked on each other as an example. Based on this, each interconnection layout layer of the three-dimensional interconnection layout may include a first layout layer and a second layout layer, wherein the first layout layer may refer to a layout layer corresponding to a structure related to the three-dimensional interconnection between grains in the first grain, such as a layout layer corresponding to a through-silicon via structure in the first grain. The second layout layer may refer to a layout layer corresponding to a structure related to the three-dimensional interconnection between grains in the second grain, such as a layout layer corresponding to a hybrid bonding structure in the second grain. Depending on the grain structure and function, the number of the first layout layer and the second layout layer may be set and adjusted accordingly, and the embodiment of the present invention does not limit this. For example, in one example, the number of the first layout layer is 3 layers, and the number of the second layout layer is 2 layers, and in another example, the number of the first layout layer is 4 layers, and the number of the second layout layer is 3 layers.

[0037] S12, determining the relative position relationship of each layout pattern between adjacent layout layers according to the pattern distribution information of each interconnected layout layer; wherein the adjacent layout layers are the interconnected layout layers adjacent to each other in the grain stacking direction in the three-dimensional interconnected layout; Various patterns may be provided in each interconnected layout layer to form a corresponding three-dimensional interconnected structure. In the embodiment of the present invention, the relative position relationship of each layout pattern between adjacent layout layers may be determined based on the pattern distribution information of each interconnected layout layer. For example, in one example, the interconnected layout layer L1 and the interconnected layout layer L2 are two adjacent layout layers. Then, based on the coordinates of pattern A in the interconnected layout layer L1 and the coordinates of pattern B in the interconnected layout layer L2, it may be determined whether pattern A overlaps with pattern B. If they overlap, what is the overlapping pattern, where is the overlapping position, etc.

[0038] S13, performing a three-dimensional interconnection check on the three-dimensional interconnection layout according to whether the relative position relationship conforms to a preset rule.

[0039] In this step, it is possible to check whether the relative position relationship of each layout pattern between adjacent layout layers conforms to the preset rules, thereby realizing the three-dimensional interconnection check of the three-dimensional interconnected layout.

[0040] The layout inspection method provided by the embodiment of the present invention can obtain a three-dimensional interconnected layout to be inspected, determine the relative position relationship of each layout pattern between adjacent layout layers according to the pattern distribution information of each interconnected layout layer in the three-dimensional interconnected layout, and perform a three-dimensional interconnection inspection on the three-dimensional interconnected layout according to whether the relative position relationship conforms to a preset rule. Since the interconnected layout layer includes a first layout layer corresponding to a structure related to the three-dimensional interconnection between grains in the first crystal grain, and a second layout layer corresponding to a structure related to the three-dimensional interconnection between grains in the second crystal grain, and the adjacent layout layers are interconnected layout layers adjacent to each other in the grain stacking direction in the three-dimensional interconnected layout, the relative position relationship between each layout pattern between each adjacent interconnected layout layer can be used to inspect the interconnection between each interconnected layout layer layer by layer and layout pattern by pattern, so as to facilitate the discovery of detailed problems in the interconnection, rather than only checking whether the two endpoints in the three-dimensional interconnection are connected, so as to effectively improve the accuracy of the three-dimensional interconnection inspection of the layout.

[0041] Specifically, in one embodiment of the present invention, in step S11, the three-dimensional interconnection layout to be checked can be obtained in a variety of ways. For example, in some examples, the three-dimensional interconnection layout can be obtained by making a separate layout for the interconnection between the grains. In other examples, the three-dimensional interconnection layout can also be obtained by extracting the layout layers related to the three-dimensional interconnection between the grains from the layout of each grain stacked on each other and recombining them.

[0042] In an embodiment of the present invention, the interconnection pattern layer may include a first pattern layer corresponding to various structures related to the three-dimensional interconnection between the grains in the first grain, and a second pattern layer corresponding to various structures related to the three-dimensional interconnection between the grains in the second grain. Figure 2 As shown, in one example, the first layout layer may include: a layout layer corresponding to the top metal MT1 of the first crystal grain DIE1, a layout layer corresponding to the through silicon via TSV1 of the first crystal grain, a layout layer corresponding to the back metal MB1 of the first crystal grain, and a layout layer corresponding to the bonding layer MH1 of the first crystal grain; the second layout layer may include: a layout layer corresponding to the bonding layer MH2 of the second crystal grain DIE2, and a layout layer corresponding to the top metal MT2 of the second crystal grain DIE2. The bonding layer MH1 of the first crystal grain DIE1 is arranged on the back metal MB1 of the first crystal grain DIE1, and the bonding layer MH2 of the second crystal grain DIE2 is arranged on the top metal MT2 of the second crystal grain DIE2. The bonding layer MH1 of the first crystal grain DIE1 and the bonding layer MH2 of the second crystal grain DIE2 correspond to each other and are used to bond the first crystal grain DIE1 to the second crystal grain DIE2; the top metal MT1 of the first crystal grain DIE1 is electrically connected to the back metal MB1 of the first crystal grain DIE1 through the through silicon via TSV1 of the first crystal grain DIE1.

[0043] After obtaining the three-dimensional interconnected layout, in step S12, the relative position relationship of each layout pattern between adjacent layout layers can be determined according to the pattern distribution information of each interconnected layout layer. Specifically, in one embodiment of the present invention, determining the relative position relationship of each layout pattern between adjacent layout layers according to the pattern distribution information of each interconnected layout layer may include: according to the pattern distribution information of each interconnected layout layer, starting from the target layer, sequentially determining the relative position relationship of each layout pattern between every two adjacent layout layers along the grain stacking direction, wherein the target layer may be any one or any multiple layers of each interconnected layout layer. Here, the grain stacking direction may be perpendicular to the grain surface, that is, it may include a direction perpendicular to the grain surface and pointing upward, or it may include a direction perpendicular to the grain surface and pointing downward, and the embodiment of the present invention does not limit this. That is to say, in the embodiment of the present invention, when determining the relative position relationship of each layout pattern between adjacent layout layers, it can be carried out in a certain order, so as to be more organized and effectively avoid repeated inspection or missed inspection.

[0044] Optionally, in an embodiment of the present invention, the target layer may include at least one of the following among the interconnected layout layers of the three-dimensional interconnected layout: a top layout layer, a bottom layout layer, and an intermediate layout layer. The top layout layer and the bottom layout layer are layout layers located at both ends of the three-dimensional interconnected layout, and the intermediate layout layer is a layout layer located in the middle of the three-dimensional interconnected layout layer. In the three-dimensional interconnected layout layer, all layout layers except the top layout layer and the bottom layout layer are intermediate layout layers. The number of adjacent layout layers of the top layout layer and the bottom layout layer is one, and the number of adjacent layout layers of each intermediate layout layer is two.

[0045] In one embodiment, the target layer includes the top layout layer and / or the bottom layout layer; when the top layout layer is used as the target layer, the grain stacking direction includes a direction from the top layout layer to the bottom layout layer; when the bottom layer is used as the target layer, the grain stacking direction includes a direction from the bottom layout layer to the top layout layer.

[0046] In another embodiment, the target layer may include an intermediate layer, and the die stacking direction may include a direction from the intermediate layer to the bottom layer, and a direction from the intermediate layer to the top layer.

[0047] In a specific implementation, according to the pattern distribution information of each interconnected layout layer, starting from the target layer, the relative position relationship of each layout pattern between every two adjacent layout layers is determined in sequence along the grain stacking direction, which may include: determining each target pattern in the target layer according to the pattern distribution information of the target layer, so that any two different target patterns are spaced apart from each other in the target layer; determining the target layer as a first iteration layer, and determining the target pattern as a first iteration pattern; respectively checking whether each of the first iteration patterns in the first iteration layer overlaps with the layout pattern in the second iteration layer; wherein the second iteration layer is overlapped with the layout pattern in the first iteration layer in the grain stacking direction; The interconnection layout layer is adjacent to an iteration layer; the layout pattern in the second iteration layer that overlaps with the first iteration pattern is determined as the second iteration pattern, and the pattern formed by the overlapping part is determined as the overlapping pattern; the second iteration layer is used as the new first iteration layer, and the second iteration pattern is used as the new first iteration pattern, and the step of respectively checking whether each of the first iteration patterns in the first iteration layer overlaps with the layout pattern in the second iteration layer is performed, and iterates in a loop until the second iteration pattern is a preset termination layer in the grain stacking direction, wherein the termination layer is at least one of the interconnection layout layers in the three-dimensional interconnection layout.

[0048] In this embodiment, starting from the target layer, the layout pattern overlap between two adjacent interconnected layout layers is checked layer by layer along the grain stacking direction until the second iterative pattern is a termination layer pre-set in the grain stacking direction. The termination layer or layers of interconnected layout layers may be set and adjusted according to specific needs. In one embodiment of the present invention, each grain stacking direction may correspond to a termination layer, and the termination layers corresponding to different grain stacking directions may be the same or different. The embodiments of the present invention are not limited to this. The interconnected layout layers from the target layer to the termination layer may include all interconnected layout layers in the three-dimensional interconnected layout layer, or may only include part of the interconnected layout layers in the three-dimensional interconnected layout layer. The embodiments of the present invention are not limited to this. For example, Figure 3 As shown, in one example, the target layer may be the LA layer, and the termination layer may be the LB layer. Figure 4 As shown, in another example, the target layer may be the LA1 and LA2 layers, and the termination layer may be the LB layer. Figure 5 As shown, in another example, the target layer may be the LA layer, and the termination layer may be the LB1 and LB2 layers. Figure 6 As shown, in yet another example, the target layer may be the LA layer, and the termination layers may be the LC1 and LC2 layers.

[0049] In an embodiment of the present invention, the target layer and the termination layer are different, the layout inspection order is also different accordingly, and the amount of calculation involved will also be different. For example, under the same conditions, the amount of calculation for checking along two different grain stacking directions will be smaller than the amount of calculation for checking along the same grain stacking direction. In specific implementations, the target layer and the termination layer can be flexibly determined as needed.

[0050] The iterative process of the first iterative layer and the second iterative layer is briefly described below.

[0051] In one embodiment of the present invention, the three interconnection layout layers L1, L2, L3 in the three-dimensional interconnection layout can be as follows: Figure 7 As shown, L1 is the target layer and L3 is the termination layer. With L1 as the first iteration layer, the layout pattern on L1 as the first iteration pattern, and L2 as the second iteration layer, the layout overlap between L1 and L2 can be checked first. Specifically, the patterns P21 and P22 in the second iteration layer L2 overlap with the first iteration pattern P1 in the first iteration layer L1, and the patterns formed by the overlapping parts are overlapping patterns PA and PB. Further, L2 can be taken as the new first iteration layer, the patterns P21 and P22 as the new first iteration patterns, and L3 as the new second iteration layer to check the overlap between the patterns P21 and P22 in L2 and the layout pattern in L3. The inspection result can be, for example, that the pattern P21 overlaps with the pattern P3 in L3, and the pattern formed by the overlapping part is the overlapping pattern PC. In this way, starting from the target layer, the relative position relationship of each layout pattern between every two adjacent layout layers in the three-dimensional interconnection layout can be determined in sequence along the grain stacking direction, so that the interconnection path between each interconnection layout layer can be gradually extended based on the above overlapping pattern.

[0052] Further, starting from the target layer, after determining the relative position relationship of each layout pattern between each two adjacent layout layers in sequence along the grain stacking direction, the three-dimensional interconnection inspection can be performed on the three-dimensional interconnection layout according to whether the relative position relationship conforms to the preset rule. Specifically, in one embodiment of the present invention, performing the three-dimensional interconnection inspection on the three-dimensional interconnection layout according to whether the relative position relationship conforms to the preset rule may include: determining a first overlapping pattern corresponding to a preset statistical layer, the first overlapping pattern being the overlapping pattern in the second iterative layer when the second iterative layer is the statistical layer, wherein the statistical layer is at least one of the interconnection layout layers from the target layer to the termination layer; determining the first overlapping information of the statistical layer according to the first overlapping pattern, the first overlapping information including the number and / or position of the first overlapping pattern; comparing the first overlapping information with the second overlapping information preset in the statistical layer to obtain a comparison result; and performing the three-dimensional interconnection inspection on the three-dimensional interconnection layout according to the comparison result.

[0053] For example, Figure 7 Taking the embodiment shown as an example, in one embodiment of the present invention, if the preset statistical layer is L3, then when the second iteration layer is L3, the overlapping pattern PC in L3 is the first overlapping pattern of the statistical layer L3, and the first overlapping information of the statistical layer L3 can be determined according to the overlapping pattern PC. Exemplarily, in one example, the first overlapping information may include: the number of the first overlapping pattern (i.e., the overlapping pattern PC) is 1, the position of the first overlapping pattern is a rectangle with (x1, y1) and (x2, y2) as vertices, etc. After obtaining the first overlapping information, the first overlapping information can be compared with the second overlapping information preset in the statistical layer L3 to obtain a comparison result; and the three-dimensional interconnection layout can be checked for three-dimensional interconnection according to the comparison result.

[0054] In an embodiment of the present invention, the second overlapping information may include the number and / or position of the second overlapping patterns expected to exist between the layout pattern in the statistical layer and the layout pattern in the adjacent layout layer of the statistical layer. For example, in one example, if the second overlapping information is that the number of second overlapping patterns is 2.

[0055] In a specific implementation, performing a three-dimensional interconnection check on the three-dimensional interconnection layout according to the comparison result may include: determining that the three-dimensional interconnection of the three-dimensional interconnection layout is qualified when the first overlap information is consistent with the second overlap information; or determining that the three-dimensional interconnection of the three-dimensional interconnection layout has defects and locating the defects when the first overlap information is inconsistent with the second overlap information. For example, in one example, if the corresponding first overlap information between the statistical layer and its adjacent layout layer includes 2 overlap patterns, and the corresponding second overlap information includes 3 overlap patterns, that is, the actual overlap pattern is one less than the expected overlap pattern, so there is a defect, based on which, the defect can be located according to the position of the redundant overlap pattern in the second overlap information.

[0056] It should be noted that, in the embodiment of the present invention, according to the specific positions of the target layer, the termination layer and the statistical layer, for each statistical layer, the statistical layer can be either a second iterative layer corresponding to one grain stacking direction or a second iterative layer corresponding to two different grain stacking directions, wherein each second iterative layer corresponding to the statistical layer can have its own corresponding first overlapping pattern. Figure 8 As shown, in one example, the first overlapping pattern of the statistical layer T in the die stacking direction D1 is PD1, and the first overlapping pattern of the statistical layer T in the die stacking direction D2 is PD2.

[0057] In the aforementioned embodiments, when determining the relative position relationship of each layout pattern between adjacent layout layers, the interconnection path between adjacent layout layers is extended layer by layer in the order from the target layer to the termination layer, but the embodiments of the present invention are not limited thereto. In other embodiments of the present invention, other methods may be used to determine the relative position relationship of each layout pattern between adjacent layout layers. Specifically, in one embodiment, determining the relative position relationship of each layout pattern between adjacent layout layers according to the pattern distribution information of each interconnected layout layer may include: determining the relative position relationship of each layout pattern between adjacent layout layers according to the pattern distribution information of each interconnected layout layer, and determining the interconnection path between each interconnected layout layer according to the layout patterns that overlap with each other in the relative position relationship. Based on this, performing a three-dimensional interconnection check on the three-dimensional interconnected layout according to whether the relative position relationship meets the preset rules may include: performing a three-dimensional interconnection check on the three-dimensional interconnected layout according to whether the interconnection path meets the preset rules. For example, if Fig. 9 As shown, it can be determined that there are overlapping patterns A1 and A2 between adjacent layout layers L1 and L2, overlapping patterns A3 between adjacent layout layers L3 and L4, and overlapping patterns A4 between adjacent layout layers L2 and L3, so that it can be determined that there are interconnection paths A1-A4-A3 between adjacent layout layers L1, L2, L3, and L4. Since the overlapping pattern A2 is not interconnected with the pattern in the L3 layer, no corresponding interconnection paths are formed in L1, L2, L3, and L4. Based on this, the three-dimensional interconnection layout can be checked for three-dimensional interconnection according to whether these interconnection paths are consistent with the preset interconnection paths.

[0058] Furthermore, after performing a three-dimensional interconnection inspection on the three-dimensional interconnection layout according to whether the relative position relationship conforms to a preset rule, the layout inspection method provided by an embodiment of the present invention may further include: highlighting defective layout portions according to the inspection results, thereby providing intuitive prompts to the user.

[0059] The layout inspection method provided by the embodiment of the present invention is described in detail below through a specific embodiment.

[0060] like Fig.10 As shown, the layout inspection method provided by the embodiment of the present invention may include: S201, obtaining a three-dimensional interconnection layout to be checked.

[0061] Among them, the three-dimensional interconnection layout includes an interconnection layout layer, and the interconnection layout layer includes a first layout layer corresponding to the structure related to the three-dimensional interconnection between grains in the first grain, and a second layout layer corresponding to the structure related to the three-dimensional interconnection between grains in the second grain; the first grain and the second grain are used to be stacked on each other to form a three-dimensional chip.

[0062] S202 . Determine target patterns in the target layer according to pattern distribution information of the target layer, so that any two different target patterns are spaced apart from each other in the target layer.

[0063] The target layer is any one or multiple layers of the interconnected layers.

[0064] S203, determining the target layer as the first iteration layer, and determining the target pattern as the first iteration pattern; S204 , respectively checking whether each first iteration pattern in the first iteration layer overlaps with a layout pattern in the second iteration layer.

[0065] Wherein, the second iteration layer is an interconnection pattern layer adjacent to the first iteration layer in the grain stacking direction; S205, determining the layout pattern in the second iteration layer that overlaps with the first iteration pattern as the second iteration pattern, and determining the pattern formed by the overlapping portion as the overlapping pattern; S206 , whether the second iteration pattern is a preset termination layer in the direction of grain stacking, if so, execute step S208 , if not, execute step S207 .

[0066] Wherein, the termination layer is at least one interconnection layout layer in the three-dimensional interconnection layout.

[0067] S207 , using the second iteration layer as a new first iteration layer, using the second iteration pattern as a new first iteration pattern, and jumping to step S204 .

[0068] S208: Determine a first overlapping pattern corresponding to a preset statistical layer, where the first overlapping pattern is an overlapping pattern in the second iterative layer when the second iterative layer is a statistical layer.

[0069] Wherein, the statistical layer is at least one interconnected layer from the target layer to the termination layer; S209: Determine first overlapping information of the statistical layer according to the first overlapping pattern.

[0070] The first overlap information includes the number and / or positions of the first overlap patterns.

[0071] S210, comparing the first overlapping information with the second overlapping information preset in the statistical layer to determine whether the two are consistent, if they are consistent, executing step S211, if they are inconsistent, executing step S212.

[0072] S211, determine whether the three-dimensional interconnection of the three-dimensional interconnection layout is qualified, and end.

[0073] S212, determining that a three-dimensional interconnection of the three-dimensional interconnection layout has a defect and locating the defect.

[0074] S213, highlighting the defective layout parts.

[0075] In a second aspect, an embodiment of the present invention provides a layout inspection device that can effectively improve the accuracy of three-dimensional interconnection inspection of a layout.

[0076] like Fig.11 As shown, an embodiment of the present invention further provides a layout inspection device, comprising: The acquisition unit 31 is used to acquire a three-dimensional interconnection layout to be checked; the three-dimensional interconnection layout includes an interconnection layout layer, and the interconnection layout layer includes a first layout layer corresponding to a structure related to the three-dimensional interconnection between the grains in the first grain, and a second layout layer corresponding to a structure related to the three-dimensional interconnection between the grains in the second grain; the first grain and the second grain are used to be stacked on each other to form a three-dimensional chip; A determination unit 32 is used to determine the relative position relationship of each layout pattern between adjacent layout layers according to the pattern distribution information of each interconnection layout layer; wherein the adjacent layout layers are the interconnection layout layers adjacent to each other in the grain stacking direction in the three-dimensional interconnection layout; The checking unit 33 is used to perform a three-dimensional interconnection check on the three-dimensional interconnection layout according to whether the relative position relationship conforms to a preset rule.

[0077] The layout inspection device provided by the embodiment of the present invention can obtain a three-dimensional interconnected layout to be inspected, determine the relative position relationship of each layout pattern between adjacent layout layers according to the pattern distribution information of each interconnected layout layer in the three-dimensional interconnected layout, and perform a three-dimensional interconnection inspection on the three-dimensional interconnected layout according to whether the relative position relationship conforms to a preset rule. Since the interconnected layout layer includes a first layout layer corresponding to a structure related to the three-dimensional interconnection between grains in the first crystal grain, and a second layout layer corresponding to a structure related to the three-dimensional interconnection between grains in the second crystal grain, and the adjacent layout layers are interconnected layout layers adjacent to each other in the grain stacking direction in the three-dimensional interconnected layout, the relative position relationship between each layout pattern between each adjacent interconnected layout layer can be used to inspect the interconnection between each interconnected layout layer layer by layer and layout pattern by pattern, so as to facilitate the discovery of detailed problems in the interconnection, rather than only checking whether the two endpoints in the three-dimensional interconnection are connected, so as to effectively improve the accuracy of the three-dimensional interconnection inspection of the layout.

[0078] In one embodiment, the determination unit 32 is specifically used to determine the relative position relationship of each layout pattern between every two adjacent layout layers along the grain stacking direction based on the pattern distribution information of each of the interconnected layout layers, starting from the target layer, wherein the target layer is any one layer or any multiple layers of each of the interconnected layout layers.

[0079] In one embodiment, the target layer includes at least one of the following among the interconnection layout layers of the three-dimensional interconnection layout: a top layout layer, a bottom layout layer, and a middle layout layer.

[0080] In one embodiment, the target layer includes the top layout layer and / or the bottom layout layer; when the top layout layer is used as the target layer, the grain stacking direction includes a direction from the top layout layer to the bottom layout layer; when the bottom layer is used as the target layer, the grain stacking direction includes a direction from the bottom layout layer to the top layout layer.

[0081] In one embodiment, the target layer includes the intermediate layer; the grain stacking direction includes a direction from the intermediate layer to the bottom layer, and a direction from the intermediate layer to the top layer.

[0082] In one implementation, the determining unit 32 may include: A first determining module is used to determine each target pattern in the target layer according to the pattern distribution information of the target layer, so that any two different target patterns are spaced apart from each other in the target layer; A second determining module, configured to determine the target layer as a first iteration layer, and determine the target pattern as a first iteration pattern; A first inspection module is used to respectively inspect whether each of the first iteration patterns in the first iteration layer overlaps with a layout pattern in a second iteration layer; wherein the second iteration layer is the interconnection layout layer adjacent to the first iteration layer in the grain stacking direction; A third determining module is used to determine the layout pattern in the second iteration layer that overlaps with the first iteration pattern as the second iteration pattern, and determine the pattern formed by the overlapping portion as the overlapping pattern; A trigger module is used to use the second iterative layer as the new first iterative layer and the second iterative pattern as the new first iterative pattern, triggering the first inspection module to respectively check whether each of the first iterative patterns in the first iterative layer overlaps with the layout pattern in the second iterative layer, and iterate in a loop until the second iterative pattern is a preset termination layer in the grain stacking direction, wherein the termination layer is at least one of the interconnection layout layers in the three-dimensional interconnection layout.

[0083] In one implementation, the checking unit 33 may include: a fourth determination module, configured to determine a first overlapping pattern corresponding to a preset statistical layer, wherein the first overlapping pattern is the overlapping pattern in the second iterative layer when the second iterative layer is the statistical layer, wherein the statistical layer is at least one of the interconnected layers from the target layer to the termination layer; a fifth determining module, configured to determine first overlapping information of the statistical layer according to the first overlapping pattern, where the first overlapping information includes the number and / or position of the first overlapping pattern; A comparison module, used for comparing the first overlapping information with the second overlapping information preset by the statistical layer to obtain a comparison result; The second inspection module is used to perform a three-dimensional interconnection inspection on the three-dimensional interconnection layout according to the comparison result.

[0084] In one embodiment, the second inspection module is specifically used to: determine that the three-dimensional interconnection of the three-dimensional interconnection layout is qualified when the first overlap information is consistent with the second overlap information; or determine that the three-dimensional interconnection of the three-dimensional interconnection layout has defects and locate the defects when the first overlap information is inconsistent with the second overlap information.

[0085] In one embodiment, the second overlapping information includes the number and / or location of second overlapping patterns expected to exist between the layout pattern in the statistical layer and the layout pattern in the adjacent layout layer of the statistical layer.

[0086] In one embodiment, the determination unit 32 can be specifically used to determine the relative position relationship of each layout pattern between the adjacent layout layers according to the pattern distribution information of each interconnected layout layer, and determine the interconnection path between each interconnected layout layer according to the layout patterns overlapping each other in the relative position relationship; the inspection unit 33 can be specifically used to: perform a three-dimensional interconnection inspection on the three-dimensional interconnected layout according to whether the interconnection path meets the preset rules.

[0087] In one embodiment, the layout inspection device provided by an embodiment of the present invention may also include a display unit for highlighting defective layout parts according to the inspection results after performing a three-dimensional interconnection inspection on the three-dimensional interconnection layout based on whether the relative position relationship conforms to a preset rule.

[0088] In one embodiment, the first pattern layer includes: a pattern layer corresponding to the top metal of the first crystal grain, a pattern layer corresponding to the through silicon via of the first crystal grain, a pattern layer corresponding to the back metal of the first crystal grain, and a pattern layer corresponding to the bonding layer of the first crystal grain; the second pattern layer includes: a pattern layer corresponding to the bonding layer of the second crystal grain, and a pattern layer corresponding to the top metal of the second crystal grain; wherein the bonding layer of the first crystal grain is arranged on the back metal of the first crystal grain, and the bonding layer of the second crystal grain is arranged on the top metal of the second crystal grain, the bonding layer of the first crystal grain and the bonding layer of the second crystal grain correspond to each other, and are used to bond the first crystal grain to the second crystal grain; the top metal of the first crystal grain is electrically connected to the back metal of the first crystal grain through the through silicon via of the first crystal grain.

[0089] In a third aspect, an embodiment of the present invention further provides an electronic device that can effectively improve the accuracy of three-dimensional interconnection inspection of a layout.

[0090] like Fig.12 As shown, the electronic device provided by an embodiment of the present invention may include: a processor 71 and a memory 72, wherein the processor 71 is electrically connected to the memory 72; the memory 72 is used to store executable program codes; the processor 71 runs a program corresponding to the executable program code by reading the executable program code stored in the memory 72, so as to implement any one of the layout inspection methods provided by the aforementioned embodiments.

[0091] The specific execution process of the above steps by the processor 71 and the steps further executed by the processor 71 by running the executable program code can be found in the description of the previous embodiment and will not be repeated here.

[0092] In the fourth aspect, an embodiment of the present invention further provides a computer-readable storage medium, which stores one or more programs, and the one or more programs can be executed by one or more processors to implement any one of the layout inspection methods provided in the aforementioned embodiments, thereby also being able to achieve the corresponding technical effects, which have been described in detail above and will not be repeated here.

[0093] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or device including the elements.

[0094] Each embodiment in this specification is described in a related manner, and the same or similar parts between the embodiments can be referenced to each other, and each embodiment focuses on the differences from other embodiments.

[0095] In particular, for the device embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiment.

[0096] For the convenience of description, the above device is described by dividing the functions into various units / modules. Of course, when implementing the present invention, the functions of each unit / module can be implemented in the same or multiple software and / or hardware.

[0097] Those skilled in the art can understand that all or part of the processes in the above-mentioned embodiments can be implemented by instructing the relevant hardware through a computer program, and the program can be stored in a computer-readable storage medium, and when the program is executed, it can include the processes of the embodiments of the above-mentioned methods. The storage medium can be a disk, an optical disk, a read-only memory (ROM) or a random access memory (RAM), etc.

[0098] The above is only a specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily thought of by a person skilled in the art within the technical scope disclosed by the present invention should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.

Claims

1. A layout inspection method, characterized in that: include: Acquire a three-dimensional interconnection layout to be inspected; the three-dimensional interconnection layout includes an interconnection layout layer, the interconnection layout layer includes a first layout layer corresponding to a structure related to the three-dimensional interconnection between grains in a first grain, and a second layout layer corresponding to a structure related to the three-dimensional interconnection between grains in a second grain; the first grain and the second grain are used to be stacked on each other to form a three-dimensional chip; Determine the relative position relationship of each layout pattern between adjacent layout layers according to the pattern distribution information of each interconnected layout layer; wherein the adjacent layout layers are the interconnected layout layers adjacent to each other in the grain stacking direction in the three-dimensional interconnected layout; According to whether the relative position relationship conforms to a preset rule, a three-dimensional interconnection check is performed on the three-dimensional interconnection layout.

2. The method according to claim 1, characterized in that Determining the relative position relationship of each layout pattern between adjacent layout layers according to the pattern distribution information of each interconnected layout layer includes: According to the pattern distribution information of each interconnected layout layer, starting from the target layer, the relative position relationship of each layout pattern between every two adjacent layout layers is determined in sequence along the grain stacking direction, wherein the target layer is any one or more layers of each interconnected layout layer.

3. The method according to claim 2, characterized in that The target layer includes at least one of the following among the interconnection layout layers of the three-dimensional interconnection layout: a top layout layer, a bottom layout layer, and a middle layout layer.

4. The method according to claim 3, characterized in that The target layer includes the top layout layer and / or the bottom layout layer; when the top layout layer is used as the target layer, the grain stacking direction includes the direction from the top layout layer to the bottom layout layer; when the bottom layer is used as the target layer, the grain stacking direction includes the direction from the bottom layout layer to the top layout layer.

5. The method according to claim 3, characterized in that: The target layer includes the middle layer; the grain stacking direction includes a direction from the middle layer to the bottom layer, and a direction from the middle layer to the top layer.

6. The method according to any one of claims 2 to 5, characterized in that The method of determining the relative position relationship of each layout pattern between every two adjacent layout layers in sequence along the grain stacking direction based on the pattern distribution information of each interconnected layout layer, starting from the target layer, includes: Determine each target pattern in the target layer according to the pattern distribution information of the target layer, so that any two different target patterns are spaced apart from each other in the target layer; Determine the target layer as a first iteration layer, and determine the target pattern as a first iteration pattern; Checking whether each of the first iteration patterns in the first iteration layer overlaps with a layout pattern in a second iteration layer; wherein the second iteration layer is the interconnection layout layer adjacent to the first iteration layer in the grain stacking direction; Determine the layout pattern in the second iteration layer that overlaps with the first iteration pattern as the second iteration pattern, and determine the pattern formed by the overlapping portion as the overlapping pattern; Taking the second iterative layer as the new first iterative layer and the second iterative pattern as the new first iterative pattern, jump to the step of respectively checking whether each of the first iterative patterns in the first iterative layer overlaps with the layout pattern in the second iterative layer, and iterate in a loop until the second iterative pattern is a preset termination layer in the grain stacking direction, wherein the termination layer is at least one of the interconnection layout layers in the three-dimensional interconnection layout.

7. The method according to claim 6, characterized in that The performing three-dimensional interconnection inspection on the three-dimensional interconnection layout according to whether the relative position relationship conforms to a preset rule comprises: Determine a first overlapping pattern corresponding to a preset statistical layer, wherein the first overlapping pattern is the overlapping pattern in the second iterative layer when the second iterative layer is the statistical layer, wherein the statistical layer is at least one of the interconnected layers from the target layer to the termination layer; Determining first overlapping information of the statistical layer according to the first overlapping pattern, where the first overlapping information includes the number and / or position of the first overlapping pattern; Comparing the first overlapping information with the second overlapping information preset in the statistical layer to obtain a comparison result; A three-dimensional interconnection check is performed on the three-dimensional interconnection layout according to the comparison result.

8. The method according to claim 7, characterized in that The performing a three-dimensional interconnection check on the three-dimensional interconnection layout according to the comparison result comprises: When the first overlapping information is consistent with the second overlapping information, determining that the three-dimensional interconnection of the three-dimensional interconnection layout is qualified; or, When the first overlapping information is inconsistent with the second overlapping information, it is determined that there is a defect in the three-dimensional interconnection of the three-dimensional interconnection layout and the defect is located.

9. The method according to claim 7, characterized in that: The second overlapping information includes the number and / or position of second overlapping patterns expected to exist between the layout pattern in the statistical layer and the layout pattern in the adjacent layout layer of the statistical layer.

10. The method according to claim 1, characterized in that Determining the relative position relationship of each layout pattern between adjacent layout layers according to the pattern distribution information of each interconnected layout layer includes: Determine the relative position relationship of each layout pattern between the adjacent layout layers according to the pattern distribution information of each interconnected layout layer, and determine the interconnection path between each interconnected layout layer according to the layout patterns overlapping each other in the relative position relationship; The performing three-dimensional interconnection inspection on the three-dimensional interconnection layout according to whether the relative position relationship conforms to a preset rule comprises: A three-dimensional interconnection check is performed on the three-dimensional interconnection layout according to whether the interconnection path complies with a preset rule.

11. The method according to any one of claims 1 to 5, characterized in that After performing a three-dimensional interconnection check on the three-dimensional interconnection layout according to whether the relative position relationship conforms to a preset rule, the method further comprises: Based on the inspection results, the defective layout areas are highlighted.

12. The method according to any one of claims 1 to 5, characterized in that The first pattern layer includes: a pattern layer corresponding to the top metal of the first crystal grain, a pattern layer corresponding to the through silicon via of the first crystal grain, a pattern layer corresponding to the back metal of the first crystal grain, and a pattern layer corresponding to the bonding layer of the first crystal grain; The second layer comprises: a layer corresponding to the bonding layer of the second crystal grain and a layer corresponding to the top metal layer of the second crystal grain; The bonding layer of the first crystal grain is arranged on the back metal of the first crystal grain, and the bonding layer of the second crystal grain is arranged on the top metal of the second crystal grain. The bonding layer of the first crystal grain and the bonding layer of the second crystal grain correspond to each other and are used to bond the first crystal grain to the second crystal grain. The top metal of the first crystal grain is electrically connected to the back metal of the first crystal grain through a through silicon via of the first crystal grain.

13. A layout inspection device, characterized in that: include: an acquisition unit, configured to acquire a three-dimensional interconnection layout to be inspected; the three-dimensional interconnection layout includes an interconnection layout layer, the interconnection layout layer includes a first layout layer corresponding to a structure related to the three-dimensional interconnection between the grains in the first grain, and a second layout layer corresponding to a structure related to the three-dimensional interconnection between the grains in the second grain; the first grain and the second grain are used to be stacked on each other to form a three-dimensional chip; A determination unit, configured to determine the relative position relationship of each layout pattern between adjacent layout layers according to the pattern distribution information of each interconnected layout layer; wherein the adjacent layout layers are the interconnected layout layers adjacent to each other in the grain stacking direction in the three-dimensional interconnected layout; The checking unit is used to perform a three-dimensional interconnection check on the three-dimensional interconnection layout according to whether the relative position relationship conforms to a preset rule.

14. The device according to claim 13, characterized in that The determination unit is specifically used to determine the relative position relationship of each layout pattern between every two adjacent layout layers along the grain stacking direction based on the pattern distribution information of each interconnected layout layer, starting from the target layer, wherein the target layer is any one or more layers in each interconnected layout layer.

15. The device according to claim 14, characterized in that The target layer includes at least one of the following among the interconnection layout layers of the three-dimensional interconnection layout: a top layout layer, a bottom layout layer, and a middle layout layer.

16. The device according to claim 15, characterized in that The target layer includes the top layout layer and / or the bottom layout layer; when the top layout layer is used as the target layer, the grain stacking direction includes the direction from the top layout layer to the bottom layout layer; when the bottom layer is used as the target layer, the grain stacking direction includes the direction from the bottom layout layer to the top layout layer.

17. The device according to claim 15, characterized in that The target layer includes the middle layer; the grain stacking direction includes a direction from the middle layer to the bottom layer, and a direction from the middle layer to the top layer.

18. The device according to any one of claims 14 to 17, characterized in that The determining unit comprises: A first determining module is used to determine each target pattern in the target layer according to the pattern distribution information of the target layer, so that any two different target patterns are spaced apart from each other in the target layer; A second determining module, configured to determine the target layer as a first iteration layer, and determine the target pattern as a first iteration pattern; A first inspection module is used to respectively inspect whether each of the first iteration patterns in the first iteration layer overlaps with a layout pattern in a second iteration layer; wherein the second iteration layer is the interconnection layout layer adjacent to the first iteration layer in the grain stacking direction; A third determining module is used to determine the layout pattern in the second iteration layer that overlaps with the first iteration pattern as the second iteration pattern, and determine the pattern formed by the overlapping portion as the overlapping pattern; A trigger module is used to use the second iterative layer as the new first iterative layer and the second iterative pattern as the new first iterative pattern, triggering the first inspection module to respectively check whether each of the first iterative patterns in the first iterative layer overlaps with the layout pattern in the second iterative layer, and iterate in a loop until the second iterative pattern is a preset termination layer in the grain stacking direction, wherein the termination layer is at least one of the interconnection layout layers in the three-dimensional interconnection layout.

19. The device according to claim 18, characterized in that The inspection unit comprises: a fourth determination module, configured to determine a first overlapping pattern corresponding to a preset statistical layer, wherein the first overlapping pattern is the overlapping pattern in the second iterative layer when the second iterative layer is the statistical layer, wherein the statistical layer is at least one of the interconnected layers from the target layer to the termination layer; a fifth determining module, configured to determine first overlapping information of the statistical layer according to the first overlapping pattern, where the first overlapping information includes the number and / or position of the first overlapping pattern; A comparison module, used for comparing the first overlapping information with the second overlapping information preset by the statistical layer to obtain a comparison result; The second inspection module is used to perform a three-dimensional interconnection inspection on the three-dimensional interconnection layout according to the comparison result.

20. The device according to claim 19, characterized in that The second inspection module is specifically used to: When the first overlapping information is consistent with the second overlapping information, determining that the three-dimensional interconnection of the three-dimensional interconnection layout is qualified; or, When the first overlapping information is inconsistent with the second overlapping information, it is determined that there is a defect in the three-dimensional interconnection of the three-dimensional interconnection layout and the defect is located.

21. The device according to claim 19, characterized in that The second overlapping information includes the number and / or position of second overlapping patterns expected to exist between the layout pattern in the statistical layer and the layout pattern in the adjacent layout layer of the statistical layer.

22. The device according to claim 13, characterized in that The determining unit is specifically used to determine the relative position relationship of each layout pattern between the adjacent layout layers according to the pattern distribution information of each interconnected layout layer, and determine the interconnection path between each interconnected layout layer according to the layout patterns overlapping each other in the relative position relationship; The inspection unit is specifically used to perform a three-dimensional interconnection inspection on the three-dimensional interconnection layout according to whether the interconnection path complies with a preset rule.

23. The device according to any one of claims 13 to 17, characterized in that It also includes a display unit for highlighting defective layout parts according to the inspection result after performing a three-dimensional interconnection inspection on the three-dimensional interconnection layout according to whether the relative position relationship conforms to a preset rule.

24. The device according to any one of claims 13 to 17, characterized in that The first pattern layer includes: a pattern layer corresponding to the top metal of the first crystal grain, a pattern layer corresponding to the through silicon via of the first crystal grain, a pattern layer corresponding to the back metal of the first crystal grain, and a pattern layer corresponding to the bonding layer of the first crystal grain; The second layer comprises: a layer corresponding to the bonding layer of the second crystal grain and a layer corresponding to the top metal layer of the second crystal grain; The bonding layer of the first crystal grain is arranged on the back metal of the first crystal grain, and the bonding layer of the second crystal grain is arranged on the top metal of the second crystal grain. The bonding layer of the first crystal grain and the bonding layer of the second crystal grain correspond to each other and are used to bond the first crystal grain to the second crystal grain. The top metal of the first crystal grain is electrically connected to the back metal of the first crystal grain through a through silicon via of the first crystal grain.

25. An electronic device, characterized in that: The electronic device includes: a processor and a memory, wherein the processor is electrically connected to the memory; the memory is used to store executable program code; the processor runs a program corresponding to the executable program code by reading the executable program code stored in the memory, so as to implement the layout inspection method described in any one of claims 1 to 12.

26. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores one or more programs, and the one or more programs can be executed by one or more processors to implement the layout inspection method according to any one of claims 1 to 12.

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