Memory device, memory system, and operating method of memory device

Abstract

A memory device includes a memory cell array including memory cell rows, a first random number generator that generates an n-bit first pseudo-random bit sequence signal based on a first seed and a first degree, a first memory cell row selection circuit and a second memory cell row selection circuit, and a refresh control circuit. The first memory cell row selection circuit randomly selects a first memory cell row at a first cycle, and stores a row address of the selected first memory cell row in a first queue. A second memory cell row selection circuit randomly selects a second memory cell row at a second cycle and stores a row address of the selected second memory cell row in a second queue. The refresh control circuit performs a refresh operation on a memory cell row physically adjacent to a memory cell row corresponding to each row address stored in the first queue and the second queue.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to Korean Patent Application No. 10-2023-0128351, filed on September 25, 2023, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] Embodiments of the present disclosure relate to a memory device, a memory system, and a method of operating a memory device. Background Art

[0004] As the integration degree of the memory device increases, the spacing between the multiple word lines included in the memory device decreases. As the spacing between the word lines decreases, the coupling effect between adjacent word lines increases. Whenever data is input to and output from the memory cell, the word line switches between an active state and an inactive state. Such a phenomenon may occur that as the coupling effect between adjacent word lines increases, the data of the memory cell connected to the word line adjacent to the word line that is frequently activated is damaged. This phenomenon is called row hammering, in which the data of the memory cell may become damaged due to word line interference before the memory cell is refreshed. Summary of the invention

[0005] Aspects of the present disclosure provide a memory device in which data reliability is improved against a row hammering phenomenon.

[0006] Aspects of the present disclosure also provide a memory system in which data reliability is improved against a row hammering phenomenon.

[0007] Aspects of the present disclosure also provide a method of operating a memory device in which data reliability is improved against a row hammering phenomenon.

[0008] According to one aspect of the present disclosure, a memory device is provided, comprising: a memory cell array including a plurality of memory cell rows; a first random number generator configured to generate an n-bit first pseudo-random bit sequence signal based on a first seed and a first degree; a first memory cell row selection circuit configured to randomly select a first memory cell row from a plurality of memory cell rows in a first cycle in response to specific m bits among the received n-bit first pseudo-random bit sequence signals matching each other, and store a row address of the selected first memory cell row in a first queue; a second memory cell row selection circuit configured to randomly select a second memory cell row from a plurality of memory cell rows in a second cycle different from the first cycle in response to specific k bits among the received n-bit first pseudo-random bit sequence signals matching each other, and store a row address of the selected second memory cell row in a second queue different from the first queue; and a refresh control circuit configured to perform a refresh operation on a memory cell row physically adjacent to a memory cell row corresponding to each row address stored in the first queue and the second queue, wherein each of n, m, and k is an integer of 2 or greater, and n, m, and k are different from each other.

[0009] According to one aspect of the present disclosure, there is provided a memory system, including: a memory controller configured to generate a row hammer refresh command based on a command received from a host; a memory cell array including a plurality of memory cell rows; a row hammer control circuit configured to receive the row hammer refresh command and, in response to the received row hammer refresh command, output a row hammer address corresponding to at least one memory cell row subjected to row hammering during a row hammer monitoring time interval among the plurality of memory cell rows; and a refresh control circuit configured to perform a refresh operation on a memory cell row physically adjacent to the memory cell row corresponding to the row hammer address based on the received row hammer address. The row hammering control circuit includes: a first random number generator, configured to generate an n-bit first pseudo-random bit sequence signal based on a first seed and a first degree; a first memory cell row selection circuit, configured to randomly select a first memory cell row from a plurality of memory cell rows in a first cycle in response to specific m bits among the received n-bit first pseudo-random bit sequence signals matching each other, and store the row address of the selected first memory cell row in a first queue; a second random number generator, configured to generate a k-bit second pseudo-random bit sequence signal based on a second seed and a second degree; and a second memory cell row selection circuit, configured to randomly select a second memory cell row from a plurality of memory cell rows in a second cycle different from the first cycle in response to specific j bits among the received k-bit second pseudo-random bit sequence signals matching each other, and store the row address of the selected second memory cell row in a second queue different from the first queue. The row hammer control circuit provides the row addresses stored in the first queue and the second queue as row hammer addresses to the refresh control circuit, the first seed and the second seed are different from each other, or the first degree and the second degree are different from each other, and each of n, m, k and j is an integer of 2 or greater.

[0010] According to one aspect of the present disclosure, a method for operating a memory device is provided, the memory device comprising a memory cell array including a plurality of memory cell rows, a first random number generator configured to generate an n-bit first pseudo-random bit sequence signal, a first memory cell row selection circuit and a second memory cell row selection circuit configured to randomly select at least one memory cell row from the plurality of memory cell rows based on the first pseudo-random bit sequence signal, and a refresh control circuit configured to perform a refresh operation on memory cell rows that are physically adjacent to the memory cell rows selected by the first memory cell row selection circuit and the second memory cell row selection circuit. The method includes: generating an n-bit first pseudo-random bit sequence signal based on a first seed and a first degree by a first random number generator; randomly selecting a memory cell row from a plurality of memory cell rows in a first cycle by a first memory cell row selection circuit in response to specific m bits of the received n-bit first pseudo-random bit sequence signal matching each other; storing a row address of the selected memory cell row in a first queue by the first memory cell row selection circuit; randomly selecting a memory cell row from a plurality of memory cell rows in a second cycle different from the first cycle by a second memory cell row selection circuit in response to specific k bits of the received n-bit first pseudo-random bit sequence signal matching each other; storing the row address of the selected memory cell row in a second queue different from the first queue by the second memory cell row selection circuit; and performing a refresh operation on a memory cell row physically adjacent to a memory cell row corresponding to each row address stored in the first queue and the second queue by a refresh control circuit, wherein each of n, m and k is an integer of 2 or greater, and n, m and k are different from each other. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] The above and other aspects and features of the present disclosure will become more apparent by describing in detail embodiments of the present disclosure with reference to the attached drawings.

[0012] Figure 1 is an example diagram showing a configuration of a memory system according to some embodiments.

[0013] Figure 2 is an example diagram illustrating a configuration of a memory device according to some embodiments.

[0014] Figure 3 is an example diagram showing a configuration of a row hammer control circuit according to some embodiments.

[0015] Figure 4 Is used to describe Figure 3 An example diagram of a random number generator.

[0016] Figures 5 to 7 Is used to describe Figure 3An example diagram of a memory cell row selection circuit.

[0017] Figure 8 Is used to describe Figure 3 An example diagram of the effects of a line hammer control circuit.

[0018] Fig. 9 is a diagram showing some embodiments of the present invention. Figure 3 An example diagram of a configuration of a row hammer control circuit.

[0019] Fig.10 is an exemplary diagram showing a configuration of a flag signal generating circuit according to some embodiments.

[0020] Fig.11 is an exemplary diagram showing a configuration of a flag signal generating circuit according to some embodiments.

[0021] Fig.12 is an exemplary diagram showing a configuration of a flag signal generating circuit according to some embodiments.

[0022] Figures 13 to 15 is an example diagram for describing a row hammer control circuit according to some embodiments.

[0023] Fig.16 is an exemplary diagram illustrating a structure of a stacked memory device according to some embodiments.

[0024] Fig.17 It is shown Fig.16 An example diagram of a second semiconductor layer.

[0025] Fig.18 is an example diagram for describing a memory module including a memory device according to some embodiments.

[0026] Fig.19 is an example diagram illustrating an electronic system including a memory device according to some embodiments. DETAILED DESCRIPTION

[0027] Embodiments of the present disclosure will be described more fully below with reference to the accompanying drawings.In all drawings, the same reference numerals may refer to the same elements.

[0028] It will be understood that the terms "first", "second", "third", etc. are used herein to distinguish one element from another element, and the elements are not limited by these terms. Therefore, a "first" element in one embodiment may be described as a "second" element in another embodiment.

[0029] It should be understood that descriptions of features or aspects within each embodiment should typically be considered as available for other similar features or aspects in other embodiments, unless the context clearly dictates otherwise.

[0030] As used herein, the singular forms “a”, “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise.

[0031] Hereinafter, a memory device, a memory system, and a method of operating the memory device according to some embodiments will be described with reference to the accompanying drawings.

[0032] Figure 1 is an example diagram showing a configuration of a memory system according to some embodiments.

[0033] refer to Figure 1 , the memory system 1000 may include a memory device 100 and a memory controller 200. The memory controller 200 may send and receive data to and from a host device 300, and may send a command CMD and an address ADDR to the memory device 100. The memory controller 200 may include a host interface 240, a command generator 210, an address generator 220, and a device interface 230.

[0034] The host interface 240 may receive a command CMD and an address ADDR from the host device 300 , and the command generator 210 may generate an access command and a row hammer refresh command by decoding the command CMD received from the host device 300 , and provide the access command and the row hammer refresh command to the memory device 100 through the device interface 230 .

[0035] The access command may be a signal instructing the memory device 100 to read or write data by accessing a memory cell row corresponding to the address ADDR of the memory cell array 110. The row hammering refresh command may be a signal instructing to perform an additional refresh operation on a memory cell row physically adjacent to a memory cell row intensively accessed in a short period of time.

[0036] In the following description, the terms "row" of the memory cell array 110 and "memory cell row" of the memory cell array 110 may be used interchangeably. In addition, regarding a row hammering refresh command, a memory cell row that is intensively accessed in a short period of time is referred to as a "target row."

[0037] In the following description, performing a refresh operation on a memory cell row physically adjacent to a memory cell row subjected to a row hammer attack will be referred to as row hammer care.

[0038] The address generator 220 of the memory controller 200 may generate a row address and a column address to be accessed in the memory cell array 110 by decoding the address ADDR received from the host interface 240. In addition, when the memory cell array 110 includes a plurality of banks, the address generator 220 may generate an address of a bank to be accessed.

[0039] In addition, the memory controller 200 may control memory operations such as writing and reading by providing various signals to the memory device 100 via the device interface 230. For example, the memory controller 200 may provide a precharge command to the memory device 100. The precharge command may be a command for switching the state of the memory cell array 110 from an active state to a standby state after writing or reading is completed.

[0040] According to some embodiments, when the memory controller 200 provides an access command to the memory device 100, the address ADDR of the row to be accessed may be sent to the memory device 100 together with the access command. When the memory controller 200 provides a row hammer refresh command to the memory device 100, the address of the target row to be accessed collectively may be sent to the memory device 100 together with the row hammer refresh command. When the memory device 100 receives the row hammer refresh command and the address of the target row, an additional refresh operation may be performed on a word line physically adjacent to a word line corresponding to the target row (or a memory cell row physically adjacent to a memory cell row corresponding to the target row).

[0041] The memory device 100 is a memory device based on semiconductor elements, and may include a memory cell array 110, an address buffer 120, a control logic circuit 130, a row hammering control circuit 140, and a refresh control circuit 150. As an example, the memory device 100 may be provided as a random access memory (RAM) device, such as a dynamic random access memory (DRAM), a synchronous DRAM (SDRAM), a static RAM (SRAM), a double data rate SDRAM (DDR SDRAM), a DDR2 SDRAM, a DDR3 SDRAM, a phase-change RAM (PRAM), a magnetic RAM (MRAM), and a resistive RAM (RRAM).

[0042] In addition, any memory device 100 utilizing a refresh operation may be used as the memory device 100. For example, when the resistive memory device 100 performs a refresh operation as a nonvolatile memory, the memory device 100 may be a nonvolatile memory device 100. The memory device 100 may receive or output data through a data line or perform a refresh operation in response to an address ADDR and a command CMD received from the memory controller 200.

[0043] The memory cell array 110 includes a plurality of memory cells, and the plurality of memory cells may be connected to word lines and bit lines. The control logic circuit 130 may write data to or read data from the memory cell array 110 based on a command CMD and an address ADDR received from the memory controller 200, or may provide a control signal for refreshing memory cells included in the memory cell array 110 to a row decoder and a column decoder. In this manner, the control logic circuit 130 may perform an overall operation for processing data of the memory cell array 110.

[0044] The memory device 100 may perform a normal refresh operation on at least some memory cells of the memory cell array 110 in response to a normal refresh command from the memory controller 200. At this time, when the memory device 100 performs the normal refresh operation, memory cell rows of the memory cell array 110 may be sequentially refreshed.

[0045] In addition, the memory device 100 may perform a refresh operation (e.g., row hammering maintenance) on at least some memory cells of the memory cell array 110 in response to a row hammering refresh command from the memory controller 200. When the memory device 100 performs a refresh operation in response to the row hammering refresh command, the refresh operation may be performed on word lines adjacent to the word line corresponding to the target row.

[0046] Figure 2 is an example diagram illustrating a configuration of a memory device according to some embodiments.

[0047] refer to Figure 2 , the memory device 100 may include a memory cell array 110, a row decoder 160A, a column decoder 160B, an input / output gating circuit 170, a control logic circuit 130, an address buffer 120, a memory bank control logic circuit 190, a refresh control circuit 150, a data input buffer 180A, and a data output buffer 180B. In some embodiments, the memory device 100 may also include a clock buffer, a mode register set (MRS), a voltage generation circuit, etc.

[0048] The address buffer 120 can be obtained from the memory controller 200 (such as Figure 1 The address buffer 120 receives the address ADDR including the bank address BANK_ADDR, the row address ROW_ADDR and the column address COL_ADDR. The address buffer 120 may provide the received bank address BANK_ADDR to the bank control logic circuit 190, provide the received row address ROW_ADDR to the row decoder 160A, and provide the received column address COL_ADDR to the column decoder 160B.

[0049] The memory cell array 110 may include a plurality of memory cells provided in a matrix form arranged in rows and columns. The memory cell array 110 may include a plurality of word lines WL and a plurality of bit lines BL connected to the memory cells. The plurality of word lines WL may be connected to the rows of the memory cells, and the plurality of bit lines BL may be connected to the columns of the memory cells. The data of the memory cells connected to the activated word lines WL may be sensed and amplified by a sense amplifier connected to the bit lines BL.

[0050] The memory cell array 110 may include first to fourth memory banks BANK1 to BANK4. The memory bank control logic circuit 190 may generate a memory bank control signal in response to a memory bank address BANK_ADDR. The row decoder 160A may be one of a plurality of row decoders 160A, and the column decoder 160B may be one of a plurality of column decoders 160B. In response to the generated memory bank control signal, the row decoder 160A and the column decoder 160B of a memory bank corresponding to the memory bank address among the first to fourth memory banks BANK1 to BANK4 may be activated. Although the memory device 100 is Figure 2 1 and 2. In some embodiments, the memory device 100 is shown as including four memory banks, but the embodiment is not limited thereto. For example, in some embodiments, the memory device 100 may include any number of memory banks.

[0051] A plurality of row decoders 160A and a plurality of column decoders 160B may be disposed to correspond to each of the first to fourth memory banks BANK1 to BANK4, and the row decoder 160A and the column decoder 160B connected to the memory bank corresponding to the memory bank address BANK_ADDR may be activated. The row decoder 160A may decode the row address ROW_ADDR received from the address buffer 120, select a word line WL corresponding to the row address ROW_ADDR from among a plurality of word lines WL, and may be connected to a word line driver that activates the selected word line WL.

[0052] The column decoder 160B may select a predetermined bit line BL from among a plurality of bit lines BL of the memory cell array 110. The column decoder 160B may generate a column selection signal by decoding a burst address gradually increasing by +1 based on the column address COL_ADDR in a burst mode, and connect the bit line BL selected by the generated column selection signal to the input / output gating circuit 170. The burst address refers to an address of a column position accessible in relation to a burst length BL for a read and / or write command.

[0053] The input / output gating circuit 170 may include a read data latch storing read data of the bit line BL selected by the column selection signal, and a write driver writing write data to the memory cell array 110. The read data stored in the read data latch of the input / output gating circuit 170 may be provided to the data (DQ) bus through the data output buffer 180B. The write data may be written to the memory cell array 110 through the data input buffer 180A connected to the data (DQ) bus and through the write driver of the input / output gating circuit 170.

[0054] The control logic circuit 130 may receive the clock signal CLK and the command CMD, and generate a control signal that controls the operation timing and / or memory operation of the memory device 100. The control logic circuit 130 may provide control signals to the circuits of the memory device 100 to operate according to the settings in the operation and control parameters stored by the MRS. The control logic circuit 130 may use the control signals to read data from the memory cell array 110 and write data to the memory cell array 110. Although the control logic circuit 130 and the address buffer 120 are in Figure 1 and Figure 2 1 and 120 are shown as separate components, but the embodiments are not limited thereto. For example, in some embodiments, the control logic circuit 130 and the address buffer 120 may be implemented as a single component. In addition, although the command CMD and the address ADDR are in Figure 2 The address is shown as being provided as a separate signal as present in the Low Power Double Data Rate (LPDDR) standard, but in some embodiments, the address can be considered to be included in the command.

[0055] The control logic circuit 130 may be configured to detect one or more row hammer addresses RH_ADDR that are collectively accessed during a row hammer monitoring time interval, and to perform a target refresh on a memory cell row that is adjacent to a memory cell row that is physically adjacent to a memory cell row corresponding to the detected row hammer address RH_ADDR. The control logic circuit 130 includes a row hammer control circuit 140 that detects a target row that is subjected to a row hammer attack during the row hammer monitoring time interval, and provides a row address of the target row as the row hammer address RH_ADDR to the refresh control circuit 150. Reference will be made to Figure 3 The row hammer control circuit 140 is described.

[0056] The control logic circuit 130 may control the refresh control circuit 150 to perform a normal refresh operation by increasing the refresh counter value by +1 in response to the refresh command CMD. The control logic circuit 130 may also control the refresh control circuit 150 to perform a target row refresh operation (e.g., row hammer maintenance) based on the row hammer address RH_ADDR. The refresh control circuit 150 may generate a refresh address REF_ADDR corresponding to a memory cell row on which a normal refresh operation and / or a target row refresh operation is performed. When the refresh control circuit 150 performs a target row refresh operation, the refresh address REF_ADDR output from the refresh control circuit 150 may represent a row address of a memory cell row physically adjacent to a target row subjected to a row hammer attack.

[0057] Figure 3 is an example diagram showing a configuration of a row hammer control circuit according to some embodiments.

[0058] refer to Figure 3 The row hammer control circuit 140 may include a random number generator 141, a memory cell row selection circuit 142A, and a memory cell row selection circuit 142B. The random number generator 141 may operate when an enable signal RNG1_EN is applied. The random number generator 141 may generate a random number using an algorithm for random number generation, and may have hardware logic for random number generation. The random number generator 141 may also be referred to as a random number generator circuit.

[0059] In some embodiments, the random number generator 141 may be implemented as a linear feedback shift register (where n is an integer of 2 or greater) that generates an n-bit pseudo random bit sequence signal 1 (PRBS1) based on a first seed and a first degree. Figure 4 Describe the linear feedback shift register.

[0060] The memory cell row selection circuit 142A may operate when the enable signal RPC1_EN is applied. The memory cell row selection circuit 142A may receive the n-bit pseudo-random bit sequence signal PRBS1 from the random number generator 141. When the enable signal RPC1_EN is applied to the memory cell row selection circuit 142A, the memory cell row selection circuit 142A may select the n-bit pseudo-random bit sequence signal PRBS1 in the memory cell array 110 (e.g., Figure 2 142A). At this time, the memory cell row selected by the memory cell row selection circuit 142A may be a target row that is intensively accessed during the row hammer monitoring time interval of the control logic circuit 130, that is, a memory cell row that has been subjected to a row hammer attack. In addition, the memory cell row selection circuit 142A may select the memory cell rows one by one in a cycle T1.

[0061] When the memory cell row selection circuit 142A selects a memory cell row in cycle T1, the memory cell row selection circuit 142A may output a logic high selection signal Pick1. Based on the logic high selection signal Pick1, the memory cell row selection circuit 142A may store the row address of the selected memory cell row in the queue Q1. At this time, the queue Q1 may be exclusively assigned to the memory cell row selection circuit 142A. That is, the memory cell row selection circuit 142A may store the row address of the selected memory cell row only in the queue Q1. The row address stored in the queue Q1 may be used as Figure 2 The row hammer address RH_ADDR is provided to the refresh control circuit 150 (such as Figure 2 Thereafter, the refresh control circuit 150 may generate a refresh address REF_ADDR corresponding to a memory cell row on which a target row refresh operation (eg, a row hammer maintenance operation) is to be performed based on the received row hammer address RH_ADDR.

[0062] The memory cell row selection circuit 142B can operate when the enable signal RPC2_EN is applied. Since the memory cell row selection circuit 142A and the memory cell row selection circuit 142B are operated by different enable signals from each other, one of the memory cell row selection circuit 142A and the memory cell row selection circuit 142B is turned on and operated, while the other can be turned off and not operated.

[0063] Like the memory cell row selection circuit 142A, the memory cell row selection circuit 142B can receive the n-bit pseudo-random bit sequence signal PRBS1 from the random number generator 141, and can randomly select a memory cell row from a plurality of memory cell rows of the memory cell array 110 on this basis. At this time, the memory cell row selected by the memory cell row selection circuit 142B can be a target row that is centrally accessed during the row hammer monitoring time interval of the control logic circuit 130, that is, a memory cell row that is subjected to a row hammer attack. At this time, the memory cell row selection circuit 142B can select the memory cell rows one by one in a cycle T2.

[0064] At this time, the period T1 during which the memory cell row selection circuit 142A selects a memory cell row and the period T2 during which the memory cell row selection circuit 142B selects a memory cell row can both be average periods. Figure 5 Describe the average period over which a row of memory cells is selected by the memory cell row selection circuit.

[0065] In some embodiments, the period T1 at which the memory cell row selection circuit 142A selects a memory cell row may be different from the period T2 at which the memory cell row selection circuit 142B selects a memory cell row. That is, although both the memory cell row selection circuit 142A and the memory cell row selection circuit 142B receive the same n-bit pseudo-random bit sequence signal PRBS1 from the random number generator 141, the period for selecting a memory cell row may be different from each other depending on the operation of each of the memory cell row selection circuits 142A and 142B. Figure 5 and Figure 6 The operation of each of the memory cell row selection circuits 142A and 142B is described.

[0066] When the memory cell row selection circuit 142B selects a memory cell row with a cycle T2, the memory cell row selection circuit 142B may output a logic high selection signal Pick2. Based on the logic high selection signal Pick2, the memory cell row selection circuit 142B may store the row address of the selected memory cell row in the queue Q2. At this time, the queue Q2 may be exclusively assigned to the memory cell row selection circuit 142B. That is, the memory cell row selection circuit 142B may store the row address of the selected memory cell row only in the queue Q2. The row address stored in the queue Q2 may be used as Figure 2 The row hammer address RH_ADDR is provided to the refresh control circuit 150 (such as Figure 2Thereafter, the refresh control circuit 150 may generate a refresh address REF_ADDR corresponding to a memory cell row on which a target row refresh operation (eg, a row hammer maintenance operation) is to be performed based on the received row hammer address RH_ADDR.

[0067] On the other hand, when the refresh control circuit 150 performs a target row refresh operation, the order between the row addresses stored in the queue Q1 and the row addresses stored in the queue Q2 may be defined. Figures 10 to 12 The order in which the refresh control circuit 150 performs the target row refresh operation on the row address stored in the queue Q1 and the row address stored in the queue Q2 is described.

[0068] Figure 4 Is used to describe Figure 3 An example diagram of a random number generator.

[0069] refer to Figure 4 , Figure 3 The random number generator 141 may be implemented as a linear feedback shift register 400. The linear feedback shift register 400 may generate and output a linear random number sequence based on a primitive polynomial. The linear feedback shift register 400 may include a shift register unit 401, a feedback constant unit 402, and a linear feedback function unit 403.

[0070] The shift register unit 401 includes n shift registers (S 0 , S 1 ,……,S n-1 ). n shift registers (S 0 , S 1 ,……,S n-1 ) can receive the output P of the linear feedback function unit 403 and convert the shift register (S 0 , S 1 ,……,S n-1 ) of each level (s 0 、s 1 ,……,s n-1 ) is output to each stage of the feedback constant unit 402.

[0071] The feedback constant unit 402 can take mode values ​​0 and 1 as coefficients of the primitive polynomial and has a value C indicating a connection state with the shift register unit 401. i (C 0 =1, i=1, 2...). The feedback constant unit 402 can receive the output (s 0 、s 1 ,……,s n-1 ), and compare them with their own constant value Ci (C 0 =1, i=1, 2, ...) are output to the linear feedback function unit 403. The linear feedback function unit 403 and the feedback constant unit 402 receive the output (s 0 、s 1 ,……,s n-1 ), generate output P through equation 1, and output them to shift register unit 401.

[0072] [Equation 1]

[0073] P=s 0 +C 1 s 1 +…+C n-1 s n-1

[0074] The operation process of the linear feedback shift register 400 is as follows. The linear feedback function unit 403 calculates and outputs the output P. Thereafter, the shift register unit 401 outputs all bits (s 0 、s 1 ,……,s n-1 ), and receives the output P of the linear feedback function unit 403 and shifts it. 0 , S 1 ,……,S n-1 ) output (s 0 、s 1 ,……,s n-1 ) is output to the feedback constant unit 402. All bits (s 0 、s 1 ,……,s n-1 ) (output whenever the operation process is repeated) can be output as a random value. The output bit of the shift register unit 401 can be output as a pseudo-random bit sequence signal PRBS. The seed corresponding to the initial bit value of the linear feedback shift register 400 and / or the degree corresponding to the number of bits included in one cycle of the output signal of the linear feedback shift register 400 can vary according to the embodiment.

[0075] Figures 5 to 7 Is used to describe Figure 3 An example diagram of a memory cell row selection circuit.

[0076] Figure 3 The memory cell row selection circuits 142A and 142B may be implemented as Figures 5 to 7 In the following description, although the memory cell row selection circuit 142A will be described as being implemented as Figure 5 The memory cell row selection circuit 500 and the memory cell row selection circuit 142B are implemented as Figure 6 This is an example of a memory cell row selection circuit 500A, but the embodiment is not limited thereto.

[0077] In the following description, we will give Figure 3 The random number generator 141 outputs an example of a 10-bit pseudo-random bit sequence signal PRBS[9:0]. However, the embodiment is not limited thereto. For example, in some embodiments, the number of bits of the pseudo-random bit sequence signal generated by the random number generator 141 may vary depending on the degree of the random number generator 141.

[0078] First reference Figure 5 , the memory cell row selection circuit 500 may include a logic gate G1 and an inverter INV1. The memory cell row selection circuit 500 may receive a 10-bit pseudo-random bit sequence signal PRBS[9:0] output from the random number generator 141. The logic gate G1 of the memory cell row selection circuit 500 may receive an input of a specific bit among the 10-bit pseudo-random bit sequence signal PRBS[9:0] output from the random number generator 141. For example, Figure 5 As shown, the logic gate G1 can receive inputs of PRBS[0], PRBS[1], PRBS[2], PRBS[3], and PRBS[4] among the 10-bit pseudo-random bit sequence signal PRBS[9:0]. The logic gate G1 can perform a NAND calculation on the input signal and output the result as a signal S1. For example, when the signal PRBS[4:0] input to the logic gate G1 is "11111", a logic low signal S1 can be output.

[0079] The logic low signal S1 is input to the inverter INV1, and a logic high selection signal Pick1 may be output. The selection signal Pick1 output from the inverter INV1 may correspond to the selection signal from Figure 3 Whenever the memory cell row selection circuit 500 outputs the logic high selection signal Pick1, the memory cell row selection circuit 500 can select a memory cell from the memory cell array 110 (such as Figure 1 A memory cell row is selected from a plurality of memory cell rows (as shown).

[0080] In this way, the period T1 during which the memory cell row selection circuit 500 outputs the logic high selection signal Pick1, that is, the period T1 during which the memory cell row selection circuit 500 selects one memory cell row from among a plurality of memory cell rows in the memory cell array 110, can be determined by the following Equation 2.

[0081] [Equation 2]

[0082] T=2 m TRC (m = number of specific bits that match each other, TRC = minimum time interval between actions)

[0083] According to the above equation 2, the memory cell row selection circuit 500 can select a memory cell row in 32 TRC cycles. That is, the memory cell row selection circuit 500 can select a memory cell row every 32 actions on average. Here, 1 action can represent the number of actions in the control logic circuit 130 (e.g. Figure 1 That is, when there are an average of 32 row hammer attacks during the row hammer monitoring time interval, the memory cell row selection circuit 500 can select a target row.

[0084] The period T1 during which the memory cell row selection circuit 500 selects a target row is determined based on the pseudo-random bit sequence signal PRBS1 output from the random number generator 141, and thus may correspond to an average period. For example, among the 10-bit pseudo-random bit sequence signals PRBS[9:0] input to the memory cell row selection circuit 500, the situation in which PRBS[4:0] are all matched to "11111" may change at each row hammer monitoring time interval. For example, among the 10-bit pseudo-random bit sequence signals PRBS[9:0] input to the memory cell row selection circuit 500, the situation in which PRBS[4:0] are all matched to "11111" may be once every 28 actions. In other examples, the situation in which PRBS[4:0] are all matched to "11111" may be once every 30 actions, once every 32 actions, once every 34 actions, or once every 35 actions. The average number of row hammer attacks that occur when the memory cell row selection circuit 500 selects a memory cell row for each row hammer monitoring time interval may correspond to the period T1 of the memory cell row selection circuit 500 .

[0085] In this manner, the period T1 during which the memory cell row selection circuit 500 selects one memory cell row from among the plurality of memory cell rows in the memory cell array 110 is based on the period T2 of the memory cell row selected from the plurality of memory cell rows implemented as the linear feedback shift register 400 (eg, Figure 4 The memory cell row selection circuit 500 can randomly select a target row based on the pseudo-random bit sequence signal PRBS1 output by the random number generator 141 (shown).

[0086] Next, refer to Figure 6, the memory cell row selection circuit 500A may include a logic gate G2 and an inverter INV2. Like the memory cell row selection circuit 500, the memory cell row selection circuit 500A may receive a random number generator 141 (eg, Figure 3 The logic gate G2 of the memory cell row selection circuit 500A may receive input of a specific bit among the 10-bit pseudo-random bit sequence signal PRBS[9:0] outputted from the random number generator 141.

[0087] The number of bits input to the logic gate G2 of the memory cell row selection circuit 500A may be different from the number of bits input to the logic gate G1 of the memory cell row selection circuit 500. For example, Figure 5 As shown, the logic gate G1 of the memory cell row selection circuit 500 can receive 5 bits, but the logic gate G2 of the memory cell row selection circuit 500A can receive 6 bits.

[0088] For example, Figure 6 As shown, the logic gate G2 can receive the input of PRBS[1], PRBS[2], PRBS[5], PRBS[6], PRBS[7] and PRBS[8] among the 10-bit pseudo-random bit sequence signals PRBS[9:0]. The logic gate G2 can perform a NAND calculation on the input signal and then output the result as a signal S2. When the input signals PRBS[1], PRBS[2], PRBS[5], PRBS[6], PRBS[7] and PRBS[8] are all "1", the logic gate G2 can output a logic low signal S2.

[0089] The logic low signal S2 is input to the inverter INV2, and a logic high selection signal Pick2 may be output. The selection signal Pick2 output from the inverter INV2 may correspond to the selection signal from Figure 3 The memory cell row selection circuit 142B outputs the selection signal Pick2. Whenever the memory cell row selection circuit 500A outputs the logic high selection signal Pick2, the memory cell row selection circuit 500A can select a memory cell from the memory cell array 110 (such as Figure 1 A memory cell row is selected from a plurality of memory cell rows (as shown).

[0090] In this way, the period during which the memory cell row selection circuit 500A outputs the logic high selection signal Pick2, i.e., the period T2 during which the memory cell row selection circuit 500A selects one of the plurality of memory cell rows of the memory cell array 110, can be determined as the period of 64 TRCs according to the above equation 2, i.e., once every 64 operations on average. That is, when the control logic circuit 130 (e.g., Figure 1When there are 64 row hammer attacks during the row hammer monitoring time interval (as shown in FIG. 1 ), the memory cell row selection circuit 500A may select a target row.

[0091] In this manner, since the period T2 during which the memory cell row selection circuit 500A selects one memory cell row from among the plurality of memory cell rows in the memory cell array 110 is based on the period T2 of the memory cell row selection circuit 500A implemented as a linear feedback shift register 400 (eg, Figure 4 A random number generator 141 (as shown) Figure 3 The target row is determined by the pseudo-random bit sequence signal PRBS1 output by the memory cell row selection circuit 500A, so the memory cell row selection circuit 500A can randomly select the target row.

[0092] In addition, both the memory cell row selection circuit 500 and the memory cell row selection circuit 500A receive the same n-bit pseudo-random bit sequence signal PRBS1 from the random number generator 141, but can select the target row with different cycles from each other depending on the number of specific bits input to each of the included logic gates G1 and G2.

[0093] exist Figure 5 and Figure 6 In the embodiment, although an example is described in which PRBS[0], PRBS[1], PRBS[2], PRBS[3] and PRBS[4] are matched or PRBS[1], PRBS[2], PRBS[5], PRBS[6], PRBS[7] and PRBS[8] are matched among the 10-bit pseudo-random bit sequence signal PRBS[9:0], as an example, the embodiment of the specific bit to be matched among the 10 bits of the pseudo-random bit sequence signal PRBS[9:0] is not limited to the specific bit given as an example. That is, in order to make the memory cell row selection circuit 500 or the memory cell row selection circuit 500A output the logic high selection signal Pick1 or the logic high selection signal Pick2, the type and number of the specific bits to be matched may vary according to the embodiment.

[0094] According to an embodiment, the memory cell row selection circuits 500 and 500A can both receive two or more specific bits of the 10-bit pseudo-random bit sequence signal PRBS[9:0], and can output a logic high selection signal Pick1 or a selection signal Pick2 in response to all specific bits matching "1", and select a target row.

[0095] In addition, despite Figure 5 and Figure 6 A case where all bits input to the logic gates G1 and G2 are matched to “1” is described, but the embodiment is not limited thereto.

[0096] For example, refer to Figure 7, the memory cell row selection circuit 500B may include a logic gate G3 and an inverter INV3. The memory cell row selection circuit 500B may receive a random number generator 141 (eg, Figure 3 ), and the logic gate G3 of the memory cell row selection circuit 500B can receive a specific bit among the 10-bit pseudo-random bit sequence signal PRBS[9:0] output from the random number generator 141. For example, Figure 7 As shown, the logic gate G3 can receive inputs of PRBS[0], PRBS[7], PRBS[8], and PRBS[9] among the 10-bit pseudo-random bit sequence signals PRBS[9:0]. The logic gate G3 can perform an OR calculation on the input signals and output the result as a signal S3. When the input signals PRBS[0], PRBS[7], PRBS[8], and PRBS[9] are all "0", the logic gate G3 can output a logic low signal S3.

[0097] The logic low signal S3 is input to the inverter INV3, and a logic high selection signal Pick3 may be output. Whenever the memory cell row selection circuit 500B outputs a logic high selection signal Pick3, the memory cell row selection circuit 500B may select a memory cell from the memory cell array 110 (eg, Figure 1 A memory cell row is selected from a plurality of memory cell rows (as shown).

[0098] In this way, the period during which the memory cell row selection circuit 500B outputs the logic high selection signal Pick3, i.e., the period T3 during which the memory cell row selection circuit 500B selects one of the plurality of memory cell rows of the memory cell array 110, can be determined as the period of 16 TRCs according to the above equation 2, i.e., once every 16 operations on average. That is, whenever the control logic circuit 130 (e.g., Figure 1 When there are sixteen row hammer attacks during the row hammer monitoring time interval (shown in FIG. 1 ), the memory cell row selection circuit 500B may select a target row.

[0099] In this way, in response to the fact that specific two or more bits among the pseudo-random bit sequence signal received from the random number generator match each other as "0" or "1", the memory cell row selection circuit can randomly select a memory cell row from among the multiple memory cell rows of the memory cell array 110 with an average period, and store the row address of the selected target row in the allocated queue.

[0100] Figure 8 Is used to describe Figure 3 An example diagram of the effects of a line hammer control circuit.

[0101] Figure 8 It is shown Figure 2 A timing diagram of a refresh operation of the memory device 100 is shown in FIG. Figure 8 , the memory cell array 110 (such as Figure 2 A refresh operation is performed on a memory cell row that is physically adjacent to a memory cell row subjected to a row hammer attack among a plurality of memory cell rows (as shown).

[0102] The time interval T1_Monitoring between time T_REF1 and time T_REF2 and the time interval T2_Monitoring between time T_REF2 and time T_REF3 (eg, the time interval between the times when the row hammer maintenance occurs) may correspond to the control logic circuit 130 (eg, Figure 2 During the row hammer monitoring time interval T1_Monitoring, a row hammer attack may occur on the memory device 100. Furthermore, after the row hammer monitoring time interval T1_Monitoring, during the row hammer monitoring time interval T2_Monitoring which is the next row hammer monitoring time interval, b row hammer attacks may occur (here, a and b are integers of 2 or more different from each other). In this way, the number of row hammer attacks occurring in the memory device 100 may vary for each row hammer monitoring time interval.

[0103] On the other hand, if a row hammer attacks occur during the row hammer monitoring time interval T1_Monitoring, the memory cell row selection circuit can select a memory cell row with a probability of 1 / a, and perform row hammer maintenance on the selected memory cell row at time T_REF2. That is, the defense capability of the memory device 100 can be strengthened by uniformly performing row hammer maintenance against row hammer attacks occurring on the memory device 100 during the row hammer monitoring time interval T1_Monitoring.

[0104] For example, when 50 row hammer attacks occur during the row hammer monitoring time interval, in the case where a memory cell row is not selected with a cycle of 50 TRCs (e.g., a target row is selected when there are approximately 50 row hammer attacks during the row hammer monitoring time interval), a memory cell row is selected with a cycle of 30 TRCs (e.g., a target row is selected when there are approximately 30 row hammer attacks during the row hammer monitoring time interval), and row hammer maintenance is performed on the selected memory cell row (since some of the selected memory cell rows are not input into the queue, they are not subjected to row hammer maintenance in this cycle, but may be subjected to row hammer maintenance in the next cycle). In this way, if the phenomenon that the memory cell row is selected more frequently than the number of row hammer attacks that occur during the row hammer monitoring time interval is repeated, the defense capability of the memory device 100 against the row hammer attack may deteriorate.

[0105] On the other hand, when 50 row hammer attacks occur during the row hammer monitoring time interval, in the case where a memory cell row is selected with a cycle of 70 TRCs (e.g., a target row is selected when there are approximately 70 row hammer attacks during the row hammer monitoring time interval), and row hammer maintenance is performed on the selected memory cell row, since the probability of the memory cell row being selected is low, when the row hammer maintenance is performed at time T_REF, the probability that the queue is empty may be high (e.g., the memory cell row in the queue is empty). As a result, the efficiency of the row hammer maintenance of the memory device 100 may be reduced, and the defense capability of the memory device 100 against the row hammer attack may be deteriorated.

[0106] In addition, if Figure 8 As shown, since the number of row hammer attacks occurring on the memory device 100 during the row hammer monitoring time interval may vary for each row hammer monitoring time interval, the defense capability of the memory device 100 may deteriorate when the memory cell row selected by the memory cell row selection circuit has a fixed average period and row hammer maintenance is performed.

[0107] Therefore, in some embodiments, two or more memory cell row selection circuits that select memory cell rows in different cycles are used, the row addresses of the memory cell rows selected by each memory cell row selection circuit are stored in a queue assigned to each memory cell row selection circuit, and row hammering maintenance is performed on the memory cell rows corresponding to the row addresses stored in each queue. Accordingly, the randomness of the row hammering maintenance can be enhanced, and the defense capability of the memory device 100 against the row hammering attack can be enhanced.

[0108] In addition, since the memory cell row selection circuit selects the memory cell row based on the average period of the pseudo-random bit sequence signal received from the random number generator, the randomness of the row hammering maintenance of the memory device 100 can be further enhanced.

[0109] Fig. 9 is an example diagram showing a configuration of a row hammer control circuit according to some embodiments. Hereinafter, for ease of explanation, further description of previously described elements and technical aspects may be omitted, and differences from the above-described embodiments will be mainly described.

[0110] refer to Fig. 9 , the row hammer control circuit 140A may include a random number generator 141A, a random number generator 141B, a memory cell row selection circuit 142C, and a memory cell row selection circuit 142D. The random number generator 141A may operate when an enable signal RNG2_EN is applied, and the random number generator 141B may operate when an enable signal RNG3_EN is applied. Each of the random number generator 141A and the random number generator 141B may also be referred to as a random number generator circuit.

[0111] The random number generator 141A can be implemented as a linear feedback shift register that generates a k-bit pseudo-random bit sequence signal PRBS2 based on a second seed and a second degree, and the random number generator 141B can be implemented as a linear feedback shift register that generates a j-bit pseudo-random bit sequence signal based on a third seed and a third degree (here, k and j are integers of 2 or greater).

[0112] In some embodiments, the second seed and the third seed may be different from each other, or the second degree and the third degree may be different from each other. That is, when both the random number generator 141A and the random number generator 141B are implemented as Figure 4 When the linear feedback shift register 400 is used, the seeds and the scales of the random number generators 141A and 141B may be different from each other, the random number generators 141A and 141B may have the same seed and different scales, or the random number generators 141A and 141B may have the same scale and different seeds. In this way, the row hammer control circuit 140 may include two or more random number generators that are different from each other in at least one of the seeds and the scales.

[0113] The memory cell row selection circuit 142C may operate when the enable signal RPC3_EN is applied. The memory cell row selection circuit 142C may receive a k-bit pseudo-random bit sequence signal PRBS2 from the random number generator 141A. When the enable signal RPC3_EN is applied to the memory cell row selection circuit 142C, the memory cell row selection circuit 142C may randomly select a memory cell array 110 (e.g., Figure 2 At this time, the memory cell row selected by the memory cell row selection circuit 142C may be one of the multiple memory cell rows (eg, the target row) in the control logic circuit 130 (eg, Figure 1 The target row that is accessed intensively during the row hammer monitoring time interval (as shown in FIG. 1 ), that is, the memory cell row that is subjected to the row hammer attack. In addition, the memory cell row selection circuit 142C can select the memory cell rows one by one in the cycle T4.

[0114] When the memory cell row selection circuit 142C selects a memory cell row in cycle T4, the memory cell row selection circuit 142C may output a logic high selection signal Pick3. Based on the logic high selection signal Pick3, the memory cell row selection circuit 142C may store the row address of the selected memory cell row in the queue Q3. At this time, the queue Q3 may be exclusively assigned to the memory cell row selection circuit 142C. The row address stored in the queue Q3 may be used as Figure 2 The row hammer address RH_ADDR is provided to the refresh control circuit 150 (such as Figure 2 shown).

[0115] The memory cell row selection circuit 142D may operate when the enable signal RPC4_EN is applied. The memory cell row selection circuit 142D may receive a j-bit pseudo-random bit sequence signal PRBS3 from the random number generator 141B. When the enable signal RPC4_EN is applied to the memory cell row selection circuit 142D, the memory cell row selection circuit 142D may randomly select a memory cell row (e.g., a target row) from among a plurality of memory cell rows of the memory cell array 110 based on the received j-bit pseudo-random bit sequence signal PRBS3. At this time, the memory cell row selected by the memory cell row selection circuit 142D may be a target row that is centrally accessed during the row hammer monitoring time interval of the control logic circuit 130, i.e., a memory cell row that is subjected to a row hammer attack. At this time, the memory cell row selection circuit 142D may select the memory cell rows one by one with a period T5 that is different from the period T4 of the memory cell row selection circuit 142C.

[0116] When the memory cell row selection circuit 142D selects a memory cell row in cycle T5, the memory cell row selection circuit 142D may output a logic high selection signal Pick4. Based on the logic high selection signal Pick4, the memory cell row selection circuit 142D may store the row address of the selected memory cell row in the queue Q4. At this time, the queue Q4 may be exclusively assigned to the memory cell row selection circuit 142D. The row address stored in the queue Q4 may be used as Figure 2 The row hammer address RH_ADDR is provided to the refresh control circuit 150.

[0117] In this way, the row hammer control circuit 140A may include two or more random number generators 141A and 141B that differ in at least one of the seed and the degree, and the memory cell row selection circuits 142C and 142D that have received the pseudo-random bit sequence signals PRBS2 and PRBS3 from each of the random number generators 141A and 141B may select memory cell rows at different cycles and store the row addresses of the selected memory cell rows in queues Q3 and Q4 assigned to each of them, respectively.

[0118] although Fig. 9 It is shown that the random number generator 141A sends the pseudo-random bit sequence signal PRBS2 to one memory cell row selection circuit 142C, and the random number generator 141B sends the pseudo-random bit sequence signal PRBS3 to one memory cell row selection circuit 142D, but the embodiment is not limited thereto. For example, in some embodiments, the random number generator 141A or the random number generator 141B can send the pseudo-random bit sequence signal to two or more memory cell row selection circuits, and each memory cell row selection circuit can select a memory cell row with a cycle different from each other, and store the row address of the selected memory cell row in a queue assigned to each of them.

[0119] Fig.10 is an example diagram showing a configuration of a flag signal generating circuit according to some embodiments. Hereinafter, for the sake of convenience of explanation, further description of previously described elements and technical aspects may be omitted, and differences from the above-described embodiments will be mainly described.

[0120] refer to Fig.10, the row hammer control circuit 140B may include random number generators 141C, 141D, and 141E that operate according to each of the enable signals RNG4_EN, RNG5_EN, and RNG6_EN, and memory cell row selection circuits 142E, 142F, and 142G that operate according to each of the enable signals RPC5_EN, RPC6_EN, and RPC7_EN. Each of the random number generators 141C, 141D, and 141E may output a p-bit pseudo-random bit sequence signal PRBS4, a q-bit pseudo-random bit sequence signal PRBS5, and an r-bit pseudo-random bit sequence signal PRBS6, and send these signals to the memory cell row selection circuits 142E, 142F, and 142G (here, p, q, and r are integers of 2 or greater). Each of the random number generators 141C, 141D, and 141E may also be referred to as a random number generator circuit.

[0121] The memory cell row selection circuits 142E, 142F, and 142G can select memory cell rows (i.e., target rows) at different cycles from each other based on the received signals, and output selection signals Pick5, Pick6, and Pick7. When the selection signals Pick5, Pick6, and Pick7 are logic high, each of the memory cell row selection circuits 142E, 142F, and 142G can store the row address of the selected one memory cell row in the queues Q5, Q6, and Q7.

[0122] In some embodiments, the row hammer control circuit 140B may further include a flag signal generating circuit 600A, a flag signal generating circuit 600B, and a flag signal generating circuit 600C.

[0123] The flag signal generation circuit 600A may output a flag signal Flag1 based on the selection signal Pick5 output from the memory cell row selection circuit 142E. The flag signal generation circuit 600B may output a flag signal Flag2 based on the selection signal Pick6 output from the memory cell row selection circuit 142F and the flag signal Flag1. The flag signal generation circuit 600C may output a flag signal Flag3 based on the selection signal Pick7 output from the memory cell row selection circuit 142G, the flag signal Flag1, and the flag signal Flag2.

[0124] In some embodiments, the flag signals Flag1, Flag2, and Flag3 output from each of the flag signal generating circuits 600A, 600B, and 600C of the row hammer control circuit 140B may be sent to the refresh control circuit 150 (eg, Figure 2). The refresh control circuit 150 may define the order of row hammering maintenance for the memory cell rows corresponding to the row addresses respectively stored in the queues Q5, Q6 and Q7 based on the flag signals Flag1, Flag2 and Flag3. For example, when the flag signal Flag1 is logic high and the flag signals Flag2 and Flag3 are logic low, the refresh control circuit 150 may prioritize the row hammering maintenance operations for the memory cell rows respectively corresponding to the row addresses stored in the queues Q6 and Q7, and perform a refresh operation, for example, a row hammering maintenance operation, on the memory cell rows physically adjacent to the memory cell rows corresponding to the row addresses stored in the queue Q5.

[0125] That is, the row hammering maintenance operation is performed on the memory cell row corresponding to the row address stored in the queue Q6 or the queue Q7 respectively only when the row address is not stored in the queue Q5. When the row address is stored in the queue Q5, the row hammering maintenance operation may be performed first on the memory cell row corresponding to the row address stored in the queue Q5.

[0126] However, the embodiment is not limited thereto. For example, according to an embodiment, the row hammer control circuit 140B does not send a flag signal to the refresh control circuit 150, but may determine the priority of each of the queues Q5, Q6, and Q7 depending on the logic state of each of the flag signals Flag1, Flag2, and Flag3, and provide the row address stored in any one of the queues as the row hammer address RH_ADDR to the refresh control circuit 150.

[0127] For example, in an embodiment, when the flag signal Flag1 is logic high and the flag signals Flag2 and Flag3 are logic low, the row hammer control circuit 140B may provide the row address stored in the queue Q5 as the row hammer address RH_ADDR to the refresh control circuit 150, and not provide the row addresses stored in the queues Q6 and Q7 to the refresh control circuit 150.

[0128] In an embodiment, when the flag signal Flag1 and the flag signal Flag3 are logic low and the flag signal Flag2 is logic high, the row hammer control circuit 140B may provide the row address stored in the queue Q6 as the row hammer address RH_ADDR to the refresh control circuit 150, and not provide the row address stored in each of the queues Q5 and Q7 to the refresh control circuit 150.

[0129] In an embodiment, when the flag signal Flag1 and the flag signal Flag2 are logic low and the flag signal Flag3 is logic high, the row hammer control circuit 140B may provide only the row address stored in the queue Q7 as the row hammer address RH_ADDR to the refresh control circuit 150 .

[0130] In this manner, depending on the logic states of the flag signals Flag1, Flag2, and Flag3, the refresh control circuit 150 can perform a row hammering maintenance operation on a memory cell row corresponding to a row address stored in any one of the queues Q5, Q6, and Q7 in priority to a row hammering maintenance operation on a memory cell row corresponding to a row address stored in the other queues. That is, a row hammering maintenance operation on a row address stored in a queue corresponding to a memory cell row selection circuit whose flag signal is logic high can be performed in priority to a row hammering maintenance operation on a row address stored in a queue corresponding to a memory cell row selection circuit whose flag signal is logic low.

[0131] In some embodiments, a row hammering maintenance operation on a row address stored in a queue corresponding to a memory cell row selection circuit having a relatively long cycle may be performed in preference to a row hammering maintenance operation on a row address stored in a queue corresponding to a memory cell row selection circuit having a relatively short cycle.

[0132] For example, assuming that the memory cell row selection circuit 142E selects a single memory cell row with a cycle T6, the memory cell row selection circuit 142F selects a single memory cell row with a cycle T7, and the memory cell row selection circuit 142G selects a single memory cell row with a cycle T8 (here, assuming that the cycle T6 is longer than the cycle T7, and the cycle T7 is longer than the cycle T8), the row hammer maintenance operation on the row addresses stored in the queue Q5 can be performed in priority to the row hammer maintenance operation on the row addresses stored in the queue Q6, and the row hammer maintenance operation on the row addresses stored in the queue Q6 can be performed in priority to the row hammer maintenance operation on the row addresses stored in the queue Q7.

[0133] For example, assuming that the memory cell row selection circuit 142E selects a target row when there are 200 row hammer attacks, the memory cell row selection circuit 142F selects a target row when there are 150 row hammer attacks, and the memory cell row selection circuit 142G selects a target row when there are 100 row hammer attacks, the row hammer maintenance operation on the row address stored in queue Q5 can be performed in priority to the row hammer maintenance operation on the row address stored in queue Q6, and the row hammer maintenance operation on the row address stored in queue Q6 can be performed in priority to the row hammer maintenance operation on the row address stored in queue Q7.

[0134] Therefore, each circuit configuration of the flag signal generating circuits 600A, 600B and 600C can be configured so that when the flag signal Flag1 is logic high, the flag signals Flag2 and Flag3 are logic low, when the flag signals Flag1 and Flag3 are logic low, the flag signal Flag2 is logic high, and when the flag signals Flag1 and Flag2 are logic low, the flag signal Flag3 is logic high.

[0135] In some embodiments, the flag signal generating circuit 600A may include an inverter INV4, an inverter INV5, a logic gate G4, and a logic gate G5.

[0136] First, the case where each of the memory cell row selection circuits 142E, 142F, and 142G selects a memory cell row (i.e., the case where the selection signals Pick5, Pick6, and Pick7 are all logically high) will be described as an example. The logic high selection signal Pick5 may be input to the inverter INV4. The inverter INV4 may invert the logic high selection signal Pick5 and output a logic low signal S4. The logic low signal S4 and the signal S5 of the node N1 may be input to the logic gate G4. The logic gate G4 may perform a NAND calculation on the logic low signal S4 and the signal S5 to output a signal S6. At this time, the signal S6 may be logic high.

[0137] The enable signal EN1 and the logic high signal S6 may be input to the logic gate G5. When the selection signal Pick5 output from the memory cell row selection circuit 142E is logic high, the enable signal EN1 input to the logic gate G5 may be logic high. The logic gate G5 may perform a NAND calculation on the logic high enable signal EN1 and the logic high signal S6 to provide a logic low signal S5 to the node N1. The inverter INV5 may invert the logic low signal S5 and output a logic high flag signal Flag1.

[0138] In some embodiments, the flag signal generation circuit 600B may output the flag signal Flag2 based on the selection signal Pick6 output from the memory cell row selection circuit 142F and the flag signal Flag1. The flag signal generation circuit 600B may include inverters INV6, INV7, logic gates G6, G7, and G8.

[0139] The logic high flag signal Flag1 may be input to the inverter INV6 of the flag signal generating circuit 600B. The inverter INV6 may invert the logic high flag signal Flag1 to output a logic low signal S7. The logic low signal S7 and the logic high pick signal Pick6 may be input to the logic gate G6. The logic gate G6 may perform a NAND calculation on the logic low signal S7 and the logic high pick signal Pick6, and output a logic high signal S8.

[0140] The logic high signal S8 and the signal S9 of the node N2 may be input to the logic gate G7. The logic gate G7 may perform a NAND calculation on the logic high signal S8 and the signal S9 to output a signal S10. The enable signal EN2 and the signal S10 may be input to the logic gate G8. At this time, when the flag signal Flag1 is logic high, the enable signal EN2 input to the logic gate G8 may be logic low. The logic gate G8 may perform a NAND calculation on the logic low enable signal EN2 and the signal S10 to provide a logic high signal S9 to the node N2. The inverter INV7 may invert the logic high signal S9 to output a logic low flag signal Flag2.

[0141] In some embodiments, the flag signal generation circuit 600C may output the flag signal Flag3 based on the selection signal Pick7, the flag signal Flag1, and the flag signal Flag2 output from the memory cell row selection circuit 142G. The flag signal generation circuit 600C may include logic gates G9, G10, G11, G12, and an inverter INV8.

[0142] The logic high flag signal Flag1 and the logic low flag signal Flag2 may be input to the logic gate G9. The logic gate G9 may perform a NOR calculation on the logic high flag signal Flag1 and the logic low flag signal Flag2, and output a logic low signal S11. The logic low signal S11 and the logic high pick signal Pick7 may be input to the logic gate G10. The logic gate G10 may perform a NAND calculation on the logic low signal S11 and the logic high pick signal Pick7 to output a logic high signal S12.

[0143] A signal S13 of a node N3 connected to an output terminal of the logic gate G12 may be input to the logic gate G11. The logic gate G11 may perform a NAND calculation on a logic high signal S12 and the signal S13 to output a signal S14. An enable signal EN3 and the signal S14 may be input to the logic gate G12. When the flag signal Flag1 or the flag signal Flag2 is logic high, the enable signal EN3 input to the logic gate G12 may be logic low. The logic gate G12 may perform a NAND calculation on a logic low enable signal EN3 and the signal S14 to provide a logic high signal S13 to the node N3. The inverter INV8 may invert the logic high signal S13 and output a logic low flag signal Flag3.

[0144] In this way, when the flag signal Flag1 is logic high, each of the flag signals Flag2 and Flag3 is logic low, and a row hammering maintenance operation on the row address stored in the queue Q5 corresponding to the memory cell row selection circuit 142E having the longest cycle can be performed in priority to the row hammering maintenance operation on the row address stored in the queues Q6 and Q7 corresponding to each of the other memory cell row selection circuits 142F and 142G.

[0145] Next, an example will be described by the case where the memory cell row selection circuit 142E does not select a memory cell row and the memory cell row selection circuits 142F and 142G both select a memory cell row (i.e., the selection signal Pick5 is logic low, and the selection signals Pick6 and Pick7 are logic high). Hereinafter, for ease of explanation, further description of previously described elements and technical aspects may be omitted, and the differences from the above-described embodiment will be mainly described.

[0146] The logic low selection signal Pick5 may be input to the inverter INV4. The inverter INV4 may invert the logic low selection signal Pick5 to output a logic high signal S4. The logic high signal S4 and the signal S5 of the node N1 may be input to the logic gate G4. The logic gate G4 may perform a NAND calculation on the logic high signal S4 and the signal S5 to output a signal S6.

[0147] The enable signal EN1 and the signal S6 may be input to the logic gate G5. When the selection signal Pick5 output from the memory cell row selection circuit 142E is logic low, the enable signal EN1 input to the logic gate G5 may be logic low. The logic gate G5 may perform a NAND calculation on the logic low enable signal EN1 and the signal S6 to provide a logic high signal S5 to the node N1. The inverter INV5 may invert the logic high signal S5 to output a logic low flag signal Flag1.

[0148] The logic low flag signal Flag1 may be input to the inverter INV6 of the flag signal generating circuit 600B. The inverter INV6 may invert the logic low flag signal Flag1 to output a logic high signal S7. The logic high signal S7 and the logic high pick signal Pick6 may be input to the logic gate G6. The logic gate G6 may perform a NAND calculation on the logic high signal S7 and the logic high pick signal Pick6, and output a logic low signal S8. The logic low signal S8 and the signal S9 of the node N2 may be input to the logic gate G7. The logic gate G7 may perform a NAND calculation on the logic low signal S8 and the signal S9 to output a logic high signal S10.

[0149] The enable signal EN2 and the logic high signal S10 may be input to the logic gate G8. If the flag signal Flag1 is logic low and the pick signal Pick6 is logic high, the enable signal EN2 input to the logic gate G8 may be logic high. The logic gate G8 may perform a NAND calculation on the logic high enable signal EN2 and the logic high signal S10 to provide a logic low signal S9 to the node N2. The inverter INV7 may invert the logic low signal S9 to output a logic high flag signal Flag2.

[0150] The logic low flag signal Flag1 and the logic high flag signal Flag2 may be input to the logic gate G9 of the flag signal generating circuit 600C. The logic gate G9 may perform a NOR calculation on the logic low flag signal Flag1 and the logic high flag signal Flag2, and output a logic low signal S11. The logic low signal S11 and the logic high pick signal Pick7 may be input to the logic gate G10. The logic gate G10 may perform a NAND calculation on the logic low signal S11 and the logic high pick signal Pick7, and output a logic high signal S12.

[0151] A signal S13 of a node N3 connected to an output terminal of the logic gate G12 may be input to the logic gate G11. The logic gate G11 may perform a NAND calculation on a logic high signal S12 and the signal S13 to output a signal S14. An enable signal EN3 and the signal S14 may be input to the logic gate G12. When the flag signal Flag1 or the flag signal Flag2 is logic high, the enable signal EN3 input to the logic gate G12 may be logic low. The logic gate G12 may perform a NAND calculation on a logic low enable signal EN3 and the signal S14 to provide a logic high signal S13 to the node N3. The inverter INV8 may invert the logic high signal S13 to output a logic low flag signal Flag3.

[0152] In this way, when the flag signal Flag1 is logic low and the pick signal Pick6 is logic high, the flag signal Flag2 may become logic high, and the flag signal Flag3 may become logic low. As a result, when the memory cell row selection circuit 142E having the longest cycle does not select a memory cell row, a row hammering maintenance operation on a row address stored in a queue Q6 corresponding to a memory cell row selection circuit 142F having the next longest cycle may be performed in priority to a row hammering maintenance operation on a row address stored in a queue Q7 corresponding to another memory cell row selection circuit 142G.

[0153] Next, an example will be described by the case where the memory cell row selection circuits 142E and 142F do not select a memory cell row and the memory cell row selection circuit 142G selects one memory cell row (ie, the pick signals Pick5 and Pick6 are logic low, and the pick signal Pick7 is logic high).

[0154] The logic low selection signal Pick5 may be input to the inverter INV4. The inverter INV4 may invert the logic low selection signal Pick5 to output a logic high signal S4. The logic high signal S4 and the signal S5 of the node N1 may be input to the logic gate G4. The logic gate G4 may perform a NAND calculation on the logic high signal S4 and the signal S5 to output a signal S6.

[0155] The enable signal EN1 and the signal S6 may be input to the logic gate G5. When the selection signal Pick5 output from the memory cell row selection circuit 142E is logic low, the enable signal EN1 input to the logic gate G5 may be logic low. The logic gate G5 may perform a NAND calculation on the logic low enable signal EN1 and the signal S6 to provide a logic high signal S5 to the node N1. The inverter INV5 may invert the logic high signal S5 to output a logic low flag signal Flag1.

[0156] The logic low flag signal Flag1 may be input to the inverter INV6 of the flag signal generating circuit 600B. The inverter INV6 may invert the logic low flag signal Flag1 to output a logic high signal S7. The logic high signal S7 and the logic low pick signal Pick6 may be input to the logic gate G6. The logic gate G6 may perform a NAND calculation on the logic high signal S7 and the logic low pick signal Pick6 to output a logic high signal S8. The logic high signal S8 and the signal S9 of the node N2 may be input to the logic gate G7. The logic gate G7 may perform a NAND calculation on the logic high signal S8 and the signal S9 to output a signal S10.

[0157] The enable signal EN2 and the signal S10 may be input to the logic gate G8. When the selection signal Pick6 is logic low, the enable signal EN2 input to the logic gate G8 may be logic low. The logic gate G8 may perform a NAND calculation on the logic low enable signal EN2 and the signal S10 to provide a logic high signal S9 to the node N2. The inverter INV7 may invert the logic high signal S9 to output a logic low flag signal Flag2.

[0158] The logic low flag signal Flag1 and the logic low flag signal Flag2 may be input to the logic gate G9 of the flag signal generating circuit 600C. The logic gate G9 may perform a NOR calculation on the logic low flag signal Flag1 and the logic low flag signal Flag2, and output a logic high signal S11. The logic high signal S11 and the logic high pick signal Pick7 may be input to the logic gate G10. The logic gate G10 may perform a NAND calculation on the logic high signal S11 and the logic high pick signal Pick7, and output a logic low signal S12.

[0159] A signal S13 of a node N3 connected to an output terminal of the logic gate G12 may be input to the logic gate G11. The logic gate G11 may perform a NAND calculation on a logic low signal S12 and a signal S13, and output a logic high signal S14. An enable signal EN3 and a logic high signal S14 may be input to the logic gate G12. When the flag signals Flag1 and Flag2 are logic low and the pick signal Pick7 is logic high, the enable signal EN3 may be logic high. The logic gate G12 may perform a NAND calculation on a logic high enable signal EN3 and a logic high signal S14, and provide a logic low signal S13 to the node N3. The inverter INV8 may invert the logic low signal S13 to output a logic high flag signal Flag3.

[0160] In this way, when the flag signals Flag1 and Flag2 are logic low and the pick signal Pick7 is logic high, the flag signal Flag3 may be logic high. Accordingly, when the memory cell row selection circuits 142E and 142F having a longer cycle than the memory cell row selection circuit 142G do not select a memory cell row, a row hammering maintenance operation on the row address stored in the queue Q7 corresponding to the memory cell row selection circuit 142G may be performed first. Thereafter, when the flag signal Flag1 or the flag signal Flag2 becomes logic high, a row hammering maintenance operation on the row address stored in the queue corresponding to the memory cell row selection circuits 142E and 142F having a long cycle may be performed in preference to the row hammering maintenance operation on the row address stored in the queue corresponding to the memory cell row selection circuit 142G.

[0161] Fig.11is an exemplary diagram showing a configuration of a flag signal generating circuit according to some embodiments.

[0162] refer to Fig.11 , the row hammer control circuit 140C may include random number generators 141F, 141G, and 141H that operate according to each of the enable signals RNG7_EN, RNG8_EN, and RNG9_EN, and memory cell row selection circuits 142H, 142I, 142J, and 142K that operate according to each of the enable signals RPC8_EN, RPC9_EN, RPC10_EN, and RPC11_EN. Each of the random number generators 141F, 141G, and 141H may output an s-bit pseudo-random bit sequence signal PRBS7, a t-bit pseudo-random bit sequence signal PRBS8, and a u-bit pseudo-random bit sequence signal PRBS9, and transmit these signals to the memory cell row selection circuits 142H, 142I, 142J, and 142K. Each of the random number generators 141F, 141G, and 141H may also be referred to as a random number generator circuit.

[0163] The memory cell row selection circuits 142H, 142I, 142J, and 142K can select memory cell rows at different cycles from each other based on the received signals, and respectively output selection signals Pick8, Pick9, Pick10, and Pick11. When the selection signals Pick8, Pick9, Pick10, and Pick11 are logic high, each of the memory cell row selection circuits 142H, 142I, 142J, and 142K can store the row address of the selected one memory cell row in each of the queues Q8, Q9, Q10, and Q11.

[0164] Although the hammer control circuit 140C Fig.11 141F, 141G and 141H and four memory cell row selection circuits 142H, 142I, 142J and 142K are shown in FIG. 140C, but the embodiment is not limited thereto. For example, the number of random number generators and memory cell row selection circuits included in the row hammer control circuit 140C may vary according to the embodiment.

[0165] In some embodiments, the row hammer control circuit 140C may further include a queue selection circuit 143 and a multiplexer 144. The queue selection circuit 143 may receive an s-bit pseudo-random bit sequence signal PRBS7 from a random number generator 141F together with the memory cell row selection circuit 142H. The queue selection circuit 143 may send a signal S15 including the first bit among the s-bit pseudo-random bit sequence signal PRBS7 received from the random number generator 141F to the multiplexer 144. At this time, the number of bits of the first bit may be determined by the number of memory cell row selection circuits included in the row hammer control circuit 140C. For example, Fig.11 As shown, when the number of memory cell row selection circuits included in the row hammer control circuit 140C is 4, the queue selection circuit 143 can send a signal S15 including 2 bits of the s-bit pseudo-random bit sequence signal PRBS7 received from the random number generator 141F to the multiplexer 144.

[0166] The multiplexer 144 may output any one of the flag signals Flag8, Flag9, Flag10, and Flag11 in response to the signal S15 received from the queue selection circuit 143. The flag signals Flag8, Flag9, Flag10, and Flag11 may correspond to the memory cell row selection circuits 142H, 142I, 142J, and 142K, respectively. In addition, the flag signals Flag8, Flag9, Flag10, and Flag11 may correspond to the queues Q8, Q9, Q10, and Q11 specifically assigned to the memory cell row selection circuits 142H, 142I, 142J, and 142K, respectively.

[0167] The row hammer control circuit 140C may provide the row address stored in the queue corresponding to the flag signal output from the multiplexer 144 as the row hammer address RH_ADDR to the refresh control circuit 150 (eg, Figure 2 For example, when the multiplexer 144 outputs the flag signal Flag8, the row hammer control circuit 140C may provide the first stored row address among the row addresses stored in the queue Q8 to the refresh control circuit 150 as the row hammer address RH_ADDR.

[0168] In some embodiments, the signal S15 including the first bit may refer to any one of the memory cell row selection circuits 142H, 142I, 142J, and 142K included in the row hammer control circuit 140C. For example, assuming that the cycle of the memory cell row selection circuit selecting a memory cell row is longer in the order of the memory cell row selection circuit 142H, the memory cell row selection circuit 142I, the memory cell row selection circuit 142J, and the memory cell row selection circuit 142K, when the signal S15 is "00", the multiplexer 144 may select the memory cell row selection circuit 142H and output the flag signal Flag8. In addition, when the signal S15 is "01", the multiplexer 144 can select the memory cell row selection circuit 142I and output the flag signal Flag9, when the signal S15 is "10", the multiplexer 144 can select the memory cell row selection circuit 142J and output the flag signal Flag10, and when the signal S15 is "11", the multiplexer 144 can select the memory cell row selection circuit 142K and output the flag signal Flag11. However, the embodiment is not limited to this. For example, according to an embodiment, the flag signal output from the multiplexer 144 according to the signal S15 including the first bit and the memory cell row selection circuit corresponding thereto can be randomly determined regardless of the cycle of the memory cell row selection circuit.

[0169] In this way, the order in which the row addresses stored in each of the queues Q8, Q9, Q10 and Q11 are provided as the row hammer address RH_ADDR to the refresh control circuit 150 can be randomly determined by the queue selection circuit and the multiplexer, the queue selection circuit receiving a pseudo-random bit sequence signal from any one of the random number generators included in the row hammer control circuit 140C, and the multiplexer outputting a flag signal in response to the bit signal output from the queue selection circuit.

[0170] Fig.12 is an exemplary diagram showing a configuration of a flag signal generating circuit according to some embodiments.

[0171] refer to Fig.12The row hammer control circuit 140D may include random number generators 141I, 141J, and 141K that operate according to each of the enable signals RNG10_EN, RNG11_EN, and RNG12_EN, and memory cell row selection circuits 142L, 142M, 142N, and 142O that operate according to each of the enable signals RPC12_EN, RPC13_EN, RPC14_EN, and RPC15_EN. Each of the random number generators 141I, 141J, and 141K may output a v-bit pseudo-random bit sequence signal, a w-bit pseudo-random bit sequence signal, and an x-bit pseudo-random bit sequence signal, and send these signals to the memory cell row selection circuits 142L, 142M, 142N, and 142O, respectively (here, v, w, and x are all integers of 2 or greater). Each of the random number generators 141I, 141J, and 141K may also be referred to as a random number generator circuit.

[0172] The memory cell row selection circuits 142L, 142M, 142N, and 142O may select memory cell rows at different cycles based on received signals, and respectively output selection signals Pick12, Pick13, Pick14, and Pick15. When the selection signals Pick12, Pick13, Pick14, and Pick15 are logic high, each of the memory cell row selection circuits 142L, 142M, 142N, and 142O may store a row address of a selected memory cell row in each of the queues Q12, Q13, Q14, and Q15.

[0173] Although the hammer control circuit 140D Fig.12 141I, 141J and 141K and four memory cell row selection circuits 142L, 142M, 142N and 142O are shown in the figure, but the embodiment is not limited thereto. For example, the number of random number generators and memory cell row selection circuits included in the row hammering control circuit 140D and the number of memory cell row selection circuits receiving a pseudo-random bit sequence signal from a random number generator may vary according to the embodiment.

[0174] In some embodiments, the row hammer control circuit 140D may further include a counter 145 and a multiplexer 146. The counter 145 may also be referred to as a counter circuit. The counter 145 may send a count signal including a second bit to the multiplexer 146. The number of bits of the count signal may be determined by the number of memory cell row selection circuits included in the row hammer control circuit 140D. For example, Fig.12As shown, when the number of memory cell row selection circuits included in the row hammer control circuit 140D is 4, the counter 145 may send a 2-bit counting signal to the multiplexer 146.

[0175] The multiplexer 146 may output any one of the flag signals Flag12, Flag13, Flag14, and Flag15 in response to the count signal received from the counter 145. The flag signals Flag12, Flag13, Flag14, and Flag15 may correspond to the memory cell row selection circuits 142L, 142M, 142N, and 142O, respectively. In addition, the flag signals Flag12, Flag13, Flag14, and Flag15 may correspond to the queues Q12, Q13, Q14, and Q15 specifically allocated to the memory cell row selection circuits 142L, 142M, 142N, and 142O, respectively.

[0176] The row hammer control circuit 140D may provide the row address stored in the queue corresponding to the flag signal output from the multiplexer 146 as the row hammer address RH_ADDR to the refresh control circuit 150 (eg, Figure 2 For example, when the multiplexer 146 outputs the flag signal Flag12, the row hammer control circuit 140D may provide the first stored row address among the row addresses stored in the queue Q12 as the row hammer address RH ADDR to the refresh control circuit 150.

[0177] In some embodiments, the count signal including the second bit may refer to any one of the memory cell row selection circuits included in the row hammer control circuit 140D. For example, assuming that the cycle of the memory cell row selection circuit selecting one memory cell row is longer in the order of the memory cell row selection circuit 142L, the memory cell row selection circuit 142M, the memory cell row selection circuit 142N, and the memory cell row selection circuit 142O, when the count signal is "00", the multiplexer 146 may select the memory cell row selection circuit 142L and output the flag signal Flag12. In addition, when the count signal is "01", the multiplexer 146 may select the memory cell row selection circuit 142M and output the flag signal Flag13, when the count signal is "10", the multiplexer 146 may select the memory cell row selection circuit 142N and output the flag signal Flag14, and when the count signal is "11", the multiplexer 146 may select the memory cell row selection circuit 142O and output the flag signal Flag15. However, the embodiment is not limited thereto. For example, according to an embodiment, the flag signal output from the multiplexer 146 in response to the count signal including the second bit and the memory cell row selection circuit corresponding thereto may be randomly determined regardless of the cycle of the row selection circuit.

[0178] In this way, the order in which the row addresses stored in the queues Q12, Q13, Q14 and Q15 are provided as the row hammer addresses RH_ADDR to the refresh control circuit 150 can be determined by the counter and the multiplexer according to a fixed order, and the counter outputs count signals of specific bits in sequence, and the multiplexer outputs a flag signal corresponding to each memory cell row selection circuit (or a queue assigned to the memory cell row selection circuit) in response to receiving the count signal from the counter.

[0179] Figures 13 to 15 is an example diagram for describing a row hammer control circuit according to some embodiments.

[0180] First, refer to Fig.13 , the row hammer control circuit 140E may include a random number generator 141L that operates according to an enable signal RNG13_EN, and memory cell row selection circuits 142P and 142Q that operate according to corresponding enable signals RPC16_EN and RPC17_EN. The random number generator 141L may output a y-bit pseudo-random bit sequence signal PRBS13, and send the signal to the memory cell row selection circuits 142P and 142Q, respectively (here, y is an integer of 2 or greater). The random number generator 141L may also be referred to as a random number generator circuit.

[0181] The memory cell row selection circuits 142P and 142Q can select memory cell rows with different cycles from each other based on the received signals, and output selection signals Pick16 and Pick17, respectively. When the selection signal Pick16 is logic high, the memory cell row selection circuit 142P can store the row address of a selected memory cell row in queues Q16a and Q16b. At this time, the number of queues specifically assigned to the memory cell row selection circuit 142P can be two or more. Similarly, when the selection signal Pick17 is logic high, the memory cell row selection circuit 142Q can store the row address of a selected memory cell row in queues Q17a and Q17b. At this time, the number of queues specifically assigned to the memory cell row selection circuit 142Q can also be two or more.

[0182] Although the hammer control circuit 140E Fig.13 140E is shown as including one random number generator and two memory cell row selection circuits, but the embodiment is not limited thereto. For example, the number of random number generators and memory cell row selection circuits included in the row hammer control circuit 140E and the number of memory cell row selection circuits receiving a pseudo-random bit sequence signal from a random number generator may vary according to the embodiment.

[0183] In some embodiments, the row hammer control circuit 140E may include queue selection signal generators 147A and 147B. The queue selection signal generator 147A may generate a signal for selecting any one of the queues Q16a and Q16b specifically assigned to the memory cell row selection circuit 142P. For example, when the memory cell row selection circuit 142P outputs a logic high selection signal Pick16, the row address of the memory cell row selected by the memory cell row selection circuit 142P may be stored in the queue Q16a or Q16b. At this time, when the queue selection signal generator 147A outputs the queue selection signal QP16a, the row address may be stored in the queue Q16a, and when the queue selection signal generator 147A outputs the queue selection signal QP16b, the row address may be stored in the queue Q16b.

[0184] Similarly, the queue selection signal generator 147B may generate a signal for selecting one of the queues Q17a and Q17b specifically assigned to the memory cell row selection circuit 142Q. For example, when the memory cell row selection circuit 142Q outputs a logic high selection signal Pick17, the row address of the memory cell row selected by the memory cell row selection circuit 142Q may be stored in the queue Q17a or Q17b. At this time, when the queue selection signal generator 147B outputs the queue selection signal QP17a, the row address may be stored in the queue Q17a, and when the queue selection signal generator 147B outputs the queue selection signal QP17b, the row address may be stored in the queue Q17b.

[0185] At this time, each of the queue pick signal generator 147A and the queue pick signal generator 147B may output queue pick signals QP16a and QP16b and queue pick signals QP17a and QP17b based on the enable signals RPC16_EN and RPC17_EN and the pick signals Pick16 and Pick17.

[0186] As previously referenced Figure 3As described, since the memory cell row selection circuit 142P and the memory cell row selection circuit 142Q operate by different enable signals from each other, any one of the memory cell row selection circuit 142P and the memory cell row selection circuit 142Q can be turned on to operate, and the other can be turned off to not operate. Hereinafter, an example will be described in which the memory cell row selection circuit 142P is turned off when the enable signal RPC16_EN is in a logic low state and the memory cell row selection circuit 142Q is turned on when the enable signal RPC17_EN is in a logic high state. At this time, since the memory cell row selection circuit 142P does not operate, the selection signal Pick16 can be logic low, and since the memory cell row selection circuit 142Q operates, the selection signal Pick17 can be logic high.

[0187] Fig.14 It is shown Fig.13 An example diagram of a queue selection signal generator 147A. Fig.15 It is shown Fig.13 An example diagram of a queue selection signal generator 147B.

[0188] refer to Fig.14 The queue selection signal generator 147A may include a latch LATCH1, a latch LATCH2, a data signal generator 148A and a clock signal generator 149A.

[0189] The latch LATCH1 may receive the clock signal CLK1, and output the input data signal D1 to the latch LATCH2 based on the clock signal CLK1. At this time, the data signal D2 output from the latch LATCH1 is a signal obtained by delaying the data signal D1 for a predetermined time, and may correspond to the queue selection signal QP16a. The latch LATCH2 receives the clock signal CLK1, and may output the data signal D3 obtained by delaying the input data signal D2 for a predetermined period of time based on the clock signal CLK1. At this time, the data signal D3 is a signal obtained by delaying the data signal D2 for a predetermined time, and may correspond to the queue selection signal QP16b.

[0190] The clock signal generator 149A may include an inverter INV9 and logic gates G13, G14, and G15. When the memory cell row selection circuit 142P is turned off, the inverter INV9 of the clock signal generator 149A may invert the logic low enable signal RPC16_EN to output a logic high signal S16. The logic gate G13 may receive the logic high signal S16 and the logic high selection signal Pick17, and perform a NAND calculation to output a logic low signal S17.

[0191] Logic gate G14 may receive logic low enable signal RPC16_EN and logic low pick signal Pick16 and perform NAND calculation to output logic high signal S18. Logic gate G15 may receive logic high signal S18 and logic low signal S17 and perform NAND calculation to output logic high clock signal CLK1.

[0192] The data signal generator 148A may include inverters INV10 and INV11 and logic gates G16, G17, G18, G19, G20, and G21. The inverter INV10 may invert the logic low enable signal RPC16_EN to output a logic high signal S18. The inverter INV11 may invert the logic high enable signal RPC17_EN to output a logic low signal S19. The logic gate G16 may receive the logic low signal S19 and the logic low enable signal RPC16_EN, and perform an AND calculation to output a logic low signal S20. The logic gate G17 may receive the logic high signal S18 and the logic low signal S20, and perform an OR calculation to output a logic high signal S21.

[0193] The logic high signal S21 and the queue selection signal QP17b may be input to the logic gate G18. At this time, since the memory cell row selection circuit 142P is in the off state, the row address of the memory cell row selected by the memory cell row selection circuit 142P may no longer be stored in the queues Q16a and Q16b specifically assigned to the existing memory cell row selection circuit 142P. Accordingly, another memory cell row selection circuit 142Q included in the row hammer control circuit 140E may also utilize the queues Q16a and Q16b in addition to the existing specifically assigned queues Q17a and Q17b. That is, the row address of the memory cell row selected by the memory cell row selection circuit 142Q may be stored in the queues Q16a, Q16b, Q17a, and Q17b.

[0194] Therefore, in order for the memory cell row selection circuit 142Q to utilize the queues Q16a and Q16b, the queue selection signal QP17b of the data signal generator 148A may be logic high, and the queue selection signal QP16b may be logic low. That is, as will be described below with reference to Fig.15 Described from Fig.15 The queue selection signal QP17 b output by the latch LATCH4 may be input to the data signal generator 148A included in the queue selection signal generator 147A at a logic high.

[0195] Therefore, the logic gate G18 may perform a NAND calculation on the logic high queue selection signal QP17b and the logic high signal S21, and output a logic low signal S22. At the same time, the logic gate G19 may receive the logic low enable signal RPC16_EN and the logic high enable signal RPC17_EN, and perform an AND calculation to output a logic low signal S23. The logic gate G20 may receive the logic low signal S23 and the logic low queue selection signal QP16b, and output a logic high signal S24. The logic gate G21 may receive the logic low signal S22 and the logic high signal S24, and perform a NAND calculation to output a logic high data signal D1.

[0196] In this way, when the clock signal CLK1 is logic high and the data signal D1 input to the latch LATCH1 is "1" corresponding to logic high, the latch LATCH1 can receive the data signal D1 and output the data signal D2 corresponding to logic high after a predetermined period of time has passed, that is, the logic high queue selection signal QP16a. Thereafter, when the clock signal CLK1 is logic high and the data signal D2 input to the latch LATCH2 is "1" corresponding to logic high, the latch LATCH2 receives the data signal D2 and can output the data signal D3 corresponding to logic high after a predetermined period of time has passed, that is, the logic high queue selection signal QP16b.

[0197] In this way, when the memory cell row selection circuit 142P is turned off and the memory cell row selection circuit 142Q is turned on, as the logic high queue selection signal QP17b and the logic low queue selection signal QP16b are applied to the data signal generator 148A, the logic high queue selection signal QP16a and the queue selection signal QP16b can be output from the latch LATCH1 and the latch LATCH2, respectively. Accordingly, the row address of the memory cell row selected by the memory cell row selection circuit 142Q can also be stored in the queues Q16a and Q16b specifically assigned to the existing memory cell row selection circuit 142P.

[0198] refer to Fig.15 The queue selection signal generator 147B may include a latch LATCH3, a latch LATCH4, a data signal generator 148B and a clock signal generator 149B.

[0199] The latch LATCH3 may receive the clock signal CLK2, and output the input data signal D4 to the latch LATCH4 based on the clock signal CLK2. At this time, the data signal D5 output from the latch LATCH3 is a signal obtained by delaying the data signal D4 by a predetermined time, and may correspond to the queue selection signal QP17a. The latch LATCH4 may receive the clock signal CLK2, and output the data signal D6 obtained by delaying the input data signal D5 by a predetermined time period based on the clock signal CLK2. At this time, the data signal D6 is a signal obtained by delaying the data signal D5 by a predetermined time, and may correspond to the queue selection signal QP17b.

[0200] The clock signal generator 149B may include an inverter INV12 and logic gates G22, G23, and G24. When the memory cell row selection circuit 142P is turned off, the inverter INV12 of the clock signal generator 149B may invert the logic high enable signal RPC17_EN to output a logic low signal S25. The logic gate G22 may receive the logic low signal S25 and the logic low selection signal Pick16, and perform a NAND calculation to output a logic high signal S26.

[0201] Logic gate G23 may receive logic high enable signal RPC17_EN and logic high pick signal Pick17 and perform NAND calculation to output logic low signal S27. Logic gate G24 may receive logic high signal S26 and logic low signal S27 and perform NAND calculation to output logic high clock signal CLK2.

[0202] The data signal generator 148B may include inverters INV13 and INV14 and logic gates G25, G26, G27, G28, G29, and G30. The inverter INV13 may invert the logic high enable signal RPC17_EN to output a logic low signal S28. The inverter INV14 may invert the logic low enable signal RPC16_EN to output a logic high signal S29. The logic gate G25 may receive the logic high signal S29 and the logic high enable signal RPC17_EN, and perform an AND operation to output a logic high signal S30. The logic gate G26 may receive the logic high signal S30 and the logic low signal S28, and perform an OR operation to output a logic high signal S31.

[0203] The logic high signal S31 and the queue selection signal QP16b can be input to the logic gate G27. Fig.14As described, since the memory cell row selection circuit 142Q can additionally utilize queues Q16a and Q16b in addition to the existing specially allocated queues Q17a and Q17b, in order for the memory cell row selection circuit 142Q to use queues Q16a, Q16b, the queue selection signal QP17b input to the data signal generator 148B can be logic low, and the queue selection signal QP16b can be logic high.

[0204] Therefore, the logic gate G27 may perform a NAND calculation on the logic high queue selection signal QP16b and the logic high signal S31, and output a logic low signal S32. At the same time, the logic gate G28 may receive the logic low enable signal RPC16_EN and the logic high enable signal RPC17_EN, and perform an AND calculation to output a logic low signal S33. The logic gate G29 may receive the logic low signal S33 and the logic low queue selection signal QP17b, and output a logic high signal S34. The logic gate G30 may receive the logic low signal S32 and the logic high signal S34, and perform a NAND calculation to output a logic high data signal D4.

[0205] In this way, when the clock signal CLK2 is logic high and the data signal D4 input to the latch LATCH3 is "1" corresponding to logic high, the latch LATCH3 receives the data signal D4 and can output the data signal D5 corresponding to logic high after the predetermined time period has passed, that is, the logic high queue selection signal QP17a. Thereafter, when the clock signal CLK2 is logic high and the data signal D5 input to the latch LATCH4 is "1" corresponding to logic high, the latch LATCH4 can receive the data signal D5 and can output the data signal D6 corresponding to the logic high level after the predetermined time period has passed, that is, the logic high queue selection signal QP17b.

[0206] As a result, when the memory cell row selection circuit 142P is turned off and the memory cell row selection circuit 142Q is turned on, as the logic high queue selection signal QP16b and the logic low queue selection signal QP17b are applied to the data signal generator 148B, the logic high queue selection signal QP17a and the queue selection signal QP17b can be output from the latch LATCH3 and the latch LATCH4, respectively. As a result, in addition to the queues Q16a and Q16b additionally assigned to the memory cell row selection circuit 142P, the row address of the memory cell row selected by the memory cell row selection circuit 142Q can also be stored in the queues Q17a and Q17b exclusively assigned to the memory cell row selection circuit 142Q from the beginning.

[0207] Although referenced Figures 13 to 15The case where the memory cell row selection circuit 142P is turned off is described as an example, but the embodiment is not limited thereto. For example, according to the embodiment, when the enable signal RNG13_EN becomes a logic low state and the random number generator 141L is turned off, the memory cell row selection circuits 142P and 142Q also no longer operate, and the selection signals Pick16 and Pick17 may become logic low. At this time, if the row hammer control circuit 140E also includes another random number generator, the memory cell row selection circuit that receives the pseudo-random bit sequence signal from the random number generator may additionally store the row address of the memory cell row selected by itself in the queues Q16a, Q16b, Q17a, and Q17b.

[0208] Fig.16 is an exemplary diagram illustrating a structure of a stacked memory device according to some embodiments. Fig.17 It is shown Fig.16 An example diagram of a second semiconductor layer.

[0209] refer to Fig.16 and Fig.17 , the memory device 700 may include a plurality of semiconductor dies or semiconductor layers LA1 to LAk (where k is an integer of 3 or greater). The memory device 700 may correspond to Figure 1 The memory device 100 of the present invention. The semiconductor layer LA1 located at the bottom may be a master layer, and the remaining semiconductor layers LA2 to LAk may be slave layers.

[0210] The semiconductor layers LA1 to LAk transmit and receive signals through through-silicon vias (TSVs), and the main layer LA1 can communicate with an external memory controller 200 (eg, Figure 1 The configuration and operation of the semiconductor memory device 700 will be described below with the first semiconductor layer 710 as the master layer and the k-th semiconductor layer 720 as the slave layer as the center.

[0211] The first semiconductor layer 710 and the kth semiconductor layer 720 include various peripheral circuits 722 driving the memory region 721. For example, as shown in FIG. Figure 2 As described, the peripheral circuit 722 may include a row driver (X-driver) driving a word line of each memory region, a column driver (Y-driver) driving a bit line of each memory region, a data input / output unit controlling input and output of data, a command buffer receiving and buffering a command CMD received from outside the semiconductor memory device 700, and an address buffer 120 (such as a memory device 700) receiving and buffering an address received from outside the semiconductor device 700. Figure 2 shown).

[0212] The first semiconductor layer 710 may further include a control logic circuit 130 (eg, Figure 1 The control logic circuit can be based on the memory controller ( Figure 1 200) to control access to the memory area 721, and generate a control signal for accessing the memory area 721.

[0213] According to some embodiments, the second semiconductor layer 720 may include a plurality of memory cell regions. For example, the second semiconductor layer 720 may include four memory cell regions 721, and may include a bit line sense amplifier region (BLSA) 723 for reading data of each memory cell between the memory cell regions 721, a sub word line driver region (SWD) 722, a row decoder 724, and a column decoder 725.

[0214] Fig.18 is an example diagram for describing a memory module including a memory device according to some embodiments.

[0215] refer to Fig.18 According to some embodiments, the memory device 800 may be installed on the electronic device in the form of a memory module. At least one memory device 800 may be installed. The memory device 800 may correspond to Figure 1 A memory device 100 is provided.

[0216] The memory device 800 may include a plurality of volatile memories 811 to 818, a memory controller 820, and a plurality of memory input / output pins 830. The memory controller 820 may correspond to Figure 1 The memory device 800 may write data or output written data under the control of an external CPU.

[0217] When the memory device 800 includes DRAM, for example, the CPU can control the memory device 800 according to a communication protocol such as double data rate (DDR) and low power DDR (LPDDR). For example, the CPU sends a command and an address to the memory device 800 to read data stored in the memory device 800.

[0218] According to some embodiments, the plurality of volatile memories 811 to 818 may be, for example, at least one of a DRAM and an SDRAM. Each of the plurality of volatile memories 811 to 818 may perform communication of data DQ in response to a signal provided from the memory controller 820. According to some embodiments, the memory device 800 may further include a data buffer for data communication, and the data buffer may transmit and receive data DQ to and from the memory controller 820 in synchronization with the data strobe signal DQS.

[0219] According to some embodiments, for example, the memory controller 820 can communicate with multiple volatile memories 811 to 818 according to one of the standards of memory modules (such as Dual In-line Memory Module (DIMM), Registered DIMM (RDIMM), Load Reduced DIMM (LRDIMM) and Unregistered Dual In-Line Memory Module (UDIMM)).

[0220] According to some embodiments, the memory controller 820 may receive a command / address signal CA and a clock signal CLK of the memory device 800 through a memory input / output pin 830 and provide the received signals to the plurality of volatile memory devices 811 to 818 .

[0221] Fig.19 is an example diagram illustrating an electronic system including a memory device according to some embodiments.

[0222] refer to Fig.19 For example, the electronic system 2000 according to some embodiments may be a mobile system such as a mobile phone, a smart phone, a tablet PC (tablet personal computer), a wearable device, a healthcare device, or an Internet of Things (IoT) device. However, Fig.19 The electronic system 2000 is not limited to a mobile system. For example, according to an embodiment, the electronic system 2000 may also be a personal computer, a laptop computer, a server, a media player, or an automotive device (such as a navigation device).

[0223] The electronic system 2000 may include a main processor 2100, memories 2200a and 2200b, and storage devices 2300a and 2300b, and may further include one or more of an image capture device 2410, a user input device 2420, a sensor 2430, a communication device 2440, a display 2450, a speaker 2460, a power supply device 2470, and a connection interface 2480.

[0224] In the following, at least one of the memories 2200a and 2200b is assumed to be based on reference Figures 1 to 18 At least one of the memory devices of some embodiments described.

[0225] The main processor 2100 may control the overall operation of the electronic system 2000, for example, operations of other components forming the electronic system 2000. Such a main processor 2100 may be implemented as, for example, a general-purpose processor, a dedicated processor, an application processor, and the like.

[0226] The main processor 2100 may include one or more CPU cores 2110, and may also include a controller 2120 that controls memories 2200a and 2200b and / or storage devices 2300a and 2300b. According to an embodiment, the main processor 2100 may also include an accelerator 2130, which is a dedicated circuit for high-speed data calculations such as artificial intelligence (AI) data calculations. Such an accelerator 2130 may include, for example, a graphics processing unit (GPU), a neural processing unit (NPU), and / or a data processing unit (DPU), etc., and may be implemented as a separate chip physically independent of other components of the main processor 2100.

[0227] The memories 2200a and 2200b may be used as the main memory unit of the electronic system 2000, and may include, for example, volatile memory such as SRAM and / or DRAM, but may also include, for example, non-volatile memory such as flash memory, PRAM and / or RRAM. The memories 2200a and 2200b may also be implemented in the same package as the main processor 2100.

[0228] The storage devices 2300a and 2300b may be used as non-volatile storage devices for storing data regardless of whether power is supplied, and may have a relatively larger capacity than the memories 2200a and 2200b. The storage devices 2300a and 2300b may include storage controllers 2310a and 2310b, and non-volatile memories (NVM) 2320a and 2320b that store data under the control of the storage controllers 2310a and 2310b. The non-volatile memories 2320a and 2320b may include flash memories of a 2-dimensional (2D) structure or a 3-dimensional (3D) vertical NAND (Vertical NAND, V-NAND) structure, but may also include other types of non-volatile memories, such as PRAM and / or RRAM, for example.

[0229] The storage devices 2300a and 2300b may be included in the electronic system 2000 in a state of being physically separated from the main processor 2100, and may be implemented in the same package as the main processor 2100. In addition, since the storage devices 2300a and 2300b may be, for example, solid state devices (SSDs) or memory cards, the storage devices 2300a and 2300b may also be detachably coupled to other components of the electronic system 2000 through an interface (such as the connection interface 2480 described below). Such storage devices 2300a and 2300b may be, but are not necessarily limited to, devices that follow standard protocols, such as universal flash storage (UFS), embedded multi-media card (eMMC), or high-speed non-volatile memory express (NVMe) protocols.

[0230] The image capturing device 2410 may capture still images or moving images and may be, for example, a camera, a camcorder, and / or a webcam, etc.

[0231] The user input device 2420 may receive various types of data input from a user of the electronic system 2000 , and may be, for example, a touch pad, a keypad, a keyboard, a mouse, and / or a microphone.

[0232] The sensor 2430 may detect various types of physical quantities that may be acquired from outside the electronic system 2000, and convert the detected physical quantities into electrical signals. Such a sensor 2430 may be, for example, a temperature sensor, a pressure sensor, an illumination sensor, a position sensor, an acceleration sensor, a biosensor, and / or a gyro sensor.

[0233] The communication device 2440 may transmit and receive signals to and from other devices outside the electronic system 2000 according to various communication protocols. Such a communication device 2440 may be implemented to include, for example, an antenna, a transceiver, and / or a modem.

[0234] The display 2450 and the speaker 2460 may each be used as an output device for outputting visual information and auditory information to a user of the electronic system 2000 .

[0235] The power supply device 2470 may appropriately convert power supplied from a battery equipped in the electronic system 2000 and / or an external power source, and supply the power to each constituent element of the electronic system 2000 .

[0236] The connection interface 2480 may provide a connection between the electronic system 2000 and an external device that may be connected to the electronic system 2000 to send and receive data to and from the electronic system 2000. The connection interface 2480 may be implemented, for example, by various interface types, such as Advanced Technology Attachment (ATA), Serial ATA (SATA), external SATA (e-SATA), Small Computer Small Interface (SCSI), Serial Attached SCSI (SAS), Peripheral Component Interconnection (PCI), PCI express (PCIe), NVMe, IEEE 1394, Universal Serial Bus (USB), secure digital (SD) card, Multi-Media Card (MMC), eMMC, UFS, embedded Universal Flash Storage (eUFS), and Compact Flash (CF) card interfaces.

[0237] As is conventional in the field of the present disclosure, embodiments are described and illustrated in the accompanying drawings according to functional blocks, units and / or modules. It will be appreciated by those skilled in the art that these blocks, units and / or modules are physically implemented by electronic (or optical) circuits (such as logic circuits, discrete components, microprocessors, hard-wired circuits, memory elements, wiring connections, etc.) that can be formed using semiconductor-based manufacturing techniques or other manufacturing techniques. In the case where these blocks, units and / or modules are implemented by microprocessors, etc., they can be programmed to perform various functions discussed herein using software (e.g., microcode), and can be optionally driven by firmware and / or software. Alternatively, each block, unit and / or module can be implemented by dedicated hardware, or implemented as a combination of dedicated hardware to perform some functions and processors (e.g., one or more programmed microprocessors and associated circuits) to perform other functions.

[0238] While the present disclosure has been particularly shown and described with reference to embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the present disclosure as defined by the appended claims.

Claims

1. A memory device, comprising: a memory cell array comprising a plurality of memory cell rows; A first random number generator configured to generate an n-bit first pseudo-random bit sequence signal based on a first seed and a first degree; a first memory cell row selection circuit configured to randomly select a first memory cell row from among the plurality of memory cell rows in a first cycle in response to specific m bits among the received n-bit first pseudo-random bit sequence signals matching each other, and store a row address of the selected first memory cell row in a first queue; a second memory cell row selection circuit configured to randomly select a second memory cell row from among the plurality of memory cell rows in a second cycle different from the first cycle in response to specific k bits among the received n-bit first pseudo-random bit sequence signals matching each other, and store a row address of the selected second memory cell row in a second queue different from the first queue; as well as a refresh control circuit configured to perform a refresh operation on a memory cell row physically adjacent to a memory cell row corresponding to each of the row addresses stored in the first queue and the second queue, Here, each of n, m and k is an integer of 2 or more, and n, m and k are different from each other.

2. The memory device according to claim 1, further comprising: A second random number generator configured to generate a j-bit second pseudo-random bit sequence signal based on a second seed and a second degree; as well as a third memory cell row selection circuit configured to randomly select a third memory cell row from among the plurality of memory cell rows in a third cycle different from the first cycle and the second cycle in response to specific p bits among the received j-bit second pseudo-random bit sequence signals matching each other, and store a row address of the selected third memory cell row in a third queue different from the first queue and the second queue, wherein the refresh control circuit is configured to perform a refresh operation on a memory cell row physically adjacent to a memory cell row corresponding to a row address stored in the third queue, The first seed and the second seed are different from each other, or the first degree and the second degree are different from each other, and Each of j and p is an integer of 2 or more, and j and p are different from each other.

3. The memory device according to claim 2, in, In response to the first random number generator being powered off, The third memory cell row selection circuit stores the row address of the selected third memory cell row in the first queue and the second queue.

4. The memory device according to claim 2, in, In response to the second random number generator being powered off, The first memory cell row selection circuit or the second memory cell row selection circuit stores the row address of the selected first memory cell row or the selected second memory cell row in the third queue.

5. The memory device according to claim 1, in, The first period is longer than the second period, The first memory cell row selection circuit is configured to output a first selection signal of logic high when the first memory cell row is randomly selected from among the plurality of memory cell rows, The first selection signal is input to a first flag signal generating circuit, Wherein, the first flag signal generating circuit comprises: a first inverter configured to invert the first selection signal and output a first signal; a first logic gate configured to perform a NAND calculation on the first signal and a second signal of the first node and output a third signal; a second logic gate configured to perform the NAND calculation on the first enable signal and the third signal and output the second signal; and a second inverter configured to invert the second signal and output a first flag signal, In response to the first selection signal being logic high, the first enable signal has a logic high level.

6. The memory device according to claim 5, in, The second memory cell row selection circuit is configured to output a second selection signal of logic high when the second memory cell row is randomly selected from among the plurality of memory cell rows, The second selection signal and the first flag signal are input to a second flag signal generating circuit. Wherein, the second flag signal generating circuit comprises: a third inverter, configured to invert the first flag signal and output a fourth signal; a third logic gate configured to perform the NAND calculation on the fourth signal and the second selected signal and output a fifth signal; a fourth logic gate configured to perform the NAND calculation on the fifth signal and the sixth signal of the second node and output a seventh signal; a fifth logic gate configured to perform the NAND calculation on the second enable signal and the seventh signal and output the sixth signal; and a fourth inverter configured to invert the sixth signal and output a second flag signal, In response to the first flag signal being logic high, the second enable signal has a logic low level, and In response to the first flag signal being logic low and the second selection signal being logic high, the second enable signal has a logic high level.

7. The memory device according to claim 1, in, In response to the number of m bits that match each other among the n-bit first pseudo-random bit sequence signal being greater than the number of k bits that match each other among the n-bit first pseudo-random bit sequence signal, The refresh control circuit performs the refresh operation on the memory cell row that is physically adjacent to the memory cell row corresponding to the row address stored in the first queue in priority to the refresh operation on the memory cell row that is physically adjacent to the memory cell row corresponding to the row address stored in the second queue.

8. The memory device according to claim 1, in, In response to the first period being longer than the second period, The refresh control circuit performs the refresh operation on the memory cell row that is physically adjacent to the memory cell row corresponding to the row address stored in the first queue in priority to the refresh operation on the memory cell row that is physically adjacent to the memory cell row corresponding to the row address stored in the second queue.

9. The memory device of claim 1 , further comprising: A queue selection circuit is configured to receive the n-bit first pseudo-random bit sequence signal from the first random number generator; as well as a multiplexer configured to receive a signal including a first bit among the n-bit first pseudo-random bit sequence signals from the queue selection circuit, The multiplexer outputs a first flag signal corresponding to the first queue or a second flag signal corresponding to the second queue in response to receiving the signal including the first bit.

10. The memory device according to claim 9, in, In response to the multiplexer outputting the first flag signal, The refresh control circuit performs the refresh operation on the memory cell row that is physically adjacent to the memory cell row corresponding to the row address stored in the first queue in priority to the refresh operation on the memory cell row that is physically adjacent to the memory cell row corresponding to the row address stored in the second queue.

11. The memory device of claim 1 , further comprising: a counter configured to output a count signal including a first bit; as well as a multiplexer configured to receive the count signal, The multiplexer outputs a first flag signal corresponding to the first queue or a second flag signal corresponding to the second queue in response to receiving the counting signal.

12. The memory device according to claim 11, in, In response to the multiplexer outputting the first flag signal, The refresh control circuit performs the refresh operation on the memory cell row that is physically adjacent to the memory cell row corresponding to the row address stored in the first queue in priority to the refresh operation on the memory cell row that is physically adjacent to the memory cell row corresponding to the row address stored in the second queue.

13. A memory system comprising: a memory controller configured to generate a row hammer refresh command based on a command received from a host; a memory cell array comprising a plurality of memory cell rows; a row hammer control circuit configured to receive the row hammer refresh command and, in response to the received row hammer refresh command, output a row hammer address corresponding to at least one memory cell row among the plurality of memory cell rows that is subjected to row hammering during a row hammer monitoring time interval; a refresh control circuit configured to perform a refresh operation on a memory cell row physically adjacent to a memory cell row corresponding to the row hammering address based on the received row hammering address, Wherein, the row hammer control circuit comprises: A first random number generator configured to generate an n-bit first pseudo-random bit sequence signal based on a first seed and a first degree; a first memory cell row selection circuit configured to randomly select a first memory cell row from among the plurality of memory cell rows in a first cycle in response to specific m bits among the received n-bit first pseudo-random bit sequence signals matching each other, and store a row address of the selected first memory cell row in a first queue; A second random number generator configured to generate a k-bit second pseudo-random bit sequence signal based on a second seed and a second degree; and a second memory cell row selection circuit configured to randomly select a second memory cell row from among the plurality of memory cell rows in a second cycle different from the first cycle in response to specific j bits among the received k-bit second pseudo-random bit sequence signals matching each other, and store a row address of the selected second memory cell row in a second queue different from the first queue, wherein the row hammer control circuit provides the row addresses stored in the first queue and the second queue as the row hammer addresses to the refresh control circuit, The first seed and the second seed are different from each other, or the first degree and the second degree are different from each other, and Each of n, m, k, and j is an integer of 2 or greater.

14. The memory system of claim 13, further comprising: a third memory cell row selection circuit configured to randomly select a third memory cell row from among the plurality of memory cell rows in a third cycle different from the first cycle and the second cycle in response to specific p bits among the received n-bit first pseudo-random bit sequence signals matching each other, and store the row address of the selected third memory cell row in a third queue different from the first queue and the second queue, Here, p is an integer of 2 or more, and p is different from m.

15. The memory system according to claim 14, in, In response to the first period being longer than the second period and the second period being longer than the third period, The refresh control circuit: performing the refresh operation on a row of memory cells that is physically adjacent to the row of memory cells that corresponds to the row address stored in the first queue in preference to the refresh operation on a row of memory cells that is physically adjacent to the row of memory cells that corresponds to the row address stored in the second queue, and The refresh operation is performed on the memory cell row physically adjacent to the memory cell row corresponding to the row address stored in the second queue in preference to the refresh operation on the memory cell row physically adjacent to the memory cell row corresponding to the row address stored in the third queue.

16. The memory system according to claim 13, in, In response to the first memory cell row selection circuit being powered off, The second memory cell row selection circuit stores the row address of the selected second memory cell row in the first queue.

17. The memory system according to claim 13, in, In response to the first random number generator being powered off, The second memory cell row selection circuit stores the row address of the selected second memory cell row in the first queue.

18. A method of operating a memory device, the memory device comprising a memory cell array including a plurality of memory cell rows, a first random number generator configured to generate an n-bit first pseudo-random bit sequence signal, a first memory cell row selection circuit and a second memory cell row selection circuit configured to randomly select at least one memory cell row from the plurality of memory cell rows based on the n-bit first pseudo-random bit sequence signal, and a refresh control circuit configured to perform a refresh operation on a memory cell row physically adjacent to the memory cell row selected by the first memory cell row selection circuit and the second memory cell row selection circuit, the method comprising: The first random number generator generates the n-bit first pseudo-random bit sequence signal based on a first seed and a first degree; The first memory cell row selection circuit randomly selects a memory cell row from among the plurality of memory cell rows in a first cycle in response to specific m bits of the received n-bit first pseudo-random bit sequence signal matching each other; The first memory cell row selection circuit stores the row address of the selected memory cell row in a first queue; The second memory cell row selection circuit randomly selects a memory cell row from among the plurality of memory cell rows in a second cycle different from the first cycle in response to specific k bits of the received n-bit first pseudo-random bit sequence signal matching each other; storing, by the second memory cell row selection circuit, the row address of the selected memory cell row in a second queue different from the first queue; as well as performing a refresh operation by the refresh control circuit on a memory cell row physically adjacent to the memory cell row corresponding to each row address stored in the first queue and the second queue, Here, each of n, m, and k is an integer of 2 or more, and n, m, and k are different from each other.

19. The method of operating the memory device according to claim 18, in, Performing the refresh operation on the memory cell row physically adjacent to the memory cell row corresponding to each of the row addresses stored in the first queue and the second queue by the refresh control circuit includes: When no row address is stored in the first queue, the refresh control circuit performs the refresh operation on the memory cell row physically adjacent to the memory cell row corresponding to the row address stored in the second queue in response to no row address being stored in the first queue and the first cycle being longer than the second cycle.

20. The method of operating the memory device according to claim 18, further comprising: The row address of the selected memory cell row is stored in the first queue by the second memory cell row selection circuit in response to an enable signal not being applied to the first memory cell row selection circuit.

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