Method, system and device for testing NAND FLASH reading function and host

Abstract

The invention discloses a method, a system and a device for testing a reading function of an NAND FLASH and a host, and the method comprises the following steps: the NAND FLASH sends read data of each port to a local parity check module according to a reading function test instruction; controlling the parity check module to generate read data to be verified according to the read data of each port; sending the to-be-verified read data to the test equipment through any port; receiving a test result fed back by the test equipment; the test result comprises a comparison result of the to-be-verified read data and preset verification data; and determining that the reading function of each port is normal and / or abnormal according to the test result. The method comprises the following steps: integrating read data of each port through a parity check module to obtain read data to be verified; the to-be-verified read data can be sent to the test equipment through any port, so that the test is completed; and the reading function test of each port is completed through any port, so that the test efficiency is improved.

Description

Technical Field

[0001] The present invention relates to the field of electronic storage technology, and in particular to a NAND FLASH reading function testing method, system, device and host. Background Art

[0002] With the rapid development of electronic devices, electronic devices have higher and higher requirements for memory read speed and reliability. SPI NAND Flash (Serial Peripheral Interface NAND Flash) is a non-volatile memory that is widely used due to its small size, low power consumption, fast read and write speed, etc. SPI NAND Flash has multiple ports for read operations. Therefore, in the production process of SPI NAND Flash, it is necessary to test the read function of all ports of SPI NAND Flash.

[0003] However, the existing SPI NAND Flash test method can only perform a read test through a single port, so that the SPI NAND Flash cannot implement a multi-port parallel read test, resulting in a problem of low efficiency in the SPI NAND Flash read test.

[0004] Therefore, there is still an urgent need for a method that can improve the efficiency of SPI NAND Flash read testing. Summary of the invention

[0005] The main purpose of the present invention is to provide a NAND FLASH read function test method, system, device and host to solve the problem that the existing defective SPI NAND Flash cannot realize multi-port parallel read test and the read test efficiency is low.

[0006] To achieve the above object, the present invention provides a method for testing a NAND FLASH read function, the method comprising:

[0007] NAND FLASH sends the read data of each port to the local parity check module according to the read function test instruction;

[0008] Controlling the parity check module to generate read data to be verified according to the read data of each port;

[0009] Sending the read data to be verified to a test device via any port, wherein the test device is a device for detecting a NAND FLASH read function;

[0010] Receiving the test result fed back by the test device; the test result includes the comparison result of the read data to be verified and the preset verification data;

[0011] It is determined according to the test results whether the reading function of each port is normal and / or abnormal.

[0012] In some embodiments, the controlling the parity check module to generate the read data to be verified according to the read data of each port includes:

[0013] Control the parity check module to add parity check data to the read data of each port to obtain the parity check read data of each port;

[0014] The to-be-verified read data is generated according to the parity check read data of each of the ports.

[0015] In some embodiments, the receiving the test result fed back by the test device includes:

[0016] The comparison result fed back by the test device is received; the comparison result is obtained by the test device splitting the read data to be verified into parity check read data of each port, and comparing the parity check read data of each port with the preset check data respectively.

[0017] In some embodiments, determining whether the reading function of each port is normal and / or abnormal according to the test result includes:

[0018] If the parity check read data of the port is consistent with the preset check data, it is determined that the reading function of the port is normal; and / or,

[0019] If the parity check read data of the port is inconsistent with the preset check data, it is determined that the reading function of the port is abnormal.

[0020] In some embodiments, the controlling the parity check module to add parity check data to the read data of each port, and after obtaining the parity check read data of each port, further comprises:

[0021] Performing cyclic redundancy check calculation on the parity check read data of each port to obtain a calculation result of each port;

[0022] The read data to be verified is generated according to the parity check read data of each port and the calculation result of each port.

[0023] In some embodiments, the preset check data includes preset parity check data and preset redundant check data; and the receiving of the test result fed back by the test device includes:

[0024] Receive the comparison result fed back by the test device; the comparison result is obtained by the test device splitting the read data to be verified into parity check read data of each port and calculation results of each port, and comparing the parity check read data of each port with the preset parity check data, and comparing the calculation results of each port with the preset redundant check data.

[0025] The present invention also proposes a test system for a NAND FLASH read function, the test system for the NAND FLASH read function comprising a NAND FLASH and a test device; the NAND FLASH comprising a plurality of ports, a parity check module and a storage module; the parity check module is connected to the plurality of ports and the storage module; the NAND FLASH communicates with the test device using any of the ports; the test system for the NAND FLASH read function can execute any of the above-mentioned test methods for the NAND FLASH read function.

[0026] In some embodiments, the NAND FLASH further includes a cyclic redundancy check module; the cyclic redundancy check module is connected to the parity check module.

[0027] The present invention also provides a NAND FLASH reading function test device, comprising:

[0028] at least one processor; and,

[0029] a memory communicatively connected to the at least one processor; wherein,

[0030] The memory stores instructions executed by the at least one processor, and the instructions are executed by the at least one processor so that the at least one processor can execute any one of the above-mentioned NAND FLASH reading function testing methods.

[0031] The present invention also provides a NAND FLASH reading function test host, the NAND FLASH reading function test host comprising a test host body and a plurality of NAND FLASH reading function test systems as described in any one of the above; a plurality of the test devices are installed on the test host body.

[0032] The present invention arranges a parity check module inside the NAND FLASH, and the parity check module is connected to each port of the NAND FLASH; when the NAND FLASH is read and tested, the read data of each port can be first sent to the parity check module, the parity check module integrates the read data of each port to obtain the read data to be verified, and then any port sends the read data to be verified to the test equipment, thereby completing the test; the test equipment can perform a read test on all ports of the NAND FLASH through any port of the NAND FLASH, thereby improving the read test efficiency of the NAND FLASH. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Figure 1 It is a flow chart of a method for testing the NAND FLASH reading function of the present invention;

[0034] Figure 2 Another schematic diagram of the flow chart of the method for testing the NAND FLASH reading function of the present invention;

[0035] Figure 3 Another schematic diagram of the flow chart of the method for testing the NAND FLASH reading function of the present invention;

[0036] Figure 4 It is a structural schematic diagram of a test system for NAND FLASH reading function of the present invention;

[0037] Figure 5 Another structural schematic diagram of the test system for the NAND FLASH reading function of the present invention;

[0038] Figure 6 It is a schematic diagram of the structure of a test device for NAND FLASH reading function according to an embodiment of the present invention.

[0039] The realization of the purpose, functional features and advantages of the present invention will be further explained in conjunction with embodiments and with reference to the accompanying drawings. DETAILED DESCRIPTION

[0040] The scheme in the embodiment of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiment of the present invention. Obviously, the described embodiment is only a part of the embodiment of the present invention, not all of the embodiments. Based on the embodiment of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0041] It should be noted that all directional indications in the embodiments of the present invention (such as up, down, left, right, front, back, etc.) are only used to explain the relative position relationship, movement status, etc. between the components under a certain specific posture (as shown in the accompanying drawings). If the specific posture changes, the directional indication will also change accordingly.

[0042] It should also be noted that when an element is referred to as being "fixed on" or "disposed on" another element, it may be directly on the other element or there may be an intermediate element at the same time. When an element is referred to as being "connected to" another element, it may be directly connected to the other element or there may be an intermediate element at the same time.

[0043] In addition, the descriptions of "first", "second", etc. in the present invention are only used for descriptive purposes and cannot be understood as indicating or implying their relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include at least one of the features. In addition, the technical solutions between the various embodiments can be combined with each other, but they must be based on the ability of ordinary technicians in the field to implement them. When the combination of technical solutions is contradictory or cannot be implemented, it should be deemed that such a combination of technical solutions does not exist and is not within the scope of protection required by the present invention.

[0044] To achieve the above object, the present invention provides a method for testing a NAND FLASH read function, the method comprising:

[0045] Step S110, NAND FLASH sends the read data of each port to the local parity check module according to the read function test instruction;

[0046] Step S120, controlling the parity check module to generate read data to be verified according to the read data of each port;

[0047] Step S130, sending the read data to be verified to a test device via any port, wherein the test device is a device for detecting a NAND FLASH read function;

[0048] Step S140, receiving the test result fed back by the test equipment; the test result includes the comparison result of the read data to be verified and the preset verification data;

[0049] Step S150: determining whether the reading function of each port is normal and / or abnormal according to the test result.

[0050] In some embodiments, reference Figure 1 and Figure 4, the NAND FLASH read function test method is applied to the NAND FLASH read function test system; wherein, NAND FLASH refers to SPI NAND Flash. The NAND FLASH read function test system may include NAND FLASH and a test device; wherein, the test device is a device for detecting the NAND FLASH read function. NAND FLASH includes multiple ports, a parity check module and a storage module, wherein, Figure 4 IO0 to IOn represent multiple ports.

[0051] It can be understood that, in this embodiment, NAND FLASH sends the read data to be verified to the test equipment via any port, wherein any port is taken as IO0 for illustration.

[0052] First, connect any port of the NAND FLASH's multiple ports to a test device, wherein the test device is a device for detecting the NAND FLASH read function. When the test device needs to detect the read function of each port of the NAND FLASH, it will send a read function test instruction to the NAND FLASH.

[0053] NAND FLASH will control the storage module to send the read data of each port to the local parity check module according to the read function test instruction; wherein the local parity check module refers to the parity check module set inside NAND FLASH.

[0054] It can be understood that, in this embodiment, the ports in the multi-ports of the NAND FLASH refer to ports provided on the surface of the NAND FLASH for connecting to external devices, wherein the external devices include test equipment, computers, and the like.

[0055] The storage module may be provided with multiple read interfaces; the read interfaces are used to directly read the data stored in the storage module. When the port is directly connected to the read interface, the port can directly read data from the storage module through the read interface. In this embodiment, each read interface on the storage module is not directly connected to each port; each read interface on the storage module is indirectly connected to each port through a parity check module. The read data of each port refers to the read data obtained by each port from the corresponding read interface on the storage module.

[0056] The NAND FLASH control parity check module performs parity check on the read data of each port and integrates the read data of each port to obtain the read data to be verified. When the read data of each port needs to be output through a single port, the read data of each port needs to be integrated together. After the read data of each port is integrated, it can be output through any port.

[0057] NAND FLASH sends the read data to be verified to the test equipment through any port. The test equipment will compare the read data to be verified with the preset verification data, obtain the comparison results of the read functions of each port, and obtain the test results based on the comparison results of the read functions of each port. The test equipment will also send the test results back to NAND FLASH.

[0058] NAND FLASH will receive the test results fed back by the test equipment; the test results are the comparison results between the read data to be verified and the preset verification data.

[0059] NAND FLASH determines whether the read function of each port is normal and / or abnormal based on the test results. Three situations may occur. For example, the first situation: the read function of all ports is normal. The second situation: the read function of all ports is abnormal. The third situation: the read function of some ports is normal and the read function of some ports is abnormal.

[0060] In this embodiment, a parity check module is set inside the NAND FLASH, and the parity check module is connected to each port of the NAND FLASH; when the NAND FLASH is read and tested, the read data of each port can be sent to the parity check module first, and the parity check module integrates the read data of each port to obtain the read data to be verified, and then any port sends the read data to be verified to the test equipment, thereby completing the test; the test equipment can perform a read test on all ports of the NAND FLASH through any port of the NAND FLASH, thereby improving the read test efficiency of the NAND FLASH.

[0061] In some embodiments, the control parity check module generates the read data to be verified according to the read data of each port, including:

[0062] Step S160, controlling the parity check module to add parity check data to the read data of each port to obtain the parity check read data of each port;

[0063] Step S161 , generating read data to be verified according to the parity check read data of each port.

[0064] In this embodiment, refer to Figure 2When NAND FLASH executes step S120, it will control the parity check module to perform parity check on the read data. NAND FLASH controls the parity check module to add corresponding parity check data to the read data of each port, so that the read data of each port is accompanied by corresponding parity check data, thereby obtaining the parity check read data of each port. By checking the parity check data, the integrity and accuracy of the read data can be judged. NAND FLASH will also integrate the parity check read data of each port to obtain the read data to be verified. Among them, the read data to be verified is a collection of the parity check read data of each port; if the read data to be verified is split, the parity check read data of each port can be obtained.

[0065] In some embodiments, the aforementioned receiving the test result fed back by the test device includes:

[0066] Receive the comparison result fed back by the test equipment; the comparison result is obtained by the test equipment splitting the read data to be verified into the parity check read data of each port, and comparing the parity check read data of each port with the preset check data respectively.

[0067] In this embodiment, the test result received by NAND FLASH is the comparison result of the parity check read data of each port and the preset check data. The comparison result is obtained by the test equipment. The test equipment first splits the read data to be verified into the parity check read data of each port, and then compares the parity check read data of each port with the preset check data respectively to obtain the comparison result of the parity check read data of each port.

[0068] In some embodiments, determining whether the reading function of each port is normal and / or abnormal according to the test results in the foregoing includes:

[0069] If the parity check read data of the port is consistent with the preset check data, it is determined that the reading function of the port is normal; and / or,

[0070] If the parity check read data of the port is inconsistent with the preset check data, it is determined that the reading function of the port is abnormal.

[0071] In this embodiment, after NAND FLASH receives the test results, it can determine whether the reading function of each port is normal and / or abnormal based on the test results. In the test results, there may be three situations. For example, the first one: the parity check read data of all ports is consistent with the preset check data; at this time, it can be determined that the reading function of all ports is normal. The second one: the parity check read data of all ports is inconsistent with the preset check data; at this time, it can be determined that the reading function of all ports is abnormal. The third one: the parity check read data of some ports is consistent with the preset check data, and the parity check read data of another part of the ports is inconsistent with the preset check data; at this time, it can be determined that the reading function of the port whose parity check read data is consistent with the preset check data is normal, and the reading function of the port whose parity check read data is inconsistent with the preset check data is abnormal.

[0072] In some embodiments, after the control parity check module adds parity check data to the read data of each port to obtain the parity check read data of each port, the method further includes:

[0073] Step S170, performing cyclic redundancy check calculation on the parity check read data of each port to obtain the calculation result of each port;

[0074] Step S171 , generating read data to be verified according to the parity check read data of each port and the calculation result of each port.

[0075] In this embodiment, refer to Figure 3 and Figure 5 , NAND FLASH can also include a cyclic redundancy check module, which is connected to the parity check module. After the parity check module adds parity check data to the read data of each port to obtain the parity check read data of each port; the parity check module also sends the parity check read data of each port to the cyclic redundancy check module. Let the cyclic redundancy check module perform cyclic redundancy check calculations on the parity check read data of each port, so as to obtain the calculation results of each port. Each parity check read data corresponds to a calculation result. By integrating the parity check read data of each port and its corresponding calculation results, the read data to be verified can be obtained.

[0076] In some embodiments, the preset check data includes preset parity check data and preset redundant check data; the test result fed back by the test device in the above-mentioned receiving includes:

[0077] Receive the comparison result fed back by the test equipment; the comparison result is obtained by the test equipment splitting the read data to be verified into the parity check read data of each port and the calculation result of each port, and comparing the parity check read data of each port with the preset parity check data, and comparing the calculation result of each port with the preset redundant check data.

[0078] In this embodiment, the preset verification data includes preset parity check data and preset redundant check data. At this time, the comparison result includes the comparison results of two types of data. The test equipment first splits the read data to be verified into the parity check read data of each port and the calculation result of each port; then the parity check read data of each port is compared with the preset parity check data respectively to obtain the comparison result of the parity check data of each port, and the calculation result of each port is compared with the preset redundant check data to obtain the comparison result of the redundant check data of each port. The comparison results of these two types of data are integrated to obtain the comparison result. The test equipment feeds back the comparison result to NAND FLASH. NAND FLASH receives the comparison result fed back by the test equipment.

[0079] In this embodiment, the NAND FLASH needs to determine that the parity check read data of the port is consistent with the preset check data and the calculation result of the port is consistent with the preset redundancy check data, so as to determine that the reading function of the port is normal.

[0080] The present invention arranges a parity check module inside the NAND FLASH, and the parity check module is connected to each port of the NAND FLASH; when the NAND FLASH is read and tested, the read data of each port can be first sent to the parity check module, the parity check module integrates the read data of each port to obtain the read data to be verified, and then any port sends the read data to be verified to the test equipment, thereby completing the test; the test equipment can perform a read test on all ports of the NAND FLASH through any port of the NAND FLASH, thereby improving the read test efficiency of the NAND FLASH.

[0081] The present invention also proposes a test system for NAND FLASH reading function, the test system for NAND FLASH reading function comprises NAND FLASH and a test device; the NAND FLASH comprises multiple ports, a parity check module and a storage module; the parity check module is connected to the multiple ports and the storage module; the NAND FLASH uses any port to communicate with the test device; the test system for NAND FLASH reading function can execute any of the above-mentioned test methods for NAND FLASH reading function.

[0082] In this embodiment, see Figure 4The NAND FLASH read function test system includes NAND FLASH and a test device. The test device is a device for detecting the NAND FLASH read function. The NAND FLASH includes multiple ports, a parity check module and a storage module. Figure 4 IO0 to IOn represent multiple ports; IO0 is connected to the test equipment for illustration. The parity check module is connected to multiple ports and the storage module; and the NAND FLASH communicates with the test equipment via IO0.

[0083] In some embodiments, the NAND FLASH further includes a cyclic redundancy check module; the cyclic redundancy check module is connected to the parity check module.

[0084] In this embodiment, see Figure 5 , NAND FLASH may also include a cyclic redundancy check module; the cyclic redundancy check module is connected to the parity check module; the cyclic redundancy check module may perform a secondary check on the data checked by the parity check module.

[0085] The present invention also provides a NAND FLASH reading function test device, see Figure 6 , Figure 6 It is a structural schematic diagram of a test device for NAND FLASH reading function in a hardware operating environment involved in an embodiment of the present invention.

[0086] The NAND FLASH read function test device of the embodiment of the present invention may be a processor capable of executing the NAND FLASH read function test method; there is at least one processor. Figure 6 As shown, the test device for the NAND FLASH reading function may include: a processor 1001 (e.g., a CPU), a network interface 1004, a user interface 1003, a memory 1005, and a communication bus 1002. Among them, the communication bus 1002 is used to realize the connection and communication between these components. The user interface 1003 may include a display screen (Display), an input unit, such as a keyboard (Keyboard), and the optional user interface 1003 may also include a standard wired interface and a wireless interface. The network interface 1004 may optionally include a standard wired interface and a wireless interface (such as a WI-FI interface). The memory 1005 may be a high-speed RAM memory, or a stable memory (non-volatile memory), such as a disk memory. The memory 1005 may optionally be a storage device independent of the aforementioned processor 1001.

[0087] Those skilled in the art will understand that Figure 6The structure of the test device for the NAND FLASH read function shown in the figure does not constitute a limitation on the test device for the NAND FLASH read function, and may include more or less components than those shown in the figure, or combine certain components, or arrange the components differently.

[0088] like Figure 6 As shown, the memory 1005 as a computer storage medium may include an operating system, a network communication module, a user interface module and a computer program.

[0089] exist Figure 6 In the test device for the NAND FLASH reading function shown, the network interface 1004 is mainly used to connect to the background server and communicate data with the background server; the user interface 1003 is mainly used to connect to the client (user end) and communicate data with the client; and the processor 1001 can be used to call the computer program stored in the memory 1005. When the computer program is called and executed by the processor 1001, the steps of the test method for the NAND FLASH reading function described above are implemented.

[0090] The present invention also provides a NAND FLASH reading function test host, which includes a test host body and a plurality of NAND FLASH reading function test systems as described above; and a plurality of test devices are installed on the test host body.

[0091] In this embodiment, the NAND FLASH read function test host includes a test host body and multiple NAND FLASH read function test systems. Multiple test devices are installed on the test host body. The NAND FLASH read function test host can test the read function of multiple NAND FLASHs at the same time, thereby improving the test efficiency.

[0092] Based on the computer program proposed in the above embodiment, the present invention further proposes a storage medium, which stores the computer program. When the computer program is executed by a controller, the test method of the NAND FLASH reading function recorded in the above embodiment is implemented.

[0093] The present invention further provides a storage medium having a computer program stored thereon. When the computer program is executed by a processor, the steps of the method for testing the NAND FLASH reading function as described in any one of the above technical solutions are implemented.

[0094] The above description is only a partial or preferred embodiment of the present invention. Neither the text nor the drawings can limit the scope of protection of the present invention. All equivalent structural changes made by using the contents of the present invention specification and drawings under the overall concept of the present invention, or direct / indirect application in other related technical fields are included in the scope of protection of the present invention.

Claims

1. A method for testing a NAND FLASH read function, characterized in that: The test method of the NAND FLASH reading function includes: NAND FLASH sends the read data of each port to the local parity check module according to the read function test instruction; Controlling the parity check module to generate read data to be verified according to the read data of each port; Sending the read data to be verified to a test device via any port, wherein the test device is a device for detecting a NANDFLASH read function; Receiving the test result fed back by the test device; the test result includes the comparison result of the read data to be verified and the preset verification data; It is determined according to the test results whether the reading function of each port is normal and / or abnormal.

2. The method for testing the NAND FLASH read function according to claim 1, characterized in that: The controlling the parity check module to generate read data to be verified according to the read data of each port includes: Control the parity check module to add parity check data to the read data of each port to obtain the parity check read data of each port; The to-be-verified read data is generated according to the parity check read data of each of the ports.

3. The method for testing the NAND FLASH read function according to claim 2, characterized in that: The receiving the test result fed back by the test device includes: The comparison result fed back by the test device is received; the comparison result is obtained by the test device splitting the read data to be verified into parity check read data of each port, and comparing the parity check read data of each port with the preset check data respectively.

4. The method for testing the NAND FLASH read function according to claim 3, characterized in that: Determining whether the reading function of each port is normal and / or abnormal according to the test result includes: If the parity check read data of the port is consistent with the preset check data, it is determined that the reading function of the port is normal; and / or, If the parity check read data of the port is inconsistent with the preset check data, it is determined that the reading function of the port is abnormal.

5. The method for testing the NAND FLASH read function according to claim 2, characterized in that: After controlling the parity check module to add parity check data to the read data of each port to obtain the parity check read data of each port, the method further includes: Performing cyclic redundancy check calculation on the parity check read data of each port to obtain a calculation result of each port; The read data to be verified is generated according to the parity check read data of each port and the calculation result of each port.

6. The method for testing the NAND FLASH read function according to claim 5, characterized in that: The preset check data includes preset parity check data and preset redundant check data; The receiving the test result fed back by the test device includes: receiving the comparison result fed back by the testing device; The comparison result is obtained by the test device splitting the read data to be verified into parity check read data of each port and calculation results of each port, and comparing the parity check read data of each port with the preset parity check data, and comparing the calculation results of each port with the preset redundant check data.

7. A NAND FLASH reading function test system, characterized in that: The test system for the NAND FLASH reading function includes a NAND FLASH and a test device; the NAND FLASH includes multiple ports, a parity check module and a storage module; the parity check module is connected to multiple ports and the storage module; the NAND FLASH communicates with the test device using any one of the ports; the test system for the NAND FLASH reading function can execute the test method for the NAND FLASH reading function described in any one of claims 1 to 6.

8. The NAND FLASH reading function test system according to claim 7, characterized in that: The NANDFLASH further comprises a cyclic redundancy check module; the cyclic redundancy check module is connected to the parity check module.

9. A NAND FLASH reading function test device, characterized in that: include: at least one processor; as well as, a memory communicatively connected to the at least one processor; wherein, The memory stores instructions executed by the at least one processor, and the instructions are executed by the at least one processor so that the at least one processor can execute the NAND FLASH reading function testing method according to any one of claims 1 to 6.

10. A test host for NAND FLASH reading function, characterized in that: The NAND FLASH read function test host comprises a test host body and a plurality of NAND FLASH read function test systems according to any one of claims 7 to 8; a plurality of the test devices are mounted on the test host body.

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