Memory device, memory system, operating method thereof, and storage medium

Abstract

The embodiment of the invention provides a memory device, a memory system, an operation method of the memory system and a storage medium. The memory device includes a memory chip including a plurality of word lines; the plurality of memory chips coupled with each word line are divided into a first memory chip area and a second memory chip area; each word line corresponds to at least one redundant stripe, the redundant stripes comprise a first redundant stripe, and the first redundant stripe is configured to store first verification data; the first verification data is obtained by performing error correction coding on data in a first memory chip area of a word line where the first redundancy strip is located and data in a second memory chip area of a word line adjacent to the word line where the first redundancy strip is located.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular to a memory device, a memory system, an operation method thereof, and a storage medium. Background Art

[0002] Non-volatile memory devices with low power consumption, light weight and good performance, such as three-dimensional NAND memory, have been widely used in electronic products. However, in the related art, there are still many problems to be solved when performing a read operation on the memory device. Summary of the invention

[0003] In order to solve one or more of the existing technical problems, the embodiments of the present disclosure propose a memory device, a memory system and an operation method thereof, and a storage medium. Among them, the embodiments of the present disclosure provide a memory device including: a memory chip, the memory chip including a plurality of word lines; a plurality of memory slices coupled to each of the word lines are divided into a first memory slice area and a second memory slice area; each of the word lines corresponds to at least one redundant stripe, the redundant stripe includes a first redundant stripe, and the first redundant stripe is configured to: store first verification data; the first verification data is obtained by error correction coding of data in the first memory slice area of ​​the word line where the first redundant stripe is located and data in the second memory slice area of ​​the word line adjacent to the word line where the first redundant stripe is located.

[0004] In some embodiments, the redundant strip also includes a second redundant strip, and the second redundant strip is configured to: store second verification data; the second verification data is obtained by error correction encoding of data in the first storage slice area or the second storage slice area of ​​the word line where the second redundant strip is located.

[0005] In some embodiments, the memory chip includes word lines 0 to N numbered according to physical positions; the memory chip is programmed sequentially from word line 0 to word line N; N is an integer greater than 1; the word line 0 corresponds to a second redundant stripe, and the second verification data is obtained by error correction coding of data in a first storage cell area of ​​the word line 0; the word lines 1 to N-1 correspond to a first redundant stripe, and each of the first verification data is obtained by error correction coding of data in a first storage cell area of ​​the corresponding word line and data in a second storage cell area of ​​an upper word line of the corresponding word line; the N word line corresponds to a first redundant stripe and a second redundant stripe, the first verification data is obtained by error correction coding of data in a first storage cell area of ​​the N word line and data in a second storage cell area of ​​the N-1 word line, and the second verification data is obtained by error correction coding of data in a second storage cell area of ​​the N word line.

[0006] In some embodiments, the 0th word line corresponds to a group of first starting data and a group of second starting data; the first starting data includes data stored in the first storage cell of each storage cell in the second storage cell area of ​​the 0th word line; the second starting data includes data stored in the first storage cell of each storage cell in the first storage cell area of ​​the 0th word line; the 1st to N-1th word lines each correspond to a group of first starting data, and each group of the first starting data includes data stored in the first storage cell of each storage cell in the second storage cell area of ​​the corresponding word line; the Nth word line corresponds to a group of second starting data, and the second starting data includes data stored in the first storage cell of each storage cell in the second storage cell area of ​​the Nth word line.

[0007] In some embodiments, the memory chip includes a 0th word line and a 1st word line numbered according to physical positions; the 0th word line corresponds to a second redundant stripe, and the second verification data is obtained by error correction encoding of data in a first storage film area of ​​the 0th word line; the 1st word line corresponds to a first redundant stripe and a second redundant stripe, the first verification data is obtained by error correction encoding of data in the first storage film area of ​​the 1st word line and data in the second storage film area of ​​the 0th word line, and the second verification data is obtained by error correction encoding of data in the second storage film area of ​​the 1st word line.

[0008] In some embodiments, the number of memory slices in the first memory slice region is the same as the number of memory slices in the second memory slice region.

[0009] In some embodiments, each of the memory chips includes (N+1) word lines; each of the word lines is coupled to M memory chips; each of the memory chips includes L memory cells; wherein the ratio of the number of memory cells occupied by the redundant stripes in each of the memory chips to the number of all memory cells in the memory chip is: (N+2)(M / 2) / (N+1)*M*L.

[0010] In some embodiments, the first memory cell region and the second memory cell region coupled to each of the word lines are located in the same memory block, or are located in different memory blocks.

[0011] The present disclosure also provides a memory system, comprising: a memory device; the memory device comprising a memory chip, the memory chip comprising a plurality of word lines; a plurality of memory slices coupled to each of the word lines are divided into a first memory slice area and a second memory slice area; each of the word lines corresponds to at least one redundant strip, the redundant strips comprising a first redundant strip, the first redundant strip being configured to: store first verification data; the first verification data is obtained by error correction encoding of data in a first memory slice area of ​​a word line where the first redundant strip is located and data in a second memory slice area adjacent to a word line where the word line is located; and a memory controller coupled to the memory device and configured to: when a plurality of erroneous data appear in a plurality of memory slices coupled to one of the word lines, correct the data using the first verification data stored in the redundant strip corresponding to the corresponding word line and the first verification data stored in the redundant strip corresponding to the word line adjacent to the corresponding word line.

[0012] In some embodiments, the redundant stripe also includes a second redundant stripe, and the second redundant stripe is configured to: store second verification data; the second verification data is obtained by error correction encoding of data in the first storage slice area or the second storage slice area of ​​the word line where the second redundant stripe is located; the memory controller is also configured to: when multiple erroneous data appear in multiple storage slices coupled to one of the word lines, correct them using the second verification data stored in the redundant stripe corresponding to the corresponding word line and the first verification data stored in the redundant stripe corresponding to the word line adjacent to the corresponding word line; or, correct them using the first verification data and the second verification data stored in the redundant stripe corresponding to the corresponding word line.

[0013] In some embodiments, the memory chip includes word lines 0 to N numbered according to physical positions; the memory chip is programmed sequentially from word line 0 to word line N; N is an integer greater than 1; the word line 0 corresponds to a second redundant stripe, and the second verification data is obtained by error correction coding of data in a first storage cell area of ​​the word line 0; the word lines 1 to N-1 correspond to a first redundant stripe, and each of the first verification data is obtained by error correction coding of data in a first storage cell area of ​​the corresponding word line and data in a second storage cell area of ​​an upper word line of the corresponding word line; the N word line corresponds to a first redundant stripe and a second redundant stripe, the first verification data is obtained by error correction coding of data in a first storage cell area of ​​the N word line and data in a second storage cell area of ​​the N-1 word line, and the second verification data is obtained by error correction coding of data in a second storage cell area of ​​the N word line.

[0014] In some embodiments, the 0th word line corresponds to a group of first starting data and a group of second starting data; the first starting data includes data stored in the first storage cell of each storage cell in the second storage cell area of ​​the 0th word line; the second starting data includes data stored in the first storage cell of each storage cell in the first storage cell area of ​​the 0th word line; the 1st to N-1th word lines each correspond to a group of first starting data, and each group of the first starting data includes data stored in the first storage cell of each storage cell in the second storage cell area of ​​the corresponding word line; the Nth word line corresponds to a group of second starting data, and the second starting data includes data stored in the first storage cell of each storage cell in the second storage cell area of ​​the Nth word line.

[0015] In some embodiments, the memory chip includes a 0th word line and a 1st word line numbered according to physical positions; the 0th word line corresponds to a second redundant stripe, and the second verification data is obtained by error correction encoding of data in a first storage film area of ​​the 0th word line; the 1st word line corresponds to a first redundant stripe and a second redundant stripe, the first verification data is obtained by error correction encoding of data in the first storage film area of ​​the 1st word line and data in the second storage film area of ​​the 0th word line, and the second verification data is obtained by error correction encoding of data in the second storage film area of ​​the 1st word line.

[0016] In some embodiments, the number of memory slices in the first memory slice region is the same as the number of memory slices in the second memory slice region.

[0017] In some embodiments, each of the memory chips includes (N+1) word lines; each of the word lines is coupled to M memory chips; each of the memory chips includes L memory cells; wherein the ratio of the number of memory cells occupied by the redundant stripes in each of the memory chips to the number of all memory cells in the memory chip is: (N+2)(M / 2) / (N+1)*M*L.

[0018] In some embodiments, the first memory cell region and the second memory cell region coupled to each of the word lines are located in the same memory block, or are located in different memory blocks.

[0019] The present disclosure also provides an operating method of a memory system, the memory system comprising: a memory device; the memory device comprising a memory chip, the memory chip comprising a plurality of word lines; a plurality of memory slices coupled to each of the word lines are divided into a first memory slice area and a second memory slice area; each of the word lines corresponds to at least one redundant stripe, the redundant stripe comprising a first redundant stripe, the first redundant stripe being configured to: store first verification data; the first verification data is obtained by error correction encoding of data in a first memory slice area of ​​the word line where the first redundant stripe is located and data in a second memory slice area adjacent to the word line where the word line is located; and a memory controller coupled to the memory device; wherein the operating method comprises: when a plurality of erroneous data appear in a plurality of memory slices coupled to one of the word lines, correction is performed using the first verification data stored in the redundant stripe corresponding to the corresponding word line and the first verification data stored in the redundant stripe corresponding to the word line adjacent to the corresponding word line.

[0020] In some embodiments, the redundant stripe also includes a second redundant stripe, and the second redundant stripe is configured to: store second verification data; the second verification data is obtained by error correction encoding of data in the first storage chip area or the second storage chip area of ​​the word line where the second redundant stripe is located; the operation method includes: when multiple erroneous data appear in multiple storage chips coupled to one of the word lines, correcting using the second verification data stored in the redundant stripe corresponding to the corresponding word line and the first verification data stored in the redundant stripe corresponding to the word line adjacent to the corresponding word line; or correcting using the first verification data and the second verification data stored in the redundant stripe corresponding to the corresponding word line.

[0021] The embodiments of the present disclosure further provide a storage medium having executable instructions stored thereon. When the executable instructions are executed by a memory controller, the steps of the method described in the above embodiments of the present disclosure can be implemented.

[0022] The embodiments of the present disclosure provide a memory device, a memory system and an operation method thereof, and a storage medium. The memory device includes: a memory chip, the memory chip includes a plurality of word lines; a plurality of memory slices coupled to each word line are divided into a first memory slice area and a second memory slice area; each word line corresponds to at least one redundant stripe, the redundant stripe includes a first redundant stripe, the first redundant stripe is configured to: store first verification data; the first verification data is obtained by error correction coding of data in the first memory slice area of ​​the word line where the first redundant stripe is located and data in the second memory slice area of ​​the word line adjacent to the word line where the first redundant stripe is located. In the disclosed embodiment, a plurality of memory cells coupled to each word line are divided into a first memory cell region and a second memory cell region; the second memory cell region coupled to the first word line of the plurality of word lines and the first memory cell region coupled to the second word line correspond to a first redundant stripe; the second memory cell region coupled to the second word line and the first memory cell region coupled to the third word line correspond to a first redundant stripe; and so on, the first memory cell region coupled to the last word line of the plurality of word lines and the second memory cell region coupled to the previous word line of the last word line correspond to a first redundant stripe; in this case, in all word lines between the first word line and the last word line, a memory cell region coupled to each of every two word lines corresponds to a first redundant stripe, so that, on the one hand, when an error occurs in each of the two memory cell regions coupled to the same word line, the two first check data corresponding to the same word line can be used to correct the two errors, thereby improving the error correction capability and enhancing the reliability of the memory device; on the other hand, the two memory cell regions respectively coupled to the two word lines correspond to the same first redundant stripe, thereby reducing the number of first redundant stripes and the space occupied by them, thereby improving the utilization rate of memory resources. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 A schematic diagram of an exemplary system having a memory system according to an embodiment of the present disclosure;

[0024] Figure 2a A schematic diagram of an exemplary memory card having a memory system according to an embodiment of the present disclosure;

[0025] Figure 2b A schematic diagram of an exemplary solid-state drive having a memory system according to an embodiment of the present disclosure;

[0026] Figure 3a A schematic diagram of the distribution of storage cells of a three-dimensional NAND memory according to an embodiment of the present disclosure;

[0027] Figure 3b A schematic diagram of an exemplary memory including a peripheral circuit according to an embodiment of the present disclosure;

[0028] Figure 4 A cross-sectional schematic diagram of a memory cell array including a NAND memory string according to an embodiment of the present disclosure;

[0029] Figure 5 A schematic diagram of an exemplary memory device including a memory cell array and a peripheral circuit according to an embodiment of the present disclosure;

[0030] Figure 6a A schematic diagram of a storage unit structure in which one page corresponds to one verification data provided by an embodiment of the present disclosure;

[0031] Figure 6b A schematic diagram of a storage unit structure in which one page corresponds to multiple verification data provided by an embodiment of the present disclosure;

[0032] Figure 7 A block diagram of a memory system provided by an embodiment of the present disclosure;

[0033] Figure 8 A schematic diagram of a layout structure of user data and verification data in a plurality of word lines provided by an embodiment of the present disclosure;

[0034] Fig. 9 A schematic diagram of the layout structure of user data and verification data in two word lines provided in an embodiment of the present disclosure.

[0035] In the above drawings (which are not necessarily drawn to scale), similar reference numerals may describe similar components in different views. Similar reference numerals with different letter suffixes may represent different examples of similar components. The accompanying drawings generally illustrate various embodiments discussed herein by way of example and not limitation. DETAILED DESCRIPTION

[0036] The exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although the exemplary embodiments of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the specific embodiments set forth herein. On the contrary, these embodiments are provided in order to enable a more thorough understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art.

[0037] In the following description, a large number of specific details are given to provide a more thorough understanding of the present disclosure. However, it is obvious to those skilled in the art that the present disclosure can be implemented without one or more of these details. In other examples, in order to avoid confusion with the present disclosure, some technical features known in the art are not described; that is, all features of actual embodiments are not described here, and well-known functions and structures are not described in detail.

[0038] In the drawings, the sizes of layers, regions, elements and their relative sizes may be exaggerated for clarity. Like reference numerals denote like elements throughout.

[0039] It should be understood that when an element or layer is referred to as "on ...", "adjacent to ...", "connected to" or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to or coupled to other elements or layers, or there can be intervening elements or layers. On the contrary, when an element is referred to as "directly on ...", "directly adjacent to ...", "directly connected to" or "directly coupled to" other elements or layers, there is no intervening element or layer. It should be understood that although the terms first, second, third, etc. can be used to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the teachings of the present disclosure, the first element, component, region, layer or part discussed below can be represented as the second element, component, region, layer or part. And when the second element, component, region, layer or part is discussed, it does not indicate that the present disclosure necessarily has the first element, component, region, layer or part.

[0040] Spatially relative terms such as "under", "beneath", "below", "under", "above", "above", etc., may be used here for convenience of description to describe the relationship between an element or feature shown in the figure and other elements or features. It should be understood that in addition to the orientation shown in the figure, the spatial relationship terms are intended to also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is turned over, then the elements or features described as "under other elements" or "under it" or "under it" will be oriented as "on" other elements or features. Therefore, the exemplary terms "under" and "under" may include both upper and lower orientations. The device can be oriented otherwise (rotated 90 degrees or other orientations) and the spatial descriptors used herein are interpreted accordingly.

[0041] The purpose of the terms used herein is only to describe specific embodiments and is not intended to be a limitation of the present disclosure. When used herein, the singular forms "one", "an" and "said / the" are also intended to include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "consisting of" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0042] In order to enable a more detailed understanding of the features and technical contents of the embodiments of the present disclosure, the implementation of the embodiments of the present disclosure is described in detail below in conjunction with the accompanying drawings. The attached drawings are for reference only and are not used to limit the embodiments of the present disclosure.

[0043] The memory device in the embodiments of the present disclosure includes but is not limited to a three-dimensional NAND memory. For ease of understanding, a three-dimensional NAND memory is taken as an example for description.

[0044] Figure 1 A block diagram of an exemplary system 100 having a memory device according to some aspects of the present disclosure is shown. The system 100 may be a mobile phone, a desktop computer, a laptop computer, a tablet computer, a vehicle computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device having a memory therein. Figure 1 As shown in , system 100 may include a host 108 and a memory system 102, the memory system 102 having one or more memory devices 104 and a memory controller 106. The host 108 may be a processor (e.g., a central processing unit (CPU)) or a system on chip (SoC) (e.g., an application processor (AP)) of an electronic device. The host 108 may be configured to send data to the memory device 104 or receive data from the memory device 104.

[0045] According to some embodiments, the memory controller 106 is coupled to the memory device 104 and the host 108 and is configured to control the memory device 104. The memory controller 106 can manage data stored in the memory device 104 and communicate with the host 108. In some embodiments, the memory controller 106 is designed to operate in a low duty cycle environment, such as a secure digital (SD) card, a compact flash (CF) card, a universal serial bus (USB) flash drive, or other media for use in electronic devices such as personal computers, digital cameras, mobile phones, etc. In some embodiments, the memory controller 106 is designed to operate in a high duty cycle environment solid state drive (SSD) or embedded multimedia card (eMMC), which is used as a data storage for mobile devices such as smart phones, tablet computers, laptop computers, etc. and enterprise storage arrays.

[0046] The memory controller 106 may be configured to control the operation of the memory device 104, such as read, erase, and program operations. The memory controller 106 may also be configured to manage various functions regarding data stored or to be stored in the memory device 104, including but not limited to bad block management, garbage collection, logical to physical address translation, wear leveling, etc. In some embodiments, the memory controller 106 is also configured to process error correction codes (ECC) regarding data read from or written to the memory device 104. The memory controller 106 may also perform any other suitable functions, such as formatting the memory device 104. The memory controller 106 may communicate with an external device (e.g., a host 108) according to a specific communication protocol. For example, the memory controller 106 can communicate with external devices through at least one of various interface protocols, such as USB protocol, MMC protocol, peripheral component interconnect (PCI) protocol, PCI Express (PCI-E) protocol, advanced technology attachment (ATA) protocol, serial ATA protocol, parallel ATA protocol, small computer mini interface (SCSI) protocol, enhanced small disk interface (ESDI) protocol, integrated drive electronics (IDE) protocol, Firewire protocol, etc.

[0047] The memory controller 106 and the one or more memory devices 104 may be integrated into various types of storage devices, for example, included in the same package (e.g., a Universal Flash Storage (UFS) package or an eMMC package). That is, the memory system 102 may be implemented and packaged into different types of terminal electronic products. Figure 2a In one example shown in , the memory controller 106 and the single memory device 104 can be integrated into a memory card 202. The memory card 202 may include a PC card (PCMCIA, Personal Computer Memory Card International Association), a CF card, a Smart Media (SM) card, a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), UFS, etc. The memory card 202 may also include a processor that connects the memory card 202 to a host (e.g., Figure 1 The memory card connector 204 is coupled to the host 108 in the embodiment. Figure 2b In another example shown in , the memory controller 106 and the plurality of memory devices 104 may be integrated into an SSD 206. The SSD 206 may also include a processor that interfaces the SSD 206 with a host (e.g., Figure 1In some implementations, the storage capacity and / or operating speed of the SSD 206 is greater than the storage capacity and / or operating speed of the memory card 202.

[0048] Figure 3a A schematic diagram of the structure of a storage cell array of a three-dimensional NAND memory is given as an example. Figure 3a As shown, the memory cell array of the three-dimensional NAND memory is composed of several parallel and staggered rows of memory cell rows parallel to the gate isolation structure, every two rows of memory cell rows are separated by the gate isolation structure and the upper selection gate isolation structure, and each memory cell row includes a plurality of memory cells. The gate isolation structure may include a first gate isolation structure and a second gate isolation structure, the first gate isolation structure divides the memory cell array into a plurality of memory blocks (Blocks), the plurality of second gate isolation structures may divide the memory blocks into a plurality of finger storage areas (Fingers), and the upper selection gate isolation structure disposed in the middle of each finger storage area may divide the finger storage area into two parts, thereby dividing the finger storage area into two memory slices. Figure 3a A storage block shown in FIG. 1 includes 6 storage slices. In actual applications, the number of storage slices in a storage block is not limited thereto.

[0049] In some embodiments, each memory block may be coupled to a plurality of word lines, and a plurality of memory cells coupled to each individually controlled word line constitute a page. For example, Figure 3a All memory cells in each memory slice are coupled to form a page.

[0050] It should be noted that Figure 3a The number of memory cell rows between the gate isolation structure and the upper selection gate isolation structure given in the disclosure is only an exemplary demonstration and is not used to limit the number of memory cell rows contained in a finger storage area of ​​the three-dimensional NAND memory in the present disclosure. In actual applications, the number of memory cell rows contained in a finger storage area can be adjusted according to actual conditions, such as 2, 4, 8, 16, etc.

[0051] Figure 3b 1 is a schematic circuit diagram of an exemplary memory device 300 including peripheral circuits according to some aspects of the present disclosure. The memory device 300 may be Figure 1300 is an example of a memory device 104 in FIG. The memory device 300 may include a memory cell array 301 and a peripheral circuit 302 coupled to the memory cell array 301. The memory cell array 301 is taken as an example of a three-dimensional NAND-type memory cell array, wherein the memory cell 306 is a NAND-type memory cell, and the memory cell 306 is provided in the form of an array of memory strings 308, each memory string 308 extending vertically above a substrate (not shown). In some embodiments, each memory string 308 includes a plurality of memory cells 306 coupled in series and stacked vertically. Each memory cell 306 can hold a continuous analog value, such as a voltage or charge, which depends on the number of electrons captured in the region of the memory cell 306. Each memory cell 306 can be a floating gate type memory cell including a floating gate transistor, or a charge trapping type memory cell including a charge trapping transistor.

[0052] In some embodiments, each memory cell 306 is a single-level cell (SLC) having two possible storage states and can therefore store one bit of data. For example, the first storage state "0" may correspond to a first voltage range, and the second storage state "1" may correspond to a second voltage range. In some embodiments, each memory cell 306 is a multi-bit memory cell (MLC) capable of storing more than one bit of data in more than four storage states. For example, an MLC may store two bits per cell (also referred to as a two-bit memory cell, Double-Level Cell), three bits per cell (also referred to as a three-bit memory cell (TLC, Trinary-Level Cell)), four bits per cell (also referred to as a four-bit memory cell (QLC, Quad-Level Cell)), five bits per cell (also referred to as a five-bit memory cell (PLC, Penta-level cell)), or more than five bits per cell. Each MLC may be programmed to take a range of possible nominal storage values. In one example, if each MLC stores two bits of data, the MLCs can be programmed to assume one of three possible programming levels from an erased state by writing one of three possible nominal storage values ​​to the cell, a fourth nominal storage value can be used for the erased state.

[0053] like Figure 3bAs shown in , each memory string 308 may include a lower selection transistor 310 (also known as a source selection transistor BSG, which includes a source selection gate) at its source terminal and an upper selection transistor 312 (also known as a drain selection transistor TSG, which includes a drain selection gate) at its drain terminal. The source selection transistor BSG310 and the drain selection transistor TSG312 can be configured to activate the selected memory string 308 during read and program operations. In some embodiments, the sources of the memory strings 308 in the same memory block 304 are coupled through the same source line (SL) 314 (e.g., a common SL). In other words, according to some embodiments, all memory strings 308 in the same memory block 304 have an array common source (ACS). According to some embodiments, the TSG312 of each memory string 308 is coupled to a corresponding bit line (BL) 316, and user data can be read or written from the bit line 316 via an output bus (not shown). In some embodiments, each storage string 308 is configured to be selected or deselected by applying a selection voltage (e.g., higher than the threshold voltage of a transistor having TSG312) or a deselection voltage (e.g., 0 V) ​​to a corresponding TSG312 via one or more TSG lines 313 and / or by applying a selection voltage (e.g., higher than the threshold voltage of a transistor having BSG310) or a deselection voltage (e.g., 0 V) ​​to a corresponding BSG310 via one or more BSG lines 315.

[0054] like Figure 3b As shown in , the memory string 308 can be organized into a plurality of memory blocks 304, each of which can have a common source line 314 (e.g., coupled to ground). In some embodiments, each memory block 304 is a basic data unit for an erase operation, that is, all memory cells 306 on the same memory block 304 are erased at the same time. In order to erase the memory cells 306 in a selected memory block 304, the source lines 314 coupled to the selected memory block 304 and the unselected memory blocks 304 in the same plane as the selected memory block 304 can be biased with an erase voltage (Vers) (e.g., a high positive voltage (e.g., 20V or higher)). It should be understood that in some examples, the erase operation can be performed at a half-memory block level, at a quarter-memory block level, or at a level with any suitable number of memory blocks or any suitable fraction of memory blocks. The memory cells 306 of adjacent memory strings 308 can be coupled by word lines 318, which select which row of memory cells 306 is affected by the read and program operations. In some embodiments, in combination with the previous Figure 3a, multiple memory cells are isolated by an upper selection gate isolation structure and a gate isolation structure, and multiple memory cells between the upper selection gate isolation structure and the gate isolation structure are arranged into multiple memory cell rows, and each memory cell row is parallel to the gate isolation structure and the upper selection gate isolation structure. Among them, the memory cells in the memory slice sharing the same word line form a physical page 320, and each physical page 320 can be mapped to at least one logical page according to the storage mode of the corresponding memory cell 306 (for example, SLC or MLC as mentioned above), and the logical page can constitute the basic data unit of the programming operation and the reading operation.

[0055] refer to Figure 3a , Figure 3b Each memory cell 306 in the plurality of memory cells is coupled to a corresponding word line 318, and each memory string 308 is coupled to a corresponding bit line 316 via a corresponding selection transistor (such as the top selection transistor (TSG) 312).

[0056] Figure 4 FIG. 3 is a cross-sectional schematic diagram of an exemplary memory cell array 301 including a memory string 308 using NAND as an example according to some aspects of the present disclosure. Figure 4 As shown, the NAND memory cell array 301 may include a stacked structure 410, which includes a plurality of gate layers 411 and a plurality of insulating layers 412 that are alternately stacked in sequence, and a channel structure that vertically penetrates the gate layers 411 and the insulating layers 412, wherein the channel structure is coupled with each gate layer to form a memory cell, and the channel structure is coupled with a plurality of gate layers in the stacked structure 410 to form a memory string 308. The gate layers 411 and the insulating layers 412 may be alternately stacked, and two adjacent gate layers 411 are separated by a layer of insulating layer 412.

[0057] The constituent material of the gate layer 411 may include a conductive material. Conductive materials include, but are not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicide, or any combination thereof. In some embodiments, each gate layer 411 includes a metal layer, for example, a tungsten layer. In some embodiments, each gate layer 411 includes a doped polysilicon layer. Each gate layer 411 may include a control gate surrounding a memory cell. The gate layer 411 at the top of the stacked structure 410 may extend laterally as an upper selection gate line, the gate layer 411 at the bottom of the stacked structure 410 may extend laterally as a lower selection gate line, and the gate layer 411 extending laterally between the upper selection gate line and the lower selection gate line may serve as a word line layer.

[0058] In some embodiments, the stacked structure 410 may be disposed on a substrate 401. The substrate 401 may include silicon (e.g., single crystal silicon), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon on insulator (SOI), germanium on insulator (GOI), or any other suitable material.

[0059] In some embodiments, the memory string 308 includes a channel structure extending vertically through the stacked structure 410. In some embodiments, the channel structure includes a channel hole filled with (one or more) semiconductor materials (e.g., as a semiconductor channel) and (one or more) dielectric materials (e.g., as a memory film). In some embodiments, the semiconductor channel includes silicon, for example, polysilicon. In some embodiments, the memory film is a composite dielectric layer including a tunneling layer, a storage layer (also referred to as a "charge trapping / storage layer"), and a barrier layer. The channel structure may have a cylindrical shape (e.g., a column shape). According to some embodiments, the semiconductor channel, the tunneling layer, the storage layer, and the barrier layer are arranged radially from the center of the column toward the outer surface of the column in this order. The tunneling layer may include silicon oxide, silicon oxynitride, or any combination thereof. The storage layer may include silicon nitride, silicon oxynitride, or any combination thereof. The barrier layer may include silicon oxide, silicon oxynitride, a high dielectric constant (high-k) dielectric, or any combination thereof. In one example, the memory film may include a composite layer of silicon oxide / silicon oxynitride / silicon oxide (ONO).

[0060] Return to reference Figure 3b , the peripheral circuit 302 may be coupled to the memory cell array 301 through the bit line 316, the word line 318, the source line 314, the BSG line 315, and the TSG line 313. The peripheral circuit 302 may include any suitable analog, digital, and mixed signal circuits for facilitating the operation of the memory cell array 301 by applying a voltage signal and / or a current signal to each target memory cell 306 and sensing a voltage signal and / or a current signal from each target memory cell 306 via the bit line 316, the word line 318, the source line 314, the BSG line 315, and the TSG line 313. The peripheral circuit 302 may include various types of peripheral circuits formed using metal-oxide-semiconductor (MOS) technology. For example, Figure 5 Some exemplary peripheral circuits are shown, and the peripheral circuit 302 includes a page buffer / sense amplifier 504, a column decoder / bit line driver 506, a row decoder / word line driver 508, a voltage generator 510, a control logic 512, a register 514, an interface 516, and a data bus 518. It should be understood that in some examples, it may also include Figure 5 Additional peripheral circuits not shown.

[0061] The page buffer / sense amplifier 504 can be configured to read data from the memory cell array 301 and program (write) data to the memory cell array 301 according to the control signal from the control logic 512. In one example, the page buffer / sense amplifier 504 can store the program data (write user data) to be programmed into the memory cell array 301. In another example, the page buffer / sense amplifier 504 can perform a program verification operation to ensure that the data has been correctly programmed into the memory cell 306 coupled to the selected word line 318. In yet another example, the page buffer / sense amplifier 504 can also sense a low-power signal from the bit line 316 representing the data bit stored in the memory cell 306, and amplify the small voltage swing to a recognizable logic level in a read operation. The column decoder / bit line driver 506 can be configured to be controlled by the control logic 512, and select one or more memory strings 308 by applying a bit line voltage generated from the voltage generator 510.

[0062] The row decoder / word line driver 508 may be configured to be controlled by the control logic 512 and select / deselect the memory block 304 of the memory cell array 301 and select / deselect the word line 318 of the memory block 304. The row decoder / word line driver 508 may also be configured to drive the word line 318 using the word line voltage generated from the voltage generator 510. In some embodiments, the row decoder / word line driver 508 may also select / deselect and drive the BSG line 315 and the TSG line 313. As described in detail below, the row decoder / word line driver 508 is configured to perform a programming operation on the memory cell 306 coupled to the (one or more) selected word lines 318. The voltage generator 510 may be configured to be controlled by the control logic 512 and generate a word line voltage (e.g., a read voltage, a program voltage, a pass voltage, a channel boosting voltage, a verification voltage, etc.), a bit line voltage, and a source line voltage to be supplied to the memory cell array 301.

[0063] The control logic 512 may be coupled to each of the other parts in the peripheral circuits described above, and is configured to control the operation of each of the other parts in the peripheral circuits. The register 514 may be coupled to the control logic 512, and includes a status register, a command register, and an address register for storing status information, a command operation code (OP code), and a command address for controlling the operation of each peripheral circuit. The interface 516 may be coupled to the control logic 512, and act as a control buffer to buffer control commands received from a host (not shown) and relay them to the control logic 512, and to buffer status information received from the control logic 512 and relay them to the host. The interface 516 may also be coupled to the column decoder / bit line driver 506 via the data bus 518, and act as a data I / O interface and a data buffer to buffer data and relay them to the memory cell array 301 or relay or buffer data from the memory cell array 301.

[0064] For three-dimensional NAND memory, multiple programming methods can be used to write user data, such as incremental step-pulse programming (ISPP). In the process of performing the programming operation, the user data will undergo a redundant array encoding operation before being stored in the storage unit to form verification data (Parity Data), such as parity check data. In this way, when reading the user data, the user data can be redundantly protected (Raid) by the verification data. For example, when the read user data is erroneous, the erroneous data can be corrected and data recovered by the verification data.

[0065] The verification data can be stored in some storage units (i.e., check bits) of the memory device. These storage units are not used to store actual user data but to store verification data. In addition, the verification data can also be stored in the verification buffer of the memory controller. In this way, when errors occur in reading certain user data, these erroneous data can be corrected and data recovered by the verification data stored in the check bit or the check buffer. In some embodiments, the verification data is usually calculated using algorithms such as Hamming code and XOR operation. In the embodiments of the present disclosure, the protection function of the verification data can greatly improve the reading performance. It should be noted that the verification data described below in the present disclosure is stored in some storage units (check bits) of the memory device.

[0066] Here, the parity check of obtaining parity check data is a method of checking the correctness of code transmission, which is based on whether the number of "1" in the digits of a set of binary codes being transmitted is odd or even. The use of an odd number is called odd check, and vice versa, it is called even check. Which check to use is predetermined. Usually, a parity check bit is specially set to make the number of "1" in this set of codes odd or even. If odd check is used, when the receiving end receives this set of codes, it checks whether the number of "1" is an odd number, thereby determining the correctness of the transmitted code. The data stored in the parity check bit is called parity check data.

[0067] It should be noted that the redundant protection of user data may include other various methods. Here, only the method of using verification data is exemplified.

[0068] In some specific embodiments, during the programming (writing user data) process, the user data located on the same page or on the same storage chip is subjected to an exclusive OR operation (operation symbol is XOR) to form verification data, and the verification data is stored in the verification bit (usually the last numbered storage unit) of the corresponding page or the corresponding storage chip. It should be understood that the verification data can only correct or recover the erroneous data in the corresponding storage unit, and one verification data can only correct or recover one erroneous data. For example, refer to Figure 6a , Figure 6a A schematic diagram of a memory cell structure in which one page corresponds to one verification data is shown; wherein the memory system includes one or more memory devices, each memory device includes one or more memory chips 601, and each memory chip 601 includes multiple word lines (WL0 to WLN); user data (X) in multiple memory cells coupled to the same word line WL corresponds to one verification data (P). When one error data appears in multiple memory cells coupled to the word line, the error data can be corrected or recovered by the verification data corresponding to the word line. However, when two or more error data appear in multiple memory cells coupled to the same word line, the two or more error data cannot be corrected or recovered by the verification data corresponding to the word line.

[0069] Based on this, the embodiment of the present disclosure further provides a method for setting verification data, for example, multiple storage cells coupled to the same word line correspond to multiple verification data respectively; illustratively, refer to Figure 6b , Figure 6bThe schematic diagram of the memory cell structure in which one page corresponds to multiple check data is shown; wherein the memory device includes one or more memory chips 602, each memory chip 602 includes multiple word lines (WL0 to WLN), each word line is coupled to 6 memory slices (Str0, Str1, Str2, Str3, Str4, Str5); each memory slice includes 4 memory cells (Cell1, Cell2, Cell3, Cell4), part of the memory cells (Cell1, Cell2, Cell3) of each memory slice is used to store user data (X1, X2, X3), and the check bit (Cell4) is used to store The check data (P0) is stored, wherein the check data (P0) is obtained by performing an XOR operation on all the user data (X1, X2, X3) in a memory slice; therefore, when an error data appears in multiple memory cells coupled to a memory slice, the error data can be corrected or recovered by the corresponding check data (P0); in other words, when two or more error data appear in the user data in multiple memory cells coupled to the same word line, the two or more error data are stored in different memory slices respectively, and the corresponding error data can be corrected or recovered by the two or more check data corresponding to the corresponding memory slices. However, if Figure 6b As shown, each memory slice corresponds to one verification data, so that the verification data coupled to the same word line occupies a larger storage space, thereby causing a waste of storage resources.

[0070] Based on this, another method for setting verification data is provided in an embodiment of the present disclosure, wherein a memory device includes one or more memory chips, the memory chip includes multiple word lines; each word line is coupled to multiple memory slices; the multiple memory slices coupled to each word line are divided into a first memory slice area and a second memory slice area; each word line corresponds to at least one redundant stripe, the redundant stripes include a first redundant stripe, and the first redundant stripe is configured to: store first verification data; the first verification data is obtained by error correction encoding of data in the first memory slice area of ​​the word line where the first redundant stripe is located and data in the second memory slice area of ​​the word line adjacent to the word line; and a memory controller is coupled to the memory device and is configured to: when multiple erroneous data appear in multiple memory slices coupled to a word line, correct them using the first verification data stored in the redundant stripe corresponding to the corresponding word line and the first verification data stored in the redundant stripe corresponding to the word line adjacent to the corresponding word line.

[0071] In some embodiments, the redundant stripe also includes a second redundant stripe, and the second redundant stripe is configured to: store second verification data; the second verification data is obtained by error correction encoding of data in the first storage slice area or the second storage slice area of ​​the word line where the second redundant stripe is located; the memory controller is also configured to: when multiple erroneous data appear in multiple storage slices coupled to a word line, correct them using the second verification data stored in the redundant stripe corresponding to the corresponding word line and the first verification data stored in the redundant stripe corresponding to the word line adjacent to the corresponding word line; or, correct them using the first verification data and the second verification data stored in the redundant stripe corresponding to the corresponding word line.

[0072] refer to Figure 7 , Figure 7 A block diagram of a memory system is shown. The memory system 701 includes: a memory controller 702 and a memory device 703. The memory controller 702 is used to control the memory device 703 to perform operations such as reading, writing, and erasing. Here, the memory controller 702 and the memory device 703 can be coupled in any suitable manner. In the embodiment of the present disclosure, the memory device 703 can be a semiconductor memory for storing data in a non-volatile manner, such as a NAND type memory. The memory system 701 is connected to a host 704, and the host 704 can be an electronic device such as a personal computer or a mobile terminal. The host I / F 7021 outputs commands, user data (written data), etc. received from the host 704 to the internal bus 7020, and sends user data read from the memory device 703, responses from the control unit 7023, etc. to the host 704.

[0073] The memory I / F 7022 controls the process of writing user data and the like to the memory device 703 and the process of reading from the memory device 703 based on the instruction of the control unit 7023. The control unit 7023 controls the memory system 701 as a whole, and the control unit 7023 is, for example, a central processing unit (CPU), a microprocessor (MPU), etc. When the control unit 7023 receives a command from the host 704 via the host I / F 7021, it performs control according to the command. For example, the control unit 7023 instructs the memory I / F 7022 to write user data and parity data to the memory device 703 according to the command from the host 704. In addition, the control unit 7023 instructs the memory I / F 7022 to read user data and parity data from the memory device 703 according to the command from the host 704.

[0074] The error correction (ECC) module 7024 includes an encoding unit 7025, a decoding unit 7026, and a check buffer 7027. The encoding unit 7025 encodes the user data of a predetermined size written in the same page to generate parity data. The parity data is written in the page where the user data that is the basis of the encoding has been written, and the decoding unit 7026 uses the parity data for decoding. The check buffer 7027 can be used to store the parity data.

[0075] The data buffer 7028 temporarily stores user data received from the host 704 before storing it in the memory device 703 , and temporarily stores data read from the memory device 703 before sending it to the host 704 .

[0076] As mentioned above, the memory device may include one or more memory chips (Die), each memory chip (Die) may include multiple memory blocks (Block), each memory block (Block) may include multiple memory slices (Str), each memory slice (Str) may include multiple memory cells (Cell); in addition, each memory chip (Die) may also include multiple word lines (WL), each word line (WL) is coupled with multiple memory cells (Cell). In other words, a word line may be coupled with memory cells in multiple memory slices; here, multiple memory slices coupled with the same word line may be located in the same memory block or in different memory blocks.

[0077] In the disclosed embodiment, the plurality of memory cells coupled to each word line are divided into two regions, a first memory cell region and a second memory cell region, wherein the first memory cell region and the second memory cell region may be located in the same memory block or in different memory blocks. Furthermore, the number of memory cells in the first memory cell region may be the same as or different from the number of memory cells in the second memory cell region.

[0078] In some specific embodiments, each memory chip includes (N+1) word lines; each word line is coupled to M memory slices; each memory slice includes L memory cells. The M memory slices coupled to the same word line are divided into a first memory slice region and a second memory slice region, and the number of memory slices in each memory slice region is the same, that is, both are M / 2.

[0079] Exemplary, reference Figure 8, the memory device includes a plurality of memory chips 800, each memory chip 800 includes (N+1) word lines, where the (N+1) word lines are numbered according to the physical positions of the 0th word line to the Nth word line; illustratively, such as the 0th word line WL0, the first word line WL1 to the Nth word line WLN. Each word line is coupled to 6 memory slices, and the 6 memory slices are arranged in sequence from the 0th memory slice to the 5th memory slice, such as the 0th memory slice Str0, the first memory slice Str1, the second memory slice Str2, the third memory slice Str3, the fourth memory slice Str4, and the fifth memory slice Str5; each memory slice includes 4 memory cells, and the 4 memory cells are arranged in sequence from the first memory cell to the fourth memory cell, such as the first memory cell Cell1, the second memory cell Cell2, the third memory cell Cell3, and the fourth memory cell Cell4. It should be noted that, Figure 8 It is only exemplarily shown that each memory chip includes 6 memory slices and each memory slice includes 4 memory cells (i.e., M=6, L=4), but it should be understood that each memory chip may include more memory slices, such as 12, 24, 32, etc., and each memory slice may include more memory cells, such as 32, 64, 128, etc.

[0080] In the disclosed embodiment, the six storage cells coupled to each word line are divided into a first storage cell area 801 and a second storage cell area 802. The number of storage cells in the first storage cell area 801 and the second storage cell area 802 is the same, that is, three; wherein the first storage cell area 801 includes the 0th storage cell Str0, the first storage cell Str1, and the second storage cell Str2; the second storage cell area 802 includes the third storage cell Str3, the fourth storage cell Str4, and the fifth storage cell Str5.

[0081] The four storage units in each storage slice can be used to store user data or to store user data and verification data (P1 or P2) respectively; here, the user data can be divided into starting data (S1 or S2) and non-starting data (X); among which, the starting data (S1 or S2) is stored in the first storage unit of the storage slice. In addition, one verification data can correspond to the user data in one storage slice or to the user data in multiple storage slices.

[0082] In the disclosed embodiment, each word line corresponds to at least one redundant stripe, and the redundant stripe is used to store verification data. Wherein, according to the different types of verification data stored, the redundant stripe may include a first redundant stripe and a second redundant stripe; wherein the first redundant stripe is used to store the first verification data; and the second redundant stripe is used to store the second verification data. The first redundant stripe may include a plurality of storage cells, each of which is used to store a first verification data; the second redundant stripe may also include a plurality of storage cells, each of which is used to store a second verification data. Here, the number of the first verification data and the number of the second verification data are related to the number of storage slices in the corresponding storage slice area.

[0083] The first check data is obtained by error correction coding of the data in the first storage chip area of ​​the word line where the first redundant stripe is located and the data in the second storage chip area of ​​the word line adjacent to the word line where the word line is located; specifically, one first check data in the first redundant stripe is obtained by error correction coding of the user data stored in a storage chip in the first storage chip area of ​​the word line where the first redundant stripe is located and the user data stored in a storage chip in the second storage chip area of ​​the word line adjacent to the word line where the word line is located. It should be understood that one first check data corresponds to the user data stored in two storage chips. In other words, one first check data is obtained by error correction coding (such as XOR operation) of the user data stored in the two storage chips respectively coupled to the two word lines. Here, the number of first check data is related to the number of storage chips in the first storage chip area of ​​the word line where the first redundant stripe is located and the number of storage chips in the second storage chip area of ​​the word line adjacent to the word line where the word line is located.

[0084] Similarly, the second check data is obtained by error correction coding of the data in the first storage chip area or the data in the second storage chip area of ​​the word line where the second redundant stripe is located; specifically, one second check data is obtained by error correction coding of the user data stored in a storage chip in the first storage chip area of ​​the word line where the second redundant stripe is located, or one second check data is obtained by error correction coding of the user data stored in a storage chip in the second storage chip area of ​​the word line where the second redundant stripe is located. It should be understood that one second check number corresponds to the user data stored in one storage chip. In other words, one second check data is obtained by error correction coding (such as XOR operation) of the user data stored in one storage chip. Here, the number of second check data is related to the number of storage chips in the first storage chip area of ​​the word line where the second redundant stripe is located, or the number of storage chips in the second storage chip area of ​​the word line where the second redundant stripe is located.

[0085] In some specific embodiments, the memory chip includes a first redundant stripe and a second redundant stripe, wherein a plurality of first check data coupled to the same word line constitute a first redundant stripe, and a plurality of second check data coupled to the same word line constitute a second redundant stripe.

[0086] The 0th word line corresponds to a second redundant stripe, and the second check data is obtained by performing error correction coding on the data in the first storage slice area of ​​the 0th word line;

[0087] Each of the first word line to the N-1th word line corresponds to a first redundant stripe, and each of the first verification data is obtained by performing error correction coding on data in a first storage slice area of ​​a corresponding word line and data in a second storage slice area of ​​a previous word line of the corresponding word line;

[0088] The Nth word line corresponds to a first redundant strip and a second redundant strip, the first verification data is obtained by performing error correction coding on the data in the first storage area of ​​the Nth word line and the data in the second storage area of ​​the N-1th word line, and the second verification data is obtained by performing error correction coding on the data in the second storage area of ​​the Nth word line.

[0089] Exemplary, reference Figure 8 , Figure 8 The memory chip 800 shown in FIG. 8 includes a plurality of first redundant stripes 803 and a plurality of second redundant stripes 804; a plurality of memory cells for storing first verification data coupled to the same word line constitute a first redundant stripe 803. Figure 8 As shown, each first redundant stripe 803 includes three fourth storage cells Cell4, and each fourth storage cell is used to store a first verification data P1; here, a first verification data P1 in the first redundant stripe 803 corresponding to the first word line WL1 is obtained by jointly error correction encoding the user data in a storage cell in the first storage cell area 801 (Str0, Str1, Str2) coupled to the first word line WL1, and the user data in a storage cell in the second storage cell area 802 (Str3, Str4, Str5) in the 0th word line WL0.

[0090] It should be noted that the storage slice corresponding to the first verification data P1 may be any storage slice in the corresponding storage slice area. For a clearer understanding, the correspondence between the verification data and the storage slices is in sequence according to the numbering order.

[0091] Exemplarily, the first first check data P1 in the first redundant strip 803 corresponding to the first word line WL1 is obtained by jointly error correcting the user data in the 0th storage slice Str0 in the first storage slice area 801 coupled to the first word line WL1, and the user data in the third storage slice Str3 in the second storage slice area 802 in the 0th word line WL0.

[0092] Exemplarily, the second first check data P1 in the first redundant stripe 803 corresponding to the first word line WL1 is obtained by performing common error correction coding on the user data in the first memory slice Str1 in the first memory slice region 801 coupled to the first word line WL1, and the user data in the fourth memory slice Str4 in the second memory slice region 802 in the 0th word line WL0. By analogy in the order of numbering, each first check data corresponds to the user data in the two memory slices respectively coupled to the two word lines.

[0093] In the memory chip 800, the first check data in the first redundant strip corresponding to the Nth word line is obtained by performing error correction coding on the data in the first memory slice area of ​​the Nth word line and the data in the second memory slice area of ​​the N-1th word line. The corresponding manner is the same as that in the above embodiment and will not be described in detail.

[0094] It should be noted that the data of each memory cell in the first memory cell area of ​​the 0th word line and the second memory cell area of ​​the Nth word line are error-corrected to obtain a second check data. A plurality of memory cells coupled to the same word line for storing the second check data constitute a second redundant stripe.

[0095] refer to Figure 8 Each second redundant stripe 804 includes three fourth storage cells Cell4, each fourth storage cell is used to store a second verification data P2; each second verification data P2 is obtained by error correction encoding of user data in a storage cell in the first storage cell area or user data in a storage cell in the second storage cell area of ​​the word line where the second redundant stripe is located.

[0096] Specifically, a second check data P2 in the second redundant strip 804 corresponding to the 0th word line WL0 is obtained by error correction encoding of user data in a storage chip in the first storage chip area 801 coupled to the 0th word line WL0, or, a second check data P2 in the second redundant strip 804 corresponding to the Nth word line WLN is obtained by error correction encoding of user data in a storage chip in the second storage chip area 802 coupled to the Nth word line WLN.

[0097] Exemplarily, the first second check data P2 in the second redundant stripe 804 corresponding to the 0th word line WL0 is obtained by error correction coding the user data in the 0th memory slice Str0 in the first memory slice region 801 coupled to the 0th word line WL0. The second second check data P2 in the second redundant stripe 804 corresponding to the 0th word line WL0 is obtained by error correction coding the user data in the 1st memory slice Str1 in the first memory slice region 801 coupled to the 0th word line WL0.

[0098] Exemplarily, the first second check data P2 in the second redundant strip 804 corresponding to the Nth word line WLN is obtained by error correction coding the user data in the third memory slice Str3 in the second memory slice region 802 coupled to the Nth word line WLN. The second second check data P2 in the second redundant strip 804 corresponding to the Nth word line WLN is obtained by error correction coding the user data in the fourth memory slice Str4 in the second memory slice region 802 coupled to the Nth word line WLN. By analogy in the order of numbering, each second check data corresponds to the user data in a memory slice coupled to the same word line.

[0099] In some embodiments, the ratio of the number of storage cells occupied by the redundant stripes in each memory chip to the number of all storage cells in the memory chip is: (N+2)(M / 2) / (N+1)*M*L. In this way, compared with one check data corresponding to each memory chip, that is, the ratio of the number of storage cells occupied by the redundant stripes in each memory chip to the number of all storage cells in the memory chip is: (N+1)*M*1 / (N+1)*M*L=1 / L, when two errors in multiple memory chip regions coupled to the same word line can be solved, the check data in different redundant stripes corresponding to the two word lines can be used to correct the two errors, and the storage space occupied by the check data can also be saved. In other words, the error correction capability can be improved, the reliability of the memory device can be enhanced, and the number of check data and the storage space occupied by the check data can be reduced, thereby improving the utilization rate of memory resources.

[0100] In some embodiments, the 0th word line corresponds to a group of first starting data and a group of second starting data; the first starting data includes data stored in the first storage cell of each storage cell in the second storage cell area of ​​the 0th word line; the second starting data includes data stored in the first storage cell of each storage cell in the first storage cell area of ​​the 0th word line; the 1st word line to the N-1th word line each correspond to a group of first starting data, each group of first starting data includes data stored in the first storage cell of each storage cell in the second storage cell area of ​​the corresponding word line; the Nth word line corresponds to a group of second starting data, and the second starting data includes data stored in the first storage cell of each storage cell in the second storage cell area of ​​the Nth word line.

[0101] Exemplary, reference Figure 8 , the memory chip 800 includes multiple groups of first starting data 805 and multiple groups of second starting data 806, wherein one group of first starting data 805 includes three first starting data S1, each first starting data S1 corresponds to the first verification data P1 corresponding to the memory chip where it is located; each first starting data S1 is the first user data of all user data used for error correction coding (such as XOR operation) to obtain the first verification data P1. Here, one group of second starting data 806 includes three second starting data S2, each second starting data S2 corresponds to the second verification data P2 corresponding to the memory chip where it is located; each second starting data S2 is the first user data of all user data used for error correction coding (such as XOR operation) to obtain the second verification data P2.

[0102] It should be noted that in order to distinguish the starting data from the non-starting data in the user data, Figure 8 In the figure, the first starting data is represented by "S1", the second starting data is represented by "S2", and non-starting data are represented by "X".

[0103] In some embodiments, when the memory chip includes only two word lines, that is, the memory chip includes the 0th word line and the 1st word line numbered according to the physical position; wherein the 0th word line corresponds to a second redundant stripe, and the second verification data is obtained by error correction encoding the data in the first storage cell area of ​​the 0th word line; the 1st word line corresponds to a first redundant stripe and a second redundant stripe, the first verification data is obtained by error correction encoding the data in the first storage cell area of ​​the 1st word line and the data in the second storage cell area of ​​the 0th word line, and the second verification data is obtained by error correction encoding the data in the second storage cell area of ​​the 1st word line.

[0104] Exemplary, reference Fig. 9The memory chip 900 includes a 0th word line WL0 and a 1st word line WL1, wherein the 0th word line WL0 corresponds to a second redundant stripe 804, and the second redundant stripe 804 includes three second verification data P2, wherein the first second verification data P2 is obtained by performing error correction coding on user data stored in the 0th storage slice Str0 in the first storage slice area of ​​the 0th word line WL0, the second second verification data P2 is obtained by performing error correction coding on user data stored in the first storage slice Str1 in the first storage slice area of ​​the 0th word line WL0, and the third second verification data P2 is obtained by performing error correction coding on user data stored in the second storage slice Str2 in the first storage slice area of ​​the 0th word line WL0.

[0105] The first word line WL1 corresponds to a first redundant stripe 803 and a second redundant stripe 804, each first redundant stripe 803 includes three first check data P1, and each second redundant stripe 804 includes three second check data P2; illustratively, the first first check data P1 is obtained by performing error correction coding on the data stored in the 0th storage slice Str0 in the first storage slice area 801 of the first word line WL1 and the data stored in the third storage slice Str3 in the second storage slice area 802 of the 0th word line WL0, and so on. illustratively, the first second check data P2 is obtained by performing error correction coding on the data stored in the third storage slice Str3 in the second storage slice area 802 of the first word line WL1, and so on.

[0106] Based on this, in the embodiment of the present disclosure, the multiple storage slices coupled to each word line are divided into a first storage slice area and a second storage slice area; the first storage slice area coupled to the first word line among the multiple word lines corresponds to a second redundant stripe; the second storage slice area coupled to the first word line and the first storage slice area coupled to the second word line correspond to a first redundant stripe; the second storage slice area coupled to the second word line and the first storage slice area coupled to the third word line correspond to a first redundant stripe; and so on, the first storage slice area coupled to the last word line among the multiple word lines and the second storage slice area coupled to the previous word line of the last word line correspond to a first redundant stripe; the second storage slice area coupled to the last word line corresponds to a second redundant stripe; in this In this case, among all the word lines located between the first word line and the last word line, a storage cell area coupled to each of the two word lines corresponds to a first redundant stripe, and the remaining storage cell areas in the storage cell areas coupled to the first word line and the last word line correspond to a second redundant stripe respectively; in this way, on the one hand, when an error occurs in each of the two storage cell areas coupled to the same word line, the two errors can be corrected by using the two first check data corresponding to the same word line, thereby improving the error correction capability and enhancing the reliability of the memory device; on the other hand, the two storage cell areas respectively coupled to the two word lines correspond to a first redundant stripe, thereby reducing the number of the first redundant stripes and the space they occupy, thereby improving the utilization rate of memory resources.

[0107] Based on the above memory system, the present disclosure further provides a memory device, including:

[0108] A memory chip, the memory chip comprising a plurality of word lines; a plurality of memory cells coupled to each of the word lines are divided into a first memory cell area and a second memory cell area; each of the word lines corresponds to at least one redundant stripe, the redundant stripes comprising a first redundant stripe, the first redundant stripe being configured to: store first verification data; the first verification data is obtained by error correction coding of data in a first memory cell area of ​​a word line where the first redundant stripe is located and data in a second memory cell area adjacent to a word line where the first redundant stripe is located.

[0109] In some embodiments, the redundant strip also includes a second redundant strip, and the second redundant strip is configured to: store second verification data; the second verification data is obtained by error correction encoding of data in the first storage slice area or the second storage slice area of ​​the word line where the second redundant strip is located.

[0110] In some embodiments, the memory chip includes word lines 0 to N numbered according to physical positions; the memory chip is programmed sequentially from word line 0 to word line N; N is an integer greater than 1; the word line 0 corresponds to a second redundant stripe, and the second verification data is obtained by error correction coding of data in a first storage cell area of ​​the word line 0; the word lines 1 to N-1 correspond to a first redundant stripe, and each of the first verification data is obtained by error correction coding of data in a first storage cell area of ​​the corresponding word line and data in a second storage cell area of ​​an upper word line of the corresponding word line; the N word line corresponds to a first redundant stripe and a second redundant stripe, the first verification data is obtained by error correction coding of data in a first storage cell area of ​​the N word line and data in a second storage cell area of ​​the N-1 word line, and the second verification data is obtained by error correction coding of data in a second storage cell area of ​​the N word line.

[0111] In some embodiments, the 0th word line corresponds to a group of first starting data and a group of second starting data; the first starting data includes data stored in the first storage cell of each storage cell in the second storage cell area of ​​the 0th word line; the second starting data includes data stored in the first storage cell of each storage cell in the first storage cell area of ​​the 0th word line; the 1st to N-1th word lines each correspond to a group of first starting data, and each group of the first starting data includes data stored in the first storage cell of each storage cell in the second storage cell area of ​​the corresponding word line; the Nth word line corresponds to a group of second starting data, and the second starting data includes data stored in the first storage cell of each storage cell in the second storage cell area of ​​the Nth word line.

[0112] In some embodiments, the memory chip includes a 0th word line and a 1st word line numbered according to physical positions; the 0th word line corresponds to a second redundant stripe, and the second verification data is obtained by error correction encoding of data in a first storage film area of ​​the 0th word line; the 1st word line corresponds to a first redundant stripe and a second redundant stripe, the first verification data is obtained by error correction encoding of data in the first storage film area of ​​the 1st word line and data in the second storage film area of ​​the 0th word line, and the second verification data is obtained by error correction encoding of data in the second storage film area of ​​the 1st word line.

[0113] In some embodiments, the number of memory slices in the first memory slice region is the same as the number of memory slices in the second memory slice region.

[0114] In some embodiments, each of the memory chips includes (N+1) word lines; each of the word lines is coupled to M memory chips; each of the memory chips includes L memory cells; wherein the ratio of the number of memory cells occupied by the redundant stripes in each of the memory chips to the number of all memory cells in the memory chip is: (N+2)(M / 2) / (N+1)*M*L.

[0115] In some embodiments, the first memory cell region and the second memory cell region coupled to each of the word lines are located in the same memory block, or are located in different memory blocks.

[0116] Based on the above memory system, an embodiment of the present disclosure further provides an operation method of the memory system, the memory system comprising: a memory device; the memory device comprising a memory chip, the memory chip comprising a plurality of word lines; a plurality of memory slices coupled to each of the word lines are divided into a first memory slice area and a second memory slice area; each of the word lines corresponds to at least one redundant stripe, the redundant stripes comprising a first redundant stripe, the first redundant stripe being configured to: store first verification data; the first verification data is obtained by error correction encoding of data in a first memory slice area of ​​a word line where the first redundant stripe is located and data in a second memory slice area adjacent to a word line where the word line is located; and a memory controller coupled to the memory device;

[0117] The operation method includes: when multiple erroneous data appear in multiple storage slices coupled to a word line, correction is performed using the first verification data stored in the redundant strip corresponding to the corresponding word line and the first verification data stored in the redundant strip corresponding to the word line adjacent to the corresponding word line.

[0118] In some embodiments, the redundant stripe also includes a second redundant stripe, and the second redundant stripe is configured to: store second verification data; the second verification data is obtained by error correction encoding of data in the first storage chip area or the second storage chip area of ​​the word line where the second redundant stripe is located; the operation method includes: when multiple erroneous data appear in multiple storage chips coupled to one of the word lines, correcting using the second verification data stored in the redundant stripe corresponding to the corresponding word line and the first verification data stored in the redundant stripe corresponding to the word line adjacent to the corresponding word line; or correcting using the first verification data and the second verification data stored in the redundant stripe corresponding to the corresponding word line.

[0119] The embodiments of the present disclosure further provide a storage medium having executable instructions stored thereon. When the executable instructions are executed by a memory controller, the steps of the method described in the above embodiments of the present disclosure can be implemented.

[0120] In some specific embodiments, the storage medium can be a magnetic random access memory (FRAM), a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), a flash memory, a magnetic surface storage, an optical disk, or a compact disc read-only memory (CD-ROM); it can also be various devices including one or any combination of the above-mentioned memory devices.

[0121] In some embodiments, executable instructions may be in the form of a program, software, software module, script or code, written in any form of programming language (including compiled or interpreted languages, or declarative or procedural languages), and may be deployed in any form, including as a stand-alone program or as a module, component, subroutine or other unit suitable for use in a computing environment.

[0122] As an example, executable instructions may, but need not, correspond to a file in a file system, may be stored as part of a file that stores other programs or data, such as in one or more scripts in a HyperText Markup Language (HTML) document, in a single file dedicated to the program in question, or in multiple coordinated files (e.g., files storing one or more modules, subroutines, or code portions).

[0123] It should be noted that: "first", "second", etc. are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. In addition, the technical solutions recorded in the embodiments of the present disclosure can be combined arbitrarily without conflict.

[0124] The above description is only a preferred embodiment of the present disclosure and is not intended to limit the protection scope of the present disclosure.

Claims

1. A memory device, characterized in that: include: A memory chip, wherein the memory chip includes a plurality of word lines; The plurality of memory slices coupled to each of the word lines are divided into a first memory slice region and a second memory slice region; Each of the word lines corresponds to at least one redundant strip, and the redundant strips include a first redundant strip, and the first redundant strip is configured to: store first verification data; the first verification data is obtained by error correction encoding of data in a first storage slice area of ​​the word line where the first redundant strip is located and data in a second storage slice area adjacent to the word line where the word line is located.

2. The memory device according to claim 1, wherein: The redundant strip also includes a second redundant strip, which is configured to store second verification data; the second verification data is obtained by error correction coding of data in the first storage slice area or data in the second storage slice area of ​​the word line where the second redundant strip is located.

3. The memory device according to claim 2, wherein: The memory chip includes word lines 0 to N which are numbered according to physical positions; The memory chip is programmed sequentially from the 0th word line to the Nth word line; Said N is an integer greater than 1; The 0th word line corresponds to a second redundant stripe, and the second check data is obtained by performing error correction coding on data in the first storage slice area of ​​the 0th word line; Each of the first word line to the N-1th word line corresponds to a first redundant stripe, and each of the first verification data is obtained by performing error correction coding on data in a first storage slice area of ​​a corresponding word line and data in a second storage slice area of ​​a previous word line of the corresponding word line; The Nth word line corresponds to a first redundant strip and a second redundant strip, the first verification data is obtained by performing error correction coding on the data in the first storage area of ​​the Nth word line and the data in the second storage area of ​​the N-1th word line, and the second verification data is obtained by performing error correction coding on the data in the second storage area of ​​the Nth word line.

4. The memory device according to claim 3, wherein: The 0th word line corresponds to a set of first starting data and a set of second starting data; the first starting data includes data stored in the first storage unit of each storage unit in the second storage unit region of the 0th word line; the second starting data includes data stored in the first storage unit of each storage unit in the first storage unit region of the 0th word line; The first word line to the N-1th word line each correspond to a group of the first starting data, and each group of the first starting data includes data stored in the first storage unit of each storage slice in the second storage slice area of ​​the corresponding word line; The Nth word line corresponds to a set of second starting data, and the second starting data includes data stored in the first storage unit of each memory slice in the second memory slice area of ​​the Nth word line.

5. The memory device according to claim 2, wherein: The memory chip includes a 0th word line and a 1st word line numbered according to physical positions; The 0th word line corresponds to a second redundant stripe, and the second check data is obtained by performing error correction coding on data in the first storage slice area of ​​the 0th word line; The first word line corresponds to a first redundant stripe and a second redundant stripe, the first verification data is obtained by performing error correction coding on data in a first storage region of the first word line and data in a second storage region of the 0th word line, and the second verification data is obtained by performing error correction coding on data in a second storage region of the first word line.

6. The memory device according to claim 1, wherein: The number of storage slices in the first storage slice area is the same as the number of storage slices in the second storage slice area.

7. The memory device according to claim 6, wherein: Each of the memory chips includes (N+1) word lines; each of the word lines is coupled to M memory chips; each of the memory chips includes L memory cells; The ratio of the number of storage units occupied by the redundant stripes in each storage chip to the number of all storage units in the storage chip is: (N+2)(M / 2) / (N+1)*M*L.

8. The memory device according to claim 1, wherein: The first memory cell region and the second memory cell region coupled to each of the word lines are located in the same memory block, or are located in different memory blocks.

9. A memory system, characterized in that: include: Memory device; The memory device includes a memory chip, and the memory chip includes a plurality of word lines; The plurality of memory slices coupled to each of the word lines are divided into a first memory slice region and a second memory slice region; Each of the word lines corresponds to at least one redundant stripe, the redundant stripes include a first redundant stripe, and the first redundant stripe is configured to: store first verification data; the first verification data is obtained by error correction coding of data in a first storage slice area of ​​the word line where the first redundant stripe is located and data in a second storage slice area adjacent to the word line where the word line is located; as well as a memory controller coupled to the memory device and configured to: When multiple error data appear in multiple memory slices coupled to a word line, correction is performed using first check data stored in a redundant stripe corresponding to a corresponding word line and first check data stored in a redundant stripe corresponding to a word line adjacent to the corresponding word line.

10. The memory system according to claim 9, characterized in that: The redundant stripe further includes a second redundant stripe, and the second redundant stripe is configured to: store second verification data; the second verification data is obtained by performing error correction coding on data in the first storage slice area or data in the second storage slice area of ​​the word line where the second redundant stripe is located; The memory controller is further configured to: When multiple erroneous data appear in multiple storage slices coupled to one of the word lines, correction is performed using the second check data stored in the redundant strip corresponding to the corresponding word line and the first check data stored in the redundant strip corresponding to the word line adjacent to the corresponding word line; or, correction is performed using the first check data and the second check data stored in the redundant strip corresponding to the corresponding word line.

11. The memory system according to claim 10, characterized in that: The memory chip includes word lines 0 to N which are numbered according to physical positions; the memory chip is programmed sequentially from word line 0 to N; Said N is an integer greater than 1; The 0th word line corresponds to a second redundant stripe, and the second check data is obtained by performing error correction coding on data in the first storage slice area of ​​the 0th word line; Each of the first word line to the N-1th word line corresponds to a first redundant stripe, and each of the first verification data is obtained by performing error correction coding on data in a first storage slice area of ​​a corresponding word line and data in a second storage slice area of ​​a previous word line of the corresponding word line; The Nth word line corresponds to a first redundant strip and a second redundant strip, the first verification data is obtained by performing error correction coding on the data in the first storage area of ​​the Nth word line and the data in the second storage area of ​​the N-1th word line, and the second verification data is obtained by performing error correction coding on the data in the second storage area of ​​the Nth word line.

12. The memory system according to claim 11, characterized in that: The 0th word line corresponds to a set of first starting data and a set of second starting data; the first starting data includes data stored in the first storage unit of each storage unit in the second storage unit region of the 0th word line; the second starting data includes data stored in the first storage unit of each storage unit in the first storage unit region of the 0th word line; The first word line to the N-1th word line each correspond to a group of the first starting data, and each group of the first starting data includes data stored in the first storage unit of each storage slice in the second storage slice area of ​​the corresponding word line; The Nth word line corresponds to a set of second starting data, and the second starting data includes data stored in the first storage unit of each memory slice in the second memory slice area of ​​the Nth word line.

13. The memory system according to claim 10, wherein: The memory chip includes a 0th word line and a 1st word line numbered according to physical positions; The 0th word line corresponds to a second redundant stripe, and the second check data is obtained by performing error correction coding on data in the first storage slice area of ​​the 0th word line; The first word line corresponds to a first redundant stripe and a second redundant stripe, the first verification data is obtained by performing error correction coding on data in a first storage region of the first word line and data in a second storage region of the 0th word line, and the second verification data is obtained by performing error correction coding on data in a second storage region of the first word line.

14. The memory system according to claim 9, wherein: The number of storage slices in the first storage slice area is the same as the number of storage slices in the second storage slice area.

15. The memory system according to claim 14, characterized in that: Each of the memory chips includes (N+1) word lines; each of the word lines is coupled to M memory chips; each of the memory chips includes L memory cells; The ratio of the number of storage units occupied by the redundant stripes in each storage chip to the number of all storage units in the storage chip is: (N+2)(M / 2) / (N+1)*M*L.

16. The memory system according to claim 9, wherein: The first memory cell region and the second memory cell region coupled to each of the word lines are located in the same memory block, or are located in different memory blocks.

17. A method for operating a memory system, characterized in that: The memory system comprises: a memory device; the memory device comprises a memory chip, the memory chip comprises a plurality of word lines; a plurality of memory slices coupled to each of the word lines are divided into a first memory slice region and a second memory slice region; Each of the word lines corresponds to at least one redundant stripe, the redundant stripes include a first redundant stripe, the first redundant stripe is configured to: store first verification data; the first verification data is obtained by error correction coding of data in a first storage slice region of the word line where the first redundant stripe is located and data in a second storage slice region adjacent to the word line where the first redundant stripe is located; and a memory controller coupled to the memory device; Wherein, the operation method includes: When multiple error data appear in multiple memory slices coupled to a word line, correction is performed using first check data stored in a redundant stripe corresponding to a corresponding word line and first check data stored in a redundant stripe corresponding to a word line adjacent to the corresponding word line.

18. The operating method according to claim 17, characterized in that: The redundant stripe further includes a second redundant stripe, and the second redundant stripe is configured to: store second verification data; the second verification data is obtained by performing error correction coding on data in the first storage slice area or data in the second storage slice area of ​​the word line where the second redundant stripe is located; The operation method comprises: When multiple erroneous data appear in multiple storage slices coupled to one of the word lines, correction is performed using the second check data stored in the redundant strip corresponding to the corresponding word line and the first check data stored in the redundant strip corresponding to the word line adjacent to the corresponding word line; or, correction is performed using the first check data and the second check data stored in the redundant strip corresponding to the corresponding word line.

19. A storage medium, characterized in that: The storage medium stores executable instructions, and when the executable instructions are executed by the memory controller, the steps of the method as described in any one of claims 17-18 can be implemented.

Images