Memory devices, memory systems, and operating methods thereof, storage media

Abstract

Embodiments of the present disclosure provide a memory device, a memory system and an operating method thereof, and a storage medium. The memory device includes a memory chip including a plurality of word lines. A plurality of memory dies coupled to each word line is divided into a first memory die area and a second memory die area. Each word line corresponds to at least one redundant stripe. The redundant stripe includes a first redundant stripe configured to store first check data. The first check data is obtained by error correction encoding data in the first memory die area of the word line where the first redundant stripe is located and data in the second memory die area of an adjacent word line to the word line.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and in particular to a memory device, a memory system, a method of operating the same, and a storage medium. Background Technology

[0002] Low-power, lightweight, and high-performance non-volatile memory devices, such as 3D NAND flash memory, are widely used in electronic products. However, many problems still need to be solved when performing read operations on these memory devices. Summary of the Invention

[0003] To address one or more of the existing technical problems, this disclosure provides a memory device, a memory system, an operating method thereof, and a storage medium. Specifically, this disclosure provides a memory device comprising: a memory chip including multiple word lines; multiple memory chips coupled to each word line being divided into a first memory chip region and a second memory chip region; each word line corresponding to at least one redundant stripe, the redundant stripe including a first redundant stripe, the first redundant stripe being configured to: store first check data; the first check data being obtained by error correction encoding of data in the first memory chip region of the word line containing the first redundant stripe and data in the second memory chip region of the adjacent word lines.

[0004] In some embodiments, the redundant stripe further includes a second redundant stripe, which is configured to store second check data; the second check data is obtained by error correction encoding of data in a first memory slice area or a second memory slice area of ​​the word line where the second redundant stripe is located.

[0005] In some embodiments, the memory chip includes word lines 0 to N, numbered according to physical location; the memory chip is programmed sequentially from word lines 0 to N; N is an integer greater than 1; the 0th word line corresponds to a second redundancy stripe, and the second check data is obtained by error correction encoding of data in the first memory chip region of the 0th word line; each of the 1st to (N-1th)th word lines corresponds to a first redundancy stripe, and each first check data is obtained by error correction encoding of data in the first memory chip region of the corresponding word line and data in the second memory chip region of the previous word line; the Nth word line corresponds to a first redundancy stripe and a second redundancy stripe, and the first check data is obtained by error correction encoding of data in the first memory chip region of the Nth word line and data in the second memory chip region of the (N-1th)th word line, and the second check data is obtained by error correction encoding of data in the second memory chip region of the Nth word line.

[0006] In some embodiments, the 0th word line corresponds to a set of first starting data and a set of second starting data; the first starting data includes data stored in the first storage cell of each storage chip in the second storage chip region of the 0th word line; the second starting data includes data stored in the first storage cell of each storage chip in the first storage chip region of the 0th word line; each of the 1st to the (N-1th)th word lines corresponds to a set of first starting data, and each set of first starting data includes data stored in the first storage cell of each storage chip in the second storage chip region of the corresponding word line; the Nth word line corresponds to a set of second starting data, and the second starting data includes data stored in the first storage cell of each storage chip in the second storage chip region of the Nth word line.

[0007] In some embodiments, the memory chip includes a 0th word line and a 1st word line numbered according to their physical locations; the 0th word line corresponds to a second redundancy stripe, and the second check data is obtained by error correction encoding of the data in the first memory chip region of the 0th word line; the 1st word line corresponds to a first redundancy stripe and a second redundancy stripe, and the first check data is obtained by error correction encoding of the data in the first memory chip region of the 1st word line and the data in the second memory chip region of the 0th word line, and the second check data is obtained by error correction encoding of the data in the second memory chip region of the 1st word line.

[0008] In some embodiments, the number of memory chips in the first memory chip region is the same as the number of memory chips in the second memory chip region.

[0009] In some embodiments, each of the memory chips includes (N+1) word lines; each word line is coupled to M memory chips; each memory chip includes L memory cells; wherein the ratio of the number of memory cells occupied by the redundant stripes in each memory chip to the total number of memory cells in the memory chip is: (N+2)(M / 2) / (N+1)*M*L.

[0010] In some embodiments, the first memory chip region and the second memory chip region coupled to each of the word lines are located in the same memory block, or they are located in different memory blocks.

[0011] This disclosure also provides a memory system, including: a memory device; the memory device including a memory chip, the memory chip including multiple word lines; multiple memory chips coupled to each word line being divided into a first memory chip region and a second memory chip region; each word line corresponding to at least one redundant stripe, the redundant stripe including a first redundant stripe, the first redundant stripe being configured to: store first check data; the first check data being obtained by error correction encoding of data in the first memory chip region of the word line where the first redundant stripe is located and data in the second memory chip region of the word line adjacent to the word line; and a memory controller, coupled to the memory device and configured to: when multiple erroneous data occur in the multiple memory chips coupled to a word line, perform correction using the first check data stored in the redundant stripe corresponding to the corresponding word line and the first check data stored in the redundant stripe corresponding to the word line adjacent to the corresponding word line.

[0012] In some embodiments, the redundant stripe further includes a second redundant stripe, which is configured to store second check data. The second check data is obtained by error-correcting encoding data in a first memory chip region or a second memory chip region of the word line where the second redundant stripe is located. The memory controller is further configured to: when multiple erroneous data occur in multiple memory chips coupled to a word line, correct the data by using the second check data stored in the redundant stripe corresponding to the corresponding word line and the first check data stored in the redundant stripe corresponding to the word line adjacent to the corresponding word line; or, correct the data by using the first check data and the second check data stored in the redundant stripe corresponding to the corresponding word line.

[0013] In some embodiments, the memory chip includes word lines 0 to N, numbered according to physical location; the memory chip is programmed sequentially from word lines 0 to N; N is an integer greater than 1; the 0th word line corresponds to a second redundancy stripe, and the second check data is obtained by error correction encoding of data in the first memory chip region of the 0th word line; each of the 1st to (N-1th)th word lines corresponds to a first redundancy stripe, and each first check data is obtained by error correction encoding of data in the first memory chip region of the corresponding word line and data in the second memory chip region of the previous word line; the Nth word line corresponds to a first redundancy stripe and a second redundancy stripe, and the first check data is obtained by error correction encoding of data in the first memory chip region of the Nth word line and data in the second memory chip region of the (N-1th)th word line, and the second check data is obtained by error correction encoding of data in the second memory chip region of the Nth word line.

[0014] In some embodiments, the 0th word line corresponds to a set of first starting data and a set of second starting data; the first starting data includes data stored in the first storage cell of each storage chip in the second storage chip region of the 0th word line; the second starting data includes data stored in the first storage cell of each storage chip in the first storage chip region of the 0th word line; each of the 1st to the (N-1th)th word lines corresponds to a set of first starting data, and each set of first starting data includes data stored in the first storage cell of each storage chip in the second storage chip region of the corresponding word line; the Nth word line corresponds to a set of second starting data, and the second starting data includes data stored in the first storage cell of each storage chip in the second storage chip region of the Nth word line.

[0015] In some embodiments, the memory chip includes a 0th word line and a 1st word line numbered according to their physical locations; the 0th word line corresponds to a second redundancy stripe, and the second check data is obtained by error correction encoding of the data in the first memory chip region of the 0th word line; the 1st word line corresponds to a first redundancy stripe and a second redundancy stripe, and the first check data is obtained by error correction encoding of the data in the first memory chip region of the 1st word line and the data in the second memory chip region of the 0th word line, and the second check data is obtained by error correction encoding of the data in the second memory chip region of the 1st word line.

[0016] In some embodiments, the number of memory chips in the first memory chip region is the same as the number of memory chips in the second memory chip region.

[0017] In some embodiments, each of the memory chips includes (N+1) word lines; each word line is coupled to M memory chips; each memory chip includes L memory cells; wherein the ratio of the number of memory cells occupied by the redundant stripes in each memory chip to the total number of memory cells in the memory chip is: (N+2)(M / 2) / (N+1)*M*L.

[0018] In some embodiments, the first memory chip region and the second memory chip region coupled to each of the word lines are located in the same memory block, or they are located in different memory blocks.

[0019] This disclosure also provides an operation method for a memory system, the memory system comprising: a memory device; the memory device including a memory chip, the memory chip including multiple word lines; multiple memory chips coupled to each word line being divided into a first memory chip region and a second memory chip region; each word line corresponding to at least one redundant stripe, the redundant stripe including a first redundant stripe, the first redundant stripe being configured to: store first check data; the first check data being obtained by error correction encoding of data in the first memory chip region of the word line where the first redundant stripe is located and data in the second memory chip region of the word line adjacent to the word line; and a memory controller coupled to the memory device; wherein, the operation method includes: when multiple erroneous data occur in the multiple memory chips coupled to a word line, correcting the error using the first check data stored in the redundant stripe corresponding to the corresponding word line and the first check data stored in the redundant stripe corresponding to the word line adjacent to the corresponding word line.

[0020] In some embodiments, the redundant stripe further includes a second redundant stripe, which is configured to store second check data. The second check data is obtained by error-correcting encoding data in a first memory chip region or a second memory chip region of the word line where the second redundant stripe is located. The operation method includes: when multiple erroneous data occur in multiple memory chips coupled to a word line, correcting the data using the second check data stored in the redundant stripe corresponding to the corresponding word line and the first check data stored in the redundant stripe corresponding to the word line adjacent to the corresponding word line; or, correcting the data using the first check data and the second check data stored in the redundant stripe corresponding to the corresponding word line.

[0021] This disclosure also provides a storage medium storing executable instructions, which, when executed by a memory controller, can implement the steps of the method described in the above embodiments of this disclosure.

[0022] This disclosure provides a memory device, a memory system, an operating method thereof, and a storage medium. The memory device includes: a memory chip, the memory chip including multiple word lines; multiple memory chips coupled to each word line are divided into a first memory chip region and a second memory chip region; each word line corresponds to at least one redundant stripe, the redundant stripe including a first redundant stripe, the first redundant stripe being configured to: store first check data; the first check data is obtained by error correction encoding of data in the first memory chip region of the word line containing the first redundant stripe and data in the second memory chip region of the adjacent word lines. In this embodiment, multiple memory chips coupled to each word line are divided into a first memory chip region and a second memory chip region. The second memory chip region coupled to the first word line and the first memory chip region coupled to the second word line correspond to a first redundant stripe. The second memory chip region coupled to the second word line and the first memory chip region coupled to the third word line correspond to a first redundant stripe. And so on, the first memory chip region coupled to the last word line and the second memory chip region coupled to the word line preceding the last word line correspond to a first redundant stripe. In this case, in all word lines between the first and last word lines, each pair of word lines coupled to one memory chip region jointly corresponds to a first redundant stripe. Thus, on the one hand, when an error occurs in each of the two memory chip regions coupled to the same word line, the two errors can be corrected using the two first check data corresponding to the same word line, improving the error correction capability and enhancing the reliability of the memory device. On the other hand, since the two memory chip regions coupled to the two word lines correspond to the same first redundant stripe, the number of first redundant stripes and the space they occupy are reduced, improving the utilization rate of memory resources. Attached Figure Description

[0023] Figure 1 This is a schematic diagram of an exemplary system having a memory system according to an embodiment of the present disclosure;

[0024] Figure 2a This is a schematic diagram of an exemplary memory card having a memory system according to an embodiment of the present disclosure;

[0025] Figure 2b This is a schematic diagram of an exemplary solid-state drive with a memory system according to an embodiment of the present disclosure;

[0026] Figure 3a This is a schematic diagram showing the distribution of storage cells in a three-dimensional NAND type memory according to an embodiment of the present disclosure;

[0027] Figure 3b This is a schematic diagram of an exemplary memory including peripheral circuitry according to an embodiment of the present disclosure;

[0028] Figure 4 This is a schematic cross-sectional view of a memory cell array including NAND-type memory strings according to an embodiment of the present disclosure;

[0029] Figure 5 This is a schematic diagram of an exemplary memory device including a memory cell array and peripheral circuitry according to an embodiment of the present disclosure;

[0030] Figure 6a A schematic diagram of a storage unit structure in which one page corresponds to one verification data, provided in an embodiment of this disclosure;

[0031] Figure 6b A schematic diagram of a storage unit structure in which one page corresponds to multiple verification data is provided in an embodiment of this disclosure;

[0032] Figure 7 A block diagram of a memory system provided in an embodiment of this disclosure;

[0033] Figure 8 This is a schematic diagram illustrating the layout structure of user data and verification data in multiple word lines provided in an embodiment of the present disclosure;

[0034] Figure 9 This is a schematic diagram of the layout structure of user data and verification data in two word lines provided in an embodiment of this disclosure.

[0035] In the above figures (which are not necessarily drawn to scale), similar reference numerals may describe similar parts in different views. Similar reference numerals with different letter suffixes may indicate different examples of similar parts. The figures illustrate, by way of example and not limitation, the various embodiments discussed herein. Detailed Implementation

[0036] Exemplary embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be implemented in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

[0037] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of this disclosure. However, it will be apparent to those skilled in the art that this disclosure may be practiced without one or more of these details. In other instances, to avoid confusion with this disclosure, certain technical features well-known in the art have not been described; that is, not all features of actual embodiments are described herein, nor are well-known functions and structures described in detail.

[0038] In the accompanying drawings, for clarity, the dimensions of layers, areas, and elements, as well as their relative dimensions, may be exaggerated. The same reference numerals denote the same elements throughout.

[0039] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this disclosure, the first element, component, area, layer, or portion discussed below may be referred to as a second element, component, area, layer, or portion. And the discussion of a second element, component, area, layer, or portion does not imply that the first element, component, area, layer, or portion necessarily exists in this disclosure.

[0040] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below,” “under,” or “below” other elements or features will be oriented “above” other elements or features. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0041] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprise” and / or “comprising,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0042] To gain a more detailed understanding of the features and technical content of the embodiments of this disclosure, the implementation of the embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. The accompanying drawings are for reference and illustration only and are not intended to limit the embodiments of this disclosure.

[0043] The memory devices in the embodiments of this disclosure include, but are not limited to, three-dimensional NAND type memory. For ease of understanding, three-dimensional NAND type memory will be used as an example for explanation.

[0044] Figure 1 A block diagram of an exemplary system 100 having a memory device according to some aspects of this disclosure is shown. System 100 may be a mobile phone, desktop computer, laptop computer, tablet computer, vehicle computer, game console, printer, positioning device, wearable electronic device, smart sensor, virtual reality (VR) device, augmented reality (AR) device, or any other suitable electronic device having storage therein. Figure 1 As shown, system 100 may include a host 108 and a memory system 102, the memory system 102 having one or more memory devices 104 and a memory controller 106. The host 108 may be a processor (e.g., a central processing unit (CPU)) or a system-on-a-chip (SoC) (e.g., an application processor (AP)). The host 108 may be configured to send data to or receive data from the memory device 104.

[0045] According to some embodiments, memory controller 106 is coupled to memory device 104 and host 108 and is configured to control memory device 104. Memory controller 106 can manage data stored in memory device 104 and communicate with host 108. In some embodiments, memory controller 106 is designed to operate in low duty cycle environments, such as Secure Digital (SD) cards, Compact Flash (CF) cards, Universal Serial Bus (USB) flash drives, or other media used in electronic devices such as personal calculators, digital cameras, mobile phones, etc. In some embodiments, memory controller 106 is designed to operate in high duty cycle environments in solid state drives (SSDs) or embedded multimedia cards (eMMCs), which are used as data storage in mobile devices such as smartphones, tablets, laptops, etc., and in enterprise storage arrays.

[0046] The memory controller 106 can be configured to control the operation of the memory device 104, such as read, erase, and program operations. The memory controller 106 can also be configured to manage various functions relating to data stored or to be stored in the memory device 104, including but not limited to bad block management, garbage collection, logical-to-physical address translation, wear leveling, etc. In some embodiments, the memory controller 106 is also configured to process error correction codes (ECC) relating to data read from or written to the memory device 104. The memory controller 106 can also perform any other suitable functions, such as formatting the memory device 104. The memory controller 106 can communicate with external devices (e.g., host 108) according to specific communication protocols. For example, the memory controller 106 can communicate with external devices through at least one of various interface protocols, such as USB protocol, MMC protocol, Peripheral Component Interconnect (PCI) protocol, PCI High Speed ​​(PCI-E) protocol, Advanced Technology Attachment (ATA) protocol, Serial ATA protocol, Parallel ATA protocol, Small Computer Small Interface (SCSI) protocol, Enhanced Small Disk Interface (ESDI) protocol, Integrated Drive Electronic Devices (IDE) protocol, Firewire protocol, etc.

[0047] The memory controller 106 and one or more memory devices 104 can be integrated into various types of storage devices, for example, included in the same package (e.g., a Universal Flash Storage (UFS) package or an eMMC package). That is, the memory system 102 can be implemented and packaged into different types of end electronic products. Figure 2a In one example shown, the memory controller 106 and a single memory device 104 may be integrated into a memory card 202. The memory card 202 may include a PC card (PCMCIA, Personal Computer Memory Card International Association), a CF card, a Smart Media (SM) card, a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), UFS, etc. The memory card 202 may also include a connection between the memory card 202 and a host computer (e.g., Figure 1 The memory card connector 204 is coupled to the host 108. In such a way... Figure 2b In another example shown, the memory controller 106 and multiple memory devices 104 may be integrated into the SSD 206. The SSD 206 may also include a connection between the SSD 206 and a host (e.g., Figure 1The SSD connector 208 is coupled to the host 108. In some embodiments, the storage capacity and / or operating speed of the SSD 206 is greater than the storage capacity and / or operating speed of the memory card 202.

[0048] Figure 3a An exemplary schematic diagram of a storage cell array for a three-dimensional NAND flash memory is provided, such as... Figure 3a As shown, the memory cell array of a three-dimensional NAND flash memory consists of several rows of parallel, staggered memory cell rows parallel to the gate isolation structure. Each two rows of memory cell rows are separated by a gate isolation structure and an up-select gate isolation structure. Each memory cell row includes multiple memory cells. The gate isolation structure may include a first gate isolation structure and a second gate isolation structure. The first gate isolation structure divides the memory cell array into multiple memory blocks. Multiple second gate isolation structures can divide the memory blocks into multiple finger memory regions. An up-select gate isolation structure located in the middle of each finger memory region can divide the finger memory region into two parts, thereby dividing the finger memory region into two memory chips. Figure 3a The storage block shown contains 6 storage chips. In actual applications, the number of storage chips in a storage block is not limited to this.

[0049] In some embodiments, each memory block may be coupled with multiple word lines, and the multiple memory cells coupled to each individually controlled word line constitute a page. For example, Figure 3a In each memory chip, all memory cells are coupled together to form a page.

[0050] It should be noted that, Figure 3a The number of cell rows between the gate isolation structure and the top-select gate isolation structure given is merely an exemplary example and is not intended to limit the number of cell rows contained in a single memory region of the three-dimensional NAND memory in this disclosure. In practical applications, the number of cell rows contained in a single memory region can be adjusted according to actual conditions, such as 2, 4, 8, 16, etc.

[0051] Figure 3b A schematic circuit diagram of an exemplary memory device 300, including peripheral circuitry, is shown according to some aspects of this disclosure. The memory device 300 may be... Figure 1An example of memory device 104 is provided. Memory device 300 may include a memory cell array 301 and peripheral circuitry 302 coupled to the memory cell array 301. The memory cell array 301 is illustrated as a three-dimensional NAND-type memory cell array, wherein the memory cells 306 are NAND-type memory cells, provided in the form of an array of memory strings 308, each memory string 308 extending vertically above a substrate (not shown). In some embodiments, each memory string 308 includes a plurality of memory cells 306 coupled in series and stacked vertically. Each memory cell 306 may hold a continuous analog value, such as voltage or charge, depending on the number of electrons trapped in the region of the memory cell 306. Each memory cell 306 may be a floating-gate type memory cell including a floating-gate transistor, or a charge-trapping type memory cell including a charge-trapping transistor.

[0052] In some implementations, each storage cell 306 is a single-level cell (SLC) having two possible storage states and thus capable of storing one bit of data. For example, a first storage state "0" may correspond to a first voltage range, and a second storage state "1" may correspond to a second voltage range. In some implementations, each storage cell 306 is a multi-level cell (MLC) capable of storing more than one bit of data in more than four storage states. For example, an MLC may store two bits per cell (also referred to as a double-level cell), three bits per cell (also referred to as a trinary-level cell (TLC)), four bits per cell (also referred to as a quad-level cell (QLC)), five bits per cell (also referred to as a penta-level cell (PLC)), or more than five bits per cell. Each MLC may be programmed to take a range of possible nominal storage values. In one example, if each MLC stores two bits of data, the MLC can be programmed to take one of three possible programming levels from the erase state by writing one of three possible nominal storage values ​​to the cell, with a fourth nominal storage value that can be used for the erase state.

[0053] like Figure 3bAs shown, each memory string 308 may include a lower selection transistor 310 (also referred to as a source selection transistor BSG, which includes a source selection gate) at its source end and an upper selection transistor 312 (also referred to as a drain selection transistor TSG, which includes a drain selection gate) at its drain end. The source selection transistor BSG 310 and the drain selection transistor TSG 312 may be configured to activate the selected memory string 308 during read and program operations. In some embodiments, the sources of memory strings 308 in the same memory block 304 are coupled via the same source line (SL) 314 (e.g., a common SL). In other words, according to some embodiments, all memory strings 308 in the same memory block 304 have an array common source (ACS). According to some embodiments, the TSG 312 of each memory string 308 is coupled to a corresponding bit line (BL) 316, from which user data can be read or written via an output bus (not shown). In some implementations, each memory string 308 is configured to be selected or deselected by applying a selection voltage (e.g., higher than the threshold voltage of the transistor having TSG 312) or a deselection voltage (e.g., 0V) to the corresponding TSG 312 via one or more TSG lines 313 and / or by applying a selection voltage (e.g., higher than the threshold voltage of the transistor having BSG 310) or a deselection voltage (e.g., 0V) to the corresponding BSG 310 via one or more BSG lines 315.

[0054] like Figure 3b As shown, memory strings 308 can be organized into multiple memory blocks 304, each of which can have a common source line 314 (e.g., coupled to ground). In some embodiments, each memory block 304 is the basic data unit for an erase operation, i.e., all memory cells 306 on the same memory block 304 are erased simultaneously. To erase memory cells 306 in a selected memory block 304, an erase voltage (Vers) (e.g., a high positive voltage (e.g., 20V or higher)) biased and coupled to the source line 314 of the selected memory block 304 and the unselected memory blocks 304 on the same plane as the selected memory block 304 can be used. It should be understood that in some examples, erase operations can be performed at the half-block level, at the quarter-block level, or at a level with any suitable number of memory blocks or any suitable fraction of memory blocks. Memory cells 306 of adjacent memory strings 308 can be coupled via word lines 318, which select which row of memory cells 306 is affected by read and program operations. In some embodiments, in conjunction with the foregoing... Figure 3aMultiple memory cells are isolated from each other by an upselect gate isolation structure and a gate isolation structure. The memory cells between the upselect gate isolation structure and the gate isolation structure are arranged into multiple memory cell rows, each row being parallel to both the gate isolation structure and the upselect gate isolation structure. Memory cells in a memory chip sharing the same word line form a physical page 320. Each physical page 320 can be mapped to at least one logical page according to the memory mode of the corresponding memory cell 306 (e.g., SLC or MLC as mentioned above). Logical pages can constitute the basic data unit for programming and reading operations.

[0055] refer to Figure 3a , Figure 3b Each memory cell 306 in the multiple memory cells is coupled to the corresponding word line 318, and each memory string 308 is coupled to the corresponding bit line 316 through the corresponding selection transistor (such as the selection transistor (TSG) 312 above).

[0056] Figure 4 A schematic cross-sectional view of an exemplary memory cell array 301, including a memory string 308 exemplified by NAND, is shown according to some aspects of this disclosure. Figure 4 As shown, the NAND memory cell array 301 may include a stacked structure 410, which includes a plurality of gate layers 411 and a plurality of insulating layers 412 stacked alternately in sequence, and a channel structure that vertically penetrates the gate layers 411 and the insulating layers 412. The channel structure is coupled to each gate layer to form a memory cell, and the channel structure and the plurality of gate layers in the stacked structure 410 are coupled to form a memory string 308. The gate layers 411 and the insulating layers 412 may be stacked alternately, and two adjacent gate layers 411 are separated by an insulating layer 412.

[0057] The constituent materials of the gate layer 411 may include conductive materials. Conductive materials include, but are not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicide, or any combination thereof. In some embodiments, each gate layer 411 includes a metal layer, such as a tungsten layer. In some embodiments, each gate layer 411 includes a doped polysilicon layer. Each gate layer 411 may include a control gate surrounding a memory cell. The gate layer 411 at the top of the stack 410 may extend laterally as an upper select gate line, the gate layer 411 at the bottom of the stack 410 may extend laterally as a lower select gate line, and the gate layer 411 extending laterally between the upper and lower select gate lines may serve as a word line layer.

[0058] In some embodiments, the stacked structure 410 may be disposed on the substrate 401. The substrate 401 may include silicon (e.g., single-crystal silicon), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon-on-insulator (SOI), germanium-on-insulator (GOI), or any other suitable material.

[0059] In some embodiments, the memory string 308 includes a channel structure extending vertically through the stacked structure 410. In some embodiments, the channel structure includes channel holes filled with one or more semiconductor materials (e.g., as a semiconductor channel) and one or more dielectric materials (e.g., as a memory film). In some embodiments, the semiconductor channel includes silicon, for example, polycrystalline silicon. In some embodiments, the memory film is a composite dielectric layer including a tunneling layer, a storage layer (also referred to as a "charge trap / storage layer"), and a barrier layer. The channel structure may have a cylindrical shape (e.g., a pillar shape). According to some embodiments, the semiconductor channel, tunneling layer, storage layer, and barrier layer are arranged radially from the center of the pillar toward the outer surface of the pillar in this order. The tunneling layer may include silicon oxide, silicon oxynitride, or any combination thereof. The storage layer may include silicon nitride, silicon oxynitride, or any combination thereof. The barrier layer may include silicon oxide, silicon oxynitride, a high dielectric constant (high k) dielectric, or any combination thereof. In one example, the memory film may include a composite layer of silicon oxide / silicon oxynitride / silicon oxide (ONO).

[0060] Return to reference Figure 3b The peripheral circuitry 302 can be coupled to the memory cell array 301 via bit line 316, word line 318, source line 314, BSG line 315, and TSG line 313. The peripheral circuitry 302 can include any suitable analog, digital, and mixed-signal circuitry to facilitate the operation of the memory cell array 301 by applying voltage and / or current signals to each target memory cell 306 via bit line 316, word line 318, source line 314, BSG line 315, and TSG line 313, and by sensing voltage and / or current signals from each target memory cell 306. The peripheral circuitry 302 can include various types of peripheral circuitry formed using metal-oxide-semiconductor (MOS) technology. For example, Figure 5 Some exemplary peripheral circuitry is shown. Peripheral circuitry 302 includes a page buffer / sensor amplifier 504, a column decoder / bit line driver 506, a row decoder / word line driver 508, a voltage generator 510, control logic 512, a register 514, an interface 516, and a data bus 518. It should be understood that in some examples, additional peripheral circuitry may be included. Figure 5 Additional peripheral circuitry not shown.

[0061] Page buffer / sensor amplifier 504 can be configured to read data from and program (write) data to memory cell array 301 according to control signals from control logic 512. In one example, page buffer / sensor amplifier 504 can store programming data to be programmed into memory cell array 301 (write user data). In another example, page buffer / sensor amplifier 504 can perform a programming verification operation to ensure that data has been correctly programmed into memory cell 306 coupled to selected word line 318. In yet another example, page buffer / sensor amplifier 504 can also sense a low-power signal from bit line 316 representing data bits stored in memory cell 306 and amplify a small voltage swing to a recognizable logic level during read operations. Column decoder / bit line driver 506 can be configured to be controlled by control logic 512 and select one or more memory strings 308 by applying a bit line voltage generated from voltage generator 510.

[0062] The row decoder / word line driver 508 can be configured to be controlled by control logic 512 and to select / deselect memory blocks 304 of the memory cell array 301 and to select / deselect word lines 318 of memory blocks 304. The row decoder / word line driver 508 can also be configured to drive word lines 318 using word line voltages generated from voltage generator 510. In some embodiments, the row decoder / word line driver 508 can also select / deselect and drive BSG lines 315 and TSG lines 313. As described in detail below, the row decoder / word line driver 508 is configured to perform programming operations on memory cells 306 coupled to one or more selected word lines 318. The voltage generator 510 can be configured to be controlled by control logic 512 and to generate word line voltages (e.g., read voltage, programming voltage, pass voltage, channel boost voltage, verification voltage, etc.), bit line voltages, and source line voltages to be supplied to the memory cell array 301.

[0063] Control logic 512 can be coupled to each of the other parts of the peripheral circuitry described above and is configured to control the operation of each of the other parts of the peripheral circuitry. Register 514 can be coupled to control logic 512 and includes a status register, a command register, and an address register for storing status information, command opcodes (OP codes), and command addresses for controlling the operation of each peripheral circuit. Interface 516 can be coupled to control logic 512 and acts as a control buffer to buffer control commands received from the host (not shown) and relay them to control logic 512, as well as to buffer status information received from control logic 512 and relay them to the host. Interface 516 can also be coupled to column decoder / bit line driver 506 via data bus 518 and acts as a data I / O interface and data buffer to buffer data and relay it to or from memory cell array 301.

[0064] For three-dimensional NAND flash memory, various programming methods can be used to write user data, such as Incremental Step-Pulse Programming (ISPP). During the programming process, before being stored in the memory cell, the user data undergoes a redundancy array encoding operation to form parity data, such as parity check data. This allows for RAID protection of the user data during reading; for example, if errors occur in the read user data, the parity data can be used to correct these errors and recover the data.

[0065] Check data can be stored in some storage units (i.e., check bits) of the memory device. These storage units are not used to store actual user data but are used to store check data. Additionally, check data can also be stored in the check buffer of the memory controller. This allows for error correction and data recovery when errors occur while reading certain user data, using the check data stored in the check bits or check buffer. In some embodiments, check data is typically calculated using algorithms such as Hamming codes or XOR operations. In this embodiment, utilizing the protection function of check data can significantly improve read performance. It should be noted that the check data described below is stored in some storage units (check bits) of the memory device.

[0066] Here, parity checking is a method for verifying the correctness of transmitted codes. It checks the number of "1"s in a transmitted binary code set based on whether it is odd or even. Using an odd number is called odd parity, and vice versa, it's called even parity. The parity method used is predetermined. Typically, a dedicated parity bit is used to ensure the number of "1"s in the code set is either odd or even. If odd parity is used, when the receiving end receives the code set, it checks whether the number of "1"s is odd, thus determining the correctness of the transmitted code. The data stored in this parity bit is called parity check data.

[0067] It should be noted that there are many other ways to protect user data redundancy; here, we will only use the method of verifying data as an example.

[0068] In some specific embodiments, during the programming (writing user data) process, checksum data is generated by performing an XOR operation (operator XOR) on user data located on the same page or the same storage chip. This checksum data is then stored in the checksum bit of the corresponding page or storage chip (usually the last numbered storage cell). It should be understood that the checksum data can only correct or recover erroneous data in the corresponding storage cell, and one checksum data can only correct or recover one erroneous data item. For example, refer to... Figure 6a , Figure 6a A schematic diagram of a storage cell structure is shown, illustrating a page corresponding to one parity data. The memory system includes one or more memory devices, each memory device including one or more memory chips 601, and each memory chip 601 including multiple word lines (WL0 to WLN). User data (X) in multiple storage cells coupled to the same word line WL corresponds to one parity data (P). When an erroneous data appears in multiple storage cells coupled to a word line, the erroneous data can be corrected or recovered using the parity data corresponding to that word line. However, when two or more erroneous data appear in multiple storage cells coupled to the same word line, it is impossible to correct or recover these two or more erroneous data using the parity data corresponding to that word line.

[0069] Based on this, the present disclosure provides another method for setting verification data, such as assigning multiple storage units coupled to the same word line to corresponding multiple verification data; for example, refer to Figure 6b , Figure 6bA schematic diagram of a storage unit structure showing multiple parity data per page is shown. The memory device includes one or more memory chips 602, each memory chip 602 including multiple word lines (WL0 to WLN), each word line coupled to six memory chips (Str0, Str1, Str2, Str3, Str4, Str5); each memory chip includes four memory cells (Cell1, Cell2, Cell3, Cell4), a portion of the memory cells (Cell1, Cell2, Cell3) of each memory chip are used to store user data (X1, X2, X3), and the parity bit (Cell4) is used to store... The storage uses parity data (P0), which is obtained by XORing all user data (X1, X2, X3) in a storage chip. Therefore, when an erroneous data appears in multiple storage cells coupled to a storage chip, the corresponding parity data (P0) can be used to correct or recover the erroneous data. In other words, when two or more erroneous data appear in user data in multiple storage cells coupled to the same word line, and these two or more erroneous data are stored in different storage chips, the corresponding two or more parity data for each storage chip can be used to correct or recover the erroneous data. However, if... Figure 6b As shown, each storage chip corresponds to a parity data, which results in the parity data coupled to the same word line occupying a large amount of storage space, thus wasting storage resources.

[0070] Based on this, another method for setting verification data is provided in this embodiment. The memory device includes one or more memory chips, each memory chip including multiple word lines; each word line is coupled to multiple memory chips; the multiple memory chips coupled to each word line are divided into a first memory chip region and a second memory chip region; each word line corresponds to at least one redundant stripe, the redundant stripe including a first redundant stripe, the first redundant stripe being configured to: store first verification data; the first verification data is obtained by error correction encoding of data in the first memory chip region of the word line containing the first redundant stripe and data in the second memory chip region adjacent to the word line containing the first redundant stripe; and a memory controller, coupled to the memory device and configured to: when multiple erroneous data appear in the multiple memory chips coupled to a word line, correct the error using the first verification data stored in the redundant stripe corresponding to the corresponding word line and the first verification data stored in the redundant stripe corresponding to the word line adjacent to the corresponding word line.

[0071] In some embodiments, the redundant stripe further includes a second redundant stripe, which is configured to store second check data. The second check data is obtained by error-correcting encoding data in a first memory chip region or a second memory chip region of the word line where the second redundant stripe is located. The memory controller is further configured to: when multiple erroneous data occur in multiple memory chips coupled to a word line, correct the data by using the second check data stored in the redundant stripe corresponding to the corresponding word line and the first check data stored in the redundant stripe corresponding to the word line adjacent to the corresponding word line; or, correct the data by using the first check data and the second check data stored in the redundant stripe corresponding to the corresponding word line.

[0072] refer to Figure 7 , Figure 7 A block diagram of a memory system is shown. The memory system 701 includes a memory controller 702 and a memory device 703. The memory controller 702 controls the memory device 703 to perform read, write, and erase operations. The memory controller 702 and the memory device 703 can be coupled in any suitable manner. In this embodiment, the memory device 703 can be a non-volatile semiconductor memory, such as a NAND flash memory. The memory system 701 is connected to a host 704, which can be an electronic device such as a personal computer or a mobile terminal. The host I / F 7021 outputs commands and user data (written data) received from the host 704 to the internal bus 7020, and sends user data read from the memory device 703 and responses from the control unit 7023 back to the host 704.

[0073] The memory I / F 7022 controls the processes of writing user data to and reading data from the memory device 703 based on instructions from the control unit 7023. The control unit 7023, such as a central processing unit (CPU) or microprocessor (MPU), controls the memory system 701 as a whole. The control unit 7023 performs control according to commands received from the host 704 via the host I / F 7021. For example, the control unit 7023 instructs the memory I / F 7022 to write user data and parity data to the memory device 703 based on commands from the host 704. Furthermore, the control unit 7023 instructs the memory I / F 7022 to read user data and parity data from the memory device 703 based on commands from the host 704.

[0074] The Error Correction (ECC) module 7024 includes an encoding unit 7025, a decoding unit 7026, and a parity buffer 7027. The encoding unit 7025 encodes a predetermined amount of user data written on the same page to generate parity data. The parity data is written to the page containing the user data that forms the basis of the encoding, and the decoding unit 7026 uses this parity data for decoding. The parity buffer 7027 can be used to store the parity data.

[0075] The data buffer 7028 temporarily stores user data received from the host 704 before storing it in the memory device 703, and temporarily stores data read from the memory device 703 before sending it to the host 704.

[0076] As previously described, a memory device may include one or more memory dies, each memory die may include multiple memory blocks, each memory block may include multiple memory slices, and each memory slice may include multiple memory cells. Additionally, each memory die may include multiple word lines (WLs), and each word line (WL) is coupled to multiple memory cells. In other words, a word line can be coupled to memory cells in multiple memory slices; here, multiple memory slices coupled to the same word line may be located in the same memory block or in different memory blocks.

[0077] In this embodiment of the disclosure, the multiple memory chips coupled to each word line are divided into two regions: a first memory chip region and a second memory chip region. The first and second memory chip regions can be located in the same memory block or in different memory blocks. Furthermore, the number of memory chips in the first memory chip region can be the same as or different from the number of memory chips in the second memory chip region.

[0078] In some specific embodiments, each memory chip includes (N+1) word lines; each word line is coupled to M memory chips; each memory chip includes L memory cells. The M memory chips coupled to the same word line are divided into a first memory chip region and a second memory chip region, with each region containing the same number of memory chips, i.e., M / 2.

[0079] For example, refer to Figure 8The memory device includes multiple memory chips 800, each memory chip 800 including (N+1) word lines, where the (N+1) word lines are numbered according to their physical positions from the 0th word line to the Nth word line; for example, word line 0 WL0, word lines 1 WL1 to 1 N WLN. Each word line is coupled to 6 memory chips, which are arranged sequentially from memory chip 0 to memory chip 5, such as memory chip 0 Str0, memory chip 1 Str1, memory chip 2 Str2, memory chip 3 Str3, memory chip 4 Str4, and memory chip 5 Str5; each memory chip includes 4 memory cells, which are arranged sequentially from memory cell 1 to memory cell 4, such as memory cell 1 Cell1, memory cell 2 Cell2, memory cell 3 Cell3, and memory cell 4 Cell4. It should be noted that... Figure 8 The illustration only shows, by way of example, that each memory chip includes 6 memory chips and each memory chip includes 4 memory cells (i.e., M=6, L=4). However, it should be understood that each memory chip may include more memory chips, such as 12, 24, 32, etc., and each memory chip may include more memory cells, such as 32, 64, 128, etc.

[0080] In this embodiment of the present disclosure, the six memory chips coupled to each word line are divided into a first memory chip region 801 and a second memory chip region 802. The number of memory chips in the first memory chip region 801 and the second memory chip region 802 is the same, which is three in each case. The first memory chip region 801 includes memory chip 0 (Str0), memory chip Str1, and memory chip Str2. The second memory chip region 802 includes memory chip Str3, memory chip Str4, and memory chip Str5.

[0081] Each storage chip has four storage cells, which can be used to store user data, or to store user data and checksum data (P1 or P2) separately. User data can be further divided into initial data (S1 or S2) and non-initial data (X). Initial data (S1 or S2) is stored in the first storage cell of the storage chip. Additionally, a checksum data item can correspond to user data in one storage chip or to user data in multiple storage chips.

[0082] In this embodiment, each word line corresponds to at least one redundant stripe, which is used to store parity data. Depending on the type of parity data stored, the redundant stripe may include a first redundant stripe and a second redundant stripe; the first redundant stripe stores first parity data; and the second redundant stripe stores second parity data. The first redundant stripe may include multiple storage units, each of which stores one piece of first parity data; the second redundant stripe may also include multiple storage units, each of which stores one piece of second parity data. Here, the number of first and second parity data pieces is related to the number of storage chips in the corresponding storage chip region.

[0083] The first check data is obtained by error-correcting and encoding the data in the first memory chip region of the word line where the first redundant stripe is located and the data in the second memory chip region of the adjacent word line. Specifically, one set of first check data in the first redundant stripe is obtained by error-correcting and encoding the user data stored in one memory chip in the first memory chip region of the word line where the first redundant stripe is located and the user data stored in one memory chip in the second memory chip region of the adjacent word line. It should be understood that one set of first check data corresponds to the user data stored in two memory chips. In other words, error-correcting and encoding (such as XOR operation) the user data stored in two memory chips coupled to two word lines respectively yields one set of first check data. Here, the number of first check data is related to the number of memory chips in the first memory chip region of the word line where the first redundant stripe is located and the number of memory chips in the second memory chip region of the adjacent word line.

[0084] Similarly, the second check data is obtained by error-correcting and encoding the data in the first or second memory chip region of the word line containing the second redundant stripe. Specifically, one set of second check data is obtained by error-correcting and encoding the user data stored in one memory chip within the first memory chip region of the word line containing the second redundant stripe, or by error-correcting and encoding the user data stored in one memory chip within the second memory chip region of the word line containing the second redundant stripe. It should be understood that the number of second check data corresponds to the number of user data stored in one memory chip. In other words, error-correcting and encoding (such as XOR operation) the user data stored in one memory chip yields one set of second check data. Here, the number of second check data is related to the number of memory chips in the first memory chip region of the word line containing the second redundant stripe, or the number of memory chips in the second memory chip region of the word line containing the second redundant stripe.

[0085] In some specific embodiments, the memory chip includes a first redundant stripe and a second redundant stripe. Multiple first parity data coupled to the same word line constitute a first redundant stripe; multiple second parity data coupled to the same word line constitute a second redundant stripe.

[0086] Among them, the 0th word line corresponds to a second redundant stripe, and the second check data is obtained by error correction encoding of the data in the first storage area of ​​the 0th word line;

[0087] Each of the first word lines to the (N-1)th word line corresponds to a first redundant stripe. Each first check data is obtained by error correction encoding of the data in the first memory area of ​​the corresponding word line and the data in the second memory area of ​​the word line above the corresponding word line.

[0088] The Nth word line corresponds to a first redundant stripe and a second redundant stripe. The first check data is obtained by error correction encoding of the data in the first storage area of ​​the Nth word line and the data in the second storage area of ​​the (N-1)th word line. The second check data is obtained by error correction encoding of the data in the second storage area of ​​the Nth word line.

[0089] For example, refer to Figure 8 , Figure 8 The memory chip 800 shown includes multiple first redundant stripes 803 and multiple second redundant stripes 804; multiple memory cells coupled to the same word line for storing first parity data constitute a first redundant stripe 803. Figure 8 As shown, each first redundancy stripe 803 includes three fourth storage units Cell4, each of which stores a first parity data P1. Here, the first parity data P1 in the first redundancy stripe 803 corresponding to the first word line WL1 is obtained by jointly error-correcting the user data in one storage cell of the first storage chip region 801 (Str0, Str1, Str2) coupled to the first word line WL1, and the user data in one storage cell of the second storage chip region 802 (Str3, Str4, Str5) in the 0th word line WL0.

[0090] It should be noted that the memory chip corresponding to the first verification data P1 can be any memory chip in the corresponding memory chip area. For clarity, the correspondence between the verification data and the memory chips is shown in numerical order.

[0091] For example, the first first check data P1 in the first redundant stripe 803 corresponding to the first word line WL1 is obtained by jointly error-correcting the user data in the 0th memory block Str0 in the first memory block region 801 coupled to the first word line WL1, and the user data in the third memory block Str3 in the second memory block region 802 of the 0th word line WL0.

[0092] For example, the second first check data P1 in the first redundant stripe 803 corresponding to the first word line WL1 is obtained by jointly error-correcting the user data in the first memory chip Str1 in the first memory chip region 801 coupled to the first word line WL1, and the user data in the fourth memory chip Str4 in the second memory chip region 802 of the 0th word line WL0. This process is repeated sequentially according to the numbering order, with each first check data corresponding to user data in two memory chips coupled to the two word lines respectively.

[0093] In the memory chip 800, the first check data in the first redundant stripe corresponding to the Nth word line is obtained by error correction encoding of the data in the first memory chip region of the Nth word line and the data in the second memory chip region of the (N-1)th word line. The correspondence method is the same as in the aforementioned embodiment and will not be repeated here.

[0094] It should be noted that the data in each memory chip region of the first memory chip region of the 0th word line and the second memory chip region of the Nth word line are error-corrected and encoded to obtain a second parity data. Multiple memory cells coupled to the same word line for storing the second parity data constitute a second redundancy stripe.

[0095] refer to Figure 8 Each second redundant stripe 804 includes three fourth storage cells Cell4, each of which stores a second parity data P2. Each second parity data P2 is obtained by error correction encoding of user data in a storage cell in the first storage cell region of the word line where the second redundant stripe is located or user data in a storage cell in the second storage cell region.

[0096] Specifically, the second check data P2 in the second redundant stripe 804 corresponding to the 0th word line WL0 is obtained by error correction encoding of user data in a storage chip in the first storage chip region 801 coupled to the 0th word line WL0; or, the second check data P2 in the second redundant stripe 804 corresponding to the Nth word line WLN is obtained by error correction encoding of user data in a storage chip in the second storage chip region 802 coupled to the Nth word line WLN.

[0097] For example, the first second check data P2 in the second redundancy stripe 804 corresponding to the 0th word line WL0 is obtained by error-correcting encoding the user data in the 0th memory chip Str0 of the first memory chip region 801 coupled to the 0th word line WL0. The second second check data P2 in the second redundancy stripe 804 corresponding to the 0th word line WL0 is obtained by error-correcting encoding the user data in the 1st memory chip Str1 of the first memory chip region 801 coupled to the 0th word line WL0.

[0098] For example, the first second check data P2 in the second redundancy stripe 804 corresponding to the Nth word line WLN is obtained by error-correcting and encoding user data in the third memory chip Str3 in the second memory chip region 802 coupled to the Nth word line WLN. The second second check data P2 in the second redundancy stripe 804 corresponding to the Nth word line WLN is obtained by error-correcting and encoding user data in the fourth memory chip Str4 in the second memory chip region 802 coupled to the Nth word line WLN. This process continues sequentially according to the numbering order, with each second check data corresponding to user data in a memory chip coupled to the same word line.

[0099] In some embodiments, the ratio of the number of memory cells occupied by redundant stripes in each memory chip to the total number of memory cells in the memory chip is: (N+2)(M / 2) / (N+1)*M*L. Thus, compared to each memory chip corresponding to one set of parity data, i.e., the ratio of the number of memory cells occupied by redundant stripes in each memory chip to the total number of memory cells in the memory chip is: (N+1)*M*1 / (N+1)*M*L=1 / L, this approach ensures that when two errors occur in multiple memory chip regions coupled to the same word line, it can correct two errors using parity data from different redundant stripes corresponding to the two word lines, while also saving storage space occupied by the parity data. In other words, it can improve error correction capability and enhance the reliability of the memory device while reducing the amount of parity data and its occupied storage space, thereby improving the utilization rate of memory resources.

[0100] In some embodiments, the 0th word line corresponds to a set of first starting data and a set of second starting data; the first starting data includes data stored in the first storage cell of each storage chip in the second storage chip region of the 0th word line; the second starting data includes data stored in the first storage cell of each storage chip in the first storage chip region of the 0th word line; each of the 1st to the (N-1th)th word lines corresponds to a set of first starting data, and each set of first starting data includes data stored in the first storage cell of each storage chip in the second storage chip region of the corresponding word line; the Nth word line corresponds to a set of second starting data, and the second starting data includes data stored in the first storage cell of each storage chip in the second storage chip region of the Nth word line.

[0101] For example, refer to Figure 8 The memory chip 800 includes multiple sets of first starting data 805 and multiple sets of second starting data 806. Each set of first starting data 805 includes three first starting data S1s, each corresponding to a first check data P1 of its respective memory chip. Each first starting data S1 is the first user data among all user data used for error correction encoding (such as XOR operation) to obtain the first check data P1. Similarly, each set of second starting data 806 includes three second starting data S2s, each corresponding to a second check data P2 of its respective memory chip. Each second starting data S2 is the first user data among all user data used for error correction encoding (such as XOR operation) to obtain the second check data P2.

[0102] It should be noted that, in order to distinguish between the initial data and non-initial data in the user data, Figure 8 The first starting data is represented by "S1", the second starting data by "S2", and all non-starting data are represented by "X".

[0103] In some embodiments, when the memory chip includes only two word lines, that is, the memory chip includes a 0th word line and a 1st word line numbered according to physical location; wherein, the 0th word line corresponds to a second redundancy stripe, and the second check data is obtained by error correction encoding of the data in the first memory chip area of ​​the 0th word line; the 1st word line corresponds to a first redundancy stripe and a second redundancy stripe, and the first check data is obtained by error correction encoding of the data in the first memory chip area of ​​the 1st word line and the data in the second memory chip area of ​​the 0th word line, and the second check data is obtained by error correction encoding of the data in the second memory chip area of ​​the 1st word line.

[0104] For example, refer to Figure 9The memory chip 900 includes a 0th word line WL0 and a 1st word line WL1. The 0th word line WL0 corresponds to a second redundancy stripe 804. The second redundancy stripe 804 includes three second check data P2. The first second check data P2 is obtained by error correction encoding of the user data stored in the 0th memory chip Str0 in the first memory chip region of the 0th word line WL0. The second second check data P2 is obtained by error correction encoding of the user data stored in the first memory chip Str1 in the first memory chip region of the 0th word line WL0. The third second check data P2 is obtained by error correction encoding of the user data stored in the second memory chip Str2 in the first memory chip region of the 0th word line WL0.

[0105] The first word line WL1 corresponds to a first redundant stripe 803 and a second redundant stripe 804. Each first redundant stripe 803 includes three first check data P1s, and each second redundant stripe 804 includes three second check data P2s. For example, the first check data P1 is obtained by performing joint error correction encoding on the data stored in the 0th memory chip Str0 of the first memory chip region 801 of the first word line WL1 and the data stored in the third memory chip Str3 of the second memory chip region 802 of the 0th word line WL0, and so on. Similarly, the first second check data P2 is obtained by performing error correction encoding on the data stored in the third memory chip Str3 of the second memory chip region 802 of the first word line WL1, and so on.

[0106] Based on this, in this embodiment of the disclosure, the multiple memory chips coupled to each word line are divided into a first memory chip region and a second memory chip region; the first memory chip region coupled to the first word line in the multiple word lines corresponds to a second redundant stripe; the second memory chip region coupled to the first word line and the first memory chip region coupled to the second word line correspond to a first redundant stripe; the second memory chip region coupled to the second word line and the first memory chip region coupled to the third word line correspond to a first redundant stripe; and so on, the first memory chip region coupled to the last word line and the second memory chip region coupled to the word line preceding the last word line correspond to a first redundant stripe; the second memory chip region coupled to the last word line corresponds to a second redundant stripe; in this... In this configuration, for all word lines between the first and last word lines, each pair of word lines can couple a memory chip region to form a first redundant stripe, while the remaining memory chip regions coupled to the first and last word lines can each form a second redundant stripe. This approach offers several advantages: firstly, when an error occurs in each of the two memory chip regions coupled to the same word line, the two first checksums corresponding to the same word line can be used to correct the two errors, improving error correction capability and enhancing the reliability of the memory device. Secondly, since each of the two memory chip regions coupled to a different word line corresponds to a first redundant stripe, the number of first redundant stripes and the space they occupy are reduced, improving the utilization rate of memory resources.

[0107] Based on the above-described memory system, this disclosure also provides a memory device, including:

[0108] A memory chip includes multiple word lines; multiple memory chips coupled to each word line are divided into a first memory chip region and a second memory chip region; each word line corresponds to at least one redundant stripe, the redundant stripe including a first redundant stripe, the first redundant stripe being configured to store first check data; the first check data is obtained by error correction encoding of data in the first memory chip region of the word line where the first redundant stripe is located and data in the second memory chip region of the word line adjacent to the word line.

[0109] In some embodiments, the redundant stripe further includes a second redundant stripe, which is configured to store second check data; the second check data is obtained by error correction encoding of data in a first memory slice area or a second memory slice area of ​​the word line where the second redundant stripe is located.

[0110] In some embodiments, the memory chip includes word lines 0 to N, numbered according to physical location; the memory chip is programmed sequentially from word lines 0 to N; N is an integer greater than 1; the 0th word line corresponds to a second redundancy stripe, and the second check data is obtained by error correction encoding of data in the first memory chip region of the 0th word line; each of the 1st to (N-1th)th word lines corresponds to a first redundancy stripe, and each first check data is obtained by error correction encoding of data in the first memory chip region of the corresponding word line and data in the second memory chip region of the previous word line; the Nth word line corresponds to a first redundancy stripe and a second redundancy stripe, and the first check data is obtained by error correction encoding of data in the first memory chip region of the Nth word line and data in the second memory chip region of the (N-1th)th word line, and the second check data is obtained by error correction encoding of data in the second memory chip region of the Nth word line.

[0111] In some embodiments, the 0th word line corresponds to a set of first starting data and a set of second starting data; the first starting data includes data stored in the first storage cell of each storage chip in the second storage chip region of the 0th word line; the second starting data includes data stored in the first storage cell of each storage chip in the first storage chip region of the 0th word line; each of the 1st to the (N-1th)th word lines corresponds to a set of first starting data, and each set of first starting data includes data stored in the first storage cell of each storage chip in the second storage chip region of the corresponding word line; the Nth word line corresponds to a set of second starting data, and the second starting data includes data stored in the first storage cell of each storage chip in the second storage chip region of the Nth word line.

[0112] In some embodiments, the memory chip includes a 0th word line and a 1st word line numbered according to their physical locations; the 0th word line corresponds to a second redundancy stripe, and the second check data is obtained by error correction encoding of the data in the first memory chip region of the 0th word line; the 1st word line corresponds to a first redundancy stripe and a second redundancy stripe, and the first check data is obtained by error correction encoding of the data in the first memory chip region of the 1st word line and the data in the second memory chip region of the 0th word line, and the second check data is obtained by error correction encoding of the data in the second memory chip region of the 1st word line.

[0113] In some embodiments, the number of memory chips in the first memory chip region is the same as the number of memory chips in the second memory chip region.

[0114] In some embodiments, each of the memory chips includes (N+1) word lines; each word line is coupled to M memory chips; each memory chip includes L memory cells; wherein the ratio of the number of memory cells occupied by the redundant stripes in each memory chip to the total number of memory cells in the memory chip is: (N+2)(M / 2) / (N+1)*M*L.

[0115] In some embodiments, the first memory chip region and the second memory chip region coupled to each of the word lines are located in the same memory block, or they are located in different memory blocks.

[0116] Based on the above-described memory system, this disclosure also provides an operation method for the memory system, the memory system comprising: a memory device; the memory device comprising a memory chip, the memory chip comprising multiple word lines; multiple memory chips coupled to each word line being divided into a first memory chip region and a second memory chip region; each word line corresponding to at least one redundant stripe, the redundant stripe comprising a first redundant stripe, the first redundant stripe being configured to: store first parity data; the first parity data being obtained by error correction encoding of data in the first memory chip region of the word line where the first redundant stripe is located and data in the second memory chip region of the word line adjacent to the word line where the first redundant stripe is located; and a memory controller coupled to the memory device;

[0117] The operation method includes: when multiple erroneous data occur in multiple memory chips coupled to a word line, correction is performed using the first check data stored in the redundant stripe corresponding to the corresponding word line and the first check data stored in the redundant stripe corresponding to the word line adjacent to the corresponding word line.

[0118] In some embodiments, the redundant stripe further includes a second redundant stripe, which is configured to store second check data. The second check data is obtained by error-correcting encoding data in a first memory chip region or a second memory chip region of the word line where the second redundant stripe is located. The operation method includes: when multiple erroneous data occur in multiple memory chips coupled to a word line, correcting the data using the second check data stored in the redundant stripe corresponding to the corresponding word line and the first check data stored in the redundant stripe corresponding to the word line adjacent to the corresponding word line; or, correcting the data using the first check data and the second check data stored in the redundant stripe corresponding to the corresponding word line.

[0119] This disclosure also provides a storage medium storing executable instructions, which, when executed by a memory controller, can implement the steps of the method described in the above embodiments of this disclosure.

[0120] In some specific embodiments, the storage medium may be a magnetic random access memory (FRAM), a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), a flash memory, a magnetic surface memory, an optical disc, or a compact disc read-only memory (CD-ROM), etc.; or it may be a device that includes one or any combination of the above-mentioned memory devices.

[0121] In some embodiments, executable instructions may take the form of a program, software, software module, script, or code, written in any form of programming language (including compiled or interpreted languages, or declarative or procedural languages), and may be deployed in any form, including as a standalone program or as a module, component, subroutine, or other unit suitable for use in a computing environment.

[0122] As an example, executable instructions may, but do not necessarily, correspond to files in a file system. They may be stored as part of a file that holds other programs or data, for example, in one or more scripts in a Hyper Text Markup Language (HTML) document, in a single file dedicated to the program in question, or in multiple collaborative files (e.g., a file that stores one or more modules, subroutines, or code sections).

[0123] It should be noted that terms such as "first" and "second" are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. Furthermore, the technical solutions described in the embodiments of this disclosure can be combined arbitrarily without conflict.

[0124] The above description is merely a preferred embodiment of this disclosure and is not intended to limit the scope of protection of this disclosure.

Claims

1. A memory device, characterized in that, include: A memory chip, the memory chip including multiple word lines; Each word line coupled to multiple memory chips is divided into a first memory chip region and a second memory chip region; Each word line corresponds to at least one redundant stripe, the redundant stripe including a first redundant stripe, the first redundant stripe being configured to store first check data; the first check data is obtained by error correction encoding of data in a first storage area of ​​the word line where the first redundant stripe is located and data in a second storage area of ​​a word line adjacent to the word line where the first redundant stripe is located.

2. The memory device according to claim 1, characterized in that, The redundant stripe also includes a second redundant stripe, which is configured to store second check data. The second check data is obtained by error correction encoding of data in the first or second storage area of ​​the word line where the second redundant stripe is located.

3. The memory device according to claim 2, characterized in that, The memory chip includes word lines numbered from the 0th to the Nth word lines according to their physical location; The memory chip is programmed sequentially from word line 0 to word line N; N is an integer greater than 1; The 0th word line corresponds to a second redundant stripe, and the second check data is obtained by error correction encoding of the data in the first storage area of ​​the 0th word line; Each of the first word lines to the (N-1)th word line corresponds to a first redundant stripe. Each first check data is obtained by error correction encoding of the data in the first memory area of ​​the corresponding word line and the data in the second memory area of ​​the word line above the corresponding word line. The Nth word line corresponds to a first redundant stripe and a second redundant stripe. The first check data is obtained by error correction encoding of the data in the first storage area of ​​the Nth word line and the data in the second storage area of ​​the (N-1)th word line. The second check data is obtained by error correction encoding of the data in the second storage area of ​​the Nth word line.

4. The memory device according to claim 3, characterized in that, The 0th word line corresponds to a first set of starting data and a second set of starting data; the first starting data includes the data stored in the first storage cell of each storage chip in the second storage chip region of the 0th word line; the second starting data includes the data stored in the first storage cell of each storage chip in the first storage chip region of the 0th word line. Each of the first word lines to the (N-1)th word lines corresponds to a set of the first starting data, and each set of the first starting data includes the data stored in the first storage cell of each storage chip in the second storage chip region of the corresponding word line; The Nth word line corresponds to a set of second starting data, which includes the data stored in the first storage cell of each storage chip in the second storage chip region of the Nth word line.

5. The memory device according to claim 2, characterized in that, The memory chip includes a 0th word line and a 1st word line, numbered according to their physical location; The 0th word line corresponds to a second redundant stripe, and the second check data is obtained by error correction encoding of the data in the first storage area of ​​the 0th word line; The first word line corresponds to a first redundant stripe and a second redundant stripe. The first check data is obtained by error correction encoding of the data in the first storage area of ​​the first word line and the data in the second storage area of ​​the 0th word line. The second check data is obtained by error correction encoding of the data in the second storage area of ​​the first word line.

6. The memory device according to claim 1, characterized in that, The number of memory chips in the first memory chip region is the same as the number of memory chips in the second memory chip region.

7. The memory device according to claim 6, characterized in that, Each of the memory chips includes (N+1) word lines; each word line is coupled to M memory chips; each memory chip includes L memory cells; Wherein, the ratio of the number of storage cells occupied by the redundant stripes in each of the storage chips to the total number of storage cells in the storage chip is: (N+2)(M / 2) / (N+1)*M*L.

8. The memory device according to claim 1, characterized in that, The first and second memory chip regions coupled to each of the word lines are located in the same memory block, or in different memory blocks.

9. A memory system, characterized in that, include: Memory devices; The memory device includes a memory chip, and the memory chip includes multiple word lines; Each word line coupled to multiple memory chips is divided into a first memory chip region and a second memory chip region; Each word line corresponds to at least one redundant stripe, the redundant stripe including a first redundant stripe, the first redundant stripe being configured to store first check data; the first check data is obtained by error correction encoding of data in a first storage area of ​​the word line where the first redundant stripe is located and data in a second storage area of ​​a word line adjacent to the word line where the first redundant stripe is located; as well as A memory controller, coupled to the memory device and configured to: When multiple erroneous data occur in multiple memory chips coupled to a word line, correction is performed using the first check data stored in the redundant stripe corresponding to the corresponding word line and the first check data stored in the redundant stripe corresponding to the word line adjacent to the corresponding word line.

10. The memory system according to claim 9, characterized in that, The redundant stripe further includes a second redundant stripe, which is configured to store second parity data. The second parity data is obtained by error correction encoding of data in the first or second memory slice area of ​​the word line where the second redundant stripe is located. The memory controller is also configured to: When multiple erroneous data occur in multiple memory chips coupled to a word line, correction is performed using the second check data stored in the redundant stripe corresponding to the corresponding word line and the first check data stored in the redundant stripe corresponding to the word line adjacent to the corresponding word line; or, correction is performed using the first check data and the second check data stored in the redundant stripe corresponding to the corresponding word line.

11. The memory system according to claim 10, characterized in that, The memory chip includes word lines 0 to N, numbered according to their physical locations; the memory chip is programmed sequentially from word lines 0 to N. N is an integer greater than 1; The 0th word line corresponds to a second redundant stripe, and the second check data is obtained by error correction encoding of the data in the first storage area of ​​the 0th word line; Each of the first word lines to the (N-1)th word line corresponds to a first redundant stripe. Each first check data is obtained by error correction encoding of the data in the first memory area of ​​the corresponding word line and the data in the second memory area of ​​the word line above the corresponding word line. The Nth word line corresponds to a first redundant stripe and a second redundant stripe. The first check data is obtained by error correction encoding of the data in the first storage area of ​​the Nth word line and the data in the second storage area of ​​the (N-1)th word line. The second check data is obtained by error correction encoding of the data in the second storage area of ​​the Nth word line.

12. The memory system according to claim 11, characterized in that, The 0th word line corresponds to a first set of starting data and a second set of starting data; the first starting data includes the data stored in the first storage cell of each storage chip in the second storage chip region of the 0th word line; the second starting data includes the data stored in the first storage cell of each storage chip in the first storage chip region of the 0th word line. Each of the first word lines to the (N-1)th word lines corresponds to a set of the first starting data, and each set of the first starting data includes the data stored in the first storage cell of each storage chip in the second storage chip region of the corresponding word line; The Nth word line corresponds to a set of second starting data, which includes the data stored in the first storage cell of each storage chip in the second storage chip region of the Nth word line.

13. The memory system according to claim 10, characterized in that, The memory chip includes a 0th word line and a 1st word line, numbered according to their physical location; The 0th word line corresponds to a second redundant stripe, and the second check data is obtained by error correction encoding of the data in the first storage area of ​​the 0th word line; The first word line corresponds to a first redundant stripe and a second redundant stripe. The first check data is obtained by error correction encoding of the data in the first storage area of ​​the first word line and the data in the second storage area of ​​the 0th word line. The second check data is obtained by error correction encoding of the data in the second storage area of ​​the first word line.

14. The memory system according to claim 9, characterized in that, The number of memory chips in the first memory chip region is the same as the number of memory chips in the second memory chip region.

15. The memory system according to claim 14, characterized in that, Each of the memory chips includes (N+1) word lines; each word line is coupled to M memory chips; each memory chip includes L memory cells; Wherein, the ratio of the number of storage cells occupied by the redundant stripes in each of the storage chips to the total number of storage cells in the storage chip is: (N+2)(M / 2) / (N+1)*M*L.

16. The memory system according to claim 9, characterized in that, The first and second memory chip regions coupled to each of the word lines are located in the same memory block, or in different memory blocks.

17. A method for operating a memory system, characterized in that, The memory system includes: a memory device; the memory device includes a memory chip, the memory chip including multiple word lines; multiple memory chips coupled to each word line are divided into a first memory chip region and a second memory chip region; Each word line corresponds to at least one redundant stripe, the redundant stripe including a first redundant stripe, the first redundant stripe being configured to: store first check data; the first check data is obtained by error correction encoding of data in a first storage area of ​​the word line containing the first redundant stripe and data in a second storage area of ​​adjacent word lines; and A memory controller, coupled to the memory device; The operation method includes: When multiple erroneous data occur in multiple memory chips coupled to a word line, correction is performed using the first check data stored in the redundant stripe corresponding to the corresponding word line and the first check data stored in the redundant stripe corresponding to the word line adjacent to the corresponding word line.

18. The operating method according to claim 17, characterized in that, The redundant stripe further includes a second redundant stripe, which is configured to store second parity data. The second parity data is obtained by error correction encoding of data in the first or second memory slice area of ​​the word line where the second redundant stripe is located. The operation method includes: When multiple erroneous data occur in multiple memory chips coupled to a word line, correction is performed using the second check data stored in the redundant stripe corresponding to the corresponding word line and the first check data stored in the redundant stripe corresponding to the word line adjacent to the corresponding word line; or, correction is performed using the first check data and the second check data stored in the redundant stripe corresponding to the corresponding word line.

19. A storage medium, characterized in that, The storage medium stores executable instructions, which, when executed by the memory controller, can implement the steps of the method as described in any one of claims 17-18.

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