Apparatus including a BTI controller

Abstract

In accordance with one or more embodiments of the present disclosure, an apparatus includes a memory device and a bias temperature instability (BTI) controller. The BTI controller generates and outputs a command and address signal for memory testing. The command and address signals cause the memory device in an idle state to operate for the testing.

Description

Technical Field

[0001] The present disclosure relates to a device including a BTI controller. Background Art

[0002] Bias temperature instability (BTI) is one of the important reliability factors in semiconductor devices, such as memory devices. During low power modes or during high temperature, high voltage testing, non-uniform electrical stress on the circuits of a memory device can lead to increased susceptibility of the device to, in particular, negative BTI (NBTI). NBTI can lead to device performance degradation, including increased transistor threshold voltage. For example, the switching speed of the device may be slowed due to the degradation of NBTI. As the threshold voltage becomes higher, the switching speed may be further slowed. Therefore, a technology is needed to reduce non-uniform electrical stress and alleviate the device performance degradation caused by BTI (such as NBTI). Summary of the invention

[0003] One aspect of the present disclosure relates to an apparatus comprising: a memory device; and a bias temperature instability (BTI) controller configured to generate and output command and address signals for a memory test, wherein the command and address signals operate the memory device in an idle state to perform the test.

[0004] Another aspect of the present disclosure relates to an apparatus comprising: a memory device; and a bias temperature instability (BTI) controller configured to generate command and address signals for memory testing, wherein the command and address signals supplied to the memory device in an idle state cause a memory command and address latch circuit to output internal signals to a memory body logic circuit and a memory data latch circuit in response to the received command and address signals.

[0005] Yet another aspect of the present disclosure relates to a bias temperature instability (BTI) controller for a memory device, comprising: a sequencer configured to generate a sequence command signal in response to a switching clock signal, wherein the sequence command signal identifies a memory test operation sequence at a first timing; and a formatter configured to generate command and address signals according to a certain format at a second timing based on the sequence command signal and the switching clock signal, wherein the command and address signals align command and address transition timing with the switching clock signal and can be decoded by a command and address control circuit of the memory device to obtain command and address information. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figure 1 is a block diagram of an example device according to an embodiment of the present disclosure.

[0007] Figure 2is a block diagram of an example device according to an embodiment of the present disclosure.

[0008] Figure 3 is a block diagram of an example command and address latch according to an embodiment of the present disclosure.

[0009] Figure 4 is a block diagram of an example signal pattern generator according to an embodiment of the present disclosure.

[0010] Figure 5 is a diagram of example signal waveforms for NBTI control according to an embodiment of the present disclosure.

[0011] Figure 6 is a flow chart of an example channel deactivation mode functionality according to an embodiment of the present disclosure.

[0012] Figure 7 is a block diagram of an example device according to an embodiment of the present disclosure.

[0013] Figure 8 Depicted is a schematic configuration of an example semiconductor system according to an embodiment of the present disclosure.

[0014] Fig. 9 is a block diagram of an example semiconductor system according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0015] Various example embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. The following detailed description refers to the accompanying drawings, which show, by way of illustration, specific aspects of the embodiments in which the present disclosure may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the present disclosure. Other embodiments may be utilized, and structural, logical, and electrical changes may be made without departing from the scope of the present disclosure. The various embodiments disclosed herein are not necessarily mutually exclusive, as some disclosed embodiments may be combined with one or more other disclosed embodiments to form new embodiments.

[0016] In the description, common or related elements and substantially the same elements are represented by the same symbols, and their descriptions may be reduced or omitted. In the drawings, for the convenience of description, some of the same symbols may be omitted for the same or substantially the same elements. In the drawings, the size and size ratio of each unit may not necessarily match the actual size and size ratio in the embodiments.

[0017] Figure 1is a block diagram of an example device 100 according to an embodiment of the present disclosure. The device 100 of the present embodiment includes a negative bias temperature instability (NBTI) controller 101 and a memory device 104. In some embodiments of the present disclosure, the NBTI controller 101 and the memory device 104 are included in a stacked device, which includes one or more core memory devices stacked on an interface device. The NBTI controller 101 may be included in the interface device, and the memory device 104 may be included in the one or more core memory devices. In some embodiments, the NBTI controller 101 may be included in the one or more core memory devices. In some embodiments, the memory device 104 may include one or more memory channels. Each memory channel of the memory device can be accessed independently of each other and includes circuits for performing independent access operations. For example, in some embodiments, each memory channel includes a memory bank, a memory bank logic, a data latch, and a command address latch. For the description herein, the term "coupled" may include "connected".

[0018] The NAND controller 101 includes an oscillator 102 and a controller 103. The NBTI controller 101 receives a test mode signal (tmNBTI). For example, during an idle state of the memory device 104, the tmNBTI signal is set to a high level to enable the test mode. When the test mode is enabled, an NBTI mitigation operation or function is performed. In one example, the tmNBTI signal may be provided from outside the device 100, such as a tester (e.g., automatic test equipment ATE) coupled to the device 100. In another example, the tmNBTI signal may be provided by a test mode generation circuit within the device 100. The test mode signal tmNBTI may include an NBTI mitigation enable signal. In some embodiments, the test mode may include a mode for testing a memory device and / or a mode enabled in normal use (or during normal operation) of a memory device product.

[0019] When the tmNBTI signal is received, the NBTI controller 101 starts to output a periodic clocking signal or a periodic switching clock signal (NBTI_toggle_clk) to the data path (DataP), the clock path (ClkP), and the command / address path (CmdP / AddP). On each path, there is an OR instance, such as a logical OR gate. In this document, the command and address may be referred to as CMD / ADD. For example, the NBTI_toggle_clk signal has 0 and 1 (or low and high) pulses that switch periodically at a specific cycle time. The data input (e.g., Data_ChA of channel A as illustrated in the figure among multiple channels A, B, C, etc. of the memory device 104) is coupled to the data latch 105 in the memory device 104. The clock input (Clk_chA of channel A in the example figure) and the CMD / ADD input (Cmd_chA / Add_chA of channel A in the example figure) are coupled to the CMD / ADD latch 106. The NBTI_toggle_clk signal is provided to DataP, ClkP, and CmdP / AddP through an OR instance, and is provided to Data_chA, Clk_chA, and Cmd_chA / Add_chA through corresponding buffers. The data latch 105 and the CMD / ADD latch 106 may be part of the control circuit in the memory device 104. The memory device 104 also includes a bank logic 107 and a bank 108. The bank logic 107 communicates with the data latch 105 and the CMD / ADD latch 106 regarding data, operation commands, memory addresses, etc. The bank 108 communicates with the bank logic 107 for memory operations, such as data reads and data writes.

[0020] The NBTI control operations performed by the NBTI controller 101 during the test mode when the memory device 104 is in an idle state target the signal propagation paths and their destination circuits. For example, signals and circuits that travel and operate at high frequencies (such as DATA, CLK, and CMD / ADD) are susceptible to NBTI degradation (e.g., performance degradation due to NBTI). This NBTI degradation can be mitigated by NBTI control. For example, as will be described in more detail below, the NBTI controller 101 provides a signal to the memory device 104 to perform NBTI mitigation operations during the NBTI mitigation mode. In the case where a conventional controller injects a signal with a periodic clocking / switching pulse composed of or regulated by a command and address protocol whose transition timing is not aligned with a clock signal on the corresponding path, the data latch and CMD / ADD latch configured to output in the memory device only receive such signals on their gate nodes, junction nodes, etc., and do not respond. For example, the CMD / ADD latch decodes the input signal into command and address signals and generates an output signal, but if the input signal cannot be so decoded, there will be no output from the CMD / ADD latch. Since the data latch operating in response to communication with the CMD / ADD latch does not receive any command signal from the CMD / ADD latch, the data latch also does not output any data signal, although it receives the data signal from the data path. Therefore, signal propagation does not continue to the next stage after the data latch and the CMD / ADD latch within the memory device. Therefore, although the memory bank logic of the memory device operates at a relatively high frequency and is susceptible to uneven electrical stress (e.g., uneven DC stress), the memory bank logic and the memory bank coupled thereto in the memory channel may not be fully protected from NBTI degradation because it is located further downstream of the signal propagation and does not receive signal outputs from the data latch and the CMD / ADD latch. In contrast, NBTI controller 101 provides a signal to memory device 104 to perform NBTI mitigation operations, so that the signal travels and propagates further downstream within memory device 104 and effectively reduces non-uniform electrical stress, such as DC stress. Therefore, NBTI degradation and thus device performance degradation can be further effectively prevented or mitigated.

[0021] Figure 2 is a block diagram of an example apparatus 200 according to an embodiment of the present disclosure. The apparatus 200 of the present embodiment includes a signal pattern generator 201. The signal pattern generator 201 includes an oscillator 202 and an NBTI self-controller 203. In some embodiments, the oscillator 202 and the NBTI self-controller 203 are included in an NBTI controller (e.g., NBTI controller 101). In such embodiments of the present disclosure, the NBTI self-controller 203 may be included in the controller 103.

[0022] Oscillator 202 receives a test pattern signal (tmChDis) and provides a switching clock signal to NBTI self-controller 203. The tmChDis signal may be provided, for example, by a tester coupled to device 200 and / or a test pattern generation circuit in device 200, and then provided to signal pattern generator 201, for example, via an interposer on a package substrate.

[0023] The NBTI self-controller 203 includes a data buffer 204, a clock (CLK) buffer 205, and a command / address buffer 206, and an algorithm programmable (ALPG) circuit 207. In this document, commands and addresses may be referred to as CMD / ADD. The data buffer 204 may include one or more data buffer circuits designed and configured to buffer received data signals. The CLK buffer 205 may include one or more clock buffer circuits designed and configured to buffer received clock signals. The CMD / ADD buffer 206 may include one or more buffers designed and configured to buffer received CMD / ADD signals. The ALPG circuit 207 may include one or more ALPG circuits designed and configured to provide a signal to cause the memory device 208 to perform NBTI mitigation operations when the oscillator 202 provides a switching clock signal. The signals provided by the ALPG circuit 207 and the buffers 204 , 205 , and 206 may include a data signal StData, a self-controller output clock signal StClk, and self-controller command and address signals StCMD / StAdd.

[0024] The apparatus 200 includes a memory device 208 coupled to a signal pattern generator 201 or an NBTI self-controller 203 through an interface path and circuit. In some embodiments of the present disclosure, the interface path and circuit include an OR instance (e.g., a logical OR gate) and a buffer. The memory device 208 includes one or more memory channels (Ch). Each memory channel includes one or more memory banks 212. The memory banks 212 may be arranged in an array in a memory region or a cell region on a semiconductor substrate of the memory device 208. Each memory bank 212 may include an array of memory cells. The memory banks 212 may be accessed to read data from the memory cells and write data to the memory cells. Various circuits and circuit elements (e.g., logic circuits, transistors, capacitors, diodes) for memory operations may be disposed in the memory region and / or a peripheral region around the memory region.

[0025] Memory device 208 also includes bank logic 211 coupled to bank 212. Bank logic 211 may include one or more logic circuits for memory operations.

[0026] Memory device 208 further includes data latch 209 and CMD / ADD latch 210. In the illustrated example, data latch 209 is coupled to data buffer 204 in signal pattern generator 201 through interface paths and circuits. CMD / ADD latch 210 is coupled to CLK buffer 205 and CMD / ADD buffer 206 in signal pattern generator 201 through interface paths and circuits. Data latch 209 may include a plurality of latch circuits configured to latch received data signals. CMD / ADD latch 210 may include a plurality of latch circuits configured to latch received memory command and address signals. Data latch 209 and CMD / ADD latch 210 may be part of the control circuit in memory device 208. The StData, StClk, and StCMD / StADD signals provided by the signal pattern generator 201 are provided to the memory device 208 through the interface paths and circuits as the data input Data_chA, the clock input Clk_chA, and the CMD / ADD input Cmd_chA / Add_chA, respectively. The data input Data_chA is provided to the data latch 209, and the clock input Clk_chA and the CMD / ADD input Cmd_chA / Add_chA are provided to the CMD / ADD latch 210.

[0027] Figure 3 is a block diagram of an example command and address (CMD / ADD) latch 300 according to an embodiment of the present disclosure. In some embodiments of the present disclosure, the CMD / ADD latch 300 may be the CMD / ADD latch 210 of the memory device 208. The CMD / ADD latch 300 may include one or more CMD decoders, one or more latches, and one or more set / reset flip-flops (RS-F / F). In the illustrated example, the CMD / ADD latch 300 includes a pair of first CMD decoders 301 and second CMD decoders 302, and a pair of first latches 303 and second latches 304 corresponding to each other and a pair of first RS-F / F 305 and second RS-F / F 306. The first CMD decoder 301 and the second CMD decoder 302 of the pair may have the same or substantially the same circuit structure. The first latch 303 and the second latch 304 of the pair may have the same or substantially the same circuit structure. The first RS-F / F 305 and the second RS-F / F 306 of the pair may have the same or substantially the same circuit structure.

[0028] The CMD / ADD signal is provided to the first CMD decoder 301 and the second CMD decoder 302. The first CMD decoder 301 provides the decoded command signal (CmdR) to the D line (or D input terminal) of the first latch 303. The inverted clock signal (CLKT) generated by a pair of first inverters 307 and second inverters 308 arranged in series according to the input clock signal (CLK) is input to the CK line (or CK input terminal) of the first latch 303. The first latch 303 provides a Q output to the CK line of the first RS-F / F 305. The CMD / ADD signal is also input to the D line of the first RS-F / F 305. The reset signal (Rst) is supplied to the R line (or R input terminal) of the first RS-F / F 305. The first RS-F / F 305 outputs an internal address signal (IntAddR) and an internal command signal (IntCmdR). The first latch 303 may include one or more latch circuits, each of which corresponds to the signal of the decoded command signal CmdR. The first RS-F / F 305 may include one or more flip-flop circuits, each of which corresponds to the signal of the CMD / ADD signal and provides a signal for the internal command signal IntCmdR and / or the internal address signal IntAddR.

[0029] The second CMD decoder 302 provides the decoded command signal (CmdF) to the D line of the second latch 304. The inverted clock signal (CLKF) generated by the first inverter 307 according to the input CLK signal is input to the CK line of the second latch 304. The second latch 304 provides a Q output to the CK line of the second RS-F / F 306. The CMD / ADD signal is also input to the D line of the second RS-F / F 306. The Rst signal is also input to the R line of the second RS-F / F 306. The second RS-F / F 306 outputs an internal address signal (IntAddF) and an internal command signal (IntCmdF). The second latch 304 may include one or more latch circuits, each of which corresponds to the signal of the decoded command signal CmdF. The second RS-F / F 306 may include one or more flip-flop circuits, wherein each flip-flop circuit corresponds to the signal of the CMD / ADD signal and provides a signal for the internal command signal IntCmdF and / or the internal address signal IntAddF. When activated, the reset signal Rst may be used to reset the state of the Q outputs of the first RS-F / F 305 and the second RS-F / F 306.

[0030] In operation, the first latch 303 provides a decoded command signal CmdR as its Q output for the rising edge of the clock signal CLK, and the second latch 304 provides a decoded command signal CmdF as its Q output for the falling edge of the clock signal CLK. For the first latch 303, the Q output causes the first RS-F / F 305 to provide a CMD / ADD signal as the internal command signal IntCmdR and the internal address signal IntAddR associated with the rising edge of the clock signal CLK. For the second latch 304, the Q output causes the second RS-F / F 306 to provide a CMD / ADD signal as the internal command signal IntCmdF and the internal address signal IntAddF associated with the falling edge of the clock signal CLK.

[0031] Figure 4 is a block diagram of an example of a signal pattern generator 400 according to an embodiment of the present disclosure. Figure 5 is a diagram of an example of a signal waveform for NBTI control according to an embodiment of the present disclosure. Figure 6 is a flow chart of an example channel deactivation mode functionality according to an embodiment of the present disclosure.

[0032] In some embodiments of the present disclosure, the signal pattern generator 400 may be included in the NBTI controller 101 of the apparatus 100 and / or the signal pattern generator 201 of the apparatus 200. The signal pattern generator 400 includes an oscillator 401 and an algorithm programmable (ALPG) circuit 402. The oscillator 401 and the ALPG circuit 402 may be the oscillator 202 and the ALPG circuit 207 of the NBTI self-controller 203 of the signal pattern generator 201 of the apparatus 200, respectively. The signal pattern generator 400 further includes a CLK buffer 403, a CMD / ADD buffer 404, and a data buffer 405, which may be the CLK buffer 205, the CMD / ADD buffer 206, and the data buffer 204 of the signal pattern generator 201 of the apparatus 200, respectively. The ALPG circuit 402 includes a sequencer 406, a counter 407, a formatter 408, and a data topology controller 409. The ALPG circuit 402 may be included in the ALPG circuit 207 of the signal pattern generator 201 of the apparatus 200 .

[0033] When the memory device 208 in the idle state enters the NBTI mitigation mode for testing ( Figure 6 When the signal pattern generator 400 / 201 is inputted, a valid enable signal (tmChDis) is inputted from the outside of the signal pattern generator 400 / 201. The tmChDis signal may be provided, for example, by a tester coupled to the device 200 and / or a test pattern generation circuit in the device 200, and then supplied to the signal pattern generator 400 / 201.

[0034] Upon receiving a valid tmChDis signal, the oscillator 401 is activated and the clock signal (OscClk) begins to toggle. The toggled OscClk is supplied to the ALPG circuit 402 ( Figure 6 In some embodiments, the OscClk signal may have a cycle time of, for example, 8 ns ( Figure 5 ). The cycle time is not limited thereto and may be determined based on specifications, design, function, etc. The OscClk signal is input to the sequencer 406 and formatter 408 of the ALPG circuit 402 and the clock buffer 403. From the clock buffer 403, the OscClk signal ( Figure 5 ) is output as the self-controller output clock signal (StClk) to the specified circuit and path, such as the OR logic gate and the ClkP path ( Figure 2 ).

[0035] The sequencer 406 of the NBTI self-controller 402 manages the sequence of functions to be executed at a given or predetermined timing. The counter 407 counts a plurality of functions (e.g., activation, data reading and writing, and pre-charging memory operations) to determine how many functions to repeat. The counter 407 receives a loop signal (Loop) from the sequencer 406 and provides a loop-stop signal (LoopEnd) to the sequencer 421. The counter 407 may be a counter circuit designed and configured to count from a default count number (e.g., 0) to a number incremented by one count or one spacing. The counter circuit may be a multi-bit counter. The sequencer 406 generates a sequence command signal (SeCmd) in response to the received OscClk, and outputs SeCmd to the formatter 408. SeCmd identifies which function will be executed at each given timing, activation (Act), writing (Wrt) or reading (Red) or pre-charging (Pre) ( Figure 5 ).

[0036] Based on the received OscClk and SeCmd, the formatter 408 generates and outputs self-controller command and address signals (StCMD / StAdd) formatted in a predetermined format at a predetermined timing. For example, the StCMD / StAdd converted from SeCmd matches or conforms to a predefined format and timing so that the command and address transition timing is aligned with certain pulses of the OscClk signal, and thus with the StCLK signal. Such a predefined format and timing may include or follow, for example, a protocol or standard of a standard organization such as the Joint Electron Device Engineering Council (JEDEC). For example, as Figure 5As illustrated, StCMD / StADD conforming to the JEDEC defined format provides a command for activation (ACT command) with defined timing aligned with the rising and falling edges of the OScClk signal and the first rising edge (R1), first falling edge (F1), second rising edge (R2), and second falling edge (F2) of the StClk signal for specifying a memory address. Similarly, StCMD / StADD provides a command conforming to the JEDEC defined format. Figure 5 The JEDEC-defined format and timing for data writing or reading commands (WRT command or RED command) and precharging commands (PRE command) are illustrated. StCMD / StADD from formatter 408 travels through CMD / ADD path (StcmdP / StaddP) and CMD / ADD buffer 404 / 206, further through logic OR gates and buffers, and to CMD / ADD latch 210 ( Figure 2 ).

[0037] The sequencer 406 also outputs a data flip command signal (DFlip) to the data topology controller 409. The data topology controller 409 manages the signal polarity based on the DFlip signal received from the sequencer 406. The data topology controller 409, for example, communicates with the ACT command ( Figure 5 ) outputs and provides a polarity-reversed data signal (StData) through the StData path (StDataP) and the data buffer 405. StData then travels through the logic OR gate and buffer to the data latch 209 ( Figure 2 ).

[0038] In response to toggling the OscClk signal and based on the SeCmd signal, the ALPG circuit 402 causes the memory device to perform a write sequence of activating (Act), writing (Wrt), and precharging (Pre). Figure 6 603 in FIG. 4). The ALPG circuit 402 can also enable the memory device to perform a read sequence of activation (Act), reading (Red), and precharging (Pre). Figure 6 604 in ). If the NBTI mitigation mode is not exited ( Figure 6 605 in the above), that is, the tmChDis signal is still at a high level, then the address for at least one of activation, writing and reading is increased, and the data polarity is changed ( Figure 6 Then, the ALPG circuit 402 loops the write sequence (Act-Wrt-Pre) and the read sequence (Act-Red-Pre) until the NBTI mitigation mode is exited, that is, the low level tmChDis is input to the NBTI controller 400. If the NBTI mitigation mode is exited ( Figure 6607), that is, the tmChDis signal is at a low level, then OscClk switching stops ( Figure 6 608 in FIG. 1 ). The memory device 208 then returns to the idle state.

[0039] The signal pattern generator 400 / 201 generates command and address signals formatted according to a predefined protocol that aligns the timing of command and address transitions with the clock signal. Information specifying the type of memory command and information specifying the memory address are included in the formatted command and address signals. The command and address signals and therefore the command and address information are formatted in a defined manner and output at a defined timing according to, for example, an industrial protocol or standard (such as those defined by JEDEC). The formatted command and address signals may therefore be referred to as a command and address protocol.

[0040] The CMD / ADD latch 210 of the corresponding channel of the memory device 208 can then respond to the received signal, decode or translate the command (e.g., Act, Wrt, Red, and Pre) and the address (e.g., the bank / cell address), and send the command signal and the address signal to the bank logic 211 and the data latch 209. When receiving the signal from the CMD / ADD latch 210, the data latch 209 starts to communicate with the bank logic 211 and sends the data signal for testing through the data bus (DataBus). At the same time, the CMD / ADD latch 210 also provides the internal command and address signals to the bank logic 211. Through these functions, the internal paths and circuits of the memory device 208 located at the next stage or further downstream of the signal propagation after the CMD / ADD latch 210 and the DATA latch 209 can operate based on the formatted command and address signals or command and address protocols. Thus, non-uniform DC stress may be reduced, and thus NBTI degradation of such paths and circuits may be mitigated during idle states of the memory device 208 .

[0041] In some embodiments, the formatter 408 ( Figure 4 ) may have a two-stage configuration with a first command formatter and a second command formatter. The first command formatter may receive the OscClk signal and the SeCmd signal and provide a high frequency output of a clock signal and a sequence command signal. The second command formatter may receive the high frequency output from the first command formatter and provide a low frequency output of a clock signal and a sequence command signal as a slow StCMD / StAdd signal. The low frequency, slow StCMD / StAdd signal makes the stress input cycle slower and can limit current consumption.

[0042] Figure 77 is a block diagram of an example apparatus 700 according to an embodiment of the present disclosure. Apparatus 700 includes a signal pattern generator 701 and a memory device 708. Signal pattern generator 701 includes an oscillator 702 and an NBTI self-controller 703. In some embodiments, oscillator 702 and NBTI self-controller 703 are included in an NBTI controller, such as NBTI controller 101. In such embodiments of the present disclosure, NBTI self-controller 703 may be included in controller 103.

[0043] The NBTI self-controller 703 includes a data buffer 704, a clock buffer 705, a command and address buffer 706, and an algorithm programmable (ALPG) circuit 707. The memory device 708 includes a plurality of memory channels ChA to ChL and a bank logic circuit, a data latch circuit, and a command and address latch circuit.

[0044] In addition to some modifications specific to the parallel functional mode of at least two or more channels or all channels of the memory device 708, Figure 7 The circuits, paths, buffers, etc. described in the description may be the same or substantially the same as the corresponding circuits, paths, buffers, etc. in the aforementioned embodiments and examples.

[0045] In some cases, on a target memory device, it may be desirable to simultaneously protect all memory banks in all channels from NBTI degradation during a device idle state. For such cases, memory device 708 enters parallel functional mode upon receiving a test mode signal (tmCompress) specific to parallel functional mode. tmCompress may be supplied from a tester coupled to apparatus 700 and / or from a test pattern generator circuit in apparatus 700. In this mode, command decoder circuits (e.g., tmCompress) of the CMD / ADD latch circuits of all memory channels are activated. Figure 3 The CMD decoders 301 and 302 of the CMD / ADD latch circuit 300 in the NBTI mode ignore or do not respond to channel information contained in the command and address signals. Instead, the same inputs for clock, command / address, and data are shared among all memory channels. During NBTI mitigation, the StData, StClk, and StCMD / StADD signals provided by the signal pattern generator 701 are provided to the memory device 708 as data input Data_ch_all, clock input Clk_ch_all, and CMD / ADD input Cmd_ch_all / Add_ch_all, respectively, through interface paths and circuits. The data input Data_ch_all, the clock input Clk_ch_all, and the CMD / ADD input Cmd_ch_all / Add_ch_all are provided to all memory channels so that NBTI mitigation can be performed for all memory channels.

[0046] In the present embodiment and examples, the NBTI controller 101, 203, 402 or 703 may not be limited to NBTI degradation control, but may be applicable to positive BTI (PBTI) degradation control as appropriate.

[0047] Figure 8 A schematic configuration of an example semiconductor system 800 according to an embodiment of the present disclosure is depicted. In an embodiment of the present disclosure, the semiconductor system 800 includes a semiconductor memory device 801. The semiconductor memory device 801 may include a memory device 104, 208, or 708. In some embodiments of the present disclosure, the semiconductor memory device 801 includes an NBTI controller 101, a signal pattern generator 201, and / or a signal pattern generator 701. The semiconductor system 800 may also include a central processing unit (CPU) and a memory controller 804 on an interposer 805 on a package substrate 808, which may be a controller chip. The interposer 805 may include one or more power lines 810 that may supply a power supply voltage from the package substrate 808. The interposer 805 may include a plurality of channels 811 that may interconnect the CPU and the memory controller 804 with the semiconductor memory device 801. The semiconductor memory device 801 may be a dynamic random access memory (DRAM). The memory controller 804 may provide a clock signal, a command signal, and may further transmit and receive a data signal. The plurality of channels 811 may transmit data signals between the memory controller 804 and the memory device 801 .

[0048] The semiconductor memory device 801 may include a plurality of dies (or chips) 802, which include at least one interface (IF) die (or chip) 803 and a plurality of memory core dies (or chips) 806 stacked on each other. The number of memory core dies 806 may not be limited to four in the illustrated example, and may be more or less as appropriate. Each memory core die 806 may include a plurality of memory cells and a circuit system for accessing the memory cells. For example, the memory cells may be DRAM cells. The memory cells may be arranged in an array. The semiconductor memory device 801 may include a conductive via 807, which couples the IF die 803 and the memory core die 806 by penetrating the IF die 803 and the memory core die 806. The IF die 803 may be coupled to the interposer 805 via an interconnect 809. For example, the interconnect 809 may be a microbump having a bump pitch of less than about one hundred microns or less than one hundred microns and exposed to the outside of the IF die 803. A portion of each of the interconnects 809 may be coupled to one or more power lines 810. Another portion of each of the interconnects 809 may be coupled to one or more channels 811.

[0049] DRAM is just one example, and the embodiments and descriptions herein are not intended to be limited to DRAM. Memory devices other than DRAM (e.g., static random access memory (SRAM), flash memory, erasable programmable read-only memory (EPROM), magnetoresistive random access memory (MRAM), and phase change memory) may also be applied as the memory device 801. Furthermore, devices other than memory (including logic ICs such as microprocessors and application-specific integrated circuits (ASICs)) may also be applied as the semiconductor device according to the present embodiment.

[0050] Fig. 9 is a block diagram of an example semiconductor device 900 according to an embodiment of the present disclosure. The semiconductor device 900 may be a semiconductor memory device, such as a DRAM device. In some embodiments of the present disclosure, the semiconductor device 900 is included in a semiconductor memory device, such as Figure 8 A semiconductor memory device 801. The DRAM device may include an interface die and a plurality of core dies stacked on the interface die. Fig. 9 In the example diagram of , certain components are shown as being located on the interface die 930, while other components are shown as part of each core die 940. For clarity, only a single core die 940 and its components are shown, however, there may be multiple core dies (e.g., 2, 4, 6, 8, 16, or more), each with similar components to each other. Fig. 9 The example semiconductor device 900 shows a particular arrangement of components between the interface die 930 and the core die 940, however other arrangements may be used in other embodiments (e.g., in some embodiments, the refresh control circuit 916 may be on the interface die 930). For illustration purposes, the core die 940 is drawn as a smaller box than the interface die 930, however, the core die 940 and the interface die 930 may have any size relationship to each other. For example, the core die 940 and the interface die 930 may have approximately the same size.

[0051] The semiconductor device 900 includes a memory array 918 on each core die 940. The memory array 918 is shown as including a plurality of memory banks. Fig. 9 In the embodiment of the present invention, the memory array 918 is shown to include eight memory banks BANK0 to BANK7. More or fewer memory banks may be included in the memory array 918 of other embodiments. Each memory bank includes a plurality of word lines WL, a plurality of bit lines BL, and a plurality of memory cells MC arranged at the intersections of the plurality of word lines WL and the plurality of bit lines BL. The selection of the word lines WL is performed by a row decoder 908 and the selection of the bit lines BL is performed by a column decoder 910, each of which may also be located on each core die. Fig. 9In the embodiment of the present invention, the row decoder 908 includes a corresponding row decoder for each memory bank, and the column decoder 910 includes a corresponding column decoder for each memory bank. The bit lines BL are coupled to corresponding sense amplifiers (SAMPs) of the memory array 918. Data read from the bit lines BL are amplified by the sense amplifiers SAMPs and are transferred to the read / write amplifier (RWAMP) 920 through the complementary local data lines (LIOT / B), the transfer gates (TG), and the complementary main data lines (MIOT / B) coupled to the RWAMP 920. Conversely, the write data output from the RWAMP 920 is transferred to the sense amplifiers SAMPs through the complementary main data lines MIOT / B, the transfer gates TG, and the complementary local data lines LIOT / B, and is written into the memory cells MC coupled to the bit lines BL.

[0052] The semiconductor device 900 may employ a plurality of external terminals positioned on the interface die 930, including a command and address terminal coupled to a command and address (C / A) bus to receive commands and addresses as well as a CS signal, a clock terminal to receive clocks CK and / CK, a data terminal DQ to provide data, and a power supply terminal to receive power supply potentials VDD, VSS, VDDQ, and VSSQ.

[0053] The clock terminal on the interface die 930 is supplied with external clocks CK and / CK provided to the input circuit 912. The external clocks may be complementary. The input circuit 912 generates an internal clock ICLK based on the CK and / CK clocks. The ICLK clock is provided to the command decoder 906 and the internal clock generator 914. The internal clock generator 914 provides various internal clocks LCLK based on the ICLK clock. The LCLK clock can be used to time the operation of various internal circuits. The internal data clock LCLK is provided to the input / output (I / O) circuit 922 to time the operation of the circuits included in the I / O circuit 922, for example, to the data receiver to time the reception of the write data.

[0054] The internal clock LCLK may include a read clock (RCLK) for controlling the timing of read operations and a write clock (WCLK) for controlling the timing of write operations. The internal clock may be passed to I / O circuits 922 and also to internal components of core die 940, such as RWAMP 920.

[0055] The C / A terminal may be supplied with a memory address. The memory address supplied to the C / A terminal is transmitted to the address decoder 904 via the command / address input circuit 902. The address decoder 904 receives the address and supplies the decoded row address XADD to the row decoder 908, and supplies the decoded column address YADD to the column decoder 910. The address decoder 904 may also supply a decoded memory bank address BADD, which may indicate a memory bank of the memory array 918 containing the decoded row address XADD and column address YADD. The C / A terminal may be supplied with a command. Command examples include timing commands for controlling the timing of various operations, access commands for accessing memory (e.g., read commands for performing read operations and write commands for performing write operations), and other commands and operations. The access command may be associated with one or more row addresses XADD, column addresses YADD, and memory bank addresses BADD to indicate the (several) memory cells to be accessed.

[0056] The command may be provided as an internal command signal to a command decoder 906 via the command / address input circuit 902. The command decoder 906 includes circuitry for decoding the internal command signal to generate various internal signals and commands for performing an operation. For example, the command decoder 906 may provide a row command signal to select a word line and a column command signal to select a bit line.

[0057] The semiconductor device 900 may receive an access command as a read command. When the read command is received and the bank address, row address, and column address are supplied in time with the read command, read data is read from the memory cell corresponding to the row address and the column address in the memory array 918. The read command is received by the command decoder 906, and the command decoder 906 provides an internal command so that the data read from the memory array 918 is provided to the RWAMP 920. The read data is output from the data terminal DQ to the outside of the semiconductor device 900 via the I / O circuit 922.

[0058] The semiconductor device 900 may receive an access command as a write command. When the write command is received and the memory address, row address, and column address are supplied in time with the write command, the write data is supplied to the RWAMP 920 through the DQ terminal. The write data supplied to the data terminal DQ is written to the memory cell corresponding to the row address and the column address in the memory array 918. The write command is received by the command decoder 906, which provides an internal command so that the write data is received by the data receiver in the I / O circuit 922. The write clock may also be provided to the external clock terminal for timing the data receiver of the I / O circuit 922 to receive the write data. The write data is supplied to the RWAMP 920 via the I / O circuit 922.

[0059] The semiconductor device 900 may also receive a command that causes it to perform one or more refresh operations as part of a self-refresh mode. In some embodiments, the self-refresh mode command may be issued externally to the semiconductor device 900. In some embodiments, the self-refresh mode command may be periodically generated by a component of the device. In some embodiments, the refresh signal AREF may also be activated when an external signal indicates a self-refresh entry command.

[0060] The power supply terminal is supplied with power supply potentials VDD and VSS. The power supply potentials VDD and VSS are supplied to the internal voltage generator circuit 924. The internal voltage generator circuit 924 generates various internal potentials such as VPP, VOD, VARY, VPERI, and the like based on the power supply potentials VDD and VSS supplied to the power supply terminal.

[0061] The power supply terminal is also supplied with power supply potentials VDDQ and VSSQ. The power supply potentials VDDQ and VSSQ are supplied to the I / O circuit 922. The power supply potentials VDDQ and VSSQ supplied to the power supply terminal may be the same potentials as the power supply potentials VDD and VSS supplied to the power supply terminal in the embodiment of the present disclosure. In another embodiment of the present disclosure, the power supply potentials VDDQ and VSSQ supplied to the power supply terminal may be different potentials from the power supply potentials VDD and VSS supplied to the power supply terminal. The power supply potentials VDDQ and VSSQ supplied to the power supply terminal are used for the I / O circuit 922 so that the power supply noise generated by the I / O circuit 922 does not propagate to other circuit blocks.

[0062] Although various embodiments of the present disclosure have been described in detail, it will be understood by those skilled in the art that the embodiments of the present disclosure may extend beyond the specifically described embodiments to other alternative embodiments and / or uses and modifications and equivalents thereof. In addition, other modifications within the scope of the present disclosure will be readily apparent to those skilled in the art based on the described embodiments. It is also contemplated that various combinations or sub-combinations of the specific features and aspects of the embodiments may be formed and still fall within the scope of the present disclosure. It should be understood that the various features and aspects of the embodiments may be combined or substituted with each other to form a variation pattern of the embodiments. Therefore, it is desired that the scope of the present disclosure should not be limited to the specific embodiments described above.

Claims

1. A device comprising: Memory device; and A bias temperature instability (BTI) controller is configured to generate and output command and address signals for a memory test, wherein the command and address signals cause the memory device in an idle state to operate for the test.

2. The apparatus of claim 1, wherein the command and address signals are supplied to command and address control circuitry of the memory device to cause the command and address control circuitry to generate output signals for bank logic circuitry.

3. The apparatus of claim 1, wherein the command and address signals are supplied to command and address control circuitry of the memory device, the command and address control circuitry translating command and address information from the command and address signals.

4. The apparatus of claim 1, further comprising an oscillator configured to generate a clock signal, wherein the BTI controller generates the command and address signals with command and address transition timing aligned with the clock signal. The apparatus of claim 4 , wherein the clock signal is a switching clock signal.

6. The apparatus of claim 4, further comprising a buffer configured to delay the clock signal, wherein the command and address transition timing is aligned with the delayed clock signal.

7. The apparatus of claim 4, wherein the transition timing includes timing for a write sequence and / or a read sequence, and each timing is aligned with at least one of a rising edge and a falling edge of the clock signal.

8. The apparatus of claim 7, wherein the write sequence comprises activate, write, and precharge, and the read sequence comprises activate, read, and precharge.

9. The apparatus of claim 7, further comprising a sequencer configured to provide a sequence command signal in response to the clock signal, wherein the sequence command signal identifies the write sequence and / or the read sequence at a predefined timing.

10. The apparatus of claim 9, further comprising a formatter configured to generate the command and address signals based on the sequence command signals according to a predefined format.

11. The apparatus of claim 10, wherein the BTI controller includes the sequencer and the formatter as at least part of an algorithmic programmable circuit.

12. The apparatus of claim 1, wherein the BTI controller is a NBTI controller.

13. An apparatus comprising: Memory device; and A bias temperature instability (BTI) controller configured to generate command and address signals for memory testing, wherein The command and address signals supplied to the memory device in an idle state cause a memory command and address latch circuit to output internal signals to a bank logic circuit and a memory data latch circuit in response to the received command and address signals.

14. The apparatus of claim 13, further comprising an oscillator configured to generate a switching clock signal, wherein the BTI controller generates, in response to the switching clock signal, the command and address transition timing that aligns command and address transition timing with at least one of the switching clock signal and a delayed switching clock signal.

15. The apparatus of claim 14, wherein the transition timing includes timing for memory test operations including activation, writing or reading, and precharging, and each timing is aligned with at least one of a rising edge and a falling edge of at least one of the switching clock signal and the delayed switching clock signal.

16. The apparatus of claim 14, wherein the BTI controller is a NBTI controller.

17. A bias temperature instability (BTI) controller for a memory device, comprising: a sequencer configured to generate a sequence command signal in response to a switching clock signal, wherein the sequence command signal identifies a memory test operation sequence at a first timing; and a formatter configured to generate command and address signals according to a certain format at a second timing based on the sequence command signal and the switching clock signal, wherein The command and address signals align command and address transition timing with the switching clock signal and can be decoded by command and address control circuitry of the memory device to obtain command and address information.

18. The BTI controller of claim 17, wherein the command and address transition timing is further aligned with a delayed clock signal of the switching clock signal according to the format.

19. The BTI controller of claim 17, wherein the transition timing includes timing for transitioning memory test operations including activation, writing or reading, and precharging, and each timing is aligned with at least one of a rising edge and a falling edge of at least one of the switching clock signals φ(t) and φ(t).

20. The BTI controller of claim 17, wherein the BTI controller is a NBTI controller.

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