Surface grinding method for semiconductor device

Abstract

The invention belongs to the technical field of semiconductor manufacturing, and provides a surface grinding method of a semiconductor device, which comprises the following steps of: obtaining a first thickness of a surface structure layer of the semiconductor device; calculating the second thickness of the oxide layer needing to be removed according to the first thickness; the target thickness of the remaining oxide layer needing to be reserved is set; calculating a third thickness by using the target thickness and the second thickness; depositing and forming an oxide layer with a third thickness on the surface structure layer; and removing the oxide layer with the second thickness. The third thickness of the oxide layer to be deposited is obtained through pre-calculation, the planarization effect on the semiconductor device can be guaranteed, the oxide layer with the second thickness with the smaller numerical value is removed, the grinding amount can be reduced, productivity waste is avoided, the production efficiency is improved, the third thickness can correspondingly change along with the change of the first thickness, and the product quality is improved. The method is suitable for products of various specifications, the adaptability of the method is improved, and the method has great product popularization value.

Description

Technical Field

[0001] The present application relates to the field of semiconductor manufacturing technology, and in particular to a surface grinding method for a semiconductor device. Background Art

[0002] With the development of society and the advancement of semiconductor technology, the market has put forward higher and higher requirements on the performance of semiconductor devices. In order to improve the competitiveness of products, it is necessary to develop new semiconductor processes to improve product performance. In the production process of semiconductors, after the gate layer and / or metal layer are formed on the surface of the silicon wafer, the gate layer and / or metal layer needs to be patterned to form a gate layer and / or metal layer with a specific pattern. In the patterned gate layer and / or metal layer, there is a step structure introduced by the patterning, which makes the silicon wafer have an undulating surface. In order to make the surface of the silicon wafer flat, it is necessary to deposit a dielectric layer on the gate layer and / or metal layer of the silicon wafer to cover the surface of the silicon wafer. By grinding the deposited dielectric layer, part of the dielectric layer is removed to achieve the flattening of the surface of the silicon wafer.

[0003] However, due to the presence of steps on the surface of the silicon wafer, the deposited dielectric layer is also uneven. When the dielectric layer is ground and removed, if the grinding amount is small, the steps on the surface cannot be completely eliminated, and the purpose of flattening cannot be achieved. This will cause problems such as tungsten residue in subsequent processes. When the thickness of the dielectric layer deposition is too large, although the surface steps can be eliminated by grinding and the purpose of flattening can be achieved, it will introduce problems such as too long grinding time, uneven silicon wafer film thickness, and waste of production capacity.

[0004] Based on this, in order to solve the above problems, the present application provides a surface grinding method for a semiconductor device, which can quickly determine the thickness of the dielectric layer that needs to be deposited on the silicon wafer, avoid waste of production capacity, and at the same time ensure that the purpose of surface flattening can be achieved through grinding. Summary of the invention

[0005] In view of the shortcomings of the prior art described above, the purpose of the present application is to provide a surface grinding method for semiconductor devices to solve the problem of waste of production capacity or inability to achieve flattening when flattening the surface of silicon wafers in the prior art, and to accurately determine the thickness of the oxide layer that needs to be deposited on the surface of the silicon wafer.

[0006] In order to achieve the above-mentioned object and other related objects, the present application provides a surface grinding method of a semiconductor device, which is used to planarize the surface of the semiconductor device, wherein the surface of the semiconductor device has a patterned surface structure layer, comprising the following steps:

[0007] Obtaining the thickness of the surface structure layer and recording it as a first thickness;

[0008] The thickness to be removed by grinding is calculated based on the first thickness and recorded as the second thickness;

[0009] Setting the thickness of the remaining oxide layer on the surface structure layer after planarization and recording it as the target thickness;

[0010] Calculating a third thickness according to the target thickness and the second thickness;

[0011] forming an oxide layer having a third thickness on the surface structural layer;

[0012] The oxide layer having the second thickness is removed to obtain a remaining oxide layer having the target thickness, so as to planarize the surface of the semiconductor device.

[0013] Optionally, the surface structure layer includes a gate layer, and the first thickness is the thickness of the gate layer.

[0014] Optionally, the surface structure layer includes a metal layer and an adhesive layer, and the first thickness is the sum of the thicknesses of the metal layer and the adhesive layer.

[0015] Optionally, calculating the thickness to be removed by grinding according to the first thickness and recording it as the second thickness includes the following steps:

[0016] An exponential relationship is set between the second thickness and the surface transmittance of the semiconductor device, and the exponential relationship is recorded as h2=k1*a^(1-S), where h2 is the second thickness, a is the base parameter, k1 is the first coefficient, and S is the surface transmittance;

[0017] Based on the graphic structure of the surface structure layer, the surface transmittance S of the semiconductor device is calculated;

[0018] Calculating the first coefficient k1 using the first thickness;

[0019] Substituting the surface transmittance S and the first coefficient k1 into the above expression, the second thickness h2 is obtained.

[0020] Optionally, calculating the surface transmittance S of the semiconductor device comprises the following steps:

[0021] In the top view of the semiconductor device, obtaining a coverage area s1 of the surface structure layer and a coverage area s2 of the oxide layer;

[0022] The surface transmittance S=1-s1 / s2 is calculated.

[0023] Optionally, the calculation formula of the first coefficient k1 is k1=(m+1)*q, where m is the first thickness, and the unit is q is a preset second coefficient.

[0024] Optionally, the second coefficient q satisfies 1.5≤q≤1.7.

[0025] Optionally, the base parameter a satisfies 0.8<a<1.

[0026] Optionally, the base parameter a has a value of 0.9 to 0.99.

[0027] Optionally, the third thickness is the sum of the second thickness and the target thickness, and the oxide layer of the second thickness is removed by grinding using a grinding device to planarize the surface of the semiconductor device.

[0028] As described above, the surface grinding method of the semiconductor device provided by the present application has at least the following beneficial effects:

[0029] The surface grinding method of the semiconductor device of the present application calculates the third thickness of the oxide layer to be deposited in advance according to the first thickness of the surface structure layer and the target thickness after grinding, which can ensure that after grinding and removing the oxide layer of the second thickness, the surface of the semiconductor device is flattened, while avoiding waste of production capacity and improving the efficiency of grinding; and the third thickness is linearly related to the first coefficient and exponentially related to the surface transmittance. The first coefficient is related to the first thickness. When the first thickness or transmittance of the surface structure layer changes, the third thickness can be adaptively changed, so that the method can adapt to products of various specifications. The first coefficient is also related to the second coefficient. By adjusting the value of the second coefficient, the applicability of the method is further improved. It can be seen that the surface grinding method of the semiconductor device of the present application improves the grinding efficiency of the semiconductor device by depositing an oxide layer of appropriate thickness, ensures the flattening effect of the surface of the semiconductor device, avoids waste of production capacity, saves material costs, can be applied to products of various specifications, has good applicability, and thus has great product promotion value. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying creative work.

[0031] Figure 1 A schematic flow chart of a surface grinding method for a semiconductor device provided in an embodiment of the present application is shown.

[0032] Figure 2 and Figure 3Shown is a schematic diagram of the surface structure of a semiconductor device provided in an embodiment of the present application.

[0033] Figure 4 and Figure 5 Shown is a schematic diagram of the surface structure of a semiconductor device after a portion of the oxide layer is removed according to an embodiment of the present application.

[0034] Figure 6 Shown is a schematic diagram of the structure of comparative example 1 provided in the embodiments of the present application.

[0035] Figure 7 Shown is a schematic diagram of the structure of the product 1 of the present solution provided in an embodiment of the present application.

[0036] Figure 8 Shown is a schematic diagram of the structure of Comparative Example 2 provided in the embodiments of the present application.

[0037] Fig. 9 Shown is a schematic diagram of the structure of the product 2 of the present solution provided in an embodiment of the present application.

[0038] Reference numerals:

[0039] 10. Surface structure layer; 11. Metal layer; 12. Adhesion layer; 13. Gate layer; 21. Oxide layer. DETAILED DESCRIPTION

[0040] In order to make the technical purpose, technical solution and technical effect of the present application clearer, the technical solution in the present application will be clearly and completely described in conjunction with the embodiments below. Obviously, the described embodiments are part of the embodiments of the present application, rather than all the embodiments. The components of the embodiments of the present application described and shown in the drawings here can be arranged and designed in various different configurations.

[0041] Therefore, the following detailed description of the embodiments of the present application is not intended to limit the scope of the present application for protection, but merely represents the selected embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative work are within the scope of protection of the present application. In addition, the terms "first" and "second" are only used for descriptive purposes and cannot be understood as indicating or implying relative importance.

[0042] In the description of the present application, it should be noted that the description with reference to the terms "one embodiment", "some embodiments", "illustrative embodiments", "example", "specific example" or "some examples" means that the specific features, structures, materials or characteristics described in conjunction with the implementation or example are included in at least one implementation or example of the present application. In this specification, the schematic representation of the above terms does not necessarily refer to the same implementation or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more implementations or examples in a suitable manner.

[0043] This embodiment provides a surface grinding method for a semiconductor device, which is used to flatten the surface of the semiconductor device. The surface of the semiconductor device has a patterned surface structure layer 10, and a step structure is formed in the patterned surface structure layer 10. Optionally, the semiconductor device is, for example, a wafer.

[0044] Reference Figure 1 The surface grinding method of the semiconductor device provided in this embodiment includes steps S1 to S6, specifically including:

[0045] Step S1: obtaining the thickness of the surface structure layer 10 and recording it as a first thickness;

[0046] Step S2: The thickness of the oxide layer 21 to be removed is calculated according to the first thickness and recorded as the second thickness;

[0047] Step S3: setting the thickness of the remaining oxide layer on the surface structure layer after planarization and recording it as the target thickness;

[0048] Step S4: Calculate the third thickness according to the target thickness and the second thickness;

[0049] Step S5: forming an oxide layer 21 with a third thickness on the surface structure layer 10;

[0050] Step S6: removing the oxide layer 21 of the second thickness to obtain a remaining oxide layer with a target thickness, so as to planarize the surface of the semiconductor device.

[0051] The surface grinding method of the semiconductor device of this embodiment will be described in detail below with reference to the accompanying drawings. It should be noted that the above sequence does not strictly represent the process sequence of the surface grinding method of the semiconductor device protected by this application, and those skilled in the art can change it according to the actual processing steps.

[0052] First, step S1 is performed to obtain the thickness of the surface structure layer 10 and record it as the first thickness.

[0053] In this embodiment, the surface structure layer 10 means the structure layer on the outside of the semiconductor device in the current semiconductor process. In the front process, after the surface structure layer 10 is formed, a patterned surface structure layer 10 is formed by processes such as photolithography and etching, and the patterned surface structure layer 10 forms a step structure with other structure layers of the semiconductor device, and the height of the step structure is numerically equal to the height of the surface structure layer 10. The surface structure layer 10 of the semiconductor device can be a single-layer structure or a multi-layer structure.

[0054] In an alternative embodiment, reference Figure 2 The surface structure layer 10 is, for example, a single-layer structure, including a gate layer 13, and the first thickness is the thickness of the gate layer 13. The thickness of the gate layer 13 can be directly obtained through product specification parameters, process parameters of the previous process or other appropriate methods.

[0055] In an alternative embodiment, reference Figure 3 The surface structure layer 10 is, for example, a multi-layer structure, including a metal layer 11 and an adhesive layer 12, and the first thickness is the sum of the thickness of the metal layer 11 and the thickness of the adhesive layer 12. The thickness of the metal layer 11 and the adhesive layer 12 can be directly obtained through product specification parameters, process parameters of the previous process or other appropriate methods.

[0056] Then, step S2 is performed to calculate the thickness of the oxide layer 21 to be removed according to the first thickness and record it as the second thickness.

[0057] In this embodiment, the second thickness is the thickness of the oxide layer 21 to be removed later. The value of the second thickness is affected by the thickness of the surface structure layer 10. Generally speaking, when the thickness of the surface structure layer 10 increases, the corresponding value of the second thickness will also increase. In addition, the inventors have found that the value of the second thickness is also affected by the surface transmittance, which means the transmittance of the surface of the semiconductor device. When the surface transmittance decreases, the corresponding value of the second thickness will also decrease. Through further research, it is found that the value of the second thickness is exponentially related to the value of the surface transmittance.

[0058] In an optional embodiment, calculating the second thickness according to the first thickness includes the following steps: setting an exponential relationship between the second thickness and the surface transmittance of the semiconductor device; calculating the surface transmittance of the semiconductor device based on the graphic structure of the surface structure layer; using the first thickness to calculate the first coefficient; substituting the surface transmittance and the first coefficient into the exponential relationship between the second thickness and the surface transmittance to obtain the second thickness. Specifically, the exponential relationship between the second thickness and the surface transmittance of the semiconductor device is given by the following formula:

[0059] h2=k1*a (1-S) (1)

[0060] Among them, h2 is the second thickness, k1 is the first coefficient, S is the surface transmittance, and a is the base parameter.

[0061] The surface structure layer 10 of the semiconductor device is generally a non-transparent structure, and light cannot pass through the surface structure layer 10 . Therefore, the value of the surface transmittance can be described by the value of the area ratio of the surface structure layer 10 .

[0062] In an optional embodiment, calculating the surface transmittance of the semiconductor device includes the following steps: in a top view of the semiconductor device, obtaining the coverage area s1 of the surface structure layer 10 and the coverage area s2 of the oxide layer 21; and calculating the surface transmittance S=1-s1 / s2 according to the coverage area s1 and the coverage area s2. For example, the value of the surface transmittance S can be 30%, 40%, 50%, 60%, 70%, 80% or other acceptable values.

[0063] The first coefficient k1 is a quantity related to the first thickness. The value of the first coefficient k1 can be adjusted according to the value of the first thickness so that the value of the second thickness can change with the change of the first thickness to adapt to the working conditions of different surface structure layer 10 thicknesses and improve the adaptability of the method.

[0064] In an optional embodiment, the calculation formula of the first coefficient k1 is k1=(h1+1)*q, wherein h1 is the first thickness, and the unit of the first thickness h1 is q is a preset second coefficient, which is a dimensionless constant. By setting a suitable value of the second coefficient q, formula (1) can be adapted to various working conditions in actual production, ensuring that the calculated second thickness can meet the design requirements of surface flattening, while avoiding waste of production capacity and improving grinding efficiency.

[0065] Furthermore, the value of the second coefficient q satisfies 1.5≤q≤1.7. By controlling the value of the second coefficient q within the range of 1.5 to 1.7, a flat surface can be obtained after the oxide layer is formed and the surface of the semiconductor device is flattened, while avoiding waste of production capacity and improving grinding efficiency. When the value of the second coefficient q is small, if the flattening effect of the surface of the semiconductor device cannot meet expectations in actual production, the value of q can be appropriately increased to improve the flattening effect, and by limiting the upper limit of the value of the second coefficient q, it can be avoided that the thickness of the formed oxide layer is too large to cause waste of production capacity.

[0066] In formula (1), a is a base parameter, which is a parameter that characterizes the relationship between the speed of the second thickness changing with the change of the surface transmittance. The value of the base parameter a satisfies the following relationship: 0.8<a<1. Optionally, the value of the base parameter a is 0.9~0.99, for example, the value of the base parameter a can be 0.9, 0.95, 0.99 or other suitable values; in this embodiment, the value of the base parameter a is preferably 0.95. By controlling the value range of a within the range of 0.8~1, or further controlling the value within the range of 0.9~0.99, formula (1) can more accurately reflect the relationship between the second thickness and the surface transmittance, and it is found that when the base parameter a is 0.95, the relationship between the second thickness and the surface transmittance described by formula (1) can more accurately reflect the actual production situation. At this time, the second thickness to be removed can have a smaller value while satisfying the surface flattening, thereby preventing waste of production capacity and improving production efficiency.

[0067] In an optional embodiment, the second coefficient q is taken as a constant parameter, the first thickness h1 and the surface transmittance S are taken as variables, and the base parameter a is taken as 0.95, then formula (1) can be expressed as h2=(h1+1)*q*0.95^(1-S), and the parameter q can be, for example, 1.5, 1.6, 1.7 or other suitable values, where the specific value of q can be adjusted according to actual production conditions.

[0068] Next, step S3 is performed to set the thickness of the remaining oxide layer on the surface structure layer after planarization and record it as the target thickness.

[0069] In this embodiment, refer to Figure 2 and Figure 3 , the target thickness is the thickness of the remaining oxide layer on the surface structure layer 10 after removing part of the oxide layer 21, and the remaining oxide layer is the remaining oxide layer 21 after removing part of the oxide layer 21. In order to ensure the planarization effect of the semiconductor device, the target thickness is a value greater than 0. The target thickness can be adaptively set according to the process or design requirements. For example, the value of the target thickness can be set to Or other suitable values. It should be noted that the order of executing step S3 can be after executing step S2, or before executing step S1 or step S2, and this embodiment is not limited thereto.

[0070] Next, step S4 is performed to calculate the third thickness according to the target thickness and the second thickness.

[0071] In this embodiment, refer to Figure 2 and Figure 3, the third thickness is the thickness of the oxide layer 21 to be formed on the surface structure layer 10 of the semiconductor device, specifically the distance between the top surface of the oxide layer 21 and the bottom surface of the surface structure layer 10. Optionally, the third thickness is h3, the target thickness is t, then the third thickness h3=t+h2, that is, the third thickness is the sum of the second thickness and the target thickness.

[0072] Next, step S5 is performed to form an oxide layer 21 with a third thickness on the surface structure layer 10 .

[0073] In this embodiment, an oxide layer 21 can be formed on the surface structure layer 10 by a chemical vapor deposition process or other suitable methods. For example, an HDP process or a PECVD process can be used to form the oxide layer 21 on the semiconductor device. The material of the oxide layer 21 can be silicon oxide or other acceptable dielectric materials. For example, the oxide layer 21 is a silicon dioxide layer.

[0074] In an optional embodiment, an oxide layer 21 of a third thickness is formed on the surface structure layer 10, comprising the following steps: placing a semiconductor device in a deposition device; using the deposition device to deposit an oxide film on the surface of the semiconductor device, and making the oxide film completely cover the surface structure layer 10; controlling the thickness of the oxide film to be a third thickness to form an oxide layer 21.

[0075] Finally, step S6 is performed to remove the oxide layer 21 of the second thickness to obtain a remaining oxide layer with a target thickness, so as to planarize the surface of the semiconductor device.

[0076] In this embodiment, a chemical mechanical polishing (CMP) process or other acceptable methods can be used to remove part of the oxide layer 21 on the surface of the semiconductor device to obtain a remaining oxide layer, so as to achieve planarization of the surface of the semiconductor device. Figure 4 and Figure 5 The thickness of the oxide layer 21 to be removed is the second thickness. After removing the second thickness of the oxide layer 21, the thickness of the remaining oxide layer on the surface of the semiconductor device is the target thickness, thereby achieving the planarization of the surface of the semiconductor device. Moreover, the value of the second thickness is relatively small, which reduces the amount of grinding of the oxide layer 21, improves the production efficiency of the process, and avoids the occurrence of problems such as waste of production capacity.

[0077] In an optional embodiment, removing a portion of the oxide layer 21 on the surface of the semiconductor device includes the following steps: installing the semiconductor device under the polishing head of a grinding device so that the oxide layer 21 faces the grinding pad of the grinding device; controlling the grinding disk and the polishing head of the grinding device to rotate to respectively drive the grinding pad and the semiconductor device to rotate; spraying the grinding liquid onto the grinding pad and making the surface structure layer 10 contact the grinding pad to grind the oxide layer 21; after removing the second thickness of the oxide layer 21, moving the semiconductor device away from the grinding pad to complete this grinding operation.

[0078] In an optional embodiment, after performing step S6 to remove part of the oxide layer 21 on the surface of the semiconductor device to planarize the surface of the semiconductor device, the following step is further included: cleaning the semiconductor device. The ground semiconductor device can be cleaned using a cleaning device to remove contaminants such as abrasive particles remaining on the surface of the semiconductor device after grinding.

[0079] Furthermore, cleaning the semiconductor device includes the following steps: placing the semiconductor device in a cleaning device; spraying a cleaning liquid onto the surface of the semiconductor device; and using a cleaning brush of the cleaning device to clean the semiconductor device. The cleaning liquid may be deionized water or other suitable materials.

[0080] To further illustrate the technical effect of the present application scheme, product 1 and product 2 adopting the scheme of this embodiment, as well as comparative example 1 and comparative example 2 corresponding to product 1 and product 2 respectively are provided, and product 1, comparative example 1, product 2 and comparative example 2 are tested respectively.

[0081] Among them, the target thickness of product 1 The surface transmittance S=47%, the surface structure layer 10 is a metal layer 11 and an adhesive layer 12, and the first thickness of the surface structure layer 10 is The second coefficient q=1.7, the comparative example 1 has the same structural parameters as the above parameters of the product 1, and the thickness of the deposited oxide layer 21 in the comparative example 1 is The third thickness of the oxide layer 21 of product 1 calculated by formula (1) is The experimental results of Comparative Example 1 and Product 1 refer to Figure 6 and Figure 7 It can be seen that the surface of the product of comparative example 1 obviously has the defect of insufficient flatness, while the surface of product 1 obtained by the present application scheme has no obvious defects and is well flattened.

[0082] Target thickness of product 2 The surface transmittance S=51%, the surface structure layer 10 is a metal layer 11 and an adhesive layer 12, and the first thickness of the surface structure layer 10 is The second coefficient q=1.5, the comparative example 2 has the same structural parameters as the above parameters of the product 2, and the thickness of the deposited oxide layer 21 in the comparative example 2 is The third thickness of the oxide layer 21 of product 2 calculated by formula (1) is The experimental results of Comparative Example 2 and Product 2 refer to Figure 8 and Fig. 9 It can be seen that the edge of the surface of the product of comparative example 2 obviously has the defect of insufficient flatness, while the surface of product 2 obtained by the present application scheme has no obvious defects and is well flattened.

[0083] As described above, the surface grinding method of the semiconductor device of the present application, on the first aspect, pre-calculates the third thickness of the oxide layer 21 to be deposited according to the first thickness of the surface structure layer 10 and the target thickness of the oxide layer 21 to be retained after grinding, so as to ensure that after the oxide layer 21 of the second thickness is removed by grinding, the surface of the semiconductor device can be flattened. At the same time, the value of the second thickness is small, which can reduce the grinding amount in the grinding process, avoid waste of production capacity, improve production efficiency, and avoid problems such as poor uniformity of wafer film thickness distribution due to excessive grinding time.

[0084] Secondly, the third thickness is linearly related to the first coefficient and is exponentially related to the surface transmittance. The first coefficient is a function of the first thickness. When the specification parameters of the semiconductor device change, for example, when the first thickness or the surface transmittance of the surface structure layer 10 changes, the third thickness can be adaptively changed, so that the method can be applicable to products of various specifications. The first coefficient is also related to the second coefficient, and the second coefficient is a constant parameter. By adjusting the value of the second coefficient, the third thickness calculated by this method can be made more accurate, while ensuring that it is adapted to products of various specifications in actual production, further improving the applicability of the method.

[0085] On the third aspect, in the present application, the second thickness and the third thickness can be quickly calculated according to formula (1), without the need to perform additional tensile tests on the semiconductor device to obtain the value of the third thickness, which greatly improves production efficiency and saves time and material costs.

[0086] It can be seen that the surface grinding method of the semiconductor device of the present application greatly improves the production efficiency of the wafer by depositing an oxide layer 21 of appropriate thickness, while ensuring a good flattening effect on the surface of the semiconductor device, avoiding waste of production capacity, saving time and material costs, and being applicable to products of various specifications and parameters, and having good applicability, and therefore has great product promotion value.

[0087] The above embodiments are merely illustrative of the principles and effects of the present application and are not intended to limit the present application. Anyone familiar with the technology may modify, change or combine the above embodiments without violating the spirit and scope of the present application. Therefore, all equivalent modifications or changes made by a person of ordinary skill in the art without departing from the spirit and technical ideas disclosed in the present application shall still be covered by the claims of the present application.

Claims

1. A surface grinding method for a semiconductor device, for planarizing the surface of a semiconductor device, wherein the surface of the semiconductor device has a patterned surface structure layer, characterized in that: The following steps are involved: Obtaining the thickness of the surface structure layer and recording it as a first thickness; The thickness of the oxide layer to be removed is calculated according to the first thickness and recorded as the second thickness; Setting the thickness of the remaining oxide layer on the surface structure layer after planarization and recording it as the target thickness; Calculating a third thickness according to the target thickness and the second thickness; forming an oxide layer having a third thickness on the surface structural layer; The oxide layer having the second thickness is removed to obtain a remaining oxide layer having the target thickness, so as to planarize the surface of the semiconductor device.

2. The surface grinding method of a semiconductor device according to claim 1, characterized in that: The surface structure layer includes a gate layer, and the first thickness is the thickness of the gate layer.

3. The surface grinding method of a semiconductor device according to claim 1, characterized in that: The surface structure layer includes a metal layer and an adhesive layer, and the first thickness is the sum of the thickness of the metal layer and the thickness of the adhesive layer.

4. The surface grinding method of a semiconductor device according to claim 1, characterized in that: The step of calculating the thickness to be removed by grinding according to the first thickness and recording it as the second thickness includes the following steps: An exponential relationship is set between the second thickness and the surface transmittance of the semiconductor device, and the exponential relationship is recorded as h2=k1*a^(1-S), wherein h2 is the second thickness, a is the base parameter, k1 is the first coefficient, and S is the surface transmittance; Based on the graphic structure of the surface structure layer, the surface transmittance S of the semiconductor device is calculated; Calculating the first coefficient k1 using the first thickness; Substituting the surface transmittance S and the first coefficient k1 into the above expression, the second thickness h2 is obtained.

5. The surface grinding method of a semiconductor device according to claim 4, characterized in that: Calculating the surface transmittance S of the semiconductor device comprises the following steps: In the top view of the semiconductor device, obtaining a coverage area s1 of the surface structure layer and a coverage area s2 of the oxide layer; The surface transmittance S=1-s1 / s2 is calculated.

6. The surface grinding method of a semiconductor device according to claim 4, characterized in that: The calculation formula of the first coefficient k1 is k1=(h1+1)*q, where h1 is the first thickness, and the unit is q is a preset second coefficient.

7. The surface grinding method of a semiconductor device according to claim 6, characterized in that: The second coefficient q satisfies 1.5≤q≤1.

7.

8. The surface grinding method of a semiconductor device according to claim 4, characterized in that: The base parameter a satisfies 0.8<a<1.

9. The surface grinding method of a semiconductor device according to claim 8, characterized in that: The base parameter a has a value of 0.9 to 0.

99.

10. The surface grinding method of a semiconductor device according to claim 1, characterized in that: The third thickness is the sum of the second thickness and the target thickness, and the oxide layer of the second thickness is removed by grinding using a grinding device to planarize the surface of the semiconductor device.

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