Semiconductor package structure and method of forming the same

Abstract

A semiconductor package structure and a forming method thereof, the forming method comprising: providing a glass substrate, the glass substrate having a plurality of discrete glass via interconnect structures therein, and a recess on a top surface of the glass substrate; providing an un-routed semiconductor chip, the un-routed semiconductor chip comprising a semiconductor substrate and a device layer on a top surface of the semiconductor substrate, the device layer having a semiconductor device therein; mounting the un-routed semiconductor chip into the recess; forming an inorganic dielectric layer on the top surface of the glass substrate, and a first interconnect structure and a second interconnect structure in the inorganic dielectric layer, the first interconnect structure being electrically connected to top surfaces of the glass via interconnect structures, and the second interconnect structure being electrically connected to the semiconductor device, the un-routed semiconductor chip, the second interconnect structure and a portion of the inorganic dielectric layer constituting a first semiconductor chip; forming an organic passivation layer on a bottom surface of the glass substrate, and a third interconnect structure in the organic passivation layer. The performance of the package structure is improved.

Description

Technical Field

[0001] This application relates to the field of semiconductor packaging, and more particularly to a semiconductor packaging structure and a method for forming the same. Background Technology

[0002] The most common type of packaging substrate currently available is the organic material substrate. Organic material substrates are easy to process and can transmit signals at high speeds, and have long been regarded as the leader in the chip industry. However, organic material substrates also have some drawbacks. For example, the difference in thermal expansion coefficients between the organic material substrate and the chip is too large. At high temperatures, the connection points between the chip and the organic material substrate are prone to breakage, making the chip easily burn out. In addition, the size of the organic material substrate is greatly limited, and it cannot accommodate a large number of chips within a limited size.

[0003] Against this backdrop, glass substrates emerged. Glass substrates offer ultra-low flatness (extremely smooth), superior thermal and mechanical stability. Due to the exceptional flatness of glass, the focus depth of photolithography can be improved, allowing for a significantly greater number of openings per square meter compared to organic substrates. This enables through-glass vias to be spaced less than 100 micrometers apart, directly increasing interconnect density between chips by 10 times. Furthermore, the coefficient of thermal expansion of glass substrates is closer to that of the chip, resulting in higher temperature tolerance and a 50% reduction in deformation. This lowers the risk of interconnect breakage and increases chip reliability. In addition, compared to traditional organic substrates, glass substrates not only consume less power but also offer faster signal transmission speeds, and their thickness can be reduced by approximately half. These advantages make glass substrates an ideal choice for next-generation high-density packaging, enabling the construction of higher-performance multi-chip packaging structures.

[0004] However, the performance of existing glass substrate-based packaging structures still needs to be improved. Summary of the Invention

[0005] The technical problem to be solved by this application is to provide a semiconductor packaging structure and a method for forming the same, so as to improve the performance of the packaging structure based on a glass substrate.

[0006] Therefore, this application first provides a method for forming a semiconductor package structure, including:

[0007] A glass substrate is provided, wherein the glass substrate has a plurality of discrete glass through-hole interconnect structures, the upper surface and the lower surface of the glass substrate expose the upper end surface and the lower end surface of the glass through-hole interconnect structure, respectively, and the glass substrate also has a groove located on the upper surface of the glass substrate.

[0008] A semiconductor chip without internal wiring is provided, the semiconductor chip without internal wiring comprising a semiconductor substrate and a device layer located on the upper surface of the semiconductor substrate, the device layer having semiconductor devices therein;

[0009] The semiconductor chip without internal wiring is mounted into the groove, and the upper surface of the device layer of the semiconductor chip without internal wiring is flush with the upper surface of the glass substrate.

[0010] An inorganic dielectric layer and a first interconnect structure and a second interconnect structure are formed on the upper surface of the glass substrate and the upper surface of the device layer of the semiconductor chip without internal wiring. The first interconnect structure is electrically connected to the upper surface of the glass via interconnect structure, and the second interconnect structure is electrically connected to the semiconductor device in the semiconductor chip without internal wiring. A portion of the second interconnect structure is also electrically connected to a portion of the first interconnect structure. The semiconductor chip without internal wiring, the second interconnect structure, and a portion of the inorganic dielectric layer constitute a first semiconductor chip.

[0011] An organic passivation layer and a third interconnect structure located in the organic passivation layer are formed on the lower surface of the glass substrate. The third interconnect structure is electrically connected to the lower end surface of the glass through-hole interconnect structure.

[0012] At least one second semiconductor chip is mounted on the upper surface of the inorganic dielectric layer, and the second semiconductor chip is electrically connected to the first interconnect structure.

[0013] In an optional embodiment, the forming method further includes: forming a plurality of discrete first welding protrusions on the lower surface of the inorganic passivation layer, wherein the first welding protrusions are electrically connected to the third interconnect structure.

[0014] In one optional embodiment, the inorganic dielectric layer, the first interconnect structure, and the second interconnect structure are fabricated using the BEOL process in semiconductor front-end fabrication, and the organic passivation layer and the third interconnect structure are fabricated using the RDL process in semiconductor back-end fabrication; the density of the first interconnect structure is greater than the density of the third interconnect structure, and the feature size of the first interconnect structure is smaller than the feature size of the third interconnect structure; the density of the second interconnect structure is greater than or equal to the density of the first interconnect structure.

[0015] In one optional embodiment, the feature size of the first interconnect structure and the second interconnect structure is 0.2-0.8 micrometers, and the feature size of the third interconnect structure is 1.5-2.5 micrometers.

[0016] In one optional embodiment, the first interconnect structure and the second interconnect structure include one or a combination of several of the following: metal wires, metal plugs, damask structures, or double damask structures; the third interconnect structure is a rewiring layer.

[0017] In one optional embodiment, the inorganic dielectric layer is a multilayer stacked structure, and the first interconnect structure and the second interconnect structure are multilayer stacked structures.

[0018] In an optional embodiment, the inorganic dielectric layer is made of one or a combination of silicon oxide, silicon nitride, silicon oxynitride, silicon carbon oxynitride, silicon carbonitride, or low dielectric constant materials; the organic passivation layer is made of resin material; and the first interconnect structure, the second interconnect structure, and the third interconnect structure are made of one or a combination of Cu, Al, W, Ag, Au, Pt, Ni, Ti, Ta, TiN, TaN, TaC, and WN.

[0019] In an optional embodiment, the device layer further includes a bottom inorganic dielectric layer located on the upper surface of the semiconductor substrate, the bottom inorganic dielectric layer covering the semiconductor device, and the device layer further includes a conductive connection structure located in the bottom inorganic dielectric layer and electrically connected to the active region of the semiconductor device, the conductive connection structure being electrically connected to the second interconnect structure.

[0020] In an optional embodiment, the semiconductor device includes one or a combination of several of bipolar transistors, field-effect transistors, and insulated-gate bipolar transistors.

[0021] In an optional embodiment, the semiconductor device further includes one or a combination of diodes, resistors, capacitors, and inductors.

[0022] In an optional embodiment, the forming method further includes: providing a passive device, attaching the passive device to the lower surface of the glass substrate or embedding it into the glass substrate from the lower surface direction of the glass substrate, wherein the passive device is electrically connected to the third interconnect structure.

[0023] This application also provides a semiconductor packaging structure, including:

[0024] A glass substrate having a plurality of discrete glass through-hole interconnect structures, the upper and lower surfaces of the glass substrate exposing the upper and lower ends of the glass through-hole interconnect structures, and the glass substrate also having a groove located on the upper surface of the glass substrate.

[0025] A semiconductor chip without internal wiring is located in the groove. The semiconductor chip without internal wiring includes a semiconductor substrate and a device layer located on the upper surface of the semiconductor substrate. The device layer has semiconductor devices. The upper surface of the device layer of the semiconductor chip without internal wiring is flush with the upper surface of the glass substrate.

[0026] An inorganic dielectric layer is located on the upper surface of the glass substrate and the upper surface of the device layer of the semiconductor chip without internal wiring, and a first interconnect structure and a second interconnect structure are located in the inorganic dielectric layer. The first interconnect structure is electrically connected to the upper end surface of the glass through-hole interconnect structure, and the second interconnect structure is electrically connected to the semiconductor device in the semiconductor chip without internal wiring. A portion of the second interconnect structure is also electrically connected to a portion of the first interconnect structure. The semiconductor chip without internal wiring, the second interconnect structure, and a portion of the inorganic dielectric layer constitute a first semiconductor chip.

[0027] An organic passivation layer located on the lower surface of the glass substrate and a third interconnect structure located in the organic passivation layer, wherein the third interconnect structure is electrically connected to the lower end surface of the glass through-hole interconnect structure;

[0028] At least one second semiconductor chip is mounted on the upper surface of the inorganic dielectric layer, and the second semiconductor chip is electrically connected to the first interconnect structure.

[0029] In an optional embodiment, the packaging structure further includes a plurality of discrete first welding protrusions located on the lower surface of the inorganic passivation layer, the first welding protrusions being electrically connected to the third interconnect structure.

[0030] In one optional embodiment, the inorganic dielectric layer, the first interconnect structure, and the second interconnect structure are formed using the BEOL process in semiconductor front-end fabrication; the organic passivation layer and the third interconnect structure are formed using the RDL process in semiconductor back-end fabrication; the density of the first interconnect structure is greater than the density of the third interconnect structure, and the feature size of the first interconnect structure is smaller than the feature size of the third interconnect structure; the density of the second interconnect structure is greater than or equal to the density of the first interconnect structure.

[0031] In one optional embodiment, the feature size of the first interconnect structure and the second interconnect structure is 0.2-0.8 micrometers, and the feature size of the third interconnect structure is 1.5-2.5 micrometers.

[0032] In one optional embodiment, the first interconnect structure and the second interconnect structure include one or a combination of several of the following: metal wires, metal plugs, damask structures, or double damask structures; the third interconnect structure is a rewiring layer.

[0033] In an optional embodiment, the inorganic dielectric layer is a multilayer stacked structure, and the first interconnect structure and the second interconnect structure are multilayer stacked structures; the material of the inorganic dielectric layer is one or a combination of several of silicon oxide, silicon nitride, silicon oxynitride, silicon carbon oxycarbide, silicon carbonitride, or low dielectric constant materials; the material of the organic passivation layer is a resin material; and the materials of the first interconnect structure, the second interconnect structure, and the third interconnect structure are one or a combination of several of Cu, Al, W, Ag, Au, Pt, Ni, Ti, Ta, TiN, TaN, TaC, and WN.

[0034] In an optional embodiment, the device layer further includes a bottom inorganic dielectric layer located on the upper surface of the semiconductor substrate, the bottom inorganic dielectric layer covering the semiconductor device, and the device layer further includes a conductive connection structure located in the bottom inorganic dielectric layer and electrically connected to the active region of the semiconductor device, the conductive connection structure being electrically connected to the second interconnect structure.

[0035] In an optional embodiment, the semiconductor device includes one or a combination of several of bipolar transistors, field-effect transistors, and insulated-gate bipolar transistors.

[0036] In an optional embodiment, the semiconductor device further includes one or a combination of diodes, resistors, capacitors, and inductors.

[0037] In an optional embodiment, the packaging structure further includes a passive device, which is mounted on the lower surface of the glass substrate or embedded in the glass substrate from the lower surface direction of the glass substrate, and the passive device is electrically connected to the third interconnect structure.

[0038] Compared with the prior art, the advantages of the technical solution of this application are as follows:

[0039] In this application, the semiconductor chip without internal wiring is fabricated using only the front-end of semiconductor manufacturing (FEOL) process to form a semiconductor device, without the back-end of semiconductor manufacturing (BEOL) process. That is, no internal wiring for interconnecting the semiconductor device is formed. After the semiconductor chip without internal wiring is mounted or embedded in a groove in a glass substrate, an inorganic dielectric layer and a first interconnect structure and a second interconnect structure located in the inorganic dielectric layer are formed on the upper surface of the glass substrate and the upper surface of the device layer of the semiconductor chip without internal wiring through the back-end of semiconductor manufacturing (BEOL) process. The semiconductor chip without internal wiring, the second interconnect structure, and part of the inorganic dielectric layer constitute a first semiconductor chip, so that the first semiconductor chip has corresponding functions (such as logic control and / or data storage). The first semiconductor chip formed through the aforementioned specific steps can increase the functionality of the package structure and improve the performance of the package structure. Furthermore, since the semiconductor chip without internal wiring is fabricated only up to the device layer without internal wiring, the fabrication process is greatly simplified. This also allows for a thinner semiconductor chip, enabling shallower grooves in the glass substrate and maintaining a thinner substrate thickness. Since the semiconductor chip without internal wiring is embedded in the glass substrate, it does not increase the thickness of the packaging structure. Moreover, the second interconnect structure (or internal wiring) for interconnecting semiconductor devices on the semiconductor chip without internal wiring is formed synchronously with the formation of the first interconnect structure on the upper surface of the glass substrate. This ensures the complete realization of the structure and function of the first semiconductor chip while maintaining compatibility between the formation process of the internal wiring of the semiconductor chip without internal wiring and the formation process of the first interconnect structure on the glass substrate. Additionally, semiconductor devices (thin-film transistor packaging) can be omitted from the upper surface of the glass substrate; all semiconductor devices are integrated on the semiconductor chip without internal wiring. This simplifies the process, reduces thermal effects, and optimizes and simplifies the layout of the wiring layer on the upper surface of the glass substrate. Attached Figure Description

[0040] Figures 1-7 This is a schematic diagram of the formation process of a semiconductor packaging structure in one embodiment of this application;

[0041] Figure 8 This is a schematic diagram of the formation process of a semiconductor packaging structure in another embodiment of this application;

[0042] Figure 9 This is a schematic diagram of the formation process of a semiconductor packaging structure in another embodiment of this application. Detailed Implementation

[0043] The specific embodiments of this application will be described in detail below with reference to the accompanying drawings. In describing the embodiments of this application in detail, for ease of explanation, the schematic diagrams may be partially enlarged without adhering to the general scale, and the schematic diagrams are merely examples and should not limit the scope of protection of this application. Furthermore, in actual manufacturing, the three-dimensional spatial dimensions of length, width, and depth should be included.

[0044] This application first provides a method for forming a semiconductor package structure, and the specific process of the forming method will be described in detail below with reference to the accompanying drawings.

[0045] refer to Figure 1 A glass substrate 100 is provided, wherein the glass substrate 100 has a plurality of discrete glass through-hole interconnect structures 103, the upper surface and the lower surface of the glass substrate 100 respectively expose the upper end surface and the lower end surface of the glass through-hole interconnect structure 103, and the glass substrate 100 also has a groove 110 located on the upper surface of the glass substrate 100.

[0046] The glass substrate 100 serves as a support carrier and wiring carrier for the packaging structure. Compared to organic material substrates, the glass substrate 100 has ultra-low flatness (extremely flat), better thermal stability, and mechanical stability. In one embodiment, the material of the glass substrate 100 is glass, crystal, or the like, and the coefficient of thermal expansion of the glass substrate 100 is less than or equal to 9 ppm / ℃, specifically 3 ppm / ℃-4 ppm / ℃ or 6 ppm / ℃-9 ppm / ℃.

[0047] The glass substrate 100 can have a relatively thin thickness and a large size. In one embodiment, the thickness of the glass substrate 100 is less than 800 micrometers. In a specific embodiment, the thickness of the glass substrate 100 can be 300-500 micrometers. In another specific embodiment, the thickness of the glass substrate 100 can be 30-200 micrometers. In one embodiment, the glass substrate 100 is rectangular in shape, and the size of the glass substrate 100 is greater than 100mm x 100mm. Specifically, the size of the glass substrate 100 can be 110mm x 110mm, 300mm x 300mm, 515mm x 510mm, 600mm x 600mm, or 620mm x 750mm.

[0048] The glass substrate 100 has a plurality of discrete through-glass via (TGV) interconnect structures 103 formed therein. In one embodiment, the material of the through-glass via interconnect structure 103 is one or a combination of two or more of the following materials: copper, tungsten, aluminum, nickel, gold, gallium, silver, and titanium. In one embodiment, the formation process of the through-glass via interconnect structure 103 includes: forming through-glass vias (TGV) in the glass substrate 100, wherein the formation of the through-glass vias can be performed by photosensitive glass method, focused power generation method, plasma etching method, laser ablation method, electrochemical discharge machining method, or laser-induced etching method; filling the through-glass vias with a conductive metal material and planarizing the conductive metal material to form the through-glass via interconnect structure 103, wherein the filling of the conductive metal material can be performed by electroplating or physical vapor deposition (e.g., sputtering), and the planarization of the conductive metal material can be performed by chemical mechanical polishing.

[0049] The groove 110 is subsequently used for mounting semiconductor chips without internal wiring. The shape of the groove 110 is the same as that of the subsequently mounted semiconductor chip without internal wiring. The depth of the groove 110 is equal to or slightly greater than the thickness of the semiconductor chip without internal wiring, and the size of the groove 110 is equal to or slightly greater than the size of the semiconductor chip without internal wiring. In one embodiment, the groove 110 is formed after the glass via interconnect structure 103 is formed. The groove 110 can be formed using photosensitive glass method, focused power generation method, plasma etching method, laser ablation method, electrochemical discharge machining method, and laser-induced etching method.

[0050] refer to Figure 2 A semiconductor chip 300 without internal wiring is provided. The semiconductor chip 300 without internal wiring includes a semiconductor substrate 302 and a device layer located on the upper surface of the semiconductor substrate 302, wherein the device layer has a semiconductor device 304.

[0051] The semiconductor chip 300 without internal wiring was fabricated by performing only the front-end of line (FEOL) process to form the semiconductor device 304, without performing the back-end of line (BEOL) process, meaning that no internal wiring for interconnecting the semiconductor device 304 was formed. Subsequently, the semiconductor chip 300 without internal wiring will be mounted on or embedded in the recess 110 of the glass substrate (see reference). Figure 3Afterwards, an inorganic dielectric layer 104 and a first interconnect structure 101 and a second interconnect structure 305 located in the inorganic dielectric layer 104 will be formed on the upper surface of the glass substrate 100 and the upper surface of the device layer of the semiconductor chip 300 without internal wiring (see reference). Figure 4 The first interconnect structure 101 is electrically connected to the upper surface of the glass via interconnect structure 103, and the second interconnect structure 305 is electrically connected to the semiconductor device 304 in the unwired semiconductor chip 300. A portion of the second interconnect structure 305 is also electrically connected to a portion of the first interconnect structure 101. The unwired semiconductor chip 300, the second interconnect structure 305, and a portion of the inorganic dielectric layer 104 constitute the first semiconductor chip (see reference). Figure 4 The first semiconductor chip 301 may have corresponding functions (such as logic control and / or data storage), and the first semiconductor chip 301 may be connected to the second semiconductor chip 201 subsequently mounted on the surface of the inorganic dielectric layer 104 (see reference) through part of the first interconnect structure 101. Figure 6 Interconnection, that is, the first semiconductor chip 301 formed through the aforementioned specific steps, can increase the functionality of the package structure and improve its performance. Furthermore, since the semiconductor chip 300 without internal wiring is only fabricated up to the device layer without internal wiring, the fabrication process of the semiconductor chip 300 without internal wiring is greatly simplified. Simultaneously, the thickness of the semiconductor chip 300 itself is thinner, thus the depth of the groove 110 in the glass substrate 100 can be shallower, allowing the glass substrate 100 to maintain a thinner thickness. Moreover, the semiconductor chip 300 without internal wiring is embedded in the glass substrate 100, without increasing the thickness of the package structure. Furthermore, the second interconnect structure 305 (or internal wiring) for interconnecting semiconductor devices on the semiconductor chip 300 without internal wiring is synchronized with the step of forming the first interconnect structure 101 on the upper surface of the glass substrate 100. This fully realizes the structure and function of the first semiconductor chip 301 while ensuring compatibility between the formation process of the internal wiring of the semiconductor chip 300 without internal wiring and the formation process of the first interconnect structure 101 on the glass substrate 100. Furthermore, semiconductor devices (thin-film transistors) do not need to be fabricated on the upper surface of the glass substrate 100. The semiconductor devices are all integrated on the semiconductor chip 300 without internal wiring. This simplifies the process and reduces the thermal effect. On the other hand, it optimizes and simplifies the layout of the wiring layer on the upper surface of the glass substrate 100.

[0052] In one embodiment, the device layer further includes a bottom inorganic dielectric layer 303 located on the upper surface of the semiconductor substrate 302, the bottom inorganic dielectric layer 303 covering the semiconductor device 304, and the device layer further includes a conductive connection structure 307 located in the bottom inorganic dielectric layer 303 and electrically connected to the active region of the semiconductor device 304. The conductive connection structure 307 is electrically connected to the second interconnect structure 305. The bottom inorganic dielectric layer 303 directly exposes part or all of the active region of the semiconductor device 304, and the bottom inorganic dielectric layer 303 exposes the upper surface of the conductive connection structure 307. In one embodiment, the semiconductor substrate 302 can be a wafer. In one embodiment, the material of the semiconductor substrate 302 is silicon (Si), germanium (Ge), or silicon-germanium (GeSi), silicon carbide (SiC); it can also be silicon-on-insulator (SOI), germanium-on-insulator (GOI); or it can be other materials, such as gallium arsenide or other III-V compounds. The semiconductor substrate 302 can also be implanted with certain dopant ions to change the electrical parameters according to design requirements. In one embodiment, a shallow trench isolation structure 306 is further formed within the semiconductor substrate 302. The shallow trench isolation structure is used to isolate different semiconductor devices 304 and prevent electrical connections between different semiconductor devices 304. The materials of the bottom inorganic dielectric layer 303 and the shallow trench isolation structure 306 can be one or more of silicon oxide, silicon nitride, and silicon oxynitride.

[0053] In one embodiment, the semiconductor device 304 includes one or more of a bipolar transistor, a field-effect transistor, and an insulated-gate bipolar transistor. In another embodiment, the semiconductor device 304 further includes one or more of a diode, a resistor, a capacitor, and an inductor. It should be noted that... Figure 2 The semiconductor device 304 described herein is illustrated using two field-effect transistors as an example. In other embodiments, the semiconductor device 304 may be other semiconductor devices, other numbers, and other layout structures.

[0054] The bipolar junction transistor (BJT), commonly known as a transistor, is an electronic device with three terminals. It is made of three semiconductor components with different doping levels within a semiconductor substrate: an emitter, a base, and a collector. The base has a different doping type than the emitter and collector. For example, in an NPN transistor, the base is P-type doped, while the emitter and collector are N-type doped. For details on the field-effect transistor (FET), please refer to [link to relevant documentation]. Figure 2 The field-effect transistor includes a gate 304a located on the upper surface of a semiconductor substrate 302, and a source 304b and a drain 304c located on both sides of the gate 304a in the semiconductor substrate 302. The field-effect transistor also includes a sidewall 304d located on the sidewall surface of the gate 304a. The field-effect transistor can include a metal-oxide-semiconductor field-effect transistor (MOSFET) or a fin field-effect transistor (FinFET). The MOSFET includes PMOS transistors and NMOS transistors. The insulated-gate bipolar transistor (IGBT) includes a gate, collector, and emitter with different doping levels. The gate has a different doping type than the emitter and collector. For example, in an N-type IGBT, if the gate is P-type, the emitter and collector are N-type doped.

[0055] refer to Figure 3 The semiconductor chip 300 without internal wiring is mounted into the groove 110, and the upper surface of the device layer of the semiconductor chip 300 without internal wiring is flush with the upper surface of the glass substrate 100.

[0056] In one embodiment, before mounting the unwired semiconductor chip 300 into the recess 110, an adhesive is applied to the lower surface (and side surface) of the unwired semiconductor chip 300.

[0057] refer to Figure 4An inorganic dielectric layer 104 and a first interconnect structure 101 and a second interconnect structure 305 are formed on the upper surface of the glass substrate 100 and the upper surface of the device layer of the semiconductor chip 300 without internal wiring. The first interconnect structure 101 is electrically connected to the upper surface of the glass via interconnect structure 103, and the second interconnect structure 305 is electrically connected to the semiconductor device 304 in the semiconductor chip 300 without internal wiring. A portion of the second interconnect structure 305 is also electrically connected to a portion of the first interconnect structure 101. The semiconductor chip 300 without internal wiring, the second interconnect structure 305 and a portion of the inorganic dielectric layer 104 constitute the first semiconductor chip 301.

[0058] The inorganic dielectric layer 104 is used for isolation between adjacent first interconnect structures 101, between adjacent second interconnect structures 305, and between adjacent first interconnect structures 101 and second interconnect structures 305.

[0059] The first interconnect structure 101 is used for interconnection between different chips. In one embodiment, a portion of the first interconnect structure 101 can be used to interconnect a second semiconductor chip 201 (refer to FIG. 5) subsequently mounted on the surface of the inorganic dielectric layer 104 with the glass via interconnect structure 103 in the glass substrate 100. In another embodiment, a portion of the first interconnect structure 101 can also be used for interconnection between a plurality of subsequently mounted second semiconductor chips 201. In yet another embodiment, a portion of the first interconnect structure 101 can also be used for interconnection with a portion of the second interconnect structure 305.

[0060] The second interconnect structure 305 is used for interconnection between semiconductor devices 304 in the device layer of the unwired semiconductor chip 300. A portion of the second interconnect structure 305 is also used for interconnection with a portion of the first interconnect structure 101, such that the first semiconductor chip 301 can be interconnected with a subsequently mounted second semiconductor chip 201 via a portion of the second interconnect structure 305 and a portion of the first interconnect structure 101, or it can still be interconnected with the glass via interconnect structure 103 in the glass substrate 100.

[0061] The inorganic dielectric layer 104 is a multi-layer (multi-layer means ≥ two layers) stacked structure. The first interconnect structure 101 and the second interconnect structure 305 can be multi-layer stacked structures. The number of layers in the first interconnect structure 101 is the same as the number of layers in the inorganic dielectric layer 104. The number of layers in the second interconnect structure 305 can be equal to or less than the number of layers in the inorganic dielectric layer 104. In one embodiment, when the inorganic dielectric layer 104 is an N-layer stacked structure (N can be 2, 3, 4, 5, 6 or greater than 6), the corresponding first interconnect structure 101 is also an N-layer stacked structure, and the second interconnect structure 305 is an N-layer or NM-layer stacked structure (where M is less than N and greater than 0, and M can be 1, 2 or greater than 2). That is, each inorganic dielectric layer 104 can have one layer of the first interconnect structure 101, while for the second interconnect structure 305, each inorganic dielectric layer 104 can have one layer of the second interconnect structure 305. Alternatively, the L-layer (L is less than N) inorganic dielectric layer 104 near the upper surface of the glass substrate 100 can have a corresponding L-layer second interconnect structure 305, while the NL-layer inorganic dielectric layer 104 away from the upper surface of the glass substrate 100 does not have a second interconnect structure 305, but only has the first interconnect structure 101. Figure 4 The inorganic dielectric layer 104 has three layers, the first interconnect structure 101 also has three layers, and the second interconnect structure 305 has two layers, as an example for illustration. The number of layers of the inorganic dielectric layer 104, the first interconnect structure 101, and the second interconnect structure 305 should not limit the scope of protection of this application. Figure 4 The specific structures of the inorganic dielectric layer 104, the first interconnect structure 101, and the second interconnect structure 305 are merely illustrative and should not limit the scope of protection of this application. In other embodiments, the inorganic dielectric layer 104 and the corresponding first interconnect structure 101 may have other numbers of layers, and the inorganic dielectric layer 104 and the corresponding first interconnect structure 101 may have other specific structures.

[0062] In one embodiment, the first interconnect structure 101 and the second interconnect structure 305 may include one or more of the following: metal wires, metal plugs, damask structures, or double damask structures; the inorganic dielectric layer 104 is made of one or more of the following: silicon oxide, silicon nitride, silicon oxynitride, silicon carbon oxynitride, silicon carbonitride, or low dielectric constant materials; and the first interconnect structure and the second interconnect structure 305 are made of one or more (two or more) of the following: Cu, Al, W, Ag, Au, Pt, Ni, Ti, Ta, TiN, TaN, TaC, and WN.

[0063] As is well known, the current semiconductor manufacturing process includes front-end semiconductor processes and back-end semiconductor processes. Front-end semiconductor processes fabricate transistors, resistors, capacitors, and other devices on wafers, as well as the internal wiring that connects these devices. Front-end semiconductor processes are further subdivided into front-end processes (FEOL) and back-end processes (BEOL). Front-end processes (FEOL) are used to fabricate transistors, resistors, capacitors, and other devices, while back-end processes (BEOL) are used to fabricate the internal wiring that connects these devices. Back-end semiconductor processes generally include wafer testing, thinning, die mounting, redistribution layer (RDL), and packaging. In current semiconductor chip packaging, redistribution is typically fabricated using a redistribution layer (RDL) process in the back-end semiconductor manufacturing process. This involves forming a resin material layer (e.g., ABF resin layer) on the surface of a substrate (such as an inorganic substrate, PCB substrate, or glass substrate); exposing and developing the resin material layer to form grooves; and then forming a redistribution layer within these grooves and on the upper surface of the resin material. This method results in a relatively low density of redistribution layers. Due to varying process requirements and yield considerations, back-end of line (BEOL) processes from the front-end semiconductor manufacturing process are not typically applied to the back-end processes in current semiconductor manufacturing.

[0064] The inventors discovered that glass substrates, due to their ultra-low flatness (extremely flat), better thermal stability, and mechanical stability, are similar to, and even superior to, silicon wafers in some aspects. This makes glass substrates highly suitable for the BEOL process in semiconductor front-end fabrication. Therefore, in one embodiment, the inventors unconventionally used the BEOL process in semiconductor front-end fabrication for the fabrication of some redistribution layers (the inorganic dielectric layer 104, the first interconnect structure 101, and the second interconnect structure 305) in the back-end process. Because the BEOL process in semiconductor front-end fabrication is more advanced, the density of the formed first interconnect structure 101 is greater than that of the third interconnect structure 102 subsequently formed on the lower surface of the glass substrate 100 (see reference). Figure 5The density of the redistribution layer (first interconnection structure 101) formed on the upper surface of the glass substrate 100 is increased, and the feature size is smaller (more first interconnection structures 101 can be laid out and more connection ports can be reserved in the same area). This allows the second semiconductor chip to reserve more external ports to be electrically connected to the corresponding connection ports in the first interconnection structure 101 when the second semiconductor chip is subsequently mounted on the upper surface of the inorganic dielectric layer 104, thereby improving the performance of the packaging structure.

[0065] In one embodiment, the density of the second interconnect structure 305 may be greater than or equal to the density of the first interconnect structure 101.

[0066] In one embodiment, the first interconnect structure 101 and the second interconnect structure 305 formed have a feature size of 0.2-0.8 micrometers, and the third interconnect structure 102 formed subsequently has a feature size of 1.5-2.5 micrometers.

[0067] In one embodiment, before forming the inorganic dielectric layer 104, the first interconnect structure 101 and the second interconnect structure 305, an upper pad is formed on the upper surface of the glass substrate 100. The upper pad is electrically connected to the upper end surface of the glass via interconnect structure 103, and the upper pad is also correspondingly used as part of the first interconnect structure 101 and the second interconnect structure 305.

[0068] refer to Figure 5 An organic passivation layer 105 and a third interconnect structure 102 located in the organic passivation layer 105 are formed on the lower surface of the glass substrate 100. The third interconnect structure 102 is electrically connected to the lower end surface of the glass through-hole interconnect structure 103.

[0069] In one embodiment, the third interconnect structure 102 is a redistribution layer (RDL). The organic passivation layer 105 is a single-layer or multi-layer stacked structure, and the third interconnect structure 102 is correspondingly a single-layer or multi-layer stacked structure. The material of the organic passivation layer 105 is a resin material, such as ABF resin or resin of other materials, and the material of the third interconnect structure 102 is one or a combination of several of Cu, Al, W, Ag, Au, Pt, Ni, Ti, Ta, TiN, TaN, TaC, and WN.

[0070] In one embodiment, before forming the organic passivation layer 105 and the third interconnect structure 102, a lower pad is formed on the lower surface of the glass substrate 100. The lower pad is electrically connected to the lower end surface of the glass via interconnect structure 103, and the lower pad is also part of the third interconnect structure 102.

[0071] In one embodiment, the organic passivation layer 105 and the third interconnect structure 102 are fabricated using the RDL process in semiconductor back-end manufacturing. In one embodiment, the process of fabricating the organic passivation layer 105 and the third interconnect structure 102 using the RDL process in semiconductor back-end manufacturing includes: forming an organic passivation layer 105 on the lower surface of a glass substrate 100, the formation process of the organic passivation layer 105 including spin coating; exposing and developing the organic passivation layer 105 to form a groove, the groove exposing the lower end surface of the glass via interconnect structure 103 or an upper pad formed on the lower end surface of the glass via interconnect structure 103; and forming the third interconnect structure 102 in the groove and on a portion of the upper surface of the organic passivation layer 105, the formation process of the third interconnect structure 102 including electroplating.

[0072] In one embodiment, the density of the formed third interconnect structure 102 is less than that of the first interconnect structure 101, the feature size of the third interconnect structure 102 is greater than that of the first interconnect structure 101, and the organic passivation layer 105 and the third interconnect structure 102 are formed after the inorganic dielectric layer 104 and the first interconnect structure 101 are formed. This allows the lower surface of the glass substrate 100 to maintain a high degree of flatness when the inorganic dielectric layer 104 and the first interconnect structure 101 are formed on the upper surface of the glass substrate 100. This facilitates the use of the more advanced BEOL process in semiconductor front-end manufacturing on the upper surface of the glass substrate 100 to create a first interconnect structure with a higher density and smaller feature size.

[0073] refer to Figure 6 At least one second semiconductor chip 201 is mounted on the upper surface of the inorganic dielectric layer 104, and the second semiconductor chip 201 is electrically connected to the first interconnect structure 101.

[0074] The second semiconductor chip 201 includes a back surface and an active surface. An integrated circuit (not shown in the figure) with a specific function is formed in the second semiconductor chip. The active surface has a plurality of external bumps 202 (the plurality of external bumps 202 correspond to a plurality of external ports of the second semiconductor chip), and the plurality of external bumps 202 are electrically connected to the integrated circuit. The external bumps 202 are microbumps (μbumps), and the material of the external bumps 202 is one or a combination of several of the following: tin, tin-silver, tin-lead, tin-silver-copper, tin-silver-zinc, tin-zinc, tin-bismuth-indium, tin-indium, tin-gold, tin-copper, tin-zinc-indium, or tin-silver-antimony.

[0075] In one embodiment, the second semiconductor chip 201 is mounted by flip-chip bonding. Specifically, the active side of the second semiconductor chip 201 is mounted face down on the upper surface of the inorganic dielectric layer 104, and the external protrusion 202 on the active side of the second semiconductor chip 201 is soldered together with the corresponding first interconnect structure 101.

[0076] The number of the mounted second semiconductor chips 201 is one or more (greater than or equal to two). Figure 4 The example of mounting two second semiconductor chips 201 is used for illustration.

[0077] In one embodiment, when there are multiple second semiconductor chips 201 mounted, the multiple second semiconductor chips 201 can be semiconductor chips with the same function or different functions.

[0078] In one embodiment, the plurality of second semiconductor chips 201 may include logic chips and / or memory chips. In some embodiments, the logic chip may include, but is not limited to, gate arrays, cell substrate arrays, embedded arrays, application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), complex programmable logic devices (CPLDs), graphics processing units (GPUs), central processing units (CPUs), microprocessor units (MPUs), microcontroller units (MCUs), logic integrated circuits (ICs), application processors (APs), display driver ICs (DDIs), radio frequency (RF) chips, power supply chips, or complementary metal-oxide-semiconductor (CMOS) image sensors. In some embodiments, the memory chip may include, but is not limited to, dynamic random access memory (DRAM), static random access memory (SRAM), magnetoresistive random access memory (MRAM), phase-change memory (PRAM), resistive random access memory (RRAM), or non-volatile memory chips (such as flash memory).

[0079] In one embodiment, reference Figure 7 It also includes: forming a plurality of discrete first welding protrusions 106 on the lower surface of the organic passivation layer 105, wherein the first welding protrusions 106 are electrically connected to the third interconnection structure 102.

[0080] The first solder bump 106 serves as a port for connecting the package structure to other substrates, other package structures, and devices. In one embodiment, the material of the first solder bump 106 is one or a combination of tin, tin silver, tin lead, tin silver copper, tin silver zinc, tin zinc, tin bismuth indium, tin indium, tin gold, tin copper, tin zinc indium, or tin silver antimony.

[0081] In one embodiment, before forming the first weld protrusion 106, a second inorganic passivation layer (not shown) may be formed on the lower surface of the organic passivation layer 105, the second inorganic passivation layer exposing a portion of the lower surface of the third interconnect structure 102.

[0082] Another embodiment of this application also provides a method for forming a semiconductor package structure, see reference. Figure 8The main difference between this embodiment and the previous embodiment is that a passive device 401 is provided. The passive device 401 is embedded in the glass substrate 100 from the lower surface direction. The passive device 401 is electrically connected to the third interconnect structure 102 to further improve the function and performance of the packaging structure. Furthermore, when the passive device 401 is embedded in the glass substrate 100, it does not occupy wiring space on the lower surface of the glass substrate 100, nor does it increase the thickness of the packaging structure. In a specific embodiment, a second groove (not shown in the figure) is pre-formed in the glass substrate 100. The second groove is located on the lower surface of the glass substrate 100. The passive device 401 is mounted in the second groove, so that the passive device 401 is embedded in the glass substrate 100. The embedded position of the passive device 401 is located below the embedded position of the semiconductor chip 300 without internal wiring.

[0083] In one embodiment, the passive device 401 is one or more of a resistor, capacitor, or inductor.

[0084] Another embodiment of this application also provides a method for forming a semiconductor package structure, see reference. Figure 9 The main difference between this embodiment and the previous embodiments is that a passive device 401 is provided and mounted on the lower surface of the glass substrate 100. The passive device 401 is electrically connected to the third interconnect structure 102 to further improve the function and performance of the packaging structure. Another embodiment of this application also provides a semiconductor packaging structure, see reference... Figure 7 ,include:

[0085] A glass substrate 100 has a plurality of discrete glass through-hole interconnect structures 103. The upper and lower surfaces of the glass substrate 100 expose the upper and lower end surfaces of the glass through-hole interconnect structures 103, respectively. The glass substrate also has a groove 110 (see reference). Figure 1 or Figure 3 The groove 110 is located on the upper surface of the glass substrate 100;

[0086] The semiconductor chip 300 without internal wiring is located in the groove 110. The semiconductor chip 300 without internal wiring includes a semiconductor substrate 302 and a device layer located on the upper surface of the semiconductor substrate 302. The device layer has a semiconductor device 304. The upper surface of the device layer of the semiconductor chip 300 without internal wiring is flush with the upper surface of the glass substrate 100.

[0087] An inorganic dielectric layer 104 is located on the upper surface of the glass substrate 100 and the upper surface of the device layer of the semiconductor chip 300 without internal wiring, and a first interconnect structure 101 and a second interconnect structure 305 are located in the inorganic dielectric layer 104. The first interconnect structure 101 is electrically connected to the upper end surface of the glass through-hole interconnect structure 103, and the second interconnect structure 305 is electrically connected to the semiconductor device 304 in the semiconductor chip 300 without internal wiring. A portion of the second interconnect structure 305 is also electrically connected to a portion of the first interconnect structure 101. The semiconductor chip 300 without internal wiring, the second interconnect structure 305, and a portion of the inorganic dielectric layer 104 constitute the first semiconductor chip 301.

[0088] An organic passivation layer 105 is located on the lower surface of the glass substrate 100, and a third interconnect structure 102 is located in the organic passivation layer 105. The third interconnect structure 102 is electrically connected to the lower end surface of the glass via interconnect structure 103, and the density of the first interconnect structure 101 is greater than the density of the third interconnect structure 102. The feature size of the first interconnect structure 101 is smaller than the feature size of the third interconnect structure 102.

[0089] At least one second semiconductor chip 201 is mounted on the upper surface of the inorganic dielectric layer 104, and the second semiconductor chip 201 is electrically connected to the first interconnect structure 101.

[0090] In one embodiment, it further includes a plurality of discrete first welding protrusions 106 located on the lower surface of the organic passivation layer 105, the first welding protrusions 106 being electrically connected to the third interconnect structure 102.

[0091] In one embodiment, the first interconnect structure 101 and the second interconnect structure 305 include one or a combination of metal wires, metal plugs, damask structures or double damask structures; the third interconnect structure 102 is a rewiring layer.

[0092] In one embodiment, the inorganic dielectric layer 104 is a multilayer stacked structure, with the first interconnect structure 101 and the second interconnect structure 305 being a multilayer stacked structure; the material of the inorganic dielectric layer 104 is one or a combination of several of silicon oxide, silicon nitride, silicon oxynitride, silicon carbon oxycarbide, silicon carbonitride, or low dielectric constant materials; the material of the organic passivation layer 105 is a resin material; and the materials of the first interconnect structure 101, the second interconnect structure 305, and the third interconnect structure 102 are one or a combination of several of Cu, Al, W, Ag, Au, Pt, Ni, Ti, Ta, TiN, TaN, TaC, and WN.

[0093] In one embodiment, the inorganic dielectric layer 104, the first interconnect structure 101, and the second interconnect structure 305 are formed using the BEOL process in semiconductor front-end fabrication; the organic passivation layer 105 and the third interconnect structure 102 are formed using the RDL process in semiconductor back-end fabrication; the density of the first interconnect structure 101 is greater than the density of the third interconnect structure 102, and the feature size of the first interconnect structure 101 is smaller than the feature size of the third interconnect structure 102; the density of the second interconnect structure 305 is greater than or equal to the density of the first interconnect structure 101. In one embodiment, the feature size of the first interconnect structure 101 and the second interconnect structure 305 is 0.2-0.8 micrometers, and the feature size of the third interconnect structure 102 is 1.5-2.5 micrometers.

[0094] In one embodiment, reference Figure 2 The device layer further includes a bottom inorganic dielectric layer 303 located on the upper surface of the semiconductor substrate 302, the bottom inorganic dielectric layer 303 covering the semiconductor device 304, and the device layer further includes a conductive connection structure 307 located in the bottom inorganic dielectric layer 303 and electrically connected to the active region of the semiconductor device 304, the conductive connection structure 307 being electrically connected to the second interconnect structure 305.

[0095] In one embodiment, the semiconductor device 304 includes a bipolar transistor and a field-effect transistor (refer to...). Figure 9 ( ) and a combination of one or more of the insulated gate bipolar transistors.

[0096] In another embodiment, the semiconductor device 304 may further include one or a combination of diodes, resistors, capacitors and inductors.

[0097] In one embodiment, the packaging structure further includes a passive device 401, which is mounted on the lower surface of the glass substrate (see reference). Figure 9 Alternatively, it can be embedded in the glass substrate 100 from the lower surface direction (see reference). Figure 8 The passive device 401 is electrically connected to the third interconnect structure 102.

[0098] It should be noted that the parts that are the same or similar to those in the embodiments of the semiconductor packaging structure and the embodiments of the semiconductor packaging structure forming method described above will not be repeated in the embodiments of the semiconductor packaging structure. For details, please refer to the limitations or descriptions of the corresponding parts in the embodiments of the semiconductor packaging structure forming method described above.

[0099] Although this application has been disclosed above with reference to preferred embodiments, it is not intended to limit this application. Any person skilled in the art can make possible changes and modifications to the technical solutions of this application by utilizing the methods and techniques disclosed above without departing from the spirit and scope of this application. Therefore, any simple modifications, equivalent changes and alterations made to the above embodiments based on the technical essence of this application without departing from the content of the technical solutions of this application shall fall within the protection scope of the technical solutions of this application.

Claims

1. A method for forming a semiconductor package structure, characterized in that, include: A glass substrate is provided, wherein the glass substrate has a plurality of discrete glass through-hole interconnect structures, the upper surface and the lower surface of the glass substrate expose the upper end surface and the lower end surface of the glass through-hole interconnect structure, respectively, and the glass substrate also has a groove located on the upper surface of the glass substrate. A semiconductor chip without internal wiring is provided, the semiconductor chip without internal wiring comprising a semiconductor substrate and a device layer located on the upper surface of the semiconductor substrate, the device layer having semiconductor devices therein; The semiconductor chip without internal wiring is mounted into the groove, and the upper surface of the device layer of the semiconductor chip without internal wiring is flush with the upper surface of the glass substrate. An inorganic dielectric layer and a first interconnect structure and a second interconnect structure are formed on the upper surface of the glass substrate and the upper surface of the device layer of the semiconductor chip without internal wiring. The first interconnect structure is electrically connected to the upper surface of the glass via interconnect structure, and the second interconnect structure is electrically connected to the semiconductor device in the semiconductor chip without internal wiring. A portion of the second interconnect structure is also electrically connected to a portion of the first interconnect structure. The semiconductor chip without internal wiring, the second interconnect structure, and a portion of the inorganic dielectric layer constitute a first semiconductor chip. An organic passivation layer and a third interconnect structure located in the organic passivation layer are formed on the lower surface of the glass substrate. The third interconnect structure is electrically connected to the lower end surface of the glass through-hole interconnect structure. At least one second semiconductor chip is mounted on the upper surface of the inorganic dielectric layer, and the second semiconductor chip is electrically connected to the first interconnect structure.

2. The method for forming a semiconductor package structure as described in claim 1, characterized in that, The forming method further includes: forming a plurality of discrete first welding protrusions on the lower surface of the organic passivation layer, wherein the first welding protrusions are electrically connected to the third interconnect structure.

3. The method for forming a semiconductor package structure as described in claim 1 or 2, characterized in that, The inorganic dielectric layer, the first interconnect structure, and the second interconnect structure are fabricated using the BEOL process in semiconductor front-end manufacturing, and the organic passivation layer and the third interconnect structure are fabricated using the RDL process in semiconductor back-end manufacturing. The density of the first interconnect structure is greater than that of the third interconnect structure, and the feature size of the first interconnect structure is smaller than that of the third interconnect structure. The density of the second interconnect structure is greater than or equal to that of the first interconnect structure.

4. The method for forming a semiconductor package structure as described in claim 3, characterized in that, The first interconnect structure and the second interconnect structure have a feature size of 0.2-0.8 micrometers, and the third interconnect structure has a feature size of 1.5-2.5 micrometers.

5. The method for forming a semiconductor package structure as described in claim 3, characterized in that, The first interconnect structure and the second interconnect structure include one or a combination of several of the following: metal wires, metal plugs, damask structures, or double damask structures; the third interconnect structure is a rewiring layer.

6. The method for forming a semiconductor package structure as described in claim 3, characterized in that, The inorganic dielectric layer is a multilayer stacked structure, and the first interconnect structure and the second interconnect structure are multilayer stacked structures.

7. The method for forming a semiconductor package structure as described in claim 3, characterized in that, The inorganic dielectric layer is made of one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbon oxynitride, silicon carbonitride, or low dielectric constant materials. The organic passivation layer is made of resin. The first interconnect structure, the second interconnect structure, and the third interconnect structure are made of one or more of Cu, Al, W, Ag, Au, Pt, Ni, Ti, Ta, TiN, TaN, TaC, and WN.

8. The method for forming a semiconductor package structure as described in claim 1, characterized in that, The device layer further includes a bottom inorganic dielectric layer located on the upper surface of the semiconductor substrate, the bottom inorganic dielectric layer covering the semiconductor device, and the device layer further includes a conductive connection structure located in the bottom inorganic dielectric layer and electrically connected to the active region of the semiconductor device, the conductive connection structure being electrically connected to the second interconnect structure.

9. The method for forming a semiconductor package structure as described in claim 8, characterized in that, The semiconductor device includes one or a combination of several of the following: bipolar transistors, field-effect transistors, and insulated-gate bipolar transistors.

10. The method for forming a semiconductor package structure as described in claim 9, characterized in that, The semiconductor device also includes one or more of diodes, resistors, capacitors and inductors.

11. The method for forming a semiconductor package structure as described in claim 1, characterized in that, The forming method further includes: providing a passive device, attaching the passive device to the lower surface of the glass substrate or embedding it into the glass substrate from the lower surface direction of the glass substrate, wherein the passive device is electrically connected to the third interconnect structure.

12. A semiconductor packaging structure, characterized in that, include: A glass substrate having a plurality of discrete glass through-hole interconnect structures, the upper and lower surfaces of the glass substrate exposing the upper and lower ends of the glass through-hole interconnect structures, and the glass substrate also having a groove located on the upper surface of the glass substrate. A semiconductor chip without internal wiring is located in the groove. The semiconductor chip without internal wiring includes a semiconductor substrate and a device layer located on the upper surface of the semiconductor substrate. The device layer has semiconductor devices. The upper surface of the device layer of the semiconductor chip without internal wiring is flush with the upper surface of the glass substrate. An inorganic dielectric layer is located on the upper surface of the glass substrate and the upper surface of the device layer of the semiconductor chip without internal wiring, and a first interconnect structure and a second interconnect structure are located in the inorganic dielectric layer. The first interconnect structure is electrically connected to the upper end surface of the glass through-hole interconnect structure, and the second interconnect structure is electrically connected to the semiconductor device in the semiconductor chip without internal wiring. A portion of the second interconnect structure is also electrically connected to a portion of the first interconnect structure. The semiconductor chip without internal wiring, the second interconnect structure, and a portion of the inorganic dielectric layer constitute a first semiconductor chip. An organic passivation layer located on the lower surface of the glass substrate and a third interconnect structure located in the organic passivation layer, wherein the third interconnect structure is electrically connected to the lower end surface of the glass through-hole interconnect structure; At least one second semiconductor chip is mounted on the upper surface of the inorganic dielectric layer, and the second semiconductor chip is electrically connected to the first interconnect structure.

13. The semiconductor packaging structure as described in claim 12, characterized in that, The packaging structure further includes a plurality of discrete first welding protrusions located on the lower surface of the organic passivation layer, the first welding protrusions being electrically connected to the third interconnect structure.

14. The semiconductor packaging structure as described in claim 12 or 13, characterized in that, The inorganic dielectric layer, the first interconnect structure, and the second interconnect structure are formed using the BEOL process in semiconductor front-end fabrication; the organic passivation layer and the third interconnect structure are formed using the RDL process in semiconductor back-end fabrication; the density of the first interconnect structure is greater than the density of the third interconnect structure, and the feature size of the first interconnect structure is smaller than the feature size of the third interconnect structure; the density of the second interconnect structure is greater than or equal to the density of the first interconnect structure.

15. The semiconductor packaging structure as described in claim 14, characterized in that, The first interconnect structure and the second interconnect structure have a feature size of 0.2-0.8 micrometers, and the third interconnect structure has a feature size of 1.5-2.5 micrometers.

16. The semiconductor packaging structure as described in claim 14, characterized in that, The first interconnect structure and the second interconnect structure include one or a combination of several of the following: metal wires, metal plugs, damask structures, or double damask structures; the third interconnect structure is a rewiring layer.

17. The semiconductor packaging structure as described in claim 14, characterized in that, The inorganic dielectric layer is a multilayer stacked structure, and the first interconnect structure and the second interconnect structure are multilayer stacked structures; the material of the inorganic dielectric layer is one or a combination of several of silicon oxide, silicon nitride, silicon oxynitride, silicon carbon oxycarbide, silicon carbonitride, or low dielectric constant materials; the material of the organic passivation layer is a resin material; and the materials of the first interconnect structure, the second interconnect structure, and the third interconnect structure are one or a combination of several of Cu, Al, W, Ag, Au, Pt, Ni, Ti, Ta, TiN, TaN, TaC, and WN.

18. The semiconductor packaging structure as described in claim 12, characterized in that, The device layer further includes a bottom inorganic dielectric layer located on the upper surface of the semiconductor substrate, the bottom inorganic dielectric layer covering the semiconductor device, and the device layer further includes a conductive connection structure located in the bottom inorganic dielectric layer and electrically connected to the active region of the semiconductor device, the conductive connection structure being electrically connected to the second interconnect structure.

19. The semiconductor packaging structure as described in claim 18, characterized in that, The semiconductor device includes one or a combination of several of the following: bipolar transistors, field-effect transistors, and insulated-gate bipolar transistors.

20. The semiconductor packaging structure as described in claim 19, characterized in that, The semiconductor device also includes one or more of diodes, resistors, capacitors and inductors.

21. The semiconductor packaging structure as described in claim 12, characterized in that, The packaging structure further includes a passive device, which is mounted on the lower surface of the glass substrate or embedded in the glass substrate from the lower surface direction of the glass substrate, and the passive device is electrically connected to the third interconnect structure.

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