Packaging structure and forming method thereof

Abstract

A method of forming a package structure includes forming an integrated circuit device on a semiconductor substrate of a wafer, forming a voltage regulator in the wafer, and forming a metal layer as part of the wafer. The transistor is formed farther away from the semiconductor substrate than the metal layer. The transistor includes a first source / drain region connected to the voltage regulator, and the voltage regulator is configured to convert a first voltage received from the first source / drain region to a second voltage lower than the first voltage, and to supply the second voltage to the integrated circuit device. An electrical connector is formed on the surface of the wafer and electrically connected to the second source / drain region of the transistor. The embodiment of the invention also discloses a packaging structure.

Description

Technical Field

[0001] Embodiments of the present application relate to a packaging structure and a method for forming the same. Background Art

[0002] An integrated circuit may require a multi-level supply voltage. For example, the supply voltage used by the integrated circuit may include 12V, 5V, 3.3V, and 0.9V. Therefore, multiple voltage regulators may be used to generate voltages of different levels. Multiple voltage regulators may be located in multiple dies to achieve voltage conversion to different voltage levels. Summary of the invention

[0003] According to one aspect of an embodiment of the present application, a method for forming a packaging structure is provided, comprising: forming an integrated circuit device on a semiconductor substrate of a wafer; forming a voltage regulator in the wafer; forming a first metal layer as part of the wafer; forming a transistor farther away from the semiconductor substrate than the first metal layer, wherein the transistor includes a first source / drain region connected to the voltage regulator, and the voltage regulator is configured to convert a first voltage received from the first source / drain region into a second voltage lower than the first voltage, and provide the second voltage to the integrated circuit device; and forming an electrical connector on a surface of the wafer, wherein the electrical connector is electrically connected to the second source / drain region of the transistor.

[0004] According to another aspect of an embodiment of the present application, a packaging structure is provided, comprising: a device die, the device die comprising: a semiconductor substrate; an integrated circuit device located on a surface of the semiconductor substrate; a voltage regulator, the voltage regulator comprising: an input terminal; and a plurality of output terminals, wherein the voltage regulator is configured to convert a first voltage received from the input terminal into a plurality of second voltages lower than the first voltage, and wherein the plurality of output terminals are electrically connected to the integrated circuit device; and an electrical connector located at the surface of the device die, wherein the device die is configured to transfer the first voltage received from the electrical connector to the input terminal.

[0005] According to another aspect of an embodiment of the present application, a packaging structure is provided, comprising: a device die, the device die comprising: a semiconductor substrate; an integrated circuit device located at the surface of the semiconductor substrate; a voltage regulator, comprising an output terminal connected to the integrated circuit device and also comprising an input terminal; a plurality of metal layers located on the semiconductor substrate; and a transistor located in the plurality of metal layers, wherein the transistor comprises: a first source / drain region connected to the input terminal of the voltage regulator; and a second source / drain region; and an electrical connector located at the surface of the device die, wherein the electrical connector is electrically connected to the second source / drain region; a printed circuit board located below the device die and electrically connected to the device die; and a power die configured to generate a supply voltage, wherein the packaging structure is configured to connect the supply voltage to the second source / drain region of the transistor. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Various aspects of the present disclosure can be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be emphasized that, in accordance with standard practice in the industry, the various components are not drawn to scale and are only used for illustrative purposes. In fact, the size of the various components may be arbitrarily increased or reduced for clarity of discussion.

[0007] Figure 1-Figure 6 A cross-sectional view of an intermediate stage during formation of a die including an embedded voltage regulator is shown in accordance with some embodiments.

[0008] Figure 7-Figure 11 A diagram illustrating a power switch for an embedded voltage regulator according to some embodiments.

[0009] Fig.12 A package of a device die including an embedded voltage regulator is shown in accordance with some embodiments.

[0010] Fig.13 A top view of a package including a power die and a device die is shown in accordance with some embodiments.

[0011] Fig.14 An embedded voltage regulator for converting a higher supply voltage to a lower supply voltage is shown in accordance with some embodiments.

[0012] Fig.15 A process flow for forming a device die including an embedded voltage regulator is shown in accordance with some embodiments. DETAILED DESCRIPTION

[0013] The following disclosure provides many different embodiments or examples for realizing different features of the present disclosure. Specific embodiments or examples of components and arrangements are described below to simplify the present disclosure. Of course, these are only examples and are not intended to be limiting. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are directly contacted, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. In addition, the present disclosure may repeat reference numbers and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0014] Additionally, for ease of description, spacing relation terms such as "below," "beneath," "lower," "above," "upper," etc. may be used herein to describe the relationship of one element or component to another element or component as shown in the figures. The spacing relation terms are intended to encompass different orientations of the device in use or in the process of operation in addition to the orientation shown in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spacing relation descriptors used herein may likewise be interpreted accordingly.

[0015] A device die including an embedded voltage regulator is provided. The embedded voltage regulator also includes a power switch formed in a back-end-of-line (BEOL) structure or a back-side interconnect structure of the device die. A method for forming a device die is also provided. According to some embodiments of the present disclosure, a higher supply voltage is provided to the device die and converted to a lower supply voltage by an embedded voltage regulator embedded inside the device die. The embedded voltage regulator may also include a power switch formed by a thin film transistor as part of its control circuit. The thin film transistor may be an InGaZnO (IGZO) transistor, which is formed in the BEOL structure of the device chip or the back-side interconnect structure of the device die. By forming the embedded voltage regulator within the device die, power losses due to the lower supply voltage are reduced.

[0016] The embodiments discussed herein are intended to provide examples to enable making or using the subject matter of the present disclosure, and those of ordinary skill in the art will readily appreciate the modifications that may be made while remaining within the intended scope of the different embodiments. In the various views and illustrative embodiments, the same reference numerals are used to represent the same elements. Although the method embodiments may be discussed as being performed in a particular order, other method embodiments may also be performed in any logical order.

[0017] Figures 1 to 6 1 shows a cross-sectional view of an intermediate stage during the formation of a device die according to some embodiments of the present disclosure. The corresponding process is also schematically reflected in Fig.15 The process flow shown.

[0018] Figure 1 A cross-sectional view of wafer 20 is shown. According to some embodiments, wafer 20 is or includes a device wafer including active devices and possibly passive devices, which are represented as integrated circuit devices 24. Wafer 20 may include a plurality of chips / dies 20' therein, of which one of chips 20' is shown.

[0019] According to some embodiments, the wafer 20 includes a semiconductor substrate 22 and a component formed at a top surface of the semiconductor substrate 22. The semiconductor substrate 22 may be formed of or include crystalline silicon, crystalline germanium, crystalline silicon germanium, crystalline carbon-doped silicon, or a III-V compound semiconductor (e.g., GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, GaInAsP, etc.). A shallow trench isolation (STI) region (not shown) may be formed in the semiconductor substrate 22 to isolate an active region within the semiconductor substrate 22.

[0020] According to some embodiments, integrated circuit device 24 is formed on the top surface of semiconductor substrate 22, collectively referred to as a front-end-of-line (FEOL) structure. Fig.15 As shown, in flow 200, the corresponding process is shown as process 202. According to some embodiments, integrated circuit device 24 may include complementary metal oxide semiconductor (CMOS) transistors, resistors, capacitors, diodes, etc. According to some embodiments, integrated circuit device 24 includes integrated circuit device 24A powered by a gated power supply and integrated circuit device 24B powered by a non-gated power supply, as discussed in detail in subsequent paragraphs.

[0021] like Figure 1 and Figure 2 As shown, interconnect structure 32 is formed on integrated circuit device 24 and is electrically connected to integrated circuit device 24. Fig.15 As shown, in the process 200, the corresponding process is shown as process 204. According to some embodiments, the interconnect structure 32 includes an interlayer dielectric (ILD) 28 formed on the semiconductor substrate 22 and filling the space between the gate stacks of the transistors (not shown) in the integrated circuit device 24. According to some embodiments, the ILD 28 is formed of silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), fluorine-doped silicate glass (FSG), etc. The ILD 28 can be formed by spin coating, flowable chemical vapor deposition (FCVD), etc. According to some embodiments, the ILD 28 can also be formed using a deposition method, such as plasma enhanced chemical vapor deposition (PECVD), low pressure chemical vapor deposition (LPCVD), etc.

[0022] Contact plug 30 is formed in ILD 28 for electrically connecting integrated circuit device 24 to overlying metal lines and vias. According to some embodiments, contact plug 30 is formed of or includes a conductive material selected from tungsten, aluminum, copper, titanium, tantalum, titanium nitride, tantalum nitride, alloys, and / or multilayers thereof. The formation of contact plug 30 may include forming a contact opening in ILD 28, filling the contact opening with a conductive material, and performing a planarization process (such as a chemical mechanical polishing (CMP) process or a mechanical grinding process) to make the top surface of contact plug 30 flush with the top surface of ILD 28.

[0023] According to some embodiments, through vias 26 (alternatively referred to as through silicon vias (TSVs) or through semiconductor vias (also referred to as TSVs) are formed in wafer 20. Through vias 26 may extend from a top surface of semiconductor substrate 22 to an intermediate level between the top surface and the bottom surface. Top ends of through vias 26 may extend to a top surface of ILD 28. Alternatively, top ends of through vias 26 may be at any available level, such as a top surface level of semiconductor substrate 22, or a top surface level of any of dielectric layers 38. Each through via 26 may be surrounded by a dielectric isolation layer (not shown) that electrically insulates the corresponding through via 26 from semiconductor substrate 22.

[0024] According to Figure 1 In some embodiments shown, the formation of through vias 26 includes a via first process or a via middle process, wherein through vias 26 are formed from the front side of semiconductor substrate 22. According to alternative embodiments, a via last process may be employed to form through vias 26, and through vias 26 may be formed from the back side of wafer 20.

[0025] The through-vias 26 include power through-vias 26A for conducting non-gated power and through-vias 26B for conducting signals. Additional through-vias may or may not be present, such as through-via 26C, which also conducts gated power that can be gated on the back side of semiconductor substrate 24.

[0026] refer to Figure 1 and Figure 2 , more metal layers and dielectric layers are formed to extend the interconnect structure 32 upward. The interconnect structure 32 also includes a dielectric layer 38 (also called an intermetallic dielectric (IMD)), an etch stop layer (not shown), and metal lines 34 and through-holes 36 formed in the dielectric layer 38. The metal lines at the same level are collectively referred to as metal layers below. According to some embodiments, the interconnect structure 32 includes multiple metal layers (M0 to Mtop), including metal lines 34 interconnected by through-holes 36. The metal layers in the interconnect structure 32 can be represented as M0, M1, M2, M3, etc.

[0027] Metal lines 34 and through-holes 36 may be formed of copper or copper alloys, or may be formed of or include other metals such as aluminum, tungsten, nickel, etc. According to some embodiments, dielectric layer 38 is formed of a low-k dielectric material. For example, the dielectric constant (k value) of the low-k dielectric material may be lower than about 3.5 or lower than about 3.0. Dielectric layer 38 may include a carbon-containing low-k dielectric material, hydrogen silsesquioxane (HSQ), methyl silsesquioxane (MSQ), etc. The etch stop layer may be formed of or include aluminum oxide, aluminum nitride, SiOC, SiON, etc., or a multilayer thereof.

[0028] Forming metal lines 34 and through-holes 36 in dielectric layers 38 may include a single damascene process and / or a dual damascene process. In a single damascene process for forming metal lines or through-holes, a trench or through-hole opening is first formed in one of dielectric layers 38, and then the trench or through-hole opening is filled with a conductive material. A planarization process, such as a CMP process, is then performed to remove excess conductive material above the top surface of the dielectric layer and leave metal lines or through-holes in the corresponding trench or through-hole opening.

[0029] In the dual damascene process, trenches and through-hole openings are formed in the dielectric layer, and the through-hole openings are located below and connected to the trenches. Then, conductive materials are filled into the trenches and through-hole openings to form metal lines and vias, respectively. The conductive materials may include a diffusion barrier layer and a copper-containing metal material on the diffusion barrier layer. The diffusion barrier layer may include titanium, titanium nitride, tantalum, tantalum nitride, etc.

[0030] The top metal layer is referred to as metal layer Mtop, the metal layer immediately below metal layer Mtop is referred to as metal layer M(top-1), the metal layer immediately below metal layer M(top-1) is referred to as metal layer M(top-2), and so on. According to some embodiments, the total number of metal layers may be greater than about 9, and may be in the range of about 9 to 16. According to some embodiments, the top metal layer Mtop is formed in dielectric layer 38T, which is the top layer of dielectric layer 38. As described above, dielectric layer 38T may be formed of or include a low-k dielectric material. Alternatively, dielectric layer 38T may be formed of or include a non-low-k dielectric material, such as undoped silicate glass (USG), silicon oxide, silicon oxynitride, silicon nitride, etc., or a combination thereof.

[0031] According to some embodiments, between the integrated circuit device 24 and the overlying interconnect structure 32 ( Figure 6) is formed in the same formation process as that of the power supply circuit 160. The voltage regulator circuit 160 is configured to convert a higher supply voltage (e.g., 12V) into a lower voltage (e.g., 5V, 3.3V, 1.2V, 0.9V, 0.75V, etc.), and can also be configured to convert the converted lower supply voltage (e.g., 5V or 3.3V) into a lower supply voltage (e.g., 3.3V, 1.26, 0.9V, or 0.75V, etc.). In addition, the voltage regulator circuit 160 may include one or more power switches (e.g., Figure 6 The thin film transistors 40 and 40' (interchangeably referred to as power switches) in FIG. 1 are used to control whether and when a supply voltage is provided to certain circuits but not to other circuits.

[0032] According to some embodiments, thin film transistor 40 is formed as a power switch in one of the metal layers or between two adjacent metal layers. Fig.15 As shown, in process 200, the corresponding process is shown as process 206. According to some example embodiments, Figure 2 As shown, thin film transistor 40 is formed at a top position of interconnect structure 32 , for example, between metal layers Mtop and M(top- 1 ).

[0033] A dielectric layer 42 may be formed on the top metal layer Mtop and the top dielectric layer 38T. Fig.15 As shown, in the process 200, the corresponding process is shown as process 208. According to some embodiments, the dielectric layer 42 may be formed of or include a silicon-based dielectric material, such as SiO, SiN, SiON, SiOCN, SiOC, etc., combinations thereof, or multiple layers thereof. The dielectric layer 42 may sometimes be used to bond to a supporting substrate, and thus may be referred to as a bonding layer hereinafter.

[0034] Forming thin film transistor 40 at the top position of interconnect structure 32 has some advantageous features. Thin film transistor 40 is used as a power switch. Therefore, the size of thin film transistor 40 (and the chip area occupied) is large. For example, the chip area occupied by thin film transistor 40 in the device die may be between about 4% and about 8% of the device die. The upper metal layer has a large pitch and a large metal line width suitable for the formation of thin film transistor 40. In addition, the upper metal layer has a greater thickness and a greater distance from its adjacent metal layer, and reduces the process difficulty of forming thin film transistor 40.

[0035] Figure 7 A perspective view of thin film transistor 40 and underlying metal layers is shown in accordance with some embodiments. Integrated circuit device 24 and M0 power rail are also schematically shown to show the location of thin film transistor 40.

[0036] Figure 8A cross-sectional view of a thin film transistor 40 according to some embodiments is shown. According to some embodiments, the thin film transistor 40 is formed on the front side of the semiconductor substrate 22 as a power switch. According to an alternative embodiment, the front side thin film transistor 40 is not formed. Instead, a back side power switch is formed. The thin film transistor 40 may include a channel layer 142, which may be formed of or include a metal oxide. For example, the channel layer 142 may include InGaZnO (IGZO) as a semiconductor. According to some embodiments, the source region 144 and the drain region 146 are in contact with the channel layer 142 and are separated from each other by a dielectric layer 148. The gate dielectric 145 may be located below the channel layer 142 and may be formed of a high K (HK) dielectric material. The bottom gate 150 may be located below the gate dielectric 145 and in contact with the gate dielectric 145. A dielectric region / dielectric layer 152 is formed to surround the bottom gate 150.

[0037] In the example shown, the thin film transistor 40 is a bottom gate transistor. According to an alternative embodiment, the thin film transistor 40 is a top gate transistor. According to yet another alternative embodiment, the thin film transistor 40 may be a dual gate transistor including both a top gate and a bottom gate.

[0038] According to some embodiments, Figure 2 As shown, the thin film transistor 40 can be formed between the metal layers Mtop and M(top-1). For example, the thin film transistor 40 can be formed between the through hole 36T ( Figure 2 ) is located at the same level as the metal layers Mtop and M(top-1). According to alternative embodiments, depending on how many integrated circuits are powered by the gated power supply, and depending on the corresponding wiring requirements, the thin film transistor 40 can be formed in any lower layer, for example, between the metal layers M(top-1) and M(top-2), between the metal layers M(top-2) and M(top-3), ... between the metal layers M3 and M2, or between the metal layers M2 and M1.

[0039] In addition, there may be multiple thin film transistors 40 (as power switches) formed at different levels. For example, when the thin film transistor 40 is formed between the metal layers Mtop and M(top-1), other thin film transistors 40 may be formed between the metal layers M(top-1) and M(top-2), between the metal layers M(top-2) and M(top-3), and / or on other levels. Forming multiple thin film transistors 40 at different levels can save more chip area, so that multiple thin film transistors 40 do not compete for the same chip area. In addition, since more metal layers can be used to route its power supply, the upper thin film transistor 40 can support more circuits, while the lower thin film transistor 40 may support fewer circuits.

[0040] Here, an example formation process of the thin film transistor 40 is briefly discussed. In the following discussion, it is assumed that the bottom gate 150 is formed on the metal layer M(top-1). According to some embodiments, the metal layer M(top-1) is formed. According to some embodiments, Figure 8 The bottom gate 150 shown may be part of a metal layer M(top-1), such as Fig. 9 Alternatively, Figure 8 As shown, bottom gate 150 is formed on and in contact with the metal line in metal layer M(top-1).

[0041] According to some embodiments, Figure 8 As shown, a dielectric layer 152 is deposited. The dielectric layer 152 may include silicon oxide, silicon nitride, silicon oxynitride, etc. Next, a bottom gate 150 is formed in the dielectric layer 152, for example, by a damascene process. The bottom gate 150 may be formed of or include copper, aluminum, tungsten, nickel, cobalt, etc. or a combination thereof. Alternatively, the bottom gate 150 and the dielectric layer 152 are formed by depositing a metal layer, patterning the metal layer to form the bottom gate 150, depositing a dielectric layer, and performing a planarization process.

[0042] Next, a gate dielectric 145 is deposited, which may include silicon oxide or a high-k dielectric material such as hafnium oxide, lanthanum oxide, zirconium oxide, etc. A channel layer 142, which may include InGaZnO, is then deposited. In subsequent processes, a source region (S) and a drain region (D) are formed over and in contact with the channel layer 142. An oxide layer 148 is formed between the source region 144 and the drain region 146, and separates the source region 144 from the drain region 146. The formation process may be similar to the formation of the bottom gate 150 and the dielectric layer 152.

[0043] In a subsequent process, dielectric layer 148, channel layer 142, gate dielectric 145, and dielectric layer 152 are patterned in an anisotropic etching process so that portions of these layers outside thin film transistor 40 are patterned, leaving thin film transistor 40 above metal layer M (top-1). A top dielectric layer 38T ( Figure 2 ), and then forming a through hole 155 ( Fig. 9 and Fig.10 ). A metal layer Mtop connected to the through via 155 may then be formed.

[0044] Fig. 91 shows an enlarged view of a thin film transistor 40 according to some embodiments. According to some embodiments, there are multiple source regions 144 and multiple drain regions 146 formed alternately. Each source region 144 is connected to an overlying through-via 155. Each drain region 146 is also connected to an overlying through-via 155. Through the through-via 155 and the overlying metal line 156 in the metal layer Mtop (see also Fig.10 ), all drain regions 146 are interconnected. Through through-holes 155 (marked with dashed lines to indicate that they are not in the plane shown) and overlying metal lines 158 ( Fig.10 ), all source regions 144 are interconnected. Therefore, the thin film transistor 40 includes a plurality of sub-transistors connected in parallel, and thus can have a large current supporting the operation of a plurality of integrated circuit devices.

[0045] Fig.10 A top view of a thin film transistor 40 according to some embodiments is shown. The channel layer 142 can be formed as a long and wide sheet. In the top view, the source region 144 and the drain region 146 can be formed as a plurality of elongated strips. The elongated strips of the source region 144 are parallel to the elongated strips of the drain region 146 and are formed on the channel layer 142. The bottom gate 150 can also be formed as an elongated strip or multiple elongated strips located below the channel layer 142 and contacting the channel layer 142. A through hole 155 connected to the source region 144 and a through hole 155 connected to the drain region 146 are also shown.

[0046] Figures 3 to 6 FIG. 2 shows a process of forming a backside feature on the backside of the semiconductor substrate 22. Referring to FIG. Figure 3 , a carrier 48 (which may be a glass carrier) is attached to the front side of the wafer 20. Fig.15 As shown, in flow 200, the corresponding process is shown as process 210. The attachment may be performed by an adhesive such as a light-to-heat conversion (LTHC) material 50, which is configured to decompose under the heat of light such as a laser beam.

[0047] According to alternative embodiments, carrier 48 may be a support substrate, which may be a blank silicon substrate according to some embodiments. The support substrate may be formed of a homogeneous material such as silicon, and there may be no other material in the support substrate except the homogeneous material. Layer 50 according to these embodiments may be a bonding layer formed of a silicon-containing dielectric material such as SiO, SiC, SiOC, SiON, SiOCN, etc.

[0048] refer to Figure 4 , a backside grinding process is performed to remove a portion of the semiconductor substrate 22 until the through hole 26 is exposed. Fig.15As shown, in the flow 200, the corresponding process is shown as process 212. Then, the semiconductor substrate 22 is slightly recessed (e.g., by etching) so that the end of the through hole 26 protrudes from the back side of the semiconductor substrate 22. Next, a dielectric layer 52 is deposited, and then a CMP process or a mechanical grinding process is performed to re-expose the through hole 26. Therefore, the through hole 26 also penetrates the dielectric layer 52. According to some embodiments, the dielectric layer 52 is formed of silicon oxide, silicon nitride, etc.

[0049] refer to Figure 5 , forming metal pad 54 and dielectric layer 56. According to some embodiments, the formation process may include depositing dielectric layer 56 on the back side of semiconductor substrate 22, etching dielectric layer 56 to form an opening, forming through-hole 26 through the opening, and filling the opening with a conductive material. Fig.15 As shown, in flow 200 , the corresponding processes are shown as processes 214 and 216 .

[0050] refer to Figure 6 In the subsequent process, a backside interconnection structure 62 is formed. Fig.15 As shown, in the process 200, the corresponding process is shown as process 218. The backside interconnect structure 62 may include a dielectric layer 58, and an RDL (redistribution layer) 60 is formed in the dielectric layer 58. The RDL 60 may be formed of or include aluminum, copper, nickel, tungsten, titanium, etc. According to some embodiments, forming a layer of RDL 60 may include forming a dielectric layer 58, etching the corresponding dielectric layer 58 to form an opening, plating a metal seed layer extending into the opening, forming a patterned plating mask in which some portions of the metal seed are exposed, and plating to form the RDL 60. According to an alternative embodiment, the RDL 60 may be formed by a damascene process.

[0051] The thin film transistor 40' may be formed within the backside interconnect structure 62. Fig.15 As shown, in process 200, the corresponding process is shown as process 220. According to some embodiments, similar to thin film transistor 40, thin film transistor 40' is formed in a metal layer that is farther from semiconductor substrate 22 than some other metal layers. For example, there may be four backside metal layers on the back side of semiconductor substrate 22, and these metal layers are referred to as BM0, BM1, BM2, and BM3. Thin film transistor 40' can be formed between metal layers BM2 and BM3, and it can also be formed between other adjacent backside metal layers (such as Fig.11 between metal layers BM3 and BM4 as shown).

[0052] According to some embodiments, backside voltage regulator circuit 160' may be formed on the backside of semiconductor substrate 22 and connected to thin film transistor 40'. The function of backside voltage regulator circuit 160' may be substantially the same as that of voltage regulator circuit 160, and the detailed structure and function are not repeated here. Backside voltage regulator circuit 160' may be connected to integrated circuit device 24 through backside RDL, TSV and frontside RDL.

[0053] The thin film transistor 40' may be formed using substantially the same process and may have a structure similar to or the same as that of the thin film transistor 40. Figures 8 to 10 The thin film transistor 40' may include a source region 144', a gate 150' and a drain region 146', as shown in FIG. Figure 6 shown.

[0054] According to some embodiments, thin film transistor 40' is formed on the back side of semiconductor substrate 22, while thin film transistor 40 is not formed. According to an alternative embodiment, thin film transistor 40 is formed on the front side of semiconductor substrate 22, while thin film transistor 40' is not formed. According to yet another alternative embodiment, thin film transistor 40 and thin film transistor 40' are formed.

[0055] Fig.11 A partial perspective view of the backside structure of wafer 20 according to some embodiments is shown. Frontside metal layer M0 (on the front side of substrate 22), integrated circuit device 24, and metal layers BM0 to BM4 (on the back side of substrate 23) are shown. According to some embodiments, thin film transistor 40' is shown as formed between metal layers BM3 and BM4.

[0056] Reference again Figure 6 , forming an electrical connector 64. Fig.15 As shown, in process 200, the corresponding process is shown as process 222. According to some embodiments, the electrical connector 64 includes a solder area, which can be formed by plating solder balls on the metal pads of the RDL 60 and reflowing the solder balls. According to alternative embodiments, the electrical connector 64 is formed of a non-reflow (non-solder) metal material. For example, the electrical connector 64 can be formed as a copper pad or a copper pillar, and may or may not include a nickel capping layer. The reconstructed wafer 170 is thus formed.

[0057] When the carrier 48 is a glass carrier, the carrier 48 can be peeled off from the wafer 20 below. Fig.15As shown, in flow 200, the corresponding process is shown as process 224. According to alternative embodiments, when carrier 48 is a silicon support substrate and is bonded to wafer 20 by fusion bonding, support substrate 48 may be removed, or may remain on wafer 20 when singulated. Then, reconstituted wafer 170 may be singulated into a plurality of identical packages 170', each package including one device die 20', and carrier 48 may or may not be included therein.

[0058] like Figure 6 As shown, according to some embodiments, when forming thin film transistor 40, actual VDD (TVDD) voltage (also referred to as power supply TVDD or supply voltage TVDD) can be delivered from electrical connector 64A to device die 20'. According to some embodiments, TVDD voltage is 12V, but can also be other voltages. TVDD voltage is conducted to thin film transistor 40 through electrical path 72 (including RDL 60, through via 26A, metal line 34 and through via 36).

[0059] The TVDD voltage is provided to the source region 144 (see also Figure 8 ), the source region 144 is also referred to as a TVDD node. The voltage on the drain region 146 may be referred to as a virtual VDD (VVDD) voltage (also referred to as a power supply VVDD or a supply voltage VVDD). Therefore, the drain region 146 is referred to as a VVDD node, which receives power when the thin film transistor 40 is turned on, and cuts off power when the thin film transistor 40 is turned off. The power supply VVDD on the VVDD node 146 is provided to the voltage regulator 160 and the integrated circuit device (which may include a power circuit) 24A through the electrical path 74.

[0060] The TVDD voltage may also be conducted to metal line 34T', which is part of top metal line 34T. The connecting metal line portion of electrical path 72 that connects the top metal pad to metal line 34T' is not shown and may be located in a plane not shown. Metal line 34T' may also be referred to as a normally open node because metal line 34T' has power whenever electrical connector 64A has power. Through electrical path 76, voltage TVDD is provided to integrated circuit device 24B, regardless of whether integrated circuit device 24A is powered off or powered on. A voltage regulator for converting a higher voltage TVDD to a lower voltage used by integrated circuit device 24B is not shown, but a voltage regulator may also exist. The voltage may also be substantially the same as voltage regulator 160.

[0061] Figure 6 Schematically illustrated is a voltage regulator circuit 160 that may extend to the surface area of ​​semiconductor substrate 22 and to interconnect structure 32. According to some embodiments, Fig.12As shown, the (high) supply voltage Vin is directly input into the device die 20 ′. The supply voltage Vin may be provided to the power switch 40 .

[0062] Fig.14 A portion of a device die 20' according to some embodiments is schematically shown. The portion shown includes a voltage regulator circuit 160. According to some embodiments, the voltage regulator circuit 160 receives an input supply voltage Vin and generates a plurality of output supply voltages Vout, such as Vout1, Vout2, Vout3, etc. According to some embodiments, the input supply voltage Vin may be 12V, but it may also be higher or lower depending on the corresponding circuit configuration. The output supply voltage Vout may be a voltage lower than the input supply voltage Vin, and may be 5V, 3.3V, 1.2V, 0.9V, 0.75V, etc. The output supply voltage Vout is provided to the integrated circuit device 24.

[0063] According to some embodiments, the voltage regulator circuit 160 includes devices for reducing the supply voltage, which may include resistors, voltage followers, amplifiers, capacitors, inductors, diodes, etc. Therefore, the voltage regulator circuit 160 may include some parts inside the semiconductor substrate 22 and some parts in the interconnect structure 32. The details of the devices for reducing the supply voltage in the voltage regulator circuit 160 are not shown here. Although not shown, the voltage regulator circuit 160 (including the power switch 40) may also include the power switch 40' ( Figure 6 ) and may or may not include devices (eg, resistors, capacitors, inductors, etc.) and structures formed in the backside interconnect structure.

[0064] Return to reference Figure 6 The device die 20' further has a signal through-hole 26B, which is connected to the electrical connector 64B for conducting the signal to the integrated circuit device 24B.

[0065] According to some embodiments, when thin film transistor 40' is formed on the back side of semiconductor substrate 22, power supply TVDD can be passed from electrical connector 64A to thin film transistor 40' through electrical path 72'. Drain region 146' is a VVDD node, which receives power when thin film transistor 40' is turned on, and cuts off power when thin film transistor 40' is turned off. Power on VVDD node 146' is provided to integrated circuit device 24A through electrical path 78, and electrical path 78 includes RDL 60, through-via 26A, metal line 34 and through-via 36. Electrical path 78 may include upper metal lines, such as top metal line 34T in the top metal layer. Electrical path 78 also includes metal line 34 and through-via 36 connected from top metal line 34T to integrated circuit device 24A.

[0066] Fig.12 Package 120 including device die 20' is shown according to some embodiments. Device die 20' is bonded to package component 80. Package component 80 can be a silicon interposer, an organic interposer, a package substrate, a package, etc. Package component 80 can be further bonded to package component 166, which can be a printed circuit board or similar package component. According to some embodiments, heat sink 84 is attached to carrier 48 by thermal interface material 86 and attached to package component 80 by adhesive 82.

[0067] Power die 162 is also bonded to package assembly 166. According to some embodiments, power die 162 can receive a supply voltage higher than supply voltage Vin, or can receive AC (alternating current) power, and generate supply voltage Vin. Supply voltage Vin can be transmitted through conductive path 163, which passes through package assembly 166 and 80. Supply voltage Vin is directly input into die 20' and converted to a lower supply voltage within die 20', rather than being converted outside die 20' and in other package assembly bonded to package assembly 166.

[0068] Embodiments of the present disclosure have some advantageous features. By providing a high supply voltage, such as a 12V voltage, directly into the device die and converting the high supply voltage to a lower supply voltage inside the device die, the lower supply voltage is not conducted outside the device die, such as through a printed circuit board, a package substrate, an interposer, etc. Therefore, the lower supply voltage has a shorter conduction path. Since the lower supply voltage suffers from higher power losses than the higher supply voltage, the overall power loss is reduced. In addition, by forming a power switch in the interconnect structure of the device die, for example, in the back-end structure and / or the back-side interconnect structure of the device die, rather than on the surface of the semiconductor substrate, chip area is saved.

[0069] According to some embodiments of the present disclosure, a method for forming a packaging structure includes: forming an integrated circuit device on a semiconductor substrate of a wafer; forming a voltage regulator in the wafer; forming a first metal layer as part of the wafer; forming a transistor farther away from the semiconductor substrate than the first metal layer, wherein the transistor includes a first source / drain region connected to the voltage regulator, and the voltage regulator is configured to convert a first voltage received from the first source / drain region into a second voltage lower than the first voltage, and provide the second voltage to the integrated circuit device; and forming an electrical connector on the surface of the wafer, wherein the electrical connector is electrically connected to the second source / drain region of the transistor.

[0070] In one embodiment, the method further comprises: sawing the wafer to form a device die; bonding the device die to a package assembly; and bonding a power die to a package assembly, wherein the power die generates a first voltage and the first voltage is provided to a second source / drain region of the transistor. In one embodiment, the power die is configured to convert alternating current to a first voltage. In one embodiment, the package assembly comprises a printed circuit board. In one embodiment, the first voltage is 12 volts and the second voltage is selected from a group consisting of 5V, 3.3V, 1.2V, 0.9V, and 0.75V. In one embodiment, forming a transistor comprises: forming a metal oxide layer as a channel layer; forming a gate dielectric in contact with the metal oxide layer; forming a gate electrode in contact with the gate dielectric; and forming a first source / drain region and a second source / drain region in contact with the metal oxide layer.

[0071] In one embodiment, the method further comprises forming a second metal layer further away from the semiconductor substrate than the first metal layer, wherein the metal oxide layer is formed between the first metal layer and the second metal layer. In one embodiment, the transistor is formed on the front side of the wafer. In one embodiment, the electrical connector is formed on the back side of the wafer.

[0072] According to some embodiments of the present disclosure, a packaging structure includes a device die, which includes a semiconductor substrate; an integrated circuit device located on a surface of the semiconductor substrate; a voltage regulator, which includes an input terminal; and multiple outputs, wherein the voltage regulator is configured to convert a first voltage received from the input terminal into multiple second voltages lower than the first voltage, and wherein the multiple output terminals are electrically connected to the integrated circuit device; and an electrical connector located at the surface of the device die, wherein the device die is configured to pass the first voltage received from the electrical connector to the input terminal.

[0073] In one embodiment, the voltage regulator is configured to convert a first voltage of 12 volts to a plurality of second voltages selected from the group consisting of 5V, 3.3V, 1.2V, 0.9V, 0.75V, and combinations thereof. In one embodiment, the structure further comprises a plurality of metal layers located above the integrated circuit device; and a transistor located above the plurality of metal layers, wherein the transistor is configured to switch on and off conduction of the first voltage received from the electrical connector to the voltage regulator. In one embodiment, the transistor comprises a thin film transistor.

[0074] In one embodiment, the device die further comprises a through hole penetrating the semiconductor substrate, wherein the through hole electrically connects the electrical connector to the transistor. In one embodiment, the transistor is configured to provide power to the voltage regulator when the transistor is turned on, and is configured to cut off power to the voltage regulator when the transistor is turned off. In one embodiment, the structure further comprises: a packaging component, wherein the device die is located above the packaging component and electrically connected to the packaging component; and a power die located above the packaging component and connected to the packaging component, wherein the power die is configured to generate a first voltage provided to the voltage regulator.

[0075] According to some embodiments of the present disclosure, a structure includes a device die, which includes a semiconductor substrate; an integrated circuit device located at a surface of the semiconductor substrate; a voltage regulator, which includes an output terminal connected to the integrated circuit device and also includes an input terminal; a plurality of metal layers located on the semiconductor substrate; and a transistor located in the plurality of metal layers, wherein the transistor includes a first source / drain region connected to the input terminal of the voltage regulator; and a second source / drain region; and an electrical connector located at the surface of the device die, wherein the electrical connector is electrically connected to the second source / drain region; a printed circuit board located below the device die and electrically connected to the device die; and a power die configured to generate a supply voltage, wherein the structure is configured to connect the supply voltage to the second source / drain region of the transistor.

[0076] In one embodiment, the transistor comprises a thin film transistor. In one embodiment, the power die is configured to generate a supply voltage of 12V. In one embodiment, the voltage regulator is configured to generate a plurality of different output voltages.

[0077] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art will appreciate that they can easily use the present disclosure as a basis for designing or modifying other processes and structures for achieving the same purpose of the embodiments introduced herein and / or achieving the same advantages thereof. Those skilled in the art will also appreciate that such equivalent structures do not deviate from the spirit and scope of the present disclosure, and that they can make various changes, substitutions, and changes in the present disclosure without departing from the spirit and scope of the present disclosure.

Claims

1. A method for forming a packaging structure, comprising: forming integrated circuit devices on the semiconductor substrate of the wafer; forming a voltage regulator in the wafer; forming a first metal layer as a portion of the wafer; forming a transistor further away from the semiconductor substrate than the first metal layer, wherein the transistor includes a first source / drain region connected to the voltage regulator, and the voltage regulator is configured to convert a first voltage received from the first source / drain region into a second voltage lower than the first voltage, and provide the second voltage to the integrated circuit device; and An electrical connector is formed on the surface of the wafer, wherein the electrical connector is electrically connected to the second source / drain region of the transistor.

2. The method according to claim 1, further comprising: sawing the wafer to form device dies; bonding the device die to a package assembly; as well as A power die is bonded to the package assembly, wherein the power die generates the first voltage and the first voltage is provided to the second source / drain region of the transistor.

3. The method according to claim 2, wherein: The power die is configured to convert alternating current into the first voltage.

4. The method according to claim 1, wherein: Forming the transistor includes: forming a metal oxide layer as a channel layer; forming a gate dielectric in contact with the metal oxide layer; forming a gate electrode in contact with the gate dielectric; and The first source / drain region and the second source / drain region are formed in contact with the metal oxide layer.

5. The method according to claim 4, further comprising forming a second metal layer further away from the semiconductor substrate than the first metal layer, wherein The metal oxide layer is formed between the first metal layer and the second metal layer.

6. A packaging structure, comprising: A device die, the device die comprising: Semiconductor substrate; an integrated circuit device located on the surface of the semiconductor substrate; A voltage regulator, the voltage regulator comprising: Input terminal; and a plurality of output terminals, wherein the voltage regulator is configured to convert a first voltage received from the input terminal into a plurality of second voltages lower than the first voltage, and wherein the plurality of output terminals are electrically connected to the integrated circuit device; and An electrical connector is located at a surface of the device die, wherein the device die is configured to pass the first voltage received from the electrical connector to the input terminal.

7. The structure according to claim 6, further comprising: a plurality of metal layers located above the integrated circuit device; as well as A transistor is located above the plurality of metal layers, wherein the transistor is configured to switch on and off conduction of the first voltage received from the electrical connector to the voltage regulator.

8. The packaging structure according to claim 6, wherein: The device die also includes: A through-hole is located in the semiconductor substrate, wherein the through-hole electrically connects the electrical connector to the transistor.

9. The package structure according to claim 6, further comprising: a package assembly, wherein the device die is located above and electrically connected to the package assembly; and A power die is located above the package assembly and connected to the package component, wherein the power die is configured to generate the first voltage provided to the voltage regulator.

10. A packaging structure, comprising: A device die, the device die comprising: Semiconductor substrate; An integrated circuit device is located at the surface of the semiconductor substrate; a voltage regulator including an output terminal connected to the integrated circuit device and also including an input terminal; A plurality of metal layers located on the semiconductor substrate; and A transistor is located in the plurality of metal layers, wherein the transistor comprises: a first source / drain region connected to the input terminal of the voltage regulator; and a second source / drain region; and an electrical connector located at a surface of the device die, wherein the electrical connector is electrically connected to the second source / drain region; a printed circuit board located below the device die and electrically connected to the device die; and The power die is configured to generate a supply voltage, wherein the package structure is configured to connect the supply voltage to the second source / drain region of the transistor.

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