Manufacturing method of semiconductor device with TSV horn mouth shape adjusting function

Abstract

The invention provides a method for manufacturing a semiconductor device with a TSV horn mouth shape adjusting function. The method comprises the following steps: S1, depositing a hard mask layer on a dielectric film layer on the top of a wafer; s2, applying photoresist on the hard mask layer and the dielectric film layer, and forming an etching pattern through photoetching; s3, etching the dielectric film layer through a silicon etching process to form a top horn mouth shape; s4, plating copper on the dielectric film layer with the top horn mouth through a copper electroplating process, and then removing copper on the surface; and S5, carrying out an annealing process so as to enable the copper grains in the TSV to be fully heated and expanded. By using the method, the electrical performance degradation of the semiconductor device caused by the TSV horn mouth can be avoided, and the horn mouth can be easily removed even under the condition that the horn mouth is generated by using a conventional etching process and hardware.

Description

Technical Field

[0001] The invention belongs to the field of semiconductor device manufacturing, and in particular relates to a semiconductor device manufacturing method with a TSV bell mouth morphology adjustment function. Background Art

[0002] The trumpet-shaped morphology at the top of TSV is one of the common morphological defects. When a trumpet-shaped morphology appears on the top, the overall morphology of TSV will change, the distance between TSVs will be shortened, and the electrical performance will be different from the original design. The trumpet-shaped morphology caused by the top dielectric film layer and the silicon loss will affect the performance of the chip. When the distance between TSV and the design is close enough and the trumpet-shaped morphology is expanded to a certain extent, the two hole interfaces contact each other and TSV short circuit occurs. Even when the subsequent linear insulating oxide layer is etched away during the etching process, a considerable part of the side wall is not protected by the insulating layer, especially the silicon part. The copper in the TSV diffuses in the silicon, and the electrical performance is affected, resulting in TSV short circuit. Summary of the invention

[0003] To this end, the present invention provides a method for manufacturing a semiconductor device with a TSV bell-mouth morphology adjustment function, the method comprising: step S1, depositing a hard mask layer on a dielectric film layer located on the top of a wafer; step S2, applying a photoresist on the hard mask layer and the dielectric film layer, and forming an etching pattern by photolithography; step S3, etching the dielectric film layer by a silicon etching process to form a top bell-mouth morphology; step S4, copper plating on the dielectric film layer with the top bell-mouth by a copper electroplating process, and then removing the copper on the surface; step S5, performing an annealing process to allow the copper grains inside the TSV to fully expand due to heat.

[0004] In addition, preferably, the semiconductor device manufacturing method of the present invention further comprises: in the step S6, copper chemical mechanical polishing is performed until the original dielectric film layer on the top is exposed.

[0005] In addition, preferably, the semiconductor device manufacturing method of the present invention further includes: using liquid tetraethoxysilane mixed with gaseous oxygen as a precursor, using plasma enhanced chemical vapor deposition of SiO2, and exposing it to air at a temperature of 100-150°C.

[0006] In addition, preferably, in the semiconductor device manufacturing method of the present invention, the deposition temperature is set to be less than or equal to the LT-SiO2 deposition temperature, and one of TiN, Screen OX, SIOC, OMCTS, and NBLoK is further deposited on the LT-SiO2 as the hard mask layer.

[0007] Furthermore, preferably, in the method for manufacturing a semiconductor device of the present invention, the deposition thickness of LT-SiO2 is greater than 50 nm.

[0008] Furthermore, preferably, in the method for manufacturing a semiconductor device of the present invention, a subsequent film layer is deposited after the LT-SiO is thinned by a CMP process.

[0009] In addition, preferably, in the semiconductor device manufacturing method of the present invention, the TSV Cu annealing temperature is not higher than the temperature of the PECVD film deposition.

[0010] Furthermore, preferably, in the method for manufacturing a semiconductor device of the present invention, the film layer deposition temperature ≥TSV Cu annealing temperature >LT-SiO2 deposition temperature.

[0011] By utilizing the present invention, the degradation of the electrical performance of the semiconductor device caused by the TSV bell mouth can be avoided, and even when the bell mouth is generated by using conventional etching processes and hardware, the bell mouth can be easily removed. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 is a schematic diagram showing a process of forming a flare on top of a TSV Last when wafers are stacked.

[0013] Figure 2 is a schematic diagram showing the top flare of a 2.5D interposer.

[0014] Figure 3 is a schematic diagram showing the top flare of a 2.5D interposer.

[0015] Figure 4 Schematic diagram showing that the TSV top flare causes TSV short circuit.

[0016] Figure 5 FIG. 4 is a schematic diagram showing that the flare at the top of a TSV causes the consumption of Liner Oxide. FIG.

[0017] Figure 6 Schematic diagram showing that a top deposited barrier layer ensures the integrity of the oxide insulating layer.

[0018] Figure 7 The diagram is a schematic diagram showing the sizes of a top deposition barrier layer and an oxidation insulation layer in a semiconductor device manufactured by a semiconductor device manufacturing method according to an embodiment of the present invention.

[0019] Figure 8 Schematic diagram showing the top hard mask layer thickening process flow

[0020] Fig. 9 1 is a schematic diagram showing the flow of a method for manufacturing a semiconductor device according to an embodiment of the present invention.

[0021] Fig.10 is a schematic diagram showing the TDS spectra of low-temperature SiO2 and hot SiO2 based on mass 18 (H2O) monitoring.

[0022] Fig.11 It shows the C-SAM and TEM images of LT-SiO2 when the temperature is increased.

[0023] Fig.12 is a schematic diagram showing the mechanism of bubble precipitation formation.

[0024] Fig.13 Schematic diagram showing the position of a bell mouth in a method for manufacturing a semiconductor device according to an embodiment of the present invention. DETAILED DESCRIPTION

[0025] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Other embodiments or variations obtained based on the embodiments in the present application by ordinary technicians in this field without creative work are all within the scope of protection of this application.

[0026] See also Figure 1 , Figure 1 FIG. 1 is a schematic diagram of a process of forming a horn on the top of TSV Last of stacked wafers in the prior art.

[0027] At present, advanced packaging is mainly divided into two forms: 2.5D and 3D. On the Fab side, 2.5D is mainly for the production of silicon adapters, and 3D is mainly for wafer-to-wafer fusion / hybrid bonding. Both involve the production of through-silicon vias (TSV). The etching difficulty of through-silicon vias increases, mainly because of their high depth and width. At the same time, the etched film layer involves factors such as the switching of dielectric layers (silicon oxide, silicon nitride, tan silicon nitride, etc.) and different types of silicon. Therefore, after the through-silicon via etching is completed, obtaining TSV holes with high verticality and smooth sidewalls puts forward high requirements on the etching process and the integration of processes before and after. In summary, TSV is a key process in both 2.5D and 3D advanced packaging processes.

[0028] Among them, the bell-shaped morphology on the top of the TSV is one of the common morphological defects, and the reasons for its formation are as follows:

[0029] 1. TSV Last process of 3D stacked wafers: Since the upper dielectric layer, silicon, and bottom dielectric layer structure need to be etched off in sequence, the top layer cannot be effectively blocked by photoresist alone as a mask layer, so an additional hard mask layer needs to be deposited for blocking. The top hard mask layer plus the dielectric layer itself are etched through photoresist as a barrier layer. The subsequent silicon and the bottom dielectric layer structure rely on the subsequently deposited hard mask layer as a barrier layer. During the silicon etching process, the surface has an uneven morphology, in which the edge protrusions are more likely to attract charges and will be etched preferentially. At the same time, the top hard mask structure, the upper dielectric layer, and the bottom dielectric layer have similar compositions and similar etching rates, resulting in a trumpet-shaped etching morphology. The overall schematic diagram is as follows Figure 1 shown.

[0030] 2. 2.5D silicon adapter Si interposer TSV blind hole process: In the 2.5D Si interposer TSV blind hole etching process, due to the large depth-width ratio of the entire Si, the depth is usually above 100um. Even if there is a large selectivity ratio between etching silicon and dielectric layers, the amount of etched silicon is large, and the loss of the top hard mask layer is also large. In addition, the above-mentioned hole surface is directly subjected to the Litho process, and the Si Etch Chamber is used to directly complete the etching of the dielectric layer and silicon in one step. Due to the parameters such as the gas and ratio for Si etching, the etching of the dielectric layer will be more difficult, so the top dielectric layer will not be etched, that is, a trumpet-shaped morphology will appear. The schematic diagram is as follows Figure 3 shown.

[0031] The following problems may occur when a bell mouth appears on the top:

[0032] ① The overall morphology of TSV will change. At the same time, the distance between TSVs will be shortened, and the electrical performance will be different from the original design.

[0033] ②The trumpet-shaped morphology caused by the loss of the top dielectric film layer and silicon will affect the performance of the chip.

[0034] ③ When the TSV distance is close enough and the bell mouth is expanded to a certain extent, the two hole interfaces contact each other, and eventually the following will appear: Figure 4 The TSV short circuit phenomenon is shown.

[0035] ④ Due to the inclined morphology of the bell mouth, the subsequent linear insulating oxide layer is etched away during the etching process, and eventually a considerable part of the side wall is not protected by the insulating layer, especially the silicon part. The copper in the TSV diffuses in the silicon, and the electrical performance is affected. In severe cases, it will lead to the following Figure 5 The TSV shown is shorted.

[0036] There are several commonly used solutions:

[0037] 1. By adjusting the structure of the surface dielectric layer hard mask: by inserting Sin into SiO2, the top bell-mouth morphology can be adjusted. Because the etching rate of Sin is lower than that of SiO2 in the usual etching process, the bell-mouth morphology of the etching can be reduced to a certain extent, but the bell-mouth still exists. If most of the top dielectric layer is replaced with Sin, the bell-mouth will be significantly reduced, but in the process of etching Sin, more by-products are generated, which are accumulated in the holes and cavities and are difficult to remove.

[0038] 2. Utilizing the low step coverage of plasma enhanced chemical vapor deposition (PECVD), the film layer can only be deposited within a certain depth on the surface of the deep silicon via. The film layer deposited on the slope is used as a barrier layer for etching the bottom insulating oxide layer, and finally the oxide layer on the side wall of the deep silicon via is completely retained to prevent the copper inside the deep silicon via from migrating to the substrate. The material of the barrier layer is determined according to the dielectric layer that needs to be etched at the bottom. The schematic diagram is as follows Figure 6 As shown in the figure, this method can solve the problem of the integrity of the insulating oxide layer at the slope and prevent copper from diffusing to the substrate. However, it cannot solve the problem of the top bell-mouth morphology. At the same time, because the step coverage of the PECVD film deposition is difficult to control and has a great relationship with the morphology of the hole, it is necessary to ensure that a sufficient barrier layer can be deposited at the slope, and at the same time, it is also necessary to ensure that it is not deposited deeper in the hole, so as not to affect the etching of the insulating oxide layer and the dielectric layer at the bottom of the hole too much. Therefore, the process difficulty of this method is relatively high.

[0039] 3. By thickening the hard mask layer on the top, the slope does not extend to the silicon position, ensuring the integrity of the insulating oxide layer at the silicon position. The defect of this method is that the thickness of the hard mask layer on the top increases, and the thickness of the PR also increases accordingly, and the etching difficulty of the top hard mask layer plus the dielectric layer increases. If the top bell-mouth part is to be completely removed in the future, a long CMP process is required. There are two materials, copper and dielectric layer, on the surface at the same time, because these two materials require different Slurry and Pad. Therefore, if this solution is used, if it is necessary to completely remove the dielectric layer at the top slope plus the copper inside the TSV, it is necessary to continuously switch the dielectric layer CMP and Cu CMP machines to finally achieve the ideal effect. The schematic diagram is shown in Figure 7 shown.

[0040] In summary, the defects of this solution are: (1) the top hard mask becomes thicker, the photoresist becomes thicker, and the etching difficulty also increases accordingly; (2) due to the increase in depth, the difficulty of TSV ECP increases, and at the same time, the surface copper thickness increases, and the Cu CMP time also increases; (3) the subsequent bell mouth removal requires continuous switching of Cu CMP and dielectric layer CMP machines, which is complicated, time-consuming and costly.

[0041] The process of the present invention is as follows Figure 8 As shown, the details are as follows:

[0042] 1. Deposit a thickened hard mask layer on the original top dielectric film layer of the wafer;

[0043] 2. Perform conventional photolithography, where the photoresist acts as a top hard mask layer plus a barrier layer for the original dielectric film layer;

[0044] 3. Perform dielectric layer and silicon etching processes, as mentioned above, at this time, a top bell-mouth morphology is formed;

[0045] 4. Carry out conventional copper electroplating process;

[0046] 5. Remove the copper on the surface;

[0047] 6. Perform annealing process to make the copper grains inside TSV expand fully due to heat. At this time, bubbles will appear inside the low-temperature deposited film layer, and the adhesion with the bottom film layer will decrease;

[0048] 7. Perform copper chemical mechanical polishing to remove the protruding copper on the surface. At this time, due to the decrease in the adhesion of the low-temperature film layer, it will fall off during the polishing process. Therefore, copper chemical mechanical polishing is used to remove the copper inside the top hard mask layer TSV and stop at the original dielectric layer on the top;

[0049] In addition, the following explanations are required.

[0050] 1. Description of the low-temperature deposited film layer: The present invention uses a mixture of liquid tetraethoxysilane (TEOS) and gaseous oxygen (O2) as a precursor, and uses plasma enhanced chemical vapor deposition of SiO2. The low temperature is 100-150°C. Then expose it to the air. Compared with SiO2 grown by thermal oxidation, SiO2 grown by low-temperature PECVD (LowTemperature SiO2: LT-SiO2) contains some hydrogen elements, as shown in Table 1. According to the TDS (Thermal Desorption Spectroscopy) analysis of SiO2 deposited by low-temperature PECVD using the above method (TEOS+O2 as a precursor), 70% of the weight loss is water, as shown in Table 1. Fig. 9 As shown, there are three peaks, Ⅰ, Ⅱ and Ⅲ respectively.

[0051] The reason for peak Ⅰ is that there are many micropores on the surface of the deposited film layer, which absorbs water from the air. This part of water is desorbed, thus forming peak Ⅰ.

[0052] The reason for Ⅱ is that the H in TEOS exists mostly in the form of -OH inside the film, and some absorbed water is attached to the -OH group in the film through hydrogen bonds. At the same time, Si-OH will undergo the following reaction at 250℃-350℃ to generate water. The above two parts of water are desorbed, thus forming peak Ⅱ.

[0053] The reason for peak III is that at temperatures above 400°C, the TEOS remaining in the film undergoes the following reaction to generate water, and this part of the water is desorbed to form peak III.

[0054] We use bonding to observe the precipitated bubbles, such as Fig.10 As shown in the figure, it can be seen that a large number of bubbles are precipitated. Fig.11 shown.

[0055] The low-temperature deposited film layer in the present invention is mainly used for depositing a hard mask. The temperature of the subsequent deposited film layer also needs to adopt this low-temperature deposition mode. If the temperature of the subsequent deposited film layer is higher than the temperature of the low-temperature deposition, the LT-SiO2 film layer will release gas, resulting in decreased adhesion of the film layer, bubbles, and inconsistent film deposition thickness, and problems with subsequent Litho and other processes. We can deposit any film layer we deem suitable on top of LT-SiO2, such as TiN, Screen OX, SIOC, OMCTS, NBLoK and other hard mask layers of different materials (as long as the temperature does not exceed the initial LT-SiO2 deposition temperature). Bubbles can be generated by heating the LT-SiO2 and then removed.

[0056] The deposition thickness of LT-SiO2 needs to be greater than 50nm. If we need a thinner thickness of LT-SiO2, we can thin it through CMP and then deposit subsequent film layers.

[0057] 2. We use the TSV Cu annealing heat treatment to achieve the expansion and growth of copper grains inside the TSV while achieving the purpose of LT-SiO2 bubble generation, without the need to add an additional annealing process. In conventional processes, the TSV Cu annealing temperature cannot be higher than the temperature of the PECVD deposited film layer. If it is higher, bubbles will be generated, affecting the quality of the film layer. Therefore, this solution is also the same: conventional film deposition temperature ≥ TSV Cu annealing temperature > LT-SiO2 deposition temperature. This ensures that LT-SiO2 generates bubbles while the film layer deposited at conventional temperature does not generate bubbles.

[0058] 3. Because the film layer of the hard mask will fall off due to the adhesion of LT-SiO2, we only need to remove the Cu inside the TSV in the later stage, so we can use Cu CMP. The time of our overall process will be greatly reduced, the complexity will be significantly reduced, and the cost will be significantly reduced.

[0059] 4. This solution can completely remove the unnecessary hard mask layer without adding additional film structure. It only needs to ensure that the bell mouth morphology ends inside the hard mask layer and above the lower interface of the LT-SiO2 film layer. Fig.12 shown.

[0060] 5. Since the aspect ratio of TSV is very deep, especially in the process of silicon etching, the doctor etching process is used, and the polymer is thicker. During the etching process, the etching ions are easier to drill into, forming pits one by one. The Cu ECP in it is difficult to remove later, and Cu residual defects often appear on the surface. It is difficult to remove it completely. After adopting this solution, since the surface copper will be peeled off with the film layer later, the surface copper will be completely removed, and there will be no problem of surface copper residue; this solution can also be extended to the conventional Damascus process to achieve the purpose of completely removing the hard mask layer and completely removing the surface copper.

[0061] 6. The LT-SiO2 of this solution can also be replaced with other film layers, such as hydrogenated, fluorinated, and halogenated amorphous carbon films. This type of film layer will also release gas during the subsequent heating process, thereby reducing the adhesion of the film layer and eventually causing the film layer to peel off, achieving the same effect as LT-SiO2.

[0062] In summary, this solution increases the thickness of the hard mask, switches part of the film layer to LT-SiO2, and sequentially performs conventional Litho Etch and other processes to control the bell mouth above the lower interface of LT-SiO2, and then performs conventional TSV ECP, Cu CMP and other processes, and uses the heat of the TSV Cu Anneal process to generate bubbles in LT-SiO2, thereby reducing the adhesion of its film layer. After the subsequent CMP applies stress, the film layer falls off, and only Cu CMP is required to remove the unnecessary Cu in the TSV. Thereby, the bell mouth defect morphology at the top of the TSV is completely eliminated. The present invention is highly practical and can be quickly applied to mass production factories.

[0063] The advantages and benefits of the present invention are as follows:

[0064] 1. Do not overly rely on process and hardware optimization. Even the bell mouth produced by conventional etching process and hardware can be easily removed by this solution.

[0065] 2. The processes used are all common Fab processes. It is only necessary to adjust the temperature of one PECVD step to convert it to LT-SiO2 without adding any additional process steps.

[0066] 3. The last step is to remove the bell mouth with CMP. As the adhesion of the film layer decreases, the hard mask layer will automatically fall off. We use Cu CMP to remove the Cu in the TSV, and a conventional Cu CMP machine can be used, which is exactly the same as the original TSV Cu2ndCMP process. After the Cu in the bell mouth of the TSV is removed, it is enough to stop at the original dielectric layer position on the top of the surface. There is no need to continuously switch between Cu CMP and dielectric layer CMP to remove excess Cu and dielectric layer due to the thickened hard mask layer in the existing process. In the present invention, only the Cu in the TSV needs to be removed. Since the proportion of TSV in the entire wafer is very low, this step requires less process time and low cost.

[0067] The surface film layer is peeled off due to decreased adhesion, so there will be no problem of surface copper residue caused by incomplete CMP removal of surface copper. This solution can also be applied to conventional copper Damascus process to achieve the purpose of completely removing the hard mask layer and completely removing the surface copper.

[0068] Table 1: Comparative analysis of the composition of LT-SiO2 and thermally oxidized SiO2

[0069]

[0070] 1. The film layer at the location where the bell mouth exists is a low-temperature deposited film layer;

[0071] 2. The lowest point of the bell mouth must be above the lower interface of the low-temperature deposited film layer.

[0072] Only when the film needs to be peeled off before Cu CMP, can a process with a temperature higher than the low-temperature film deposition and sufficient bubbles to significantly reduce the film adhesion ability appear.

[0073] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or device including the elements.

[0074] Each embodiment in this specification is described in a related manner, and the same or similar parts between the embodiments can be referenced to each other, and each embodiment focuses on the differences from other embodiments.

[0075] The above is only a specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily thought of by a person skilled in the art within the technical scope disclosed by the present invention should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.

[0076] The above embodiments of the present invention are merely examples for clearly illustrating the present invention, and are not intended to limit the embodiments of the present invention. For those skilled in the art, other different forms of changes or modifications can be made based on the above description. It is not necessary and impossible to list all the embodiments here. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in the protection scope of the claims of the present invention.

Claims

1. A method for manufacturing a semiconductor device having a TSV bell mouth morphology adjustment function, characterized in that: include: Step S1, depositing a hard mask layer on the dielectric film layer located on the top of the wafer; Step S2, applying photoresist on the hard mask layer and the dielectric film layer, and forming an etching pattern by photolithography; Step S3, etching the dielectric film layer by a silicon etching process to form a top bell-mouth morphology; Step S4, copper is plated on the dielectric film layer having the top bell mouth by a copper electroplating process, and then the copper on the surface is removed; Step S5 , performing an annealing process to allow the copper grains inside the TSV to fully expand due to heat.

2. The method for manufacturing a semiconductor device according to claim 1, wherein: Also includes: In step S6 , copper chemical mechanical polishing is performed until the original dielectric film layer on the top is exposed.

3. The method for manufacturing a semiconductor device according to claim 1, wherein: Also includes: Liquid tetraethoxysilane mixed with gaseous oxygen is used as a precursor, and SiO2 is deposited by plasma enhanced chemical vapor deposition at a temperature of 100-150°C and exposed to air.

4. The method for manufacturing a semiconductor device according to claim 3, wherein: The deposition temperature is set to be less than or equal to the LT-SiO2 deposition temperature, and one of TiN, ScreenOX, SIOC, OMCTS, and NBLoK is further deposited on the LT-SiO2 as the hard mask layer.

5. The method for manufacturing a semiconductor device according to claim 4, wherein: The deposition thickness of LT-SiO2 is greater than 50nm.

6. The method for manufacturing a semiconductor device according to claim 4, wherein: include: After thinning the LT-SiO by CMP, subsequent film layers are deposited.

7. The method for manufacturing a semiconductor device according to claim 4, wherein: The TSV Cu annealing temperature is not higher than the temperature of the PECVD deposited film.

8. The method for manufacturing a semiconductor device according to claim 4, wherein: Film deposition temperature ≥TSV Cu annealing temperature>LT-SiO2 deposition temperature.

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