Semiconductor device manufacturing method with TSV bell mouth morphology adjustment function

Abstract

The present invention provides a method for manufacturing a semiconductor device with a TSV (Transistor Subsurface Vent) morphology adjustment function, comprising: step S1, depositing a hard mask layer on a dielectric film layer located on top of a wafer; step S2, applying photoresist on the hard mask layer and the dielectric film layer, and forming an etching pattern by photolithography; step S3, etching the dielectric film layer using a silicon etching process to form a top flare morphology; step S4, copper plating the dielectric film layer having the top flare using a copper electroplating process, and then removing the copper from the surface; and step S5, performing an annealing process to allow the copper grains inside the TSV to fully expand due to heat. The present invention can avoid degradation of the electrical performance of semiconductor devices caused by TSV flares, and can easily remove the flares even when they are produced using conventional etching processes and hardware.

Description

Technical Field

[0001] The present invention belongs to the field of semiconductor device manufacturing, and in particular relates to a method for manufacturing a semiconductor device with a TSV bell mouth morphology adjustment function. Background Art

[0002] The trumpet-shaped morphology at the top of the TSV is a common morphological defect. When a trumpet-shaped morphology appears on the top, the overall morphology of the TSV will change, the distance between TSVs will be shortened, and the electrical performance will be different from the original design. The trumpet-shaped morphology caused by the loss of the top dielectric film layer and silicon will affect the performance of the chip. When the TSV is close enough to the design distance and the trumpet-shaped morphology expands to a certain extent, the two hole interfaces will contact each other and TSV short circuit will occur. Even when the subsequent linear insulating oxide layer is etched away during the etching process, a considerable part of the sidewall is not protected by the insulating layer. In particular, the copper in the TSV diffuses in the silicon, affecting the electrical performance and causing TSV short circuit. Summary of the Invention

[0003] To this end, the present invention provides a method for manufacturing a semiconductor device with a TSV bell-mouth morphology adjustment function, the method comprising: step S1, depositing a first hard mask layer on a dielectric film layer located on top of a wafer, wherein the first hard mask layer is LT-SiO2 formed by using a mixture of liquid tetraethoxysilane and gaseous oxygen as a precursor, through plasma-enhanced chemical vapor deposition, and exposing to air at a temperature of 100-150°C; step S2, applying photoresist on the first hard mask layer and the dielectric film layer, and forming an etching pattern by photolithography; step S3, etching the dielectric film layer by a silicon etching process, forming a top bell-mouth morphology above the lower interface of the LT-SiO2; step S4, plating copper on the dielectric film layer having the top bell-mouth by a copper electroplating process, and then removing the copper on the surface; step S5, performing an annealing process to allow the copper grains inside the TSV to fully expand due to heat.

[0004] Furthermore, preferably, the semiconductor device manufacturing method of the present invention further comprises: step S6, performing copper chemical mechanical polishing after the annealing process is completed, until the copper inside the top TSV is removed and the dielectric film layer is exposed.

[0005] In addition, preferably, the semiconductor device manufacturing method of the present invention further includes: using a mixture of liquid tetraethoxysilane and gaseous oxygen as a precursor, using plasma enhanced chemical vapor deposition of SiO2, and exposing it to air at a temperature of 100-150°C.

[0006] In addition, preferably, in the semiconductor device manufacturing method of the present invention, after step S1, it also includes: setting the deposition temperature to be less than or equal to the LT-SiO2 deposition temperature, and further depositing one of titanium nitride (TiN), screen oxide (Screen OX), (silicon oxycarbide) SIOC, octamethylcyclotetrasiloxane (OMCTS), and NBLoK (product name of a registered trademark of Applied Materials, Inc.) on top of the LT-SiO2 as the hard mask layer.

[0007] Furthermore, preferably, in the semiconductor device manufacturing method of the present invention, the deposition thickness of LT-SiO2 is greater than 50 nm.

[0008] By utilizing the present invention, degradation of the electrical performance of semiconductor devices caused by the TSV bell mouth can be avoided, and even when the bell mouth is generated by conventional etching processes and hardware, the bell mouth can be easily removed. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 FIG. 1 is a schematic diagram illustrating a process of forming a flare on top of a TSV last when wafers are stacked.

[0010] Figure 2 is a schematic diagram showing the top flare of a 2.5D interposer.

[0011] Figure 3 is a schematic diagram showing the top flare of a 2.5D interposer.

[0012] Figure 4 FIG. 1 is a schematic diagram showing that a TSV top flare causes a TSV short circuit.

[0013] Figure 5 FIG. 4 is a schematic diagram showing that the flare at the top of a TSV causes the consumption of liner oxide. FIG.

[0014] Figure 6 Schematic diagram showing that a top deposited barrier layer ensures the integrity of the oxide insulating layer.

[0015] Figure 7 FIG. 1 is a schematic diagram illustrating the sizes of a top deposition barrier layer and an oxidized insulating layer in a semiconductor device manufactured using a semiconductor device manufacturing method according to an embodiment of the present invention.

[0016] Figure 8 Schematic diagram showing the top hard mask layer thickening process flow

[0017] Figure 9 1 is a schematic diagram illustrating a flow of a method for manufacturing a semiconductor device according to an embodiment of the present invention.

[0018] Figure 10is a schematic diagram showing TDS spectra of low-temperature SiO2 and hot SiO2 based on mass 18 (H2O) monitoring.

[0019] Figure 11 It shows the C-SAM and TEM images of LT-SiO2 when the temperature is increased.

[0020] Figure 12 is a schematic diagram showing the mechanism of bubble precipitation formation.

[0021] Figure 13 Schematic diagram showing the position of a bell mouth in a semiconductor device manufacturing method according to an embodiment of the present invention. DETAILED DESCRIPTION

[0022] The following will be combined with the accompanying drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of the embodiments. Other embodiments or modifications derived from the embodiments of this application by ordinary technicians in this field without making any creative work are all within the scope of protection of this application.

[0023] See also Figure 1 , Figure 1 FIG. 1 is a schematic diagram of a process of forming a horn on top of a TSV Last of stacked wafers in the prior art.

[0024] At present, advanced packaging is mainly divided into two forms: 2.5D and 3D. On the Fab side, 2.5D is mainly the production of silicon adapter plates, and 3D is mainly wafer-to-wafer fusion / hybrid bonding. Both involve the production of through-silicon vias (TSV). The etching difficulty of through-silicon vias is increased, mainly due to their high depth and width. At the same time, the etched film layer involves factors such as switching between dielectric layers (silicon oxide, silicon nitride, silicon carbonitride, etc.) and different types of silicon. Therefore, after the through-silicon via etching is completed, obtaining TSV holes with high verticality and smooth sidewalls places high demands on the etching process and the integration of previous and subsequent processes. In summary, TSV is a key process in both 2.5D and 3D advanced packaging processes.

[0025] Among them, the trumpet-shaped morphology on the top of the TSV is one of the common morphological defects. The causes of its formation are as follows:

[0026] 1. TSV Last process of 3D stacked wafers: Since the upper dielectric layer, silicon, and bottom dielectric layer structure need to be etched off in sequence, the top layer cannot be effectively blocked by relying solely on photoresist as a mask layer, so an additional hard mask layer needs to be deposited for blocking. The top hard mask layer plus its own dielectric layer are etched through photoresist as a blocking layer. The subsequent silicon and the bottom dielectric layer structure rely on the subsequently deposited hard mask layer as a blocking layer. During the silicon etching process, the surface has an uneven morphology, in which the edge protrusions are more likely to attract charges and will be etched away first. At the same time, the top hard mask structure, the upper dielectric layer, and the bottom dielectric layer have similar compositions and similar etching rates, resulting in a trumpet-shaped etching morphology. The overall schematic diagram is as follows Figure 1 shown.

[0027] 2. 2.5D silicon adapter Si interposer TSV blind hole process: In the 2.5D Si interposer TSV blind hole etching process, due to the large depth-width ratio of the entire Si, the depth is usually above 100um. Even if there is a large selectivity ratio between etching silicon and dielectric layers, the loss of the top hard mask layer is also large due to the large amount of etched silicon. In addition, the above-mentioned hole surface is directly subjected to the Litho process, and the Si Etch Chamber is used to directly complete the etching of the dielectric layer and silicon in one step. Since the parameters such as the gas and ratio for Si etching will make the etching of the dielectric layer more difficult, the top dielectric layer will not be able to be etched, that is, a trumpet-shaped morphology will appear. The schematic diagram is as follows Figure 3 shown.

[0028] The following problems will occur when a bell mouth appears on the top:

[0029] ① The overall TSV morphology will change. At the same time, the distance between TSVs will be shortened, and the electrical performance will be different from the original design.

[0030] ② The trumpet-shaped morphology caused by the loss of the top dielectric film layer and silicon will affect the performance of the chip.

[0031] ③ When the TSV distance is close enough and the bell mouth is expanded to a certain extent, the two hole interfaces contact each other, and eventually the following will appear: Figure 4 The TSV short circuit phenomenon is shown.

[0032] ④ Due to the inclined morphology of the trumpet mouth, the subsequent linear insulating oxide layer is etched away during the etching process, and eventually a considerable part of the sidewall is not protected by the insulating layer, especially the silicon part. The copper in the TSV diffuses in the silicon, affecting the electrical performance. In severe cases, it will lead to Figure 5 The TSV shown is shorted.

[0033] There are several commonly used solutions:

[0034] 1. By adjusting the structure of the surface dielectric hard mask: By inserting SiO2 into the SiO2, the top bell-mouth morphology can be adjusted. Because the etching rate of SiO2 is lower than that of SiO2 during the normal etching process, the bell-mouth morphology can be reduced to a certain extent, but the bell-mouth morphology still exists. If most of the top dielectric layer is replaced with SiO2, the bell-mouth will be significantly reduced. However, during the SiO2 etching process, a large number of byproducts are generated, which accumulate in the holes and cavities and are difficult to remove.

[0035] 2. Taking advantage of the low step coverage of plasma enhanced chemical vapor deposition (PECVD), the film layer can only be deposited within a certain depth on the surface of the deep silicon via. The film layer deposited on the slope is used as a barrier layer for etching the bottom insulating oxide layer, and ultimately the oxide layer on the sidewall of the deep silicon via is completely retained to prevent the copper inside the deep silicon via from migrating to the substrate. The material of the barrier layer is determined according to the dielectric layer that needs to be etched at the bottom. The schematic diagram is as follows Figure 6 As shown in the figure, this method can address the integrity of the insulating oxide layer at the slope, preventing copper from diffusing into the substrate. However, it cannot solve the problem of the top bell-shaped morphology. Furthermore, because the step coverage of PECVD film deposition is difficult to control and is closely related to the morphology of the hole, it is necessary to ensure that sufficient barrier layer is deposited at the slope, while also ensuring that it is not deposited deeper into the hole to avoid excessively affecting the etching of the insulating oxide layer and dielectric layer at the bottom of the hole. Therefore, this method is relatively difficult to process.

[0036] 3. By thickening the hard mask layer on the top, the slope does not extend to the silicon position, ensuring the integrity of the insulating oxide layer at the silicon position. The drawback of this method is that the thickness of the hard mask layer on the top increases, and the thickness of the PR also increases accordingly, and the etching difficulty of the top hard mask layer plus the dielectric layer increases. If the top bell mouth part is to be completely removed later, a long CMP process is required. There are two materials, copper and dielectric layer, on the surface at the same time, because these two materials require different Slurry and Pad. Therefore, if this solution is used, if the dielectric layer at the top slope plus the copper inside the TSV needs to be completely removed, it is necessary to continuously switch the dielectric layer CMP and Cu CMP machines to finally achieve the ideal effect. The schematic diagram is shown as follows. Figure 7 shown.

[0037] In summary, the defects of this solution are: (1) the top hard mask becomes thicker, the photoresist becomes thicker, and the etching difficulty also increases accordingly; (2) due to the increase in depth, the difficulty of TSV ECP increases, and at the same time, the surface copper thickness increases, and the Cu CMP time also increases; (3) the subsequent bell mouth removal requires continuous switching of Cu CMP and dielectric layer CMP machines, which is complicated, time-consuming, and costly.

[0038] The process of the present invention is as follows Figure 8 As shown, the details are as follows:

[0039] 1. Deposit a thickened hard mask layer on the original top dielectric film layer of the wafer;

[0040] 2. Perform conventional photolithography, where the photoresist acts as a top hard mask layer plus a barrier layer over the original dielectric film layer;

[0041] 3. Perform dielectric layer and silicon etching processes, as described above, to form a top bell-mouth morphology;

[0042] 4. Carry out conventional copper electroplating process;

[0043] 5. Remove the copper on the surface;

[0044] 6. Perform annealing to allow the copper grains inside the TSV to fully expand due to heat. At this time, bubbles will appear inside the low-temperature deposited film layer, and the adhesion to the bottom film layer will decrease;

[0045] 7. Perform copper chemical mechanical polishing to remove the copper protruding from the surface. At this time, due to the decrease in adhesion of the low-temperature film layer, it will fall off during the polishing process. Therefore, copper chemical mechanical polishing is used to remove the copper inside the TSV of the top hard mask layer, stopping at the original dielectric layer on the top;

[0046] In addition, the following explanations are required.

[0047] 1. Description of the low-temperature deposited film layer: The present invention uses a mixture of liquid tetraethoxysilane (TEOS) and gaseous oxygen (O2) as a precursor, and adopts plasma enhanced chemical vapor deposition of SiO2. The low temperature is 100-150°C. Then expose it to the air. Compared with SiO2 grown by thermal oxidation, SiO2 grown by low-temperature PECVD (LowTemperature SiO2: LT-SiO2) contains some hydrogen elements, as shown in Table 1. According to the TDS (Thermal Desorption Spectroscopy) analysis of the above method (low-temperature PECVD deposition of SiO2 using TEOS+O2 as a precursor), 70% of the weight loss is water, as shown in Table 1. Figure 9 As shown, there are three peaks: I, II and III.

[0048] Peak I is caused by the presence of many micropores on the surface of the deposited film, which absorbs water from the air. This water is desorbed and forms peak I.

[0049] Peak II is caused by the fact that hydrogen atoms in TEOS are mostly present as -OH groups within the film. Some absorbed water bonds to these -OH groups through hydrogen bonds. Simultaneously, Si-OH reacts at 250°C-350°C to generate water. These two components of water desorb, forming Peak II.

[0050] The reason for peak III is that at temperatures above 400°C, the TEOS remaining in the film undergoes the following reaction to generate water, which is partially desorbed, thus forming peak III.

[0051] We use bonding to observe the precipitated bubbles, such as Figure 10 As shown in the figure, it can be seen that a large number of bubbles are precipitated. Figure 11 shown.

[0052] The low-temperature deposited film layer in the present invention is mainly used for depositing a hard mask. The temperature of the subsequent deposited film layer also needs to adopt this low-temperature deposition mode. If the temperature of the subsequent deposited film layer is higher than the low-temperature deposition temperature, the LT-SiO2 film layer will release gas, resulting in a decrease in the adhesion of the film layer, bubbles, and inconsistent film deposition thickness, and problems with subsequent Litho and other processes. We can deposit any film layer we think is suitable on top of LT-SiO2, such as TiN, Screen OX, SIOC, OMCTS, NBLoK and other hard mask layers of different materials (as long as the temperature does not exceed the initial LT-SiO2 deposition temperature). They can be removed later by heating the LT-SiO2 to produce bubbles.

[0053] The deposition thickness of LT-SiO2 needs to be greater than 50nm. If we need a thinner thickness of LT-SiO2, we can thin it through CMP and then deposit subsequent film layers.

[0054] 2. We utilize the TSV Cu annealing heat treatment to simultaneously expand and grow the copper grains within the TSV and prevent blistering in the LT-SiO2, eliminating the need for an additional annealing step. In conventional processes, the TSV Cu annealing temperature cannot exceed the PECVD film deposition temperature; otherwise, blistering will occur, impacting film quality. Therefore, this solution follows the same principle: conventional film deposition temperature ≥ TSV Cu annealing temperature > LT-SiO2 deposition temperature. This ensures that bubbling in the LT-SiO2 layer is avoided while conventionally deposited films do not.

[0055] 3. Because the hard mask film layer will fall off due to the adhesion of LT-SiO2, we only need to remove the Cu inside the TSV in the later stage, so we can use Cu CMP. The time of our overall process will be greatly reduced, the complexity will be significantly reduced, and the cost will be significantly reduced.

[0056] 4. This solution can completely remove the unnecessary hard mask layer without adding additional film structure. It only needs to ensure that the bell mouth morphology ends inside the hard mask layer and above the lower interface of the LT-SiO2 film layer. Figure 12 shown.

[0057] 5. Due to the high aspect ratio of TSVs, especially during silicon etching using the Dr. Etch process, the polymer layer is relatively thick, making it easier for etching ions to penetrate during the etching process, forming individual pits. The subsequent removal of Cu ECPs is difficult, and Cu residual defects often appear on the surface. This makes clean removal difficult. With this solution, the surface copper is completely removed as it is subsequently peeled off with the film layer, eliminating the problem of residual copper. This solution can also be extended to conventional Damascene processes to achieve complete removal of the hard mask layer and surface copper.

[0058] 6. The LT-SiO2 of this solution can also be replaced with other film layers, such as hydrogenated, fluorinated, and halogenated amorphous carbon films. This type of film layer will also release gas during the subsequent heating process, thereby reducing the adhesion of the film layer and eventually causing the film layer to peel off, achieving the same effect as LT-SiO2.

[0059] In summary, this solution increases the thickness of the hard mask, switches part of the film layer to LT-SiO2, and sequentially performs conventional Litho Etch and other processes to control the bell mouth above the LT-SiO2 lower interface. Conventional TSV ECP, Cu CMP and other processes are then performed. The heat of the TSV CuAnneal process is used to generate bubbles in the LT-SiO2, thereby reducing its film adhesion. After the subsequent CMP stress is applied, the film layer falls off, and only Cu CMP is required to remove the unnecessary Cu in the TSV. This completely eliminates the bell mouth defect morphology at the top of the TSV. The present invention is highly practical and can be quickly applied to mass production factories.

[0060] The advantages and benefits of the present invention are as follows:

[0061] 1. It does not rely too much on process and hardware optimization. Even the flare produced by conventional etching process and hardware can be easily removed by this solution.

[0062] 2. The processes used are all common Fab processes. Only the temperature of one PECVD step needs to be adjusted to convert to LT-SiO2. No additional process steps are added.

[0063] 3. The last step is to remove the bell mouth with CMP. As the adhesion of the film layer decreases, the hard mask layer will automatically fall off. We use Cu CMP to remove the Cu in the TSV, and a conventional Cu CMP machine can be used, which is exactly the same as the original TSV Cu2ndCMP process. After the Cu in the TSV bell mouth is removed, it is sufficient to stop at the original dielectric layer position on the top of the surface. There is no need for the existing process to continuously switch between Cu CMP and dielectric layer CMP to remove excess Cu and dielectric layer due to the thickened hard mask layer. In the present invention, only the Cu in the TSV needs to be removed. Since the proportion of TSV in the entire wafer is very low, this step requires less process time and low cost.

[0064] The surface film is peeled off due to decreased adhesion, so there is no problem of surface copper residue caused by incomplete CMP removal. This solution can also be applied to conventional copper Damascene processes to achieve the goal of completely removing the hard mask layer and the surface copper.

[0065] Table 1: Comparative analysis of the composition of LT-SiO2 and thermally oxidized SiO2

[0066]

[0067] 1. The film layer at the location where the bell mouth exists is a low-temperature deposited film layer;

[0068] 2. The lowest point of the bell mouth must be above the lower interface of the low-temperature deposited film layer.

[0069] Only when the film needs to be stripped before Cu CMP can a process with a temperature higher than the low-temperature film deposition temperature and sufficient bubbles to significantly reduce the film adhesion ability appear.

[0070] It should be noted that, in this document, relational terms such as first and second, etc., are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply the existence of any such actual relationship or order between these entities or operations. Moreover, the terms "comprises," "comprising," or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article, or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or device. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of other identical elements in the process, method, article, or device comprising the element.

[0071] Each embodiment in this specification is described in a related manner. The same or similar parts between the embodiments can be referred to each other. Each embodiment focuses on the differences from other embodiments.

[0072] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in the present invention should be included in the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be based on the scope of protection of the claims.

[0073] The above embodiments of the present invention are merely examples for the purpose of clearly illustrating the present invention and are not intended to limit the embodiments of the present invention. Those skilled in the art will appreciate that other variations or modifications may be made based on the above description. It is not necessary and impossible to enumerate all embodiments here. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention are intended to be included within the scope of protection of the claims of the present invention.

Claims

1. A method for manufacturing a semiconductor device with a TSV bell mouth morphology adjustment function, characterized in that: include: Step S1, depositing a first hard mask layer on the dielectric film layer located on the top of the wafer, wherein the first hard mask layer is LT-SiO2 formed by using a mixture of liquid tetraethoxysilane and gaseous oxygen as a precursor, through plasma-enhanced chemical vapor deposition, and exposing to air at a temperature of 100-150°C; Step S2, applying photoresist on the first hard mask layer and the dielectric film layer, and forming an etching pattern by photolithography; Step S3, etching the dielectric film layer by a silicon etching process, forming a top bell-mouth morphology above the lower interface of LT-SiO2; Step S4, copper is plated on the dielectric film layer with the top bell-mouth by a copper electroplating process, and then the copper on the surface is removed; Step S5, performing an annealing process to allow the copper grains inside the TSV to fully expand due to heat.

2. The method for manufacturing a semiconductor device according to claim 1, wherein: The method further includes: step S6 , performing copper chemical mechanical polishing after the annealing process is completed, until the copper inside the top TSV is removed and the dielectric film layer is exposed.

3. The method for manufacturing a semiconductor device according to claim 1, wherein: After step S1, the method further includes setting the deposition temperature to be less than or equal to the LT-SiO2 deposition temperature, and further depositing one of titanium nitride, shielding oxide, silicon oxycarbide, octamethylcyclotetrasiloxane, and NBLoK on the LT-SiO2 as a second hard mask layer.

4. The method for manufacturing a semiconductor device according to claim 3, wherein: The deposition thickness of LT-SiO2 is greater than 50nm.

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