Packaging structure with built-in discrete device and isolation chip

Abstract

The invention provides a packaging structure with a built-in discrete device and an isolator chip. The packaging structure comprises a frame base island, a chip, the discrete device, a bonding pad and a first plastic package body, the frame base island and the chip are plastically packaged in the first plastic package body; the chip is arranged on the base island frame; a bonding pad connected with the chip is arranged at the position, corresponding to the chip, of the first plastic package body; the discrete device is arranged on the bonding pad; the device also comprises a redistribution layer (RDL). The redistribution layer RDL is arranged at a position, corresponding to the bonding pad, on the first plastic package body and is connected with the bonding pad; the first plastic package body, the bonding pad, the discrete device and the RDL are all arranged in the second plastic package body in a plastic package mode. According to the invention, built-in packaging of discrete devices can be realized, the chip integration level is improved, the chip packaging size is controlled, the sealing function is improved, and the method is especially suitable for multi-core sealing scenes of isolator chips and the like.

Description

Technical Field

[0001] The present invention relates to the field of packaging technology, and in particular to a packaging structure with built-in discrete devices and an isolation chip. Background Art

[0002] Traditional frame-type packaging, because it only has one layer of metal frame, cannot carry complex circuit connection functions inside, and it is difficult to realize the internal multi-core plastic packaging solution. In addition, the traditional closed-package multi-chip packaging structure requires external capacitors and pull-down resistors when the power supply is supplied, which requires adding external pins to the packaging structure, such as Figure 1 As shown, only necessary discrete devices can be placed outside the frame. However, doing so will not only increase the size of the single package, but also increase the complexity and redundancy of the application end. In addition, the existing packaging process is difficult to cope with complex wiring situations, and cross-wiring is almost not allowed. Especially when using a combined packaging project, many wiring problems and risks will cause the project to fail. Summary of the invention

[0003] The technical problem to be solved by the present invention is to provide a packaging structure and an isolation chip with built-in discrete devices, so as to achieve built-in packaging of discrete devices and improve chip integration.

[0004] In order to solve the above technical problems, the first technical solution adopted by the present invention is:

[0005] A packaging structure with a built-in discrete device, comprising: a frame base island, a chip, a discrete device, a pad and a first plastic package;

[0006] The frame base island and the chip are plastic-encapsulated in the first plastic encapsulation body; the chip is arranged on the base island frame; the first plastic encapsulation body is provided with the pad connected to the chip at the position corresponding to the chip; the discrete device is arranged on the pad.

[0007] Optionally, the pad is led out by punching and electroplating at a position corresponding to the chip on the first plastic package body.

[0008] Optionally, a redistribution layer RDL is further included; the redistribution layer RDL is arranged at a position on the first plastic package body corresponding to the pad and is connected to the pad.

[0009] Optionally, the chip is a flip chip; and the pad is a pad obtained by grinding the solder joints on the flip chip.

[0010] Optionally, a redistribution layer RDL is further included; the redistribution layer RDL is arranged at a position on the first plastic package body corresponding to the pad and is connected to the pad.

[0011] Optionally, the frame base island includes a first frame base island and a second frame base island that are isolated from each other; the chip includes a first chip and a second chip; the discrete device includes a first discrete device and a second discrete device; the pad includes a first pad and a second pad;

[0012] The first chip is arranged on the first frame base island, and the second chip is arranged on the second frame base island; the first solder pad is provided on the first plastic package body at a position corresponding to the first chip, and the second solder pad is provided on the first plastic package body at a position corresponding to the second chip; the first discrete device is connected to the first chip via the first solder pad, and the second discrete device is connected to the second chip via the second solder pad.

[0013] Optionally, it also includes a first redistribution layer RDL and a second redistribution layer RDL; the first redistribution layer RDL is arranged at a position corresponding to the first pad on the first plastic package and is connected to the first pad; the second redistribution layer RDL is arranged at a position corresponding to the second pad on the first plastic package and is connected to the second pad.

[0014] Optionally, the discrete components include resistors and capacitors.

[0015] Optionally, a second plastic package body is further included; the first plastic package body, the solder pad and the discrete device are all plastic-sealed in the second plastic package body.

[0016] Another technical solution provided by the present invention is:

[0017] An isolator chip comprises the above-mentioned packaging structure with built-in discrete devices; and also comprises a second plastic package body; the first plastic package body, the solder pad and the discrete devices are all plastic-packaged in the second plastic package body.

[0018] The beneficial effect of the present invention is that: the present invention provides a pad connected to the chip at the position corresponding to the chip on the first plastic package body, and the pad can be formed by punching and electroplating, or by using the solder joints of the flip chip; then the discrete device is arranged on the pad, and all the components are plastic-sealed in the second plastic package body. In this way, the discrete device is built-in and the chip integration is improved. Doing so can not only simplify the number of external pins, improve the sealing function, and control the chip packaging size; but also will not increase the difficulty of frame processing; further, the present invention can also be well applied to the multi-chip sealing scenario, and solve the problem of complex wire crossing, so that the multi-core sealing structure can also have the above advantages, and significantly improve the integration of the multi-core sealing chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 This is a schematic diagram of the structure of a traditional chip;

[0020] Figure 2 A schematic diagram of a package structure 1 of a built-in discrete device provided in Embodiment 1 of the present invention;

[0021] Figure 3 A schematic diagram of a second packaging structure of a built-in discrete device provided in the first embodiment of the present invention;

[0022] Figure 4 A schematic diagram of a package structure 1 of a built-in discrete device provided in Embodiment 2 of the present invention;

[0023] Figure 5 A schematic diagram of a second packaging structure of a built-in discrete device provided in the second embodiment of the present invention;

[0024] Figure 6 A schematic diagram of a multi-core packaged structure 1 with built-in discrete devices provided in Embodiment 3 of the present invention;

[0025] Figure 7 A schematic diagram of a second multi-core packaged structure with built-in discrete devices provided in Embodiment 3 of the present invention;

[0026] Figure 8 A schematic diagram of a multi-core packaged structure 3 with built-in discrete devices provided in a third embodiment of the present invention;

[0027] Fig. 9 A schematic diagram of a multi-core packaged structure 4 with built-in discrete devices provided in the third embodiment of the present invention;

[0028] Fig.10 for Figure 6 Schematic diagram of the process flow of multi-core sealing structure 1;

[0029] Fig.11 for Figure 7 Schematic diagram of the process flow of multi-core sealing structure 2;

[0030] Fig.12 for Figure 8 Schematic diagram of the process flow of multi-core sealing structure 3;

[0031] Fig.13 for Fig. 9 Schematic diagram of the process flow of multi-core sealing structure four.

[0032] Description of labels:

[0033] 1. Frame base island; 2. Chip; 3. Discrete device; 4. Pad; 5. First plastic package; 6. Second plastic package; 7. Solder point; 8. Redistribution layer RDL;

[0034] 11. The first frame base island; 12. The second frame base island;

[0035] 21. First chip; 22. Second chip;

[0036] 31. a first discrete device; 32. a second discrete device;

[0037] 41. a first pad; 42. a second pad;

[0038] 81. A first redistribution layer RDL; 82. A second redistribution layer RDL. DETAILED DESCRIPTION

[0039] In order to explain the technical content, achieved objectives and effects of the present invention in detail, the following is an explanation in conjunction with the implementation modes and the accompanying drawings.

[0040] Embodiment 1

[0041] Please refer to Figure 2 , this embodiment provides a packaging structure with built-in discrete devices.

[0042] The packaging structure of the built-in discrete device provided in this embodiment is as follows: Figure 2 As shown, it includes: a frame base island 1, a chip 2, a discrete device 3, a pad 4 and a first plastic package 5;

[0043] The frame base island 1 and the chip 2 are plastic-encapsulated in the first plastic encapsulation body 5; the chip 2 is arranged on the base island frame 1; the first plastic encapsulation body 1 is provided with a solder pad 4 connected to the chip at a position corresponding to the chip 2; and the discrete device 3 is arranged on the solder pad 4.

[0044] In this embodiment, the pad can be obtained in at least the following two ways:

[0045] In some specific embodiments, Figure 2 As shown, the pad 4 can be led out by punching and electroplating. Specifically, the pad 4 vertically connected to the chip 2 is led out by punching a circuit at a position corresponding to the chip 2 above the first plastic package 5.

[0046] In some other specific embodiments, Figure 3 As shown, the pad 4 can also be obtained by grinding the upward solder joint 7 on the flip chip. That is, the chip 2 is a flip chip, and the solder joint 7 on the flip chip is directly ground to form the pad 4. This method saves the steps of making laser holes and electroplating the laser holes, and only needs to be directly ground to obtain the pad, which can greatly simplify the manufacturing process.

[0047] In this embodiment, the discrete devices may be electronic devices such as resistors, capacitors, diodes, transistors, thyristors, MOS tubes, etc., which are used to realize functions such as rectification, voltage stabilization, and switching.

[0048] In some specific implementations, the discrete device is fixedly disposed on the pad in the form of surface mounting.

[0049] In some other specific embodiments, Figure 2 As shown, the discrete device 3 includes a resistor R and a capacitor C; the mounting position of the capacitor C on the pad 4 is connected to the chip 2 and the frame base island 1. That is, the capacitor is connected to the frame base island (ground connection) and the chip through the pad.

[0050] In this embodiment, if Figure 2 As shown, preferably, the solder joints of the pads 4 are all vertical solder joints, that is, the solder joints on the pads are vertically connected to the chip and the frame base island. Here, the packaging structure of this embodiment will have the characteristics of vertical stacking and vertical connection, which can not only compress the structure size, but also shorten the signal transmission path, so that the transmission matching performance is more guaranteed.

[0051] In this embodiment, if Figure 2 and Figure 3 As shown, the second plastic package body 6 is also included; the first plastic package body 5, the pad 4 and the discrete device 3 are all plastic-encapsulated in the second plastic package body 6. That is, after the discrete device is fixedly arranged at the pad position on the first plastic package body, the whole is packaged again to obtain the second plastic package body. Here, the second plastic package body plays the role of fixing the discrete device and the first plastic package body.

[0052] The packaging structure of built-in discrete devices provided in this embodiment can realize the built-in packaging of discrete devices and improve the packaging integration; at the same time, it can also reduce the chip volume and reduce the design complexity of the application end; in addition, it can also shorten the length of the connecting line, and the corresponding parasitic parameters will also be significantly improved.

[0053] Embodiment 2

[0054] See also Figure 4 This embodiment is further expanded based on the first embodiment and can further realize packaging rewiring.

[0055] The packaging structure of the built-in discrete device provided in this embodiment is as follows: Figure 4 As shown, a redistribution layer RDL8 is also included; the redistribution layer RDL8 is arranged on the first plastic package body 5 at a position corresponding to the pad 4 and is connected to the pad 4.

[0056] The redistribution layer (RDL) refers to a metal layer capable of redistributing electrical connections.

[0057] In this embodiment, a redistribution layer RDL8 is additionally provided at the position of the pad 4 on the first plastic package body 5 to realize the rewiring function on the package surface, which can reduce the risk of wire crossing and solve the problem that complex wires are easily unable to be put into production due to cross short circuits; at the same time, the chip size can be reduced by optimizing the wiring in complex wire bonding scenarios, and the parasitic parameters can also be improved. In addition, through the redistribution layer RDL, multiple chips can be integrated into a single package to improve the sealing function.

[0058] In particular, the configuration of the redistribution layer RDL described in this embodiment is also applicable to the application scenario where the chip is a flip chip. Figure 5 As shown, a flip chip packaging structure is adopted for the chip 2, and its redistribution layer RDL8 is arranged on the first plastic package body 6 at a position corresponding to the flip chip, and is connected to the pad 4 obtained by the flip chip.

[0059] In this embodiment, corresponding to the two implementation forms of the pad, the redistribution layer RDL also has two implementation modes:

[0060] In some specific embodiments, that is, when the chip is a non-flip chip, the signal port to be connected, i.e., the pad, can be firstly led out on the first plastic package by punching and electroplating; then, a wire connecting the signal, i.e., the redistribution layer RDL, is formed by copper plating.

[0061] In some other specific embodiments, that is, when the chip is a flip chip, the solder joints facing upward on the flip chip can be ground flat first and then used as pads; then, electroplated wires are formed to connect the signals by copper plating, that is, the redistribution layer RDL. It can be understood that compared with the previous specific embodiment, this specific embodiment omits the steps of making laser holes and electroplating the laser holes, and the redistribution layer RDL can be directly made on the pads formed by the flip chip, which can greatly simplify the manufacturing process.

[0062] This embodiment is particularly suitable for packaging of MPW chips. Through rewiring within the package, it is easier to achieve multi-core packaging without delaying sample development.

[0063] Embodiment 3

[0064] Please refer to Figure 6 This embodiment is further expanded on the basis of the first and second embodiments, and provides a multi-core sealing structure with built-in discrete devices.

[0065] First, this embodiment provides a multi-core package structure with built-in discrete devices based on the first embodiment. Figure 6As shown, the frame base island 1 specifically includes a first frame base island 11 and a second frame base island 12 which are isolated (can also be understood as being independent of each other and not connected); the chip 2 specifically includes a first chip 21 and a second chip 22; the discrete device 3 specifically includes a first discrete device 31 and a second discrete device 32; the pad 4 includes a first pad 41 and a second pad 42;

[0066] The first chip 21 is arranged on the first frame base island 11, and the second chip 22 is arranged on the second frame base island 12; the first solder pad 41 is provided on the first plastic package body 5 at a position corresponding to the first chip 21, and the second solder pad 42 is provided on the first plastic package body 5 at a position corresponding to the second chip 22; the first discrete device 31 is connected to the first chip 21 through the first solder pad 41, and the second discrete device 32 is connected to the second chip 22 through the second solder pad 42.

[0067] In some specific implementations of this embodiment, Figure 7 As shown, the first chip 21 and the second chip 22 can be flip-chips, and the first pads 41 and the second pads 42 are obtained by directly grinding the solder joints 7 on the corresponding first chip 21 and the second chip 22. It can be understood that the first chip and the second chip are a multi-core sealing structure of a flip-chip, which has the advantage of simplifying the manufacturing process compared to other specific implementations of this embodiment.

[0068] Secondly, in some other specific implementations of this embodiment, based on the above-mentioned embodiment 2, the packaging surface rewiring function of the multi-core sealing structure can also be further realized by adding the redistribution layer RDL, so as to better adapt to complex wiring scenarios and improve the sealing function.

[0069] Specifically, if Figure 8 As shown, the redistribution layer RDL8 includes a first redistribution layer RDL81 and a second redistribution layer RDL82; the first redistribution layer RDL81 is arranged at a position corresponding to the first pad 41 on the first plastic package 5, and is connected to the first pad 41; the second redistribution layer RDL82 is arranged at a position corresponding to the second pad 42 on the first plastic package 5, and is connected to the second pad 42.

[0070] In some preferred implementations of the above specific implementations, a flip chip solution may also be used, that is, a redistribution layer RDL is added on the basis of the flip chip, so as to simplify the manufacturing process and have the function of rewiring the package surface.

[0071] Specifically, if Fig. 9As shown, the first chip 21 and the second chip 22 are both flip chips; the first redistribution layer RDL81 and the second redistribution layer RDL82 are respectively arranged above the first chip 21 and the second chip 22, and are respectively connected to the pads of the corresponding flip chips, namely the first pad 41 and the second pad 42.

[0072] The multi-core packaged structure provided in this embodiment includes two independent chip base island structures with consistent structures and functions. By utilizing the isolation properties between them, wireless isolated communication transmission can be realized, such as high and low voltage wireless isolation devices in power systems and other scenarios where wireless isolated transmission is required.

[0073] Embodiment 4

[0074] This embodiment further expands upon the above-mentioned embodiment 3, and provides corresponding process manufacturing flows for the above-mentioned four multi-core sealing structures.

[0075] (1) Figure 6 The first multi-core package structure (with discrete devices built in) shown in FIG. Fig.10 As shown:

[0076] S1: frame base island production;

[0077] S2: Mount the chip on the frame base island;

[0078] S3: wire connection pin;

[0079] S4: plastic sealing for the first time to obtain a first plastic sealing body;

[0080] S5: laser drilling + electroplating + surface treatment, and setting a soldering pad on the first plastic package;

[0081] S6: Mount discrete components on the pad surface;

[0082] S7: plastic-sealing for the second time to obtain a second plastic-sealed body;

[0083] S8: Cut the ribs and form them to obtain a finished chip.

[0084] The process flow of the first multi-core sealed structure (built-in discrete devices) is to lead out the signals of the discrete devices that need to be connected and externally mounted through the laser holes on the basis of the first plastic package, fill the laser holes with electroplating and perform surface treatment to form surface mount pads; and perform the second packaging after the discrete devices are configured through reflow soldering to obtain the finished chip. It can realize the packaging of built-in discrete devices and improve the packaging integration; at the same time, it can also reduce the chip size and optimize the parasitic parameters.

[0085] (two) Figure 7The second multi-core package structure (flip chip + built-in discrete devices) shown in FIG. Fig.11 As shown:

[0086] S1: frame base island production;

[0087] S2: Place the flip chip face up (i.e., the side with solder joints facing up) on the frame base island;

[0088] S3: plastic sealing for the first time to obtain a first plastic sealing body;

[0089] S4: grinding the solder joints of the flip chip and performing surface treatment to form solder pads on the first plastic package;

[0090] S5: Mount discrete components on pads;

[0091] S6: wire connection pins;

[0092] S7: plastic-sealing for the second time to obtain a second plastic-sealed body;

[0093] S8: Cut the ribs and form them to obtain a finished chip.

[0094] The process flow of the second multi-core sealing structure (flip chip + built-in discrete device) mentioned above uses a flip chip, which has solder joints facing up. Therefore, on the basis of the first plastic package, electroplating is not required, and the solder joints can be directly ground flat to obtain the pads; then the discrete devices are mounted on the pads and the second packaging is performed to obtain the finished chip. Not only can the built-in discrete device packaging be realized and the packaging integration is improved, but also the chip size can be reduced and the parasitic parameters can be optimized; more importantly, the manufacturing process can be greatly simplified.

[0095] (three) Figure 8 The second multi-core package structure (discrete device built-in + package rewiring) has a process flow as shown in FIG. Fig.12 As shown:

[0096] S1: frame base island production;

[0097] S2: Mount the chip on the frame base island;

[0098] S3: wire connection pin;

[0099] S4: plastic sealing for the first time to obtain a first plastic sealing body;

[0100] S5: laser drilling + electroplating + surface treatment, and setting a soldering pad on the first plastic package;

[0101] S6: Electroplating and rewiring on the pad to obtain a redistribution layer RDL;

[0102] S7: mounting discrete components on the redistribution layer RDL;

[0103] S8: plastic sealing for the second time to obtain a second plastic sealing body;

[0104] S9: Cut the ribs and form them to obtain a finished chip.

[0105] The process flow of the third multi-core sealed structure (built-in discrete devices + package rewiring) is based on the first plastic package body. The signals of the discrete devices that need to be connected and externally mounted are led out through laser holes, and the laser holes are filled with electroplating and surface treated to form surface mount pads; electroplating circuits are deposited on the pad positions, and a redistribution layer is formed through graphic transfer and other methods to achieve signal connection on the first plastic package body; finally, discrete devices are configured and a second package is performed to obtain finished chips. It can not only realize the packaging of built-in discrete devices and improve the packaging integration, but also reduce the chip size and optimize parasitic parameters; it can also realize internal rewiring at the package level, solve the problem that complex wiring is easily unable to be put into production due to cross short circuit problems, and improve the sealing function.

[0106] (Four) Fig. 9 The fourth multi-core package structure (flip chip + built-in discrete devices + package rewiring) shown in FIG. Fig.13 As shown:

[0107] S1: frame base island production;

[0108] S2: Place the flip chip face up (i.e., the side with solder joints facing up) on the frame base island;

[0109] S3: plastic sealing for the first time to obtain a first plastic sealing body;

[0110] S4: grinding the solder joints of the flip chip and performing surface treatment to form solder pads on the first plastic package;

[0111] S5: electroplating and rewiring on the pad to obtain a redistribution layer RDL;

[0112] S6: Mount discrete components on pads;

[0113] S7: wire connection pins;

[0114] S8: plastic sealing for the second time to obtain a second plastic sealing body;

[0115] S9: Cut the ribs and form them to obtain a finished chip.

[0116] The process flow of the fourth multi-core sealing structure (flip chip + built-in discrete device + package rewiring) mentioned above, because it is a flip chip, the solder joints can be directly ground flat on the basis of the first plastic package to obtain the pads; then the wires are electroplated on the pads to form the redistribution layer RDL; finally, the discrete devices are mounted for the second packaging to obtain the finished chip. It can not only realize the packaging of built-in discrete devices and improve the packaging integration, but also reduce the chip size and optimize the parasitic parameters; it can also realize the internal rewiring at the package level, solve the problem that complex wiring is easy to fail to land production due to cross short circuit problems, and improve the sealing function; more importantly, it can greatly simplify the manufacturing process.

[0117] Embodiment 5

[0118] This embodiment, based on any one of the above-mentioned embodiments 1 to 4, provides an isolator chip, including the packaging structure of the built-in discrete device described in any one of the above-mentioned embodiments 1 to 4; and also includes a second plastic package; the first plastic package, the solder pad and the discrete device are all plastic-encapsulated in the second plastic package.

[0119] Since this embodiment includes two independent chip base island structures with consistent structures and functions, wireless isolated communication transmission can be achieved by utilizing the isolation properties between them, such as high and low voltage wireless isolation devices in power systems and other scenarios where wireless isolated transmission is required.

[0120] In summary, the packaging structure and isolation chip with built-in discrete devices provided by the present invention can realize the built-in discrete devices and improve the chip integration. It not only simplifies the number of external pins and controls the chip packaging size, but also does not increase the difficulty of frame processing. In addition, it is particularly suitable for multi-chip sealing scenarios, solves complex wire crossing, and significantly improves the multi-core sealing capability.

[0121] The above descriptions are merely embodiments of the present invention and are not intended to limit the patent scope of the present invention. Any equivalent transformations made using the contents of the present invention's specification and drawings, or directly or indirectly applied in related technical fields, are also included in the patent protection scope of the present invention.

Claims

1. A packaging structure with built-in discrete devices, characterized in that: include: Frame base island, chip, discrete device, pad and first plastic package; The frame base island and the chip are plastic-encapsulated in the first plastic encapsulation body; the chip is arranged on the base island frame; the first plastic encapsulation body is provided with the pad connected to the chip at the position corresponding to the chip; the discrete device is arranged on the pad.

2. The packaging structure of the built-in discrete device according to claim 1, characterized in that: The pad is led out at a position corresponding to the chip on the first plastic package body by punching and electroplating.

3. The packaging structure of the built-in discrete device according to claim 1, characterized in that: It also includes a redistribution layer RDL; the redistribution layer RDL is arranged at a position on the first plastic package body corresponding to the pad and is connected to the pad.

4. The packaging structure with built-in discrete devices as claimed in claim 1, characterized in that: The chip is a flip chip; the pad is a pad obtained by grinding the solder joints on the flip chip.

5. The packaging structure with built-in discrete devices as claimed in claim 4, characterized in that: It also includes a redistribution layer RDL; the redistribution layer RDL is arranged at a position on the first plastic package body corresponding to the pad and is connected to the pad.

6. The packaging structure with built-in discrete devices as claimed in claim 1, characterized in that: The frame base island comprises a first frame base island and a second frame base island which are isolated from each other; the chip comprises a first chip and a second chip; the discrete device comprises a first discrete device and a second discrete device; the pad comprises a first pad and a second pad; The first chip is arranged on the first frame base island, and the second chip is arranged on the second frame base island; the first solder pad is provided on the first plastic package body at a position corresponding to the first chip, and the second solder pad is provided on the first plastic package body at a position corresponding to the second chip; the first discrete device is connected to the first chip via the first solder pad, and the second discrete device is connected to the second chip via the second solder pad.

7. The packaging structure with built-in discrete devices as claimed in claim 6, characterized in that: It also includes a first redistribution layer RDL and a second redistribution layer RDL; the first redistribution layer RDL is arranged at a position corresponding to the first pad on the first plastic package and is connected to the first pad; the second redistribution layer RDL is arranged at a position corresponding to the second pad on the first plastic package and is connected to the second pad.

8. The packaging structure with built-in discrete devices as claimed in claim 1, characterized in that: The discrete components include resistors and capacitors.

9. The packaging structure of a built-in discrete device according to any one of claims 1 to 8, characterized in that: It also includes a second plastic package; the first plastic package, the pad and the discrete device are all plastic-sealed in the second plastic package.

10. An isolator chip, characterized in that: A packaging structure comprising a built-in discrete device as described in any one of claims 6 to 8; further comprising a second plastic package; the first plastic package, the solder pad and the discrete device are all plastic-sealed in the second plastic package.

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