Integrated circuit package with dual hybrid bond die and method of manufacturing same

Abstract

Systems, apparatus, and articles of manufacture are disclosed to implement integrated circuit packages with dual hybrid bond dies and methods of manufacturing the same, including an integrated circuit (IC) package that includes a first semiconductor die including first metal vias spaced apart along a first layer of a first dielectric material, the first metal vias including second metal vias spaced apart along a second layer of the first dielectric material, and a second semiconductor die including second metal vias spaced apart along a second layer of the first dielectric material. The first metal vias are connected to respective first metal pads of the first semiconductor die; a second semiconductor die including a second metal pad of the second semiconductor die; and a hybrid bonding layer including a third dielectric material and third metal vias spaced apart along the third dielectric material, a subset of the third metal vias electrically coupling a first one of the first metal pads to a corresponding one of the second metal pads, a first one of the third metal vias is located outside a lateral side of the first semiconductor die.

Description

Technical Field

[0001] The present disclosure relates generally to electronic devices, and more particularly, to dual hybrid bonded dies and methods of fabricating the same. Background Art

[0002] Fast data transfer within computing, storage, and communications infrastructure is pushing the speed limits of traditional copper-based electrical links. In addition, with the increasing functionality of circuit systems and the increasing density of semiconductor devices, it has become increasingly difficult to physically place a sufficient number of interconnections on the outer surface of the die. Die stacking allows for multi-chip packaging structures that can achieve significant performance improvements in computing power and memory / processor integration. Because die stacking allows for more interconnections on the outer surface of the die, the multi-chip packaging structure made possible by die stacking allows for increased data transfer speeds. BRIEF DESCRIPTION OF THE DRAWINGS

[0003] Figure 1 An exemplary integrated circuit (IC) package electrically coupled to a circuit board is shown.

[0004] Figure 2A An exemplary semiconductor package is shown.

[0005] Figure 2B Shows Figure 2A An exemplary first portion of an exemplary semiconductor package in.

[0006] Figure 2C Shows Figure 2A An exemplary pad of an exemplary semiconductor package in FIG.

[0007] Figure 3 shows the Figure 2A An exemplary semiconductor package in.

[0008] Figure 4 The package substrate is shown Figure 2A An exemplary semiconductor package in.

[0009] Figure 5-Figure 11 Shows Figure 2A The various stages in an exemplary manufacturing process of an exemplary semiconductor package in FIG.

[0010] Fig.12 Based on the combination Figure 5-Figure 11 The exemplary techniques described herein are representative of the manufacturing Figure 2A A flowchart of an exemplary method of an exemplary semiconductor package in FIG.

[0011] Fig.13 is a top view of a wafer and die that may be included in an IC package constructed according to the teachings disclosed herein.

[0012] Fig.14 is a cross-sectional side view of an IC device that may be included in an IC package constructed according to the teachings disclosed herein.

[0013] Fig.15 is a cross-sectional side view of an IC device assembly that may include an IC package constructed according to the teachings disclosed herein.

[0014] Fig.16 is a block diagram of an exemplary electrical device that may include an IC package constructed according to the teachings disclosed herein.

[0015] Generally, the same reference numerals are used throughout the drawings and the accompanying written description to refer to the same or similar parts. The drawings are not necessarily to scale. On the contrary, the thickness of a layer or region may be exaggerated in the drawings. Although the drawings show layers and regions with clear lines and boundaries, some or all of these lines and / or boundaries may be idealized. In reality, boundaries and / or lines may be invisible, mixed and / or irregular.

[0016] As used herein, unless otherwise specified, the term "above" describes the relationship of two parts relative to the ground. A first part is above a second part if the second part has at least one portion that is between the ground and the first part. Similarly, as used herein, a first part is "below" a second part when the first part is closer to the ground than the second part. As described above, a first part can be above or below a second part in one or more of the following situations: there are other parts in between, there are no other parts in between, the first part is in contact with the second part, or the first part and the second part are not in direct contact with each other.

[0017] Notwithstanding the foregoing, "above" in reference to semiconductor devices (e.g., transistors), semiconductor dies containing semiconductor devices, and / or integrated circuit (IC) packages containing semiconductor dies during fabrication or manufacturing is not in reference to ground, but instead is in reference to an underlying substrate on which the associated components are fabricated, assembled, mounted, supported, or otherwise provided. Thus, as used herein, and unless the context indicates or implies otherwise, a first component (e.g., a transistor or other semiconductor device) within a semiconductor die is "above" a second component within a semiconductor die when the first component is farther from a substrate (e.g., a semiconductor wafer) on which the two components are fabricated or otherwise provided during fabrication / manufacturing than the second component. Similarly, a first component (e.g., a semiconductor die) within an IC package is "above" a second component within an IC package during fabrication when the first component is farther from a printed circuit board (PCB) to which the IC package is to be mounted or attached, unless the context indicates or implies otherwise. It should be understood that semiconductor devices are often used in orientations other than those in which they are fabricated or otherwise provided. Thus, when referring to a semiconductor device (e.g., a transistor), a semiconductor die containing a semiconductor device, and / or an integrated circuit (IC) package containing a semiconductor die during use, the definition of “above” in the preceding paragraph (i.e., the term “above” describes the relationship of two parts relative to ground) will likely be dictated by the context of use.

[0018] As used in this patent, stating that any part (e.g., a layer, film, region, area, or plate) is in any way on (e.g., placed, located, set on, or formed on, etc.) another part indicates that the referenced part is in contact with the other part, or that the referenced part is located above the other part with one or more intermediate parts located therebetween.

[0019] As used herein, unless otherwise indicated, connection references (e.g., attachment, coupling, connection, and linking) may include intermediate members between elements referenced by the connection reference and / or relative motion between these elements. Thus, a connection reference does not necessarily mean that two elements are directly connected and / or are in a fixed relationship to each other. As used herein, stating that any part is "in contact" with another part is defined as meaning that there is no intermediate part between the two parts.

[0020] Unless otherwise specifically stated, the use of descriptors such as "first", "second", "third", etc. in this document does not imply or otherwise indicate any meaning of priority, physical order, arrangement in a list, and / or ordering in any way, but is merely used as a number and / or arbitrary name to distinguish elements to facilitate understanding of the disclosed examples. In some examples, the descriptor "first" may be used to refer to an element in a specific embodiment, while a different descriptor such as "second" or "third" may be used in the claims to refer to the same element. In such instances, it should be understood that such descriptors are only used to explicitly identify those elements in the context of the discussion (e.g., within the claims) that might otherwise share the same name.

[0021] As used herein, "approximately" and "about" modify the subject matter / value thereof to recognize that there may be variations in actual applications. For example, "approximately" and "about" may modify dimensions that may be imprecise due to manufacturing tolerances and / or other actual imperfections as will be understood by one of ordinary skill in the art. For example, unless otherwise stated in the following description, "approximately" and "about" may indicate that such dimensions may be within a tolerance range of + / -50%.

[0022] As used herein, "substantially real time" means occurring in a near instantaneous manner recognizing that there may be realistic delays in computation time, transmission, etc. Thus, unless otherwise specified, "substantially real time" means real time + 1 second.

[0023] As used herein, the phrase "in communication" (including variations thereof) encompasses direct communication and / or indirect communication through one or more intermediate components and does not require direct physical (e.g., wired) communication and / or continuous communication, but also includes selective communication at periodic intervals, scheduled intervals, non-periodic intervals, and / or one-time events.

[0024] As used herein, "programmable circuitry" is defined to include: (i) one or more special-purpose circuits (e.g., application-specific circuits (ASICs)) that are structured to perform specific operation(s) and include one or more semiconductor-based logic devices (e.g., electrical hardware implemented by one or more transistors); and / or (ii) one or more general-purpose semiconductor-based circuits that can be programmed using instructions to perform specific function(s) and / or operation(s) and include one or more semiconductor-based logic devices (e.g., electrical hardware implemented by one or more transistors). Examples of programmable circuit systems include a programmable microprocessor (e.g., a central processing unit (CPU)) that can execute a first instruction to perform one or more operations and / or functions, a field programmable gate array (FPGA) that can be programmed with a second instruction so that the configuration and / or structure of the FPGA instantiates one or more operations and / or functions corresponding to the first instruction, a graphics processor unit (GPU) that can execute a first instruction to perform one or more operations and / or functions, a digital signal processor (DSP) that can execute a first instruction to perform one or more operations and / or functions, an XPU, a network processing unit (NPU), one or more microcontrollers that can execute a first instruction to perform one or more operations and / or functions, and / or an integrated circuit (e.g., an application specific integrated circuit (ASIC)). For example, the XPU can be implemented by a heterogeneous computing system including multiple types of programmable circuit systems (e.g., one or more FPGAs, one or more CPUs, one or more GPUs, one or more NPUs, one or more DSPs, etc., and / or any combination thereof), and an orchestration technology (e.g., (multiple) application programming interfaces (APIs)) that can assign (multiple) computing tasks to any one (or more) of the multiple types of programmable circuit systems that are suitable and can be used to perform (multiple) computing tasks.

[0025] As used herein, an integrated circuit / circuitry is defined as one or more semiconductor packages containing one or more circuit elements, such as transistors, capacitors, inductors, resistors, current paths, diodes, etc. For example, an integrated circuit may be implemented as one or more of an ASIC, an FPGA, a chip, a microchip, a programmable circuitry, a semiconductor substrate coupling multiple circuit elements, a system on a chip (SoC), etc. DETAILED DESCRIPTION

[0026] Hybrid bonding is a process that requires at least two flat and clean surfaces (e.g., hybrid bonding of a first flat and clean surface to a second flat and clean surface). Hybrid bonding has been used to connect various combinations of wafers, chips, and dies. In some examples, hybrid bonding is performed to connect a first wafer and a second wafer. According to the hybrid bonding process, after chemical mechanical planarization (e.g., CMP) of the first wafer and the second wafer, the first wafer and the second wafer can be directly bonded. After bonding, the wafer-to-wafer hybrid bonding package undergoes die singulation, testing, and processing that increases surface contamination, which may result in low yields. In some examples, hybrid bonding is performed to connect a first wafer and a chip. In such an example, due to die depolymerization, there is a higher yield for chip-to-wafer hybrid bonding packages.

[0027] Hybrid bonding connects a first metal surface and a second metal surface. In some examples, the hybrid bonding process connects two clean surfaces by hydrogen bonding. In some examples, a chip-to-chip configuration is used. However, in such examples, dirt (e.g., residue) may accumulate on the die before and after singulation of the first die. The exemplary residue on the first die reduces the connection between the dies. The reduced connection reduces the efficiency of the computing device by limiting the surface area available for hybrid bonding.

[0028] Figure 1 An exemplary integrated circuit (IC) package 100 is shown electrically coupled to a circuit board 102. In some examples, the IC package 100 is electrically coupled to the circuit board 102 via a first electrical connection 104. The first electrical connection 104 can include pins, pads, bumps, and / or balls to enable electrical coupling of the IC package 100 to the circuit board 102. The first electrical connection 104 between the IC package 100 and the circuit board 102 is sometimes referred to as a second level interconnect.

[0029] In this example, the IC package 100 includes two semiconductor dies 106, 108 (e.g., two silicon dies) mounted to a package substrate 110. The IC package 100 includes a third semiconductor die 112 bonded (e.g., abutting, attached, connected) over the first semiconductor die 106 and a fourth semiconductor die 114 bonded (e.g., abutting, attached, connected) over the second semiconductor die 108. The four dies 106, 108, 112, 114 are surrounded by a package cover or mold compound 116. Although Figure 1 The exemplary IC package 100 in FIG. 1 includes four dies 106 , 108 , 112 , 114 , but in other examples, the IC package 100 may have only one die or more than four dies. Figure 1 is a generic package showing dies that may be stacked (eg, hybrid bonded). Figure 2A-2C It is shown in Figure 1 An exemplary embodiment of die stacking in FIG.

[0030] like Figure 1 As shown in the example in , the dies 106, 108 are electrically and mechanically coupled to the package substrate 110 via a second electrical connection 118. The second electrical connection 118 may include a pin, a pad, a ball and / or a bump. The second electrical connection 118 between the dies 106, 108 and the package substrate 110 is sometimes referred to as a first-level interconnect. In some examples, one or both of the dies 106, 108 can be stacked on top of one or more other dies and / or interposers (e.g., a third die 112). In such an example, the dies 106, 108 are coupled to the lower die and / or interposer via a first set of first-level interconnects, and the lower die and / or interposer can be connected to the package substrate 110 via a separate set of first-level interconnects associated with the lower die and / or interposer.

[0031] As shown in the illustrated example, the package substrate 110 includes first electrical traces and / or wirings 120 that electrically connect the first electrical connections 104 with the second electrical connections 118, thereby enabling electrical coupling of the first die 106 and / or the second die 108 with the circuit board 102. Additionally, in some examples, the package substrate 110 includes second electrical traces and / or wirings 122 that electrically connect different ones of the first electrical connections 104 associated with the first die 106 and the second die 108, thereby enabling electrical coupling of the first die 106 and the second die 108. Figure 1 is a diagram of a general semiconductor package showing the stacked second die 108 and fourth die 114 . Figure 2A-2C It is shown that Figure 1 An exemplary stacking of dies implemented in FIG.

[0032] As used herein, a "known good die" is a die that has been tested. The die testing process is performed by using test pads that are areas of the die adjacent to the power supply. These known good dies are singulated (e.g., cut, diced into smaller wafers), and after singulation into wafers, the wafers are reassembled to form reassembled dies. The reassembled dies are then tested again to determine if the die is ready for use in a circuit (e.g., Figure 1 The exemplary third die 112 and the exemplary first die 106 may be connected by a hybrid bonding process. In some examples, the fourth die 114 and the exemplary second die 108 may be connected by a hybrid bonding process.

[0033] Figure 2Ais an illustration of an exemplary semiconductor package 200 including an exemplary first die 202, an exemplary second die 204, and an exemplary third die 206. The exemplary first die 202 includes an exemplary first bulk semiconductor region 208, the exemplary second die 204 includes an exemplary second bulk semiconductor region 210, and the exemplary third die includes an exemplary third bulk semiconductor region 212.

[0034] The exemplary first die 202 and the exemplary third die 206 are connected by an exemplary structural metal surface 214 (e.g., a cover, a substrate, a carrier, an exemplary silicon cover, structural silicon, a structural silicon surface). Based on the orientation of the semiconductor package, the exemplary structural metal surface 214 can function as a cover or a substrate (e.g., a carrier). An exemplary first dielectric filler 216 (e.g., an oxide filler) is deposited between the first die 202 and the third die 206.

[0035] The exemplary first die 202 includes an exemplary first metal interconnect 218. The exemplary first metal interconnect 218 includes a first metal via 244 ( Figure 2B-2C ) and the first metal pad 242 ( Figure 2B-2C In some examples, first metal pad 242 ( Figure 2B-2C In some examples, the first metal pad 242 ( Figure 2B-2C In some examples, the first metal pad 242 ( Figure 2B-2C ) is formed of copper. The exemplary second die 204 includes an exemplary second metal interconnect 220, and the exemplary third die 206 includes an exemplary third metal interconnect 222. The exemplary second metal interconnect 220 includes a second metal via 248 ( Figure 2B-2C ) and the second metal pad 246 ( Figure 2B-2C ) (e.g., second conductive pad, hybrid bonding pad). Exemplary first die 202 includes exemplary second dielectric filler 224. In some examples, second dielectric filler 224 is composed of the same dielectric material (e.g., oxide) as first dielectric filler 216. Exemplary second die 204 includes exemplary third dielectric filler 226, and exemplary third die 206 includes exemplary fourth dielectric filler 227.

[0036] The exemplary first die 202 and the exemplary third die 206 include an exemplary third metal pad 228 (e.g., a third conductive metal pad, a third metal via, a metal via of a first pad size, a first hybrid bonding pad). The exemplary second die 204 includes an exemplary fourth metal pad 230 (e.g., a fourth conductive metal pad, a fourth metal via, a metal via of a second pad size, a second hybrid bonding pad). The exemplary third metal pad 228 is connected to the exemplary first metal pad 242 of the first metal interconnect 218 ( Figure 2B-2C The exemplary third metal pad 228 may have a contact with the first metal pad 242 ( Figure 2B-2C In some examples, third metal pad 228 has a lateral dimension that is substantially different from first metal pad 242 (e.g., smaller than first metal pad 242 ( Figure 2B-2C ) and is larger than the first metal pad 242 ( Figure 2B-2C In some examples, third metal pad 228 may have a thickness approximately (eg, within 10%) equal to that of first metal pad 242 ( Figure 2B-2C The lateral dimensions of the lateral dimensions of the (marked in).

[0037] The exemplary fourth metal pad 230 and the exemplary second metal pad of the second metal interconnect 220 ( Figure 2B-2C ) and the exemplary third metal pad 228. The fourth metal pad 230 contacts the third metal pad 228 to allow the first metal interconnect 218 and the second metal interconnect 220 to be electrically connected. Without the third metal pad 228 and the fourth metal pad 230, the surface area of ​​the first metal interconnect 218 that contacts the second metal interconnect 220 would be reduced. The exemplary third metal pad 228 is aligned with the exemplary fourth metal pad 230, but is still aligned with the first metal pad ( Figure 2B-2C In this example, third metal pad 228 is at least approximately sixty percent aligned with fourth metal pad 230 (e.g., misaligned by as much as forty percent) and is aligned with first metal pad 242 ( Figure 2B-2C ) are at least approximately ninety percent aligned (e.g., misaligned by up to ten percent). That is, in some examples, the misalignment of third metal pad 228 with first metal pad 242 is less than the misalignment of third metal pad 228 with fourth metal pad 230. In other examples, the percentage of alignment may be based on the size of the pads (e.g., third metal pad 228, first metal pad 242 ( Figure 2B-2C), fourth metal pad 230, etc.), the spacing between pads, and the maximum current requirement. In other examples, third metal pad 228 is at least approximately ninety percent aligned with fourth metal pad 230 (e.g., misaligned by up to ten percent), and is aligned with first metal pad 242 ( Figure 2B-2C ) are at least about sixty percent aligned (e.g., misaligned by as much as forty percent). That is, in some examples, the misalignment of third metal pad 228 with first metal pad 242 is greater than the misalignment of third metal pad 228 with fourth metal pad 230. This design increases the efficiency of the computing device because the increased surface area allows faster transmission of electrical signals. Figure 2A As shown in the example of FIG. 1 , one of the third metal pads 228 is disposed in the exemplary first dielectric filler 216. A subset of the third metal pads 228 (e.g., a third metal via and a metal via of the first pad size, etc.) separates the first metal pad 242 ( Figure 2B-2C ) is electrically coupled to the first metal pad in the . A metal via of the first pad size (eg, the third metal pad 228) connects the first metal pad 242 ( Figure 2B-2C ) is electrically coupled to the first metal pad in.

[0038] In some examples, exemplary first die 202 and exemplary third die 206 can be considered as one long die in contact with exemplary second die 204. First die 202 and third die 206 are opposite to second die 204 (e.g., facing second die 204). First die 202 is laterally adjacent to exemplary third die 206. However, first die 202 can be formed by a first process and third die 206 can be formed by a second process. Exemplary first die 202 and exemplary third die 206 do not need to be from the same initial die substrate. In such an example, first metal pad 242 ( Figure 2B-2C The spacing (eg, the pitch) between the first metal pad 242 ( Figure 2B-2C The spacing (eg, the spacing) between the first metal pad 242 (marked in FIG. 1 ) and the second metal pad 242 (marked in FIG. 1 ) may be a second spacing value different from the first spacing value. Figure 2B-2C ) is misaligned to a first degree and may be aligned with the first metal pad 242 ( Figure 2B-2C However, the pitch (eg, spacing) of third metal pads 228 is consistent in both first die 202 and third die 206.

[0039] The exemplary first die 202 includes an exemplary first transistor 232, the exemplary second die 204 includes an exemplary second transistor 234, and the exemplary third die 206 includes an exemplary third transistor 236. The exemplary second die 204 includes an exemplary through-silicon via 238 and an exemplary bump 240. Figure 3-Figure 4 As described, the exemplary bumps 240 of the semiconductor package 200 may be used to attach the semiconductor package 200 to a wafer ( Figure 3 ) or package substrate ( Figure 4 ).

[0040] Figure 2B Shows Figure 2A The exemplary first portion of the exemplary semiconductor package 200 includes the exemplary first portion of the exemplary semiconductor package 200. Figure 2A The same reference numerals are used in the examples. Figure 2B Also shown is an exemplary first metal pad 242 extending from the first metal via 244 of the first metal interconnect 218. The exemplary first metal pad 242 contacts the exemplary third metal pad 228. Figure 2B In the example of , the third metal pad in exemplary third metal pad 228 is deposited inside the first metal pad in first metal pad 242. In some examples, first metal pad 242 is referred to as a first hybrid bond pad layer, and third metal pad 228 is referred to as a second hybrid bond pad layer. Since there are two separate hybrid bonds, the combination of the first hybrid bond pad layer and the second hybrid bond pad layer ( Figure 2B-2C ) may be referred to as a first hybrid bonding pad layer and a second hybrid bonding pad layer forming a dual hybrid bonding pad layer.

[0041] although Figure 2B The example in FIG. 2 shows an exemplary space between exemplary third metal pad 228 and exemplary fourth metal pad 230, but in some examples, third metal pad 228 contacts exemplary fourth metal pad 230. In some examples, third metal pad 228 contacts exemplary second metal pad 246. In such examples, second metal pad 246 is exposed for electrical connection and is absent fourth metal pad 230. Exemplary second metal pad 246 is shown extending from exemplary second metal interconnect 220 of second die 204.

[0042] Figure 2C 2 shows an exemplary pad of semiconductor package 200 in contact. Figure 2C In the example of FIG. 1 , each metal pad is labeled with a letter to indicate first, second, third, etc. However, in other examples, any number of metal pads may be used.

[0043] The exemplary first metal vias 244 include an exemplary first metal via 244A, an exemplary second metal via 244B, and an exemplary third metal via 244C. These first metal vias 244 are connected to corresponding first metal pads 242 (e.g., exemplary first metal pad 242A, exemplary second metal pad 242B, and exemplary third metal pad 242C). The exemplary second dielectric filler 224 (e.g., Figure 2A-2C In some examples, second dielectric filler 224 is formed of the same dielectric as first dielectric filler 216 (e.g., silicon oxide, silicon nitride).

[0044] The exemplary first portion of the second dielectric filler 224A and the exemplary second metal via 244B contact the exemplary first portion of the exemplary sacrificial via layer 250A. The exemplary sacrificial via layer 250 contacts the exemplary third dielectric layer 252 (e.g., silicon oxide, silicon nitride, silicon nitride carbon). The exemplary first portion of the exemplary sacrificial via layer 250A contacts the exemplary first portion of the exemplary third dielectric layer 252A. Similarly, the exemplary second portion of the exemplary sacrificial via layer 250B contacts the exemplary second portion of the exemplary third dielectric layer 252B. In some examples, the third dielectric layer 252 is the same material as the exemplary second dielectric filler 224 disposed between the first metal pads 242. In some examples, the third dielectric layer 252 is the same material as the exemplary first dielectric filler 216. In some examples, the sacrificial via layer 250 is formed as a dielectric, such as silicon oxide (SiO) or silicon nitride (SiN). However, since most of the sacrificial via layer 250 is subsequently removed, a variety of dielectrics may be used.

[0045] The exemplary second die 204 includes an exemplary first portion of an exemplary fourth dielectric layer 256A in contact with an exemplary first portion of an exemplary third dielectric layer 252A. The exemplary first portion of the fourth dielectric layer 256A is in contact with an exemplary first portion of the second sacrificial via layer 254A. Similarly, the exemplary second portion of the fourth dielectric layer 256B is in contact with an exemplary second portion of the third dielectric layer 252B and an exemplary second portion of the second sacrificial via layer 254B. The exemplary second die 204 includes a fourth metal pad 230 (e.g., a first metal pad 230A, a second metal pad 230B, a third metal pad 230C), and the fourth metal pad 230 is in contact with exemplary second metal vias 230 (e.g., a first second metal via in the second metal vias 230A, a second second metal via in the second metal vias 230B, and a third second metal via in the second metal vias 230C). Similarly, the exemplary second die 204 includes portions of the exemplary third dielectric fill 226 that have been deposited between the second metal vias 248 .

[0046] like Figure 2C As shown in the example in FIG. 1 , a corresponding third metal pad in the exemplary third metal pads 228 contacts a corresponding first metal pad in the exemplary first metal pads 242. In some examples, the first metal pads 242 are formed with exemplary first metal vias 244. In such examples, the first metal pads 242 are referred to as second metal vias or metal vias of pad size. The first metal pads 242 are electrically connected to the exemplary second metal pads 246 of the exemplary second die 204 through the exemplary third metal pads 228 and the exemplary fourth metal pads 230. As shown in FIG. Figure 2C As shown in the example of , the first metal pad 242 is mostly aligned with the exemplary third metal pad 228. The percentage of alignment or overlap between the first metal pad 242 and the third metal pad 228 is at least sixty percent or more (e.g., at least 75%, at least 90%). However, compared with the alignment of the first metal pad 242 and the third metal pad 228, the exemplary third metal pad 228 is significantly more aligned with the exemplary fourth metal pad 230. The percentage of alignment or overlap between the third metal pad 228 and the fourth metal pad 230 is at least sixty percent or more (e.g., at least 75%, at least 90%). The exemplary second metal pad 246 is almost not aligned with the exemplary first metal pad 242. However, the third metal pad 228 and the fourth metal pad 230 correct the offset between the third metal pad 228 and the fourth metal pad 230 (e.g., reduce the effect of the offset). The exemplary first metal pad 242 and the corresponding third metal pad of the third metal pad 228 are misaligned.

[0047] The exemplary fourth third metal pad in third metal pad 228D is offset deeper into exemplary second dielectric filler 224. The first third metal pad in third metal pad 228A is blocked by the exemplary first first metal pad in first metal pad 242A and therefore does not extend deep into exemplary second dielectric filler 224. The exemplary fourth third metal pad in third metal pad 228D extends beyond the lateral sides of first metal interconnect 218. The exemplary fourth third metal pad in third metal pad 228D extends a greater distance away from exemplary second dielectric filler 224 than the other exemplary third metal pads in third metal pads 228A, 228B, and 228C. The exemplary fourth third metal pad in third metal pad 228D is electrically isolated from other metals in second dielectric filler 224. This is due to the manufacturing process of distributing third metal pads 228 at a consistent pitch on the surface of first die 202 and the surface of third die 206. In some examples, the third metal pads in third metal pads 228 are recessed (eg, have a metal notch) and are disposed within the first metal pads in first metal pads 242 (eg, as shown in FIG. 1 ). Fig.11 shown).

[0048] Figure 3 302. The exemplary semiconductor package 200 is shown as being attached to an exemplary wafer 302. The exemplary wafer 302 includes exemplary through-silicon vias 304 and exemplary bumps 306 for attaching the exemplary wafer 302 to an exemplary package substrate 308. The exemplary semiconductor package 200 is hybrid bonded to the exemplary wafer 302. The exemplary through-silicon vias 238 and exemplary bumps 240 of the semiconductor package 200 are used to attach the semiconductor package 200 to the exemplary wafer 302. An exemplary underfill 310 is used to fill the gap between the package substrate 308 (e.g., a printed circuit board) and the exemplary wafer 302.

[0049] Figure 4 An exemplary semiconductor package 200 is shown positioned on a package substrate 308. An exemplary semiconductor is hybrid-bonded directly to the exemplary package substrate 308. Exemplary through-silicon vias 238 and exemplary bumps 240 of the semiconductor package 200 are attached to the exemplary package substrate 308. An exemplary underfill 310 is used to fill the gap between the package substrate 308 (e.g., a printed circuit board) and the exemplary semiconductor package 200.

[0050] Figure 5 Shown is the method used to generate Figure 2A-2C 2. The exemplary first stage 500 includes a body die 502 attached to the exemplary first transistor 232 and the exemplary third transistor 236. Figure 5The example in simplifies the semiconductor package by omitting some structures of the first metal via 244 and the first metal interconnect 218. Figure 5 In the simplification made, the exemplary first metal pad 242 is attached to the exemplary first transistor 232 (because some of the structures of the first metal interconnect 218 have been omitted). The exemplary first metal pad 242 includes a first liner 506. The exemplary body die 502 includes an exemplary metal-free region 504. The exemplary metal-free region 504 divides a portion of the second dielectric fill 224. In some examples, the metal-free region 504 is not drawn to scale.

[0051] Figure 6 The second stage 600 is shown. The exemplary second stage 600 includes adding the exemplary sacrificial via layer 250. The exemplary sacrificial via layer 250 is deposited on top of the exemplary first metal pads 242 and a portion of the second dielectric filler 224. After depositing the exemplary sacrificial via layer 250, the exemplary test pads 602 are placed in contact with the first metal pads of the exemplary first metal pads 242. The exemplary test pads 602 are used to confirm whether the die is functioning correctly. The exemplary test pads 602 include a sacrificial test layer 604. In some examples, a first test pad of the test pads 602 is larger than a corresponding first first metal pad of the first metal pads 242 that is located below the first test pad of the test pads 602. The exemplary test pads 602 are located below the exemplary first metal pads 242.

[0052] Figure 7 An exemplary third stage 700 is shown. After testing a portion of the first metal pad 242 of the body die 502, the test pad 602 and the sacrificial test layer 604 are removed. Removing the test pad 602 generates alignment marks 704 (e.g., first alignment mark 704A and second alignment mark 704B). By removing the test pad 602, the exemplary third stage 700 exposes the sacrificial via layer 250. The alignment mark 704 is a notch or opening where, in conjunction with the exemplary seventh stage 1100, metal is added to the opening to define the third metal pad 228. After removing the test pad 602, the body die 502 is singulated (e.g., cut, diced, separated) at the location of the exemplary metal-free area 504. The first singulated and tested portion of the exemplary body die 502 is now referred to as Figure 2A-2B , and another singulated and tested portion of the exemplary body die 502 is referred to as Figure 2A An exemplary third body semiconductor region 212 in FIG. Figure 2AIn the example of FIG. 2 , the third bulk semiconductor region 212 is located in the horizontal plane of the first bulk semiconductor region 208 , while the exemplary second bulk semiconductor region 210 is located in the vertical plane of the first bulk semiconductor region 208 . Figure 5-Figure 11 In the example of FIG. 1 , the first bulk semiconductor region 208 and the third bulk semiconductor region 212 are the focus. Figure 5-Figure 11 Only two dies will appear in the Figure 5-Figure 11 and Figure 2A For consistency between the present invention and the present invention, reference numerals and labels of “third bulk semiconductor region 212 ” and “third die 206 ” will be used.

[0053] In some examples, the third bulk semiconductor region 212 is a portion that is physically adjacent to the first bulk semiconductor region 208 prior to singulation. In some examples, a testing process reveals that the portion that is physically adjacent to the first bulk semiconductor region 208 is defective, and the exemplary third bulk semiconductor region 212 is a portion that is not physically adjacent to the first bulk semiconductor region 208 prior to singulation. The exemplary first bulk semiconductor region 208 and the exemplary third bulk semiconductor region 212 are positioned apart by a first distance 702.

[0054] Figure 8 An exemplary fourth stage 800 is shown. The exemplary first bulk semiconductor region 208 and the exemplary third bulk semiconductor region 212 are attached to an exemplary fusion bond carrier 804 including a fusion layer 806. The exemplary fusion layer 806 includes a second alignment space 1002. The first bulk semiconductor region 208 and the third bulk semiconductor region 212 are spaced apart by an exemplary first distance 702 when fused to the exemplary fusion bond carrier 804. Fig. 9 Previously, the exemplary first bulk semiconductor region 208 and the exemplary third bulk semiconductor region 212 were polished to a thickness of approximately ten microns. For example, a chemical mechanical planarization (CMP) process may be used to remove some of the excess semiconductor material.

[0055] Fig. 9An exemplary fifth stage 900 is shown. At the exemplary fifth stage 900, a first liner 902 is deposited over the first bulk semiconductor region 208, the spacing between the first bulk semiconductor region 208 and the third bulk semiconductor region 212 being marked by the first distance 702. After depositing the first liner 902, an exemplary first dielectric filler 216 is deposited over the first liner 902. In some examples, the first liner 902 can be formed of an alloy including silicon and nitrogen (SiN) or an alloy including silicon, carbon, and nitrogen (SiCN). However, in some cases, the liner material cannot be formed of an alloy including silicon and oxygen (SiO). Then, an exemplary structural metal surface 214 (e.g., a metal cover, a silicon cover, a silicon substrate, a metal substrate) is attached. The exemplary structural metal surface 214 includes an exemplary second liner 904.

[0056] Fig.10 An exemplary sixth stage 1000 is shown. At the exemplary sixth stage 1000, the exemplary fusion bond carrier 804 and the exemplary fusion bond layer 806 are removed, thereby exposing the exemplary sacrificial via layer 250. Removing the fusion bond carrier 804 and the fusion layer 806 exposes the exemplary alignment space 1002. The exemplary alignment space 1002 is not level with the first metal pad 242.

[0057] Fig.11 An exemplary seventh stage 1100 is shown. At the exemplary seventh stage 1100, exemplary third metal pad 228 is deposited onto first metal pad 242. Figure 2C The exemplary second metal pads 246 in are associated with the exemplary second die 204 and are not shown because the second die 204 is located in the vertical plane of the first die 202. Some of the metal fills forming the third metal pads 228 are aligned with the spaces 1002 (e.g., notches in the first metal pads in the first metal pads 242, openings in the first metal pads in the first metal pads 242, etc.). One of the third metal pads 228 is deposited in the exemplary first dielectric filler 216 (e.g., an oxide filler). Since the other third metal pads 228 are in contact with the surface of the first metal pads 242, the exemplary third metal pads in the third metal pads 228 deposited in the exemplary first dielectric filler 216 are not horizontal with the other third metal pads 228. The third dielectric layer 252 is deposited between the third metal pads in the third metal pads 228. The exemplary third dielectric layer 252 can be the same material as the first dielectric filler 216 and / or the second dielectric filler 224. Third metal pad 228 is planarized and an etch stop layer 1108 is applied.

[0058] exist Fig.11In the example of , an exemplary first width 1102 (e.g., width 1102A) is shown between some of the third metal pads 228 associated with the first bulk semiconductor region 208, and an exemplary first width 1102 (e.g., width 1102B) is shown between some of the third metal pads 228 associated with the exemplary third bulk semiconductor region 212. The exemplary width 1102A is an example of the same as the exemplary width 1102B. The exemplary second width 1104 associated with the exemplary third bulk semiconductor region 212 can be a different amount of space from the exemplary first width 1102. The exemplary third width 1106 associated with the exemplary first bulk semiconductor region 208 can be a different amount of space from the exemplary first width 1102 and the second width 1104. The exemplary first die 202 can be attached to the exemplary second die 204 ( Fig.11 ), wherein the third metal pad 228 and the fourth metal pad 230 ( Fig.11 (not shown) contact.

[0059] exist Fig.11 In the example in FIG. 2 , the horizontal plane defining the first hybrid bonding layer includes the third metal pad 228 and a portion of the dielectric.

[0060] Fig.12 It shows the above combination Figure 5-Figure 11 The described method for manufacturing a semiconductor package (e.g., Figure 2A-2C 200). In some examples, Fig.12 The exemplary method of the present invention is a method of manufacturing an integrated circuit package. Although the exemplary method of manufacturing is referenced Fig.12 The flowchart shown in FIG. 1 is described, but many other methods may be used instead. For example, the order of execution of the blocks may be changed, and / or some of the blocks described may be combined, split, rearranged, omitted, deleted, and / or implemented in any other manner. The exemplary process will use the Figure 2A-2C The associated reference numerals, some of which are in Figure 5-Figure 11 Introduced between.

[0061] The exemplary process 1200 begins at block 1202 by providing a first contact pad on a semiconductor substrate. Figure 5 5. Referring to the terminology and reference numerals of FIG. 5, the first contact pad is the first metal pad 242 placed on the body die 502. The semiconductor substrate may be formed of silicon. The first contact pad may be formed of copper. However, other materials may be used.

[0062] At block 1204, the exemplary process 1200 deposits a dielectric layer on the first contact pad. Figure 6 Referring to the terms and reference numerals of , a sacrificial via layer 250 is deposited on the first metal pad 242. Portions of the sacrificial via layer 250 are to be removed (eg, sacrificed).

[0063] At block 1206, the exemplary process 1200 deposits a test pad on the first dielectric layer. Figure 6 Referring to the terminology and reference numerals of , the test pads 602 are deposited on the exemplary sacrificial via layer 250 .

[0064] At block 1208, the exemplary process 1200 tests the semiconductor die using the test pads. Figure 6 Referring to the terms and reference numerals of FIG. 5 , test pad 602 is used to confirm the electrical connection state of first metal pad 242 constituting body die 502 .

[0065] At block 1210, the exemplary process 1200 removes the test pads to expose the first dielectric layer (eg, sacrificial via layer). Figure 7 Referring to the terms and reference numerals of , the test pads 602 are removed to expose the exemplary sacrificial via layer 250 .

[0066] At block 1212, the exemplary process 1200 dices the semiconductor substrate to define a first semiconductor die. Figure 7 The body die 502 is cut into a plurality of portions, for example, the exemplary first die 202 defined by the exemplary first body semiconductor region 208, the first transistor 232, portions of the second dielectric filler 224, and some of the first metal pads 242, and some of the sacrificial via layers 250. Because the first die 202 and the third die 206 are sequential first and second dies attached adjacent to each other, for the exemplary third body semiconductor region 212, the exemplary third transistor 236, some of the first metal pads 242, portions of the second dielectric filler 224, and some of the sacrificial via layers 250, Fig.12 The flowcharts in will use the term "second die".

[0067] At block 1214, the exemplary process 1200 attaches the first semiconductor die to a carrier wafer. Figure 8 8. Referring to the terminology and reference numerals of EMBODIMENT 2, the first die 202 is attached to an exemplary fusion bond carrier 804.

[0068] At block 1216, the exemplary process 1200 attaches a second semiconductor die to the carrier wafer adjacent to the first semiconductor die. Figure 8 The second die attached to the carrier wafer 802 is Figure 2A FIG. 2 is an exemplary third die 206 in FIG.

[0069] At block 1218, the exemplary process 1200 deposits a dielectric filler to surround the first semiconductor die and the second semiconductor die. Fig. 9 According to the terminology and reference numerals of , the dielectric filler is an exemplary first dielectric filler 216. In other examples, the dielectric filler may be an oxide.

[0070] At block 1220, the exemplary process 1200 attaches a cover plate to the first semiconductor die and the second semiconductor die, wherein the first semiconductor die and the second semiconductor die are located between the carrier wafer and the cover plate. Fig. 9 In terms and reference numerals, the cover is a structural metal surface 214, which may be considered a cover (eg, top) or a base (eg, bottom, carrier) depending on the orientation of the semiconductor package 200. The structural metal surface 214 may be formed of silicon or other similar metals.

[0071] At block 1222, the exemplary process 1200 removes the carrier wafer from the first semiconductor die and the second semiconductor die. Fig.10 1 , the fusion bond carrier 804 is removed from the first die 202 and the third die 206. The exemplary semiconductor package is rotated so that the structured metal surface 214 acts as a carrier wafer prior to the start of block 1224.

[0072] At block 1224, the exemplary process 1200 deposits a first hybrid bond pad layer on the first contact pad. Fig.11 1 , the exemplary process 1200 deposits the exemplary third metal pad 228 onto the exemplary first metal pad 242. In some examples, the first hybrid bonding pad layer includes the third metal pad 228. In other examples, the first hybrid bonding pad layer includes the third metal pad 228 and a third dielectric layer 252 located between the third metal pads 228.

[0073] At block 1226, the exemplary process 1200 bonds the first hybrid bonding layer to a second hybrid bonding layer on a separate wafer using wafer-to-wafer bonding. Figure 2A , the first hybrid bonding layer is a set of third metal pads 228 of both the first die 202 and the third die 206, and both the first die 202 and the third die 206 are bonded to the fourth metal pads 230 of the second die 204 through wafer-to-wafer bonding, wherein the fourth metal pads 230 are the second hybrid bonding layer.

[0074] Fig.13 According to the teachings disclosed herein, it can be included in Figure 1 1 and 13. A top view of wafer 1300 and die 1302 (e.g., any suitable die among the die) in IC package 100 in FIG. 1 . Wafer 1300 may be comprised of semiconductor material and may include one or more die 1302 having IC structures formed on a surface of wafer 1300. Each of die 1302 may be a repeating unit of a semiconductor product including any suitable IC. After fabrication of the semiconductor product is complete, wafer 1300 may undergo a singulation process in which die 1302 are separated from one another to provide discrete “chips” of the semiconductor product. Die 1302 may include one or more transistors (e.g., transistors discussed below). Fig.14 1440), supporting circuitry for routing electrical signals to the transistors, passive components (e.g., signal traces, resistors, capacitors, or inductors), and / or any other IC components. In some examples, wafer 1300 or die 1302 may include memory devices (e.g., random access memory (RAM) devices, such as static RAM (SRAM) devices, magnetic RAM (MRAM) devices, resistive RAM (RRAM) devices, conductive bridge RAM (CBRAM) devices, etc.), logic devices (e.g., AND, OR, NAND, or NOR gates), or any other suitable circuit elements. Multiple of these devices may be combined on a single die 1302. For example, a memory array formed from multiple memory devices may be coupled to a processing device (e.g., Fig.14 The exemplary IC packages 100 disclosed herein may be formed on the same die 1302 as the processing devices 1400 in the die array or other logic units configured to store information in the memory devices or execute instructions stored in the memory array. The exemplary IC packages 100 disclosed herein may be manufactured using die-to-wafer assembly techniques in which some dies are attached to a wafer 1300 including other dies in the die array, and the wafer 1300 is subsequently singulated.

[0075] Fig.14 1 is a cross-sectional side view of an IC device 1400 that may be included in the exemplary IC package 100 (e.g., in any of the dies) constructed according to the teachings disclosed herein. One or more IC devices in the IC device 1400 may be included in one or more dies 1302 ( Fig.13 ). The IC device 1400 may be formed on a substrate 1402 (eg, Fig.13 1300) and may be included in a die (e.g., Fig.131302 in the chip 1300). Substrate 1402 can be a semiconductor substrate composed of a semiconductor material system including, for example, an n-type or p-type material system (or a combination of the two). For example, substrate 1402 can include a crystalline substrate formed using bulk silicon or a silicon-on-insulator (SOI) substructure. In some examples, substrate 1402 can be formed using alternative materials that may or may not be combined with silicon, including but not limited to germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide. Other materials classified as II-VI, III-V, or IV groups can also be used to form substrate 1402. Although some examples of materials that can form substrate 1402 are described herein, any material that can serve as the basis of IC device 1400 can be used. Substrate 1402 can be a singulated chip (for example, Fig.13 1302) or a wafer (e.g., Fig.13 A portion of wafer 1300).

[0076] The IC device 1400 may include one or more device layers 1404 disposed on a substrate 1402. The device layer 1404 may include features of one or more transistors 1440 (e.g., metal oxide semiconductor field effect transistors (MOSFETs)) formed on the substrate 1402. For example, the device layer 1404 may include one or more source and / or drain (S / D) regions 1420, a gate 1422 for controlling the flow of current between the S / D regions 1420 in the transistor 1440, and one or more S / D contacts 1424 for routing electrical signals to / from the S / D regions 1420. The transistor 1440 may include additional features that are not depicted for clarity, such as device isolation regions, gate contacts, etc. The transistor 1440 is not limited to Fig.14 The types and configurations described in the drawings and may include a variety of other types and configurations (e.g., planar transistors, non-planar transistors, or a combination of both). Non-planar transistors may include FinFET transistors (e.g., dual-gate transistors or tri-gate transistors) and all-around gate transistors or all-around gate transistors (e.g., nanoribbon and nanowire transistors).

[0077] Each transistor 1440 may include a gate 1422 formed by at least two layers (i.e., a gate dielectric and a gate electrode). The gate dielectric may include a layer or a stack of layers. One or more layers may include silicon oxide, silicon dioxide, silicon carbide and / or a high-k dielectric material. The high-k dielectric material may include elements such as hafnium, silicon, oxygen, titanium, tantalum, lanthanum, aluminum, zirconium, barium, strontium, yttrium, lead, scandium, niobium and zinc. Examples of high-k materials that can be used in the gate dielectric include, but are not limited to, hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide and lead zinc niobate. In some examples, an annealing process may be performed on the gate dielectric to improve its quality when using a high-k material.

[0078] The gate electrode may be formed on the gate dielectric and may include at least one p-type work function metal or n-type work function metal, depending on whether the transistor 1440 is a p-type metal oxide semiconductor (PMOS) transistor or an n-type metal oxide semiconductor (NMOS) transistor. In some embodiments, the gate electrode may be composed of a stack of two or more metal layers, wherein one or more metal layers are work function metal layers and at least one metal layer is a fill metal layer. Other metal layers, such as barrier layers, may be included for other purposes. For PMOS transistors, metals that may be used for gate electrodes include, but are not limited to, ruthenium, palladium, platinum, cobalt, nickel, and conductive metal oxides (e.g., ruthenium oxide), and any metal discussed below with reference to the NMOS transistor (e.g., for work function regulation). For NMOS transistors, metals that may be used for gate electrodes include, but are not limited to, hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, and carbides of these metals (e.g., hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and aluminum carbide), and any metal discussed above with reference to the PMOS transistor (e.g., for work function regulation).

[0079] In some examples, when viewed from a cross section of transistor 1440 along the source-channel-drain direction, the gate electrode may be composed of a U-shaped structure including a bottom portion substantially parallel to the surface of the substrate and two sidewall portions substantially perpendicular to the top surface of the substrate. In other examples, at least one of the metal layers forming the gate electrode may be only a planar layer substantially parallel to the top surface of the substrate and does not include a sidewall portion substantially perpendicular to the top surface of the substrate. In other examples, the gate electrode may be composed of a combination of a U-shaped structure and a planar non-U-shaped structure. For example, the gate electrode may be composed of one or more U-shaped metal layers formed on top of one or more planar non-U-shaped layers.

[0080] In some examples, a pair of sidewall spacers can be formed on opposite sides of the gate stack to sandwich the gate stack. The sidewall spacers can be formed of materials such as silicon nitride, silicon oxide, silicon carbide, carbon-doped silicon nitride, and silicon oxynitride. Processes for forming sidewall spacers are well known in the art and generally include deposition and etching process steps. In some examples, multiple pairs of spacers can be used; for example, two, three, or four pairs of sidewall spacers can be formed on opposite sides of the gate stack.

[0081] The S / D region 1420 may be formed within the substrate 1402 and adjacent to the gate 1422 of each transistor 1440. For example, the S / D region 1420 may be formed using an implantation / diffusion process or an etching / deposition process. In the former process, dopants such as boron, aluminum, antimony, phosphorus, or arsenic may be ion implanted into the substrate 1402 to form the S / D region 1420. An annealing process may follow the ion implantation process, which activates the dopant and diffuses it further into the substrate 1402. In the latter process, the substrate 1402 may first be etched to form a recess at the location of the S / D region 1420. Then, an epitaxial deposition process may be performed to fill the recess with the material used to make the S / D region 1420. In some embodiments, the S / D region 1420 may be made using a silicon alloy (e.g., silicon germanium or silicon carbide). In some examples, the epitaxially deposited silicon alloy may be in-situ doped with a dopant such as boron, arsenic, or phosphorus. In some examples, one or more alternative semiconductor materials (eg, germanium or III-V materials or alloys) can be used to form S / D region 1420. In other examples, S / D region 1420 can be formed using one or more layers of metals and / or metal alloys.

[0082] The device layer 1404 may be provided with one or more interconnect layers (in Fig.14 1400) to and / or from devices (e.g., transistors 1440) of device layer 1404. For example, conductive features (e.g., gates 1422 and S / D contacts 1424) of device layer 1404 can be electrically coupled to interconnect structures 1428 of interconnect layers 1406-1410. One or more interconnect layers 1406-1410 can form a metallization stack (also referred to as an "ILD stack") 1419 of IC device 1400.

[0083] The interconnect structures 1428 may be arranged within the interconnect layers 1406-1410 to be arranged according to a variety of designs (specifically, the arrangement is not limited to Fig.141428) to route electrical signals. Fig.14 A particular number of interconnect layers 1406 - 1410 are depicted in FIG. 1 , but examples of the present disclosure include IC devices having more or fewer interconnect layers than depicted.

[0084] In some examples, the interconnect structure 1428 may include wires 1428a and / or vias 1428b filled with a conductive material (e.g., metal). The wires 1428a may be arranged to route electrical signals in a direction substantially parallel to a surface of the substrate 1402 on which the device layer 1404 is formed. For example, the wires 1428a may be arranged to route electrical signals in a direction substantially parallel to a surface of the substrate 1402 on which the device layer 1404 is formed. Fig.14 The vias 1428b may be arranged to route electrical signals in a direction that is substantially perpendicular to the surface of the substrate 1402 on which the device layer 1404 is formed. In some examples, the vias 1428b may electrically couple together the lines 1428a of different interconnect layers 1406-1410.

[0085] like Fig.14 As shown, interconnect layers 1406-1410 may include dielectric material 1426 disposed between interconnect structures 1428. In some examples, dielectric material 1426 disposed between interconnect structures 1428 in different ones of interconnect layers 1406-1410 may have different compositions; in other examples, the composition of dielectric material 1426 between different interconnect layers 1406-1410 may be the same.

[0086] A first interconnect layer 1406 (referred to as metal 1 or "M1") can be formed directly on the device layer 1404. In some examples, as shown, the first interconnect layer 1406 can include lines 1428a and / or vias 1428b. The lines 1428a of the first interconnect layer 1406 can be coupled to contacts of the device layer 1404 (e.g., S / D contacts 1424).

[0087] A second interconnect layer 1408 (referred to as metal 2 or "M2") can be formed directly on the first interconnect layer 1406. In some examples, the second interconnect layer 1408 can include vias 1428b to couple lines 1428a of the second interconnect layer 1408 with lines 1428a of the first interconnect layer 1406. Although the lines 1428a and vias 1428b are structurally drawn with lines within each interconnect layer (e.g., within the second interconnect layer 1408) for clarity, in some examples, the lines 1428a and vias 1428b can be continuous in structure and / or in material (e.g., filled simultaneously during a dual damascene process).

[0088] A third interconnect layer 1410 (referred to as metal 3 or "M3") (and additional interconnect layers, as desired) can be formed successively on the second interconnect layer 1408 according to similar techniques and constructions described in connection with the second interconnect layer 1408 or the first interconnect layer 1406. In some examples, interconnect layers "higher up" in the metallization stack 1419 in the IC device 1400 (i.e., further from the device layer 1404) can be thicker.

[0089] IC device 1400 may include solder resist material 1434 (eg, polyimide or similar material) formed on interconnect layers 1406-1410 and one or more conductive contacts 1436. Fig.14 , the conductive contact 1436 is shown as taking the form of a bonding pad. The conductive contact 1436 can be electrically coupled to the interconnect structure 1428 and configured to route electrical signals of the (multiple) transistors 1440 to other external devices. For example, solder joints can be formed on one or more conductive contacts 1436 to mechanically and / or electrically couple a chip including the IC device 1400 to another component (e.g., a circuit board). The IC device 1400 may include additional or alternative structures to route electrical signals from the interconnect layers 1406-1410; for example, the conductive contact 1436 may include other similar features (e.g., pillars) for routing electrical signals to external components.

[0090] Fig.15 1 is a cross-sectional side view of an IC device assembly 1500 that may include an IC package 100 constructed according to the teachings disclosed herein and having any of the exemplary packaging substrates disclosed herein. IC device assembly 1500 includes a plurality of components disposed on a circuit board 1502 (which may be, for example, a motherboard). IC device assembly 1500 includes components disposed on a first side 1540 of circuit board 1502 and an opposing second side 1542 of circuit board 1502; in general, components may be disposed on one or both of side 1540 and side 1542. Any of the IC packages discussed below with reference to IC device assembly 1500 may take the form of a plurality of components disposed on a first side 1540 of circuit board 1502 and a second side 1542 of circuit board 1502. Figure 1 Any exemplary form of IC package 100 in.

[0091] In some examples, circuit board 1502 may be a printed circuit board (PCB) including multiple metal layers separated from each other by layers of dielectric material and interconnected by conductive vias. Any one or more of the metal layers may be formed in a desired circuit pattern to route electrical signals between components coupled to circuit board 1502 (optionally, in conjunction with other metal layers). In other examples, circuit board 1502 may be a non-PCB substrate. In some examples, for example, circuit board 1502 may be Figure 1Circuit board in.

[0092] Fig.15 The IC device assembly 1500 shown in FIG. 1 includes a package structure on an interposer 1536 coupled to a first side 1540 of a circuit board 1502 via a coupling component 1516. The coupling component 1516 can electrically and mechanically couple the package structure on the interposer 1536 to the circuit board 1502 and can include solder balls (e.g., Fig.15 as shown), male and female portions of a socket, adhesives, bottom fill materials, and / or any other suitable electrical and / or mechanical coupling structures.

[0093] The package-on-interposer structure 1536 may include an IC package 1520 coupled to the interposer 1504 via a coupling component 1518. The coupling component 1518 may take any appropriate form for the application, such as those discussed above with reference to the coupling component 1516. Fig.15 1504, but multiple IC packages can be coupled to interposer 1504; indeed, additional interposers can be coupled to interposer 1504. Interposer 1504 can provide an intermediate substrate for bridging circuit board 1502 and IC package 1520. For example, IC package 1520 can be or include a die ( Fig.13 1302), IC devices (e.g., Fig.14 The interposer 1504 may be used to couple the IC package 1520 (e.g., die) to a set of BGA conductive contacts of the coupling component 1516 for coupling to the circuit board 1502. Fig.15 In the example shown in , IC package 1520 and circuit board 1502 are attached to opposite sides of interposer 1504; in other examples, IC package 1520 and circuit board 1502 can be attached to the same side of interposer 1504. In some examples, three or more components can be interconnected by way of interposer 1504.

[0094] The interposer 1504 may be formed of epoxy, glass fiber reinforced epoxy, epoxy with inorganic fillers, ceramic materials, or polymer materials such as polyimide. In some examples, the interposer 1504 may be formed of alternative rigid or flexible materials, which may include the same materials as those used in the semiconductor substrate described above, such as silicon, germanium, and other III-V and IV materials. The interposer 1504 may include metal interconnects 1508 and vias 1510, including but not limited to through silicon vias (TSVs) 1506. The interposer 1504 may also include embedded devices 1514, including both passive devices and active devices. Such devices may include but are not limited to capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, electrostatic discharge (ESD) devices, and memory devices. More complex devices such as radio frequency devices, power amplifiers, power management devices, antennas, arrays, sensors, and micro-electromechanical systems (MEMS) devices may also be formed on the interposer 1504. The package-on-interposer structure 1536 may take the form of any package-on-interposer structure known in the art.

[0095] IC device assembly 1500 may include an IC package 1524 coupled to first side 1540 of circuit board 1502 via coupling component 1522. Coupling component 1522 may take the form of any of the examples discussed above with reference to coupling component 1516, and IC package 1524 may take the form of any of the examples discussed above with reference to IC package 1520.

[0096] Fig.15 The IC device assembly 1500 shown in the figure includes a package-on-package structure 1534 coupled to the second side 1542 of the circuit board 1502 by a coupling component 1528. The package-on-package structure 1534 may include a first IC package 1526 and a second IC package 1532 coupled together by a coupling component 1530, such that the first IC package 1526 is disposed between the circuit board 1502 and the second IC package 1532. The coupling components 1528, 1530 can take the form of any of the examples of the coupling component 1516 discussed above, and the IC packages 1526, 1532 can take the form of any of the examples of the IC package 1520 discussed above. The package-on-package structure 1534 can be constructed according to any package-on-package structure known in the art.

[0097] Fig.16 A device that can include any of the exemplary packaging substrates disclosed herein and constructed according to the teachings disclosed herein Figure 11400, or one or more of the IC packages 1500, 1400, or dies 1302 disclosed herein. Fig.16 1600, but any one or more of these components may be omitted or duplicated to suit the application. In some examples, some or all of the components included in the electrical device 1600 may be attached to one or more motherboards. In some examples, some or all of these components may be fabricated onto a single system-on-chip (SoC) die.

[0098] Additionally, in various examples, the electrical device 1600 may not include Fig.16 , but the electrical device 1600 may include interface circuitry for coupling to one or more of the components. For example, the electrical device 1600 may not include the display device 1606, but may include display device interface circuitry (e.g., connector and driver circuitry) to which the display device 1606 may be coupled. In another set of examples, the electrical device 1600 may not include the audio input device 1624 or the audio output device 1608, but may include audio input or output device interface circuitry (e.g., connector and supporting circuitry) to which the audio input device 1624 or the audio output device 1608 may be coupled.

[0099] The electrical device 1600 may include a processing device 1602 (e.g., one or more processing devices). As used herein, the term "processing device" or "processor" may refer to any device or part of a device that processes electronic data from registers and / or memory to convert the electronic data into other electronic data that can be stored in registers and / or memory. The processing device 1602 may include one or more digital signal processors (DSPs), application specific integrated circuits (ASICs), central processing units (CPUs), graphics processing units (GPUs), cryptographic processors (special processors that execute cryptographic algorithms in hardware), server processors, or any other suitable processing devices. The electrical device 1600 may include a memory 1604, which itself may include one or more memory devices, such as volatile memory (e.g., dynamic random access memory (DRAM)), non-volatile memory (e.g., read-only memory (ROM)), flash memory, solid-state memory, and / or a hard drive. In some examples, the memory 1604 may include a memory that shares a die with the processing device 1602. The memory may be used as cache memory and may include embedded dynamic random access memory (eDRAM) or spin transfer torque magnetic random access memory (STT-MRAM).

[0100] In some examples, the electrical device 1600 may include a communication chip 1612 (e.g., one or more communication chips). For example, the communication chip 1612 may be configured to manage wireless communications for transmitting data to and from the electrical device 1600. The term "wireless" and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communication channels, etc. that may transmit data through a non-solid medium using modulated electromagnetic radiation. The term does not imply that the associated devices do not contain any wires, although in some examples they may not contain wires.

[0101] The communication chip 1612 may implement any of a variety of wireless standards or protocols, including but not limited to Institute of Electrical and Electronics Engineers (IEEE) standards, including Wi-Fi (IEEE 802.11 series), IEEE 802.16 standards (e.g., IEEE 802.16-2005 revision), Long Term Evolution (LTE) project, and any revisions, updates, and / or modifications (e.g., Advanced LTE project, Ultra Mobile Broadband (UMB) project (also known as "3GPP2"), etc.). Broadband wireless access (BWA) networks compatible with IEEE 802.16 are generally referred to as WiMAX networks, which is an acronym for Worldwide Interoperability for Microwave Access and is a certification mark for products that have passed conformance and interoperability testing for the IEEE 802.16 standard. The communication chip 1612 may operate according to a Global System for Mobile Communications (GSM), General Packet Radio Service (GPRS), Universal Mobile Telecommunications System (UMTS), High Speed ​​Packet Access (HSPA), Evolved HSPA (E-HSPA), or LTE network. The communication chip 1612 may operate in accordance with Enhanced Data for GSM Evolution (EDGE), GSM EDGE Radio Access Network (GERAN), Universal Terrestrial Radio Access Network (UTRAN), or Evolved UTRAN (E-UTRAN). The communication chip 1612 may operate in accordance with Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Digital Enhanced Cordless Telecommunications (DECT), Evolution Data Optimized (EV-DO) and its derivatives, and any other wireless protocols designated as 3G, 4G, 5G and higher. In other examples, the communication chip 1612 may operate in accordance with other wireless protocols. The electrical device 1600 may include an antenna 1622 to facilitate wireless communication and / or receive other wireless communications (e.g., AM or FM radio transmissions).

[0102] In some examples, the communication chip 1612 can manage wired communications, such as electrical, optical, or any other suitable communication protocol (e.g., Ethernet). As described above, the communication chip 1612 can include multiple communication chips. For example, the first communication chip 1612 can be dedicated to shorter-range wireless communications, such as Wi-Fi or Bluetooth, and the second communication chip 1612 can be dedicated to longer-range wireless communications, such as global positioning systems (GPS), EDGE, GPRS, CDMA, WiMAX, LTE, EV-DO, or others. In some examples, the first communication chip 1612 can be dedicated to wireless communications, and the second communication chip 1612 can be dedicated to wired communications.

[0103] The electrical device 1600 may include a battery / power circuit system 1614. The battery / power circuit system 1614 may include one or more energy storage devices (e.g., batteries or capacitors) and / or circuit systems for coupling components of the electrical device 1600 to an energy source separate from the electrical device 1600 (e.g., AC line power).

[0104] The electrical device 1600 may include a display device 1606 (or corresponding interface circuitry as discussed above). The display device 1606 may include any visual indicator, such as a heads-up display, a computer monitor, a projector, a touch screen display, a liquid crystal display (LCD), a light emitting diode display, or a flat panel display.

[0105] The electrical device 1600 may include an audio output device 1608 (or corresponding interface circuitry as discussed above). The audio output device 1608 may include any device that generates an audible indicator, such as a speaker, headphones, or earbuds.

[0106] The electronic device 1600 may include an audio input device 1624 (or corresponding interface circuitry as discussed above). The audio input device 1624 may include any device that produces a signal representative of sound, such as a microphone, a microphone array, or a digital musical instrument (e.g., a musical instrument with a musical instrument digital interface (MIDI) output).

[0107] The electrical device 1600 may include a GPS device 1618 (or corresponding interface circuitry as discussed above). The GPS device 1618 may communicate with a satellite-based system and may receive the location of the electrical device 1600, as is known in the art.

[0108] The electrical device 1600 may include any other output devices 1610 (or corresponding interface circuitry as discussed above). Examples of other output devices 1610 may include an audio codec, a video codec, a printer, a wired or wireless transmitter for providing information to other devices, or additional storage devices.

[0109] The electronic device 1600 may include any other input device 1620 (or corresponding interface circuitry as discussed above). Examples of other input devices 1620 may include an accelerometer, a gyroscope, a compass, an image capture device, a keyboard, a cursor control device (e.g., a mouse, a stylus, a touchpad), a barcode reader, a quick response (QR) code reader, any sensor, or a radio frequency identification (RFID) reader.

[0110] The electronic device 1600 can have any desired form factor, such as a handheld or mobile electronic device (e.g., a cell phone, a smart phone, a mobile Internet device, a music player, a tablet computer, a laptop computer, a netbook computer, an ultrabook computer, a personal digital assistant (PDA), an ultra-mobile personal computer, etc.), a desktop electronic device, a server or other networked computing component, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a vehicle control unit, a digital camera, a digital video recorder, or a wearable electronic device. In some examples, the electronic device 1600 can be any other electronic device that processes data.

[0111] "Include" and "comprising" (and all forms and tenses thereof) are used herein as open-ended terms. Thus, whenever a claim adopts any form of "include" or "comprising" (e.g., present tense, progressive tense, etc.) in a preamble or in any type of claim reference, it should be understood that additional elements, items, etc. may be present without exceeding the scope of the corresponding claim or reference. As used herein, when the phrase "at least" is used as a transitional term in, for example, the preamble of a claim, it is open-ended in the same manner as the terms "include" and "comprising" are open-ended. The term "and / or" when used, for example, in a form such as A, B, and / or C, refers to any combination or subset of A, B, C, such as: (1) only A, (2) only B, (3) only C, (4) A and B, (5) A and C, (6) B and C, or (7) A and B and C. As used herein in the context of describing structures, components, items, objects, and / or things, the phrase “at least one of A and B” is intended to refer to embodiments that include any of the following: (1) at least one A, (2) at least one B, or (3) at least one A and at least one B. Similarly, as used herein in the context of describing structures, components, items, objects, and / or things, the phrase “at least one of A or B” is intended to refer to embodiments that include any of the following: (1) at least one A, (2) at least one B, or (3) at least one A and at least one B. As used herein in the context of describing the performance or execution of processes, instructions, actions, activities, and / or steps, the phrase “at least one of A and B” is intended to refer to embodiments that include any of the following: (1) at least one A, (2) at least one B, or (3) at least one A and at least one B. Similarly, as used herein in the context of describing the implementation or execution of a process, instruction, action, activity, and / or step, the phrase "at least one of A or B" is intended to refer to an embodiment that includes any of the following: (1) at least one A, (2) at least one B, or (3) at least one A and at least one B.

[0112] As used herein, singular references (e.g., "one," "first," "second," etc.) do not exclude plural references. As used herein, the term "one" object refers to one or more objects in the object. The terms "one," "one or more," and "at least one" are used interchangeably herein. In addition, although individually enumerated, multiple modules, elements, or actions may be implemented by, for example, the same entity or object. In addition, although a single feature may be included in different examples or claims, it is possible that it may be combined, and being included in different examples or claims does not imply that the combination of features is not feasible and / or advantageous.

[0113] It will be appreciated from the foregoing that exemplary systems, devices, articles of manufacture, and methods have been disclosed as integrated circuit packages with dual hybrid bonded dies. The disclosed systems, devices, articles of manufacture, and methods improve the efficiency of a computing device by increasing the electrical connection between a first metal pad of a first die and a second metal pad of a second die through at least a second hybrid bonding layer between the first metal pad of the first die and the second metal pad of the second die. The increased electrical connection is more efficient and therefore enables the computing device to execute processor cycles faster. The disclosed systems, devices, articles of manufacture, and methods are accordingly directed to one or more improvements in the operation of a machine (e.g., a computer or other electronic and / or mechanical device).

[0114] Disclosed herein are exemplary methods, devices, systems, articles of manufacture, and methods of manufacturing for implementing an integrated circuit package with dual hybrid bonded dies. Further examples and combinations thereof include the following: Example 1 includes an integrated circuit (IC) package, including: a first semiconductor die, the first semiconductor die including first metal vias spaced apart along a first layer of a first dielectric material, the first metal vias connected to corresponding first metal pads of the first semiconductor die, the first semiconductor die including a lateral side; a second semiconductor die, the second semiconductor die including second metal vias spaced apart along a second layer of a second dielectric material, the second metal vias connected to corresponding second metal pads of the second semiconductor die; and a hybrid bonded layer, the hybrid bonded layer including a third dielectric material and third metal vias spaced apart along the third dielectric material, a subset of the third metal vias electrically coupling a first metal pad of the first metal pad to a corresponding second metal pad of the second metal pad, a first of the third metal vias being located outside the lateral side of the first semiconductor die.

[0115] Example 2 includes an IC package according to Example 1, wherein the third metal via in the third metal via has a first lateral dimension, and the first metal via in the first metal via and the second metal via in the second metal via have a second lateral dimension, and the first lateral dimension is greater than the second lateral dimension.

[0116] Example 3 includes the IC package of Example 2, wherein the first metal pad has a third lateral dimension, the first lateral dimension being approximately equal to the first lateral dimension of the third metal via.

[0117] Example 4 includes an IC package according to Example 1, wherein the hybrid bonding layer is a first hybrid bonding layer, and the IC package also includes a second hybrid bonding layer, the second hybrid bonding layer includes a fourth dielectric material and fourth metal vias spaced along the fourth dielectric material, and the fourth metal via in the fourth metal vias electrically couples the third metal via in the third metal vias to the corresponding second metal via in the second metal vias.

[0118] Example 5 includes an IC package according to Example 4, wherein a third metal via in the subset of third metal vias contacts a corresponding first metal pad in the first metal pads, and a fourth metal via in the fourth metal via contacts a corresponding second metal pad in the second metal pads.

[0119] Example 6 includes an IC package according to Example 1, wherein third metal vias in the subset of third metal vias extend a first distance away from the second layer of the second dielectric material, and a first third metal via in the third metal vias extends a second distance away from the second layer of the second dielectric material, the second distance being greater than the first distance.

[0120] Example 7 includes an IC package according to Example 1, wherein the lateral side of the first semiconductor die is a first lateral side, the first semiconductor die includes a second lateral side opposite to the first lateral side, and a second of the third metal vias is located between the first lateral side and the second lateral side, and the second of the third metal vias is electrically isolated from other metals within the first semiconductor die.

[0121] Example 8 includes an IC package according to Example 1, wherein the third metal vias in the subset of third metal vias are a first subset of third metal vias, the IC package also includes a third semiconductor die, the third semiconductor die includes fourth metal vias spaced apart along a fourth layer of a fourth dielectric material, the fourth metal vias are connected to corresponding fourth metal pads of the third semiconductor die, a second subset of the third metal vias electrically couples fourth metal pads in the fourth metal pads to corresponding second metal pads in the second metal pads, a first metal pad in the first metal pads is misaligned with the corresponding third metal via in the first subset of the third metal vias by a first degree, a fourth metal pad in the fourth metal pads is misaligned with the corresponding fourth metal via in the second subset of the fourth metal vias by a second degree, the first degree being different from the second degree.

[0122] Example 9 includes an IC package according to Example 1, wherein a first metal pad among the first metal pads: (a) is misaligned with a corresponding second metal pad among the second metal pads to a first degree, and (b) is misaligned with a corresponding third metal via among the third metal vias to a second degree, the third metal via is misaligned with the corresponding second metal pad among the second metal pads to a third degree, the second degree is less than the first degree, and the third degree is less than the first degree.

[0123] Example 10 includes the IC package of Example 1, wherein the horizontal plane defining the hybrid bonding layer includes a fourth dielectric material different from the third dielectric material, and the third metal via extends through both the third dielectric material and the fourth dielectric material.

[0124] Example 11 includes the IC package of Example 1, wherein a third metal via of the third metal vias is deposited inside a first metal via of the first metal vias.

[0125] Example 12 includes an integrated circuit (IC) comprising: a first semiconductor die, the first semiconductor die including a first pad layer having a first array of first conductive pads, a second pad layer having a second array of second conductive pads, a third pad layer having a third array of third conductive pads, the second pad layer being located between the first pad layer and the third pad layer, a second conductive pad among the second conductive pads being in direct contact with a corresponding first conductive pad among the first conductive pads and a corresponding third conductive pad among the third conductive pads; and a second semiconductor die, the second semiconductor die including a fourth pad layer having a fourth array of fourth conductive pads, the third pad layer being located between the second pad layer and the fourth pad layer, a third conductive pad among the third conductive pads being in direct contact with a corresponding fourth conductive pad among the fourth conductive pads.

[0126] Example 13 includes the IC of Example 12, wherein a first one of the second conductive pads extends beyond a lateral side of the first semiconductor die.

[0127] Example 14 includes the IC of Example 12, wherein the first conductive pad extends through a first dielectric material and the second conductive pad extends through a second dielectric material different from the first dielectric material.

[0128] Example 15 includes the IC of Example 12, wherein a portion of a second one of the third conductive pads extends into a corresponding one of the first conductive pads.

[0129] Example 16 includes an IC according to Example 12, further including a third semiconductor die, the third semiconductor die including a fifth pad layer of a fifth array having a fifth conductive pad, the third semiconductor die being laterally adjacent to the first semiconductor die, the second pad layer being located between: (a) the second semiconductor die and (b) both the first semiconductor die and the second semiconductor die.

[0130] Example 17 includes a method for manufacturing an integrated circuit (IC) package, the method comprising: providing a first contact pad on a semiconductor substrate, the first contact pad for a first semiconductor die; cutting the semiconductor substrate to define the first semiconductor die; attaching the first semiconductor die to a carrier wafer, with the first contact pad facing the carrier wafer; attaching a cover to the first semiconductor die and a second semiconductor die, the first semiconductor die and the second semiconductor die being located between the carrier wafer and the cover; attaching the second semiconductor die to the carrier wafer adjacent to the first semiconductor die; removing the carrier wafer from the first semiconductor die and the second semiconductor die; depositing a first hybrid bonding pad layer on the first contact pad, the first hybrid bonding pad layer including a second contact pad, the second contact pad in the second contact pad being in contact with the first contact pad in the first contact pad; and bonding the first hybrid bonding layer to a second hybrid bonding layer on a separate wafer using wafer-to-wafer bonding.

[0131] Example 18 includes a method according to Example 17, further comprising: depositing a first dielectric layer on the first contact pad; depositing a test pad on the first dielectric layer, the test pad being electrically coupled to a first one of the first contact pads through the first dielectric layer; testing the semiconductor die using the test pad; and removing the test pad to expose the first dielectric layer, removing the test pad removing a portion of the first dielectric layer.

[0132] Example 19 includes the method of Example 18, wherein the test pad is larger than a corresponding first contact pad of the first contact pads located below the test pad.

[0133] Example 20 includes a method according to Example 18, further comprising: depositing a second dielectric layer, the second dielectric layer being different from the first dielectric layer located above the first contact pad; etching an opening in the second dielectric layer to generate a notch; and adding metal to the opening in the second dielectric layer to define a second contact pad.

[0134] Example 21 includes the method of Example 17, further comprising, before attaching the cover, depositing a dielectric filler to surround the first semiconductor die and the second semiconductor die attached to the carrier wafer.

[0135] The following claims are hereby incorporated by reference into the detailed description. Although certain exemplary systems, devices, articles of manufacture, and methods have been disclosed herein, the coverage of this patent is not limited thereto. On the contrary, this patent covers all systems, devices, articles of manufacture, and methods that fully fall within the scope of the claims of this patent.

Claims

1. An integrated circuit (IC) package, comprising: a first semiconductor die comprising first metal vias spaced apart along a first layer of a first dielectric material, the first metal vias connected to respective first metal pads of the first semiconductor die, the first semiconductor die comprising a lateral side; a second semiconductor die comprising second metal vias spaced apart along the second layer of second dielectric material, the second metal vias connected to respective second metal pads of the second semiconductor die; as well as A hybrid bonding layer comprising a third dielectric material and third metal vias spaced apart along the third dielectric material, a subset of the third metal vias electrically coupling a first metal pad of the first metal pads to a corresponding second metal pad of the second metal pads, a first third metal via of the third metal vias being located outside of the lateral side of the first semiconductor die.

2. The IC package according to claim 1, wherein: A third metal via of the third metal vias has a first lateral dimension, and a first metal via of the first metal vias and a second metal via of the second metal vias have a second lateral dimension, the first lateral dimension being greater than the second lateral dimension.

3. The IC package according to claim 2, wherein: The first metal pad has a third lateral dimension that is approximately equal to the first lateral dimension of the third metal via.

4. The IC package according to claim 1, wherein: The hybrid bonding layer is a first hybrid bonding layer, and the IC package also includes a second hybrid bonding layer, the second hybrid bonding layer includes a fourth dielectric material and fourth metal vias spaced along the fourth dielectric material, and the fourth metal vias in the fourth metal vias electrically couple the third metal vias in the third metal vias to the corresponding second metal vias in the second metal vias.

5. The IC package according to claim 4, wherein: A third metal via in the subset of the third metal vias contacts a corresponding first metal pad in the first metal pads, and a fourth metal via in the fourth metal vias contacts a corresponding second metal pad in the second metal pads.

6. The IC package according to any one of claims 1 to 5, wherein: The third metal vias in the subset of the third metal vias extend a first distance away from the second layer of the second dielectric material, and the first of the third metal vias extends a second distance away from the second layer of the second dielectric material, the second distance being greater than the first distance.

7. The IC package according to any one of claims 1 to 5, wherein: The lateral side of the first semiconductor die is a first lateral side, the first semiconductor die includes a second lateral side opposite to the first lateral side, and a second of the third metal vias is located between the first lateral side and the second lateral side, and the second of the third metal vias is electrically isolated from other metals within the first semiconductor die.

8. The IC package according to any one of claims 1 to 5, wherein: The third metal vias in the subset of the third metal vias are a first subset of the third metal vias, the IC package also includes a third semiconductor die, the third semiconductor die includes fourth metal vias spaced apart along a fourth layer of a fourth dielectric material, the fourth metal vias are connected to corresponding fourth metal pads of the third semiconductor die, a second subset of the third metal vias electrically couples fourth metal pads in the fourth metal pads to corresponding second metal pads in the second metal pads, a first metal pad in the first metal pads is misaligned with a corresponding third metal via in the first subset of the third metal vias by a first degree, a fourth metal pad in the fourth metal pads is misaligned with a corresponding fourth metal via in the second subset of the fourth metal vias by a second degree, the first degree being different from the second degree.

9. The IC package according to any one of claims 1 to 5, wherein: A first metal pad among the first metal pads: (a) is misaligned with a corresponding second metal pad among the second metal pads by a first degree, and (b) is misaligned with a corresponding third metal via among the third metal vias by a second degree, and the third metal via is misaligned with a corresponding second metal pad among the second metal pads by a third degree, the second degree is less than the first degree, and the third degree is less than the first degree.

10. The IC package according to any one of claims 1 to 5, wherein: The horizontal plane defining the hybrid bonding layer includes a fourth dielectric material different from the third dielectric material, and the third metal via extends through both the third dielectric material and the fourth dielectric material.

11. The IC package according to any one of claims 1 to 5, wherein: A third metal via of the third metal vias is deposited inside a first metal via of the first metal vias.

12. An integrated circuit (IC), comprising: a first semiconductor die comprising a first pad layer having a first array of first conductive pads; a second pad layer having a second array of second conductive pads; a third pad layer having a third array of third conductive pads, the second pad layer being located between the first pad layer and the third pad layer, a second one of the second conductive pads being in direct contact with a corresponding first one of the first conductive pads and a corresponding third one of the third conductive pads; and A second semiconductor die, the second semiconductor die includes a fourth pad layer, the fourth pad layer has a fourth array of fourth conductive pads, the third pad layer is located between the second pad layer and the fourth pad layer, and a third conductive pad among the third conductive pads is in direct contact with a corresponding fourth conductive pad among the fourth conductive pads.

13. The IC of claim 12, wherein: A first one of the second conductive pads extends beyond a lateral side of the first semiconductor die.

14. The IC of claim 12, wherein: The first conductive pad extends through a first dielectric material, and the second conductive pad extends through a second dielectric material different from the first dielectric material.

15. The IC of claim 12, wherein: A portion of a second one of the third conductive pads extends into a corresponding one of the first conductive pads.

16. The IC of any one of claims 12-15, further comprising a third semiconductor die, the third semiconductor die comprising a fifth pad layer having a fifth array of fifth conductive pads, the third semiconductor die being laterally adjacent to the first semiconductor die, the second pad layer being located between: (a) the second semiconductor die and (b) both the first semiconductor die and the second semiconductor die.

17. A method of manufacturing an integrated circuit (IC) package, the method comprising: providing a first contact pad on a semiconductor substrate, the first contact pad being for a first semiconductor die; cutting the semiconductor substrate to define the first semiconductor die; attaching the first semiconductor die to a carrier wafer with the first contact pads facing the carrier wafer; attaching a cover plate to the first semiconductor die and the second semiconductor die, the first semiconductor die and the second semiconductor die being located between the carrier wafer and the cover plate; attaching a second semiconductor die to the carrier wafer adjacent to the first semiconductor die; removing the carrier wafer from the first semiconductor die and the second semiconductor die; depositing a first hybrid bond pad layer on the first contact pads, the first hybrid bond pad layer comprising second contact pads, a second one of the second contact pads contacting a first one of the first contact pads; and The first hybrid bonding layer is bonded to a second hybrid bonding layer on a separate wafer using wafer-to-wafer bonding.

18. The method according to claim 17, further comprising: depositing a first dielectric layer on the first contact pad; depositing a test pad on the first dielectric layer, the test pad being electrically coupled to a first one of the first contact pads through the first dielectric layer; testing the semiconductor die using the test pad; as well as The test pad is removed to expose the first dielectric layer, wherein the removing of the test pad removes a portion of the first dielectric layer.

19. The method according to claim 18, wherein: The test pad is larger than a corresponding first contact pad among the first contact pads located below the test pad.

20. The method of claim 18, further comprising: depositing a second dielectric layer, the second dielectric layer being different from the first dielectric layer overlying the first contact pad; etching an opening in the second dielectric layer to create a notch; as well as Metal is added into the opening in the second dielectric layer to define the second contact pad.

21. The method according to any one of claims 17 to 20, further comprising: Prior to attaching the cover plate, a dielectric filler is deposited to surround the first semiconductor die and the second semiconductor die attached to the carrier wafer.

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