High-precision single-frequency laser seed injection locking method

Abstract

The invention relates to a high-precision single-frequency laser seed injection locking method, which comprises the following steps of: S1, generating a resonance pulse signal based on an FPGA (Field Programmable Gate Array) unit and piezoelectric ceramics, monitoring the resonance pulse signal acquired by an ADC (Analog to Digital Converter) unit, and recording the time t1 required from the beginning of slope voltage to the occurrence of an error signal; s2, after an error signal is monitored, slowly adjusting a ramp voltage, starting a PID feedback control program based on detection of a peak detection module on an S-shaped waveform center position of a resonant cavity spectral range corresponding to a plurality of resonant pulse signals, and recording time t2; s3, after the error signal is stabilized at the 0-point position of the center of the S-shaped waveform, keeping t3 time, opening a Q switching signal and simultaneously disconnecting PID feedback control, keeping the Q switching signal for t4 time and then closing the Q switching signal, and recording the digital quantity corresponding to the ramp voltage at the moment; and S4, controlling the ramp voltage to drop to 0V, keeping for a period of time, and recording the overall time of the step S4 as t5. The invention has the characteristics of adjustable repetition frequency and extremely high time and frequency stability.

Description

Technical Field

[0001] The invention relates to the field of laser technology, and in particular to a high-precision single-frequency laser seed injection locking method. Background Art

[0002] Improving laser power or energy, compressing pulse width, narrowing line width and improving frequency stability are several important directions for the development of lasers. Pulsed lasers with single-frequency narrow linewidth, high power (large energy) and high stability have important applications in gravitational wave detection, high-resolution spectral analysis, nonlinear optics and lidar remote sensing. In order to achieve stable single-frequency narrow linewidth laser output in high-power or high-energy lasers, people have proposed to inject the single longitudinal mode, narrow linewidth, low-power continuous laser output from a high-resolution laser oscillator (seed laser or master laser) into a high-power laser oscillator (power laser or slave laser), thereby controlling the spectral characteristics, mode phase characteristics and spatial characteristics of the power oscillator through the seed laser. This technology is called seed injection technology. Seed injection technology is the most effective method to achieve Fourier transform limit linewidth and stable single-frequency output in high-peak power Q-switched lasers.

[0003] Common seed injection methods include: setup time minimization method, Pound-Drever-Hall (PDH) method, Ramp-Fire resonance detection method and various improved methods based on Ramp-Fire technology. The minimum time setup method is to adjust the cavity length by comparing the setup time of even pulses and technical pulses to minimize the setup time of the resonant cavity output pulse. When the frequency detuning amount is 0, that is, when a longitudinal mode frequency of the slave laser resonator matches the frequency of the seed light, the setup time of the Q-switched laser pulse is the shortest, and the setup time increases with the increase of the detuning amount.

[0004] The PDH frequency stabilization technology is to lock the frequency of the laser to the Fabry-Perot resonant cavity (FP cavity). The technology first uses an electro-optical crystal to phase modulate the single-frequency output of the laser, and then injects it into the FP cavity. The beat signal of the signal reflected by the FP cavity and the frequency of the laser is detected by optical heterodyne, and the cavity length of the laser is feedback-controlled to lock the frequency of the laser to the resonant frequency of the FP cavity. Since the FP cavity has very high stability and extremely narrow spectrum width, the frequency stabilization using the PDH technology can obtain extremely high frequency stability, but the system structure is relatively complex. The Ramp-fire method is to scan the cavity length of the resonant cavity with a ramp voltage and detect the resonant pulse generated by the interference of the seed laser in the resonant cavity. The position of the interference signal peak corresponds to the position where the resonant cavity of the slave laser matches the seed light frequency. The signal peak is detected by the circuit, and the Q switch is turned on at this time to establish a pulse. Since the Ramp-Fire technology scans the cavity length and resonates the slave laser in each pumping cycle, it can approximately guarantee 100% single-frequency output, and the anti-interference ability is very strong. However, since the initial phase of the interference signal obtained from each scan is not fixed, it will fluctuate randomly due to factors such as mechanical vibration and ambient temperature, causing the position of the resonance peak to fluctuate accordingly. The triggering time of the Q switch and the pulse emission time are relatively unstable, resulting in unstable output single-frequency laser energy. Therefore, it cannot be used in some occasions that have high requirements for laser pulse time stability.

[0005] The subsequent Ramp-Hold-Fire technology applies a ramp voltage to the PZT to scan the length of the slave laser resonant cavity. However, when the peak of the interference signal is detected, the Q switch is not turned on immediately, but the voltage is maintained until a fixed moment to trigger the Q switch to output the laser pulse. This method can improve the time stability of the laser pulse. However, during the voltage holding process, the mechanical ringing effect of the piezoelectric ceramic will cause the resonant cavity length to change. If the holding time is too long, the external environment will also bring additional frequency detuning. These factors will lead to instability in the pulse output frequency.

[0006] The start time of the scanning ramp voltage of the Delay-Ramp-Fire technology is not fixed relative to the pump pulse, but is adjusted according to the pulse emission time of the previous cycle, and fed back to the current pulse to adjust the pressure time to compensate for the fluctuation of the resonant cavity length, so that the time to scan to the resonant peak is relatively fixed, improving the time stability of the laser pulse. However, this method only has a good compensation effect on low-frequency disturbances, and has high requirements for the closed-loop control circuit.

[0007] Based on this, designing a single-frequency laser injection locking method with adjustable repetition frequency, high time stability and extremely high frequency stability is an urgent problem to be solved. Summary of the invention

[0008] In order to solve the technical problems existing in the above-mentioned prior art, the purpose of the present invention is to provide a high-precision single-frequency laser seed injection locking method, which has the characteristics of adjustable repetition frequency, high time stability and extremely high frequency stability.

[0009] To achieve the above-mentioned object of the invention, the present invention provides a high-precision single-frequency laser seed injection locking method, comprising the following steps:

[0010] Step S1, generating a resonant pulse signal based on the FPGA unit and the piezoelectric ceramic, monitoring the resonant pulse signal collected by the ADC unit, and recording the time t1 required from the start of the ramp voltage to the appearance of the error signal;

[0011] Step S2, after the error signal is monitored, the ramp voltage is slowly adjusted, based on the detection of the center position of the S-shaped waveform of the resonant cavity spectrum range corresponding to the multiple resonant pulse signals by the peak detection module, the PID feedback control program is started, and the time t2 is recorded;

[0012] Step S3, after the error signal stabilizes at the center of the S-shaped waveform, it is kept for t3 time, the Q switch signal is turned on and the PID feedback control is disconnected, the Q switch signal is kept for t4 time and then turned off, and the digital value corresponding to the ramp voltage at this time is recorded;

[0013] Step S4, control the ramp voltage to drop to 0V and keep it for a period of time, and record the total time of step S4 as t5.

[0014] According to one aspect of the present invention, it also includes:

[0015] Step S5, repeatedly executing the steps S1 to S4, cyclically generating single-frequency injection-locked laser.

[0016] According to one aspect of the present invention, step S1 specifically includes:

[0017] Step S11, the FPGA chip in the FPGA unit generates a digital ramp signal, and the digital ramp signal is converted into an analog signal by the first DAC chip. At the same time, the digital ramp signal generates a high-voltage analog ramp signal after passing through the first DAC chip and the voltage amplifier to drive the piezoelectric ceramic in the laser cavity to move and scan the laser cavity. When the injected seed laser and the cavity length meet the resonance condition, an electrical pulse signal is generated;

[0018] Step S12: Using the resonant light output mirror, the photodetector, and the resonant pulse signal collected by the ADC unit, monitor the resonant pulse signal collected by the ADC unit, first asynchronously synchronize the collected signal s1(t), and then derive Convert the pulse signal into an error signal and record the time t1 from the start of the ramp voltage to the appearance of the error signal.

[0019] According to one aspect of the present invention, in step S2, based on the detection of the center position of the S-shaped waveform of the resonant cavity spectrum range corresponding to the resonant pulse signal by the peak detection module, the PID feedback control process is started, which specifically includes:

[0020] Step S21, storing in real time the waveforms of the resonant cavity spectrum range corresponding to the multiple resonant pulse signals;

[0021] Step S22, when the peak detection module first determines the center position of the second S-shaped waveform in the resonant cavity spectrum range corresponding to the continuous plurality of resonant pulse signals, the ramp voltage is slightly reduced to correspondingly drive the piezoelectric ceramic to retreat;

[0022] Step S23, during the retreat of the piezoelectric ceramic, the peak detection module of the FPGA detects the center position of the waveform just stored again, and immediately starts the PID feedback control program;

[0023] Step S24, setting the proportional, integral and differential parameters, and loading the feedback control signal on the basis of the ramp voltage.

[0024] According to one aspect of the present invention, in step S3, the FPGA chip in the FPGA unit generates a digital ramp signal, the digital ramp signal is directly input into the acousto-optic Q-switch driver, and the acousto-optic Q-switch driver generates a Q-switch signal, dynamically adjusting the time of t3 so that t1+t2+t3=A, where A is a constant.

[0025] According to one aspect of the present invention, in step S4, the compensation time t5 is dynamically adjusted so that t1+t2+t3+t4+t5=T

[0026] Where T is the pulse period.

[0027] According to one aspect of the present invention, in step S4, the steady-state holding time of the PID in time t3 is automatically calculated so that the time interval of the giant pulses generated in the two preceding and succeeding scanning cycles is the set period.

[0028] According to one aspect of the present invention, the FPGA unit is designed using a five-segment state machine, including:

[0029] State G0 is used to prevent the influence caused by the unstable light output of the system;

[0030] State G1, continuously increase the PZT driving voltage, scan the resonant cavity, and record the scanning step lengths of the two scanning cycles before and after, respectively, value_pre and value. When the peak detection module of the system determines the peak point of the resonant signal, it jumps to state G2;

[0031] In the state G2, the PZT driving voltage is slightly reduced, so that the system re-detects the peak point stored at the last moment, and then starts the PID feedback control system, and after a period of time, jumps to the state G3;

[0032] In the state G3, the step length of the G2 segment of the two scanning cycles before and after is recorded as thr and hold_time. The speed at which the PZT voltage drops is affected by the characteristics of the piezoelectric ceramics used. When it drops to zero, it jumps to the state G4;

[0033] In state G4, the descending step length is the same as the step length of the G0 segment. The corresponding two scanning cycles before and after are value_pre and value respectively. The G4 state holding time needs to compensate for the duration of each state. The control scanning cycle is strictly the set cycle. The G4 segment step lengths of the two scanning cycles before and after are recorded as cntG4 and cntG4_pre.

[0034] According to one aspect of the present invention, the state step lengths in the front and back scanning cycles of the FPGA unit must satisfy:

[0035] CntG0+2value_pre+thr+cntG4_pre=1 / f

[0036] value_pre+cntG4_pre+cntG0+value+hold_time=1 / f.

[0037] Compared with the prior art, the present invention has the following beneficial effects:

[0038] The present invention proposes a high-precision single-frequency laser seed injection locking method, which avoids the frequency jitter and loss of lock problems caused by factors such as the hysteresis and creep effect of piezoelectric ceramics, mechanical vibration and ambient temperature, and has the advantages of adjustable repetition frequency, high time stability and extremely high frequency stability. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention, and for ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0040] Figure 1 A schematic diagram showing a device for implementing a seed injection locking method for a single-frequency pulse laser according to an embodiment of the present invention;

[0041] Figure 2 A flowchart of an injection locking algorithm according to an embodiment of the present invention is schematically shown;

[0042] Figure 3 Schematic representation of a resonance signal (left) and an error signal (right) according to an embodiment of the present invention;

[0043] Figure 4 Schematically showing the injection locking algorithm flow according to an embodiment of the present invention;

[0044] Figure 5 A schematic diagram showing a state transition simulation diagram of an injection locking system according to an embodiment of the present invention;

[0045] Figure 6 A schematic diagram showing a piezoelectric ceramic driving voltage signal simulation diagram according to an embodiment of the present invention;

[0046] Figure 7 The figure schematically shows a flow chart of a high-precision single-frequency laser seed injection locking method according to an embodiment of the present invention. DETAILED DESCRIPTION

[0047] The description of the embodiments of this specification should be combined with the corresponding drawings, which should be considered as part of the complete specification. In the drawings, the shape or thickness of the embodiments may be enlarged and indicated for simplification or convenience. Furthermore, the parts of each structure in the drawings will be described separately. It is worth noting that the elements not shown in the drawings or not described in words are in a form known to ordinary technicians in the relevant technical field.

[0048] The description of the embodiments herein and any reference to directions and orientations are only for the convenience of description and are not to be construed as any limitation on the scope of protection of the present invention. The following description of the preferred embodiments may involve combinations of features, which may exist independently or in combination, and the present invention is not particularly limited to the preferred embodiments. The scope of the present invention is defined by the claims.

[0049] like Figures 1 to 7 As shown, a high-precision single-frequency laser seed injection locking method of the present invention comprises the following steps:

[0050] Step S1, generating a resonant pulse signal based on the FPGA unit and the piezoelectric ceramic, monitoring the resonant pulse signal collected by the ADC unit, and recording the time t1 required from the start of the ramp voltage to the appearance of the error signal;

[0051] Step S2, after the error signal is monitored, the ramp voltage is slowly adjusted, based on the detection of the center position of the S-shaped waveform of the resonant cavity spectrum range corresponding to the multiple resonant pulse signals by the peak detection module, the PID feedback control program is started, and the time t2 is recorded;

[0052] Step S3, after the error signal stabilizes at the center of the S-shaped waveform, it is kept for t3 time, the Q switch signal is turned on and the PID feedback control is disconnected, the Q switch signal is kept for t4 time and then turned off, and the digital value corresponding to the ramp voltage at this time is recorded;

[0053] Step S4, control the ramp voltage to drop to 0V and keep it for a period of time, and record the total time of step S4 as t5.

[0054] In this embodiment, by improving the single-frequency laser injection locking technology of Ramp-Fire, the frequency jitter and unlocking problems caused by factors such as the mechanical ringing effect of piezoelectric ceramics, mechanical vibration and ambient temperature are avoided. At the same time, by strictly controlling the opening time, reducing the time error of the Q switch and the jitter of the energy output, the high timing stability of the laser pulse can be guaranteed, and it has the advantages of adjustable repetition frequency and extremely high frequency stability.

[0055] The device diagram for realizing the seed injection locking method of single-frequency pulse laser is shown in FIG. Figure 1 shown.

[0056] In one embodiment of the present invention, preferably, it further comprises:

[0057] Step S5, repeatedly executing the steps S1 to S4, cyclically generating single-frequency injection-locked laser, ensuring high repeatability of pulse generation time, and PID locking ensuring high frequency stability of each pulse generation.

[0058] like Figure 4 As shown, in the first step, FPGA generates a rising ramp signal (scanning laser collects resonance signal and converts it into error signal at the same time); in the second step, when the peak detection module determines the resonance signal peak twice, the PID locking program is started; in the third step, after the error signal is stably maintained at the S-shaped center 0 position for a period of time, the Q switch signal is turned on and the PID locking is disconnected; in the fourth step, FPGA controls the ramp voltage to drop to the voltage OV and maintain it for a period of time; after completing the fourth step, return to the first step, which is step S5.

[0059] In one embodiment of the present invention, preferably, the step S1 specifically includes:

[0060] Step S11, the FPGA chip in the FPGA unit generates a digital ramp signal, and the digital ramp signal is converted into an analog signal by the first DAC chip. At the same time, the digital ramp signal generates a high-voltage analog ramp signal after passing through the first DAC chip and the voltage amplifier to drive the piezoelectric ceramic in the laser cavity to move and scan the laser cavity. When the injected seed laser and the cavity length meet the resonance condition, an electrical pulse signal is generated;

[0061] Step S12: Using the resonant light output mirror, the photodetector, and the resonant pulse signal collected by the ADC unit, monitor the resonant pulse signal collected by the ADC unit, first asynchronously synchronize the collected signal s1(t), and then derive Convert the pulse signal into an error signal and record the time t1 from the start of the ramp voltage to the appearance of the error signal.

[0062] like Figure 2 As shown, compared with the resonant pulse signal, the resonant error signal obtained by differentiation amplifies the signal characteristics, is easy to judge, and facilitates the subsequent cavity length locking.

[0063] Figure 2 In the figure, Laserswitchsignal represents the optical switch signal; Sawtoothscanningsignal represents the sawtooth scanning signal; Resonant signal represents the resonance signal; Resonanterror signal represents the resonance error signal; PID triggersignal PID represents the trigger signal; Delaytrigger signal represents the PZT retreat trigger signal; Holdtrigger signal represents the PZT hold trigger signal; Q-Switchtrigger signal represents the Q switch trigger signal.

[0064] In one embodiment of the present invention, preferably, in step S2, based on the detection of the center position of the S-shaped waveform of the resonant cavity spectrum range corresponding to the resonant pulse signal by the peak detection module, the PID feedback control process is started, which specifically includes:

[0065] Step S21, real-time storage of waveforms of the resonant cavity spectral range corresponding to multiple resonant pulse signals, specifically: performing slope differential derivation on the second resonant signal converted into an analog signal by the second DAC chip, converting the resonant pulse signal into a resonant error signal, and storing the error signal value sampled in real time in the FPGA, the second resonant signal is a detection signal characterizing light intensity;

[0066] Step S22: monitoring Figure 3 The signal shown in the figure is used, and the ramp voltage is slowly adjusted. When the peak detection module first determines the center position of the second S-shaped waveform in the resonant cavity spectrum range corresponding to the continuous multiple resonant pulse signals, the ramp voltage is slightly reduced to drive the piezoelectric ceramic backward.

[0067] Step S23, during the retreat of the piezoelectric ceramic, the peak detection module of the FPGA detects the center position of the waveform just stored again, and immediately starts the PID feedback control program;

[0068] Step S24, setting the proportional, integral and differential parameters, and loading the feedback control signal on the basis of the ramp voltage.

[0069] In this embodiment, when the system determines that the value of the resonance error signal is zero, and the values ​​of several resonance error signals input continuously thereafter gradually decrease, it is deemed that the resonance error signal zero value point (corresponding to the resonance signal peak value) is determined, and the FPGA stores the current zero value point position. When the system determines that it is effective, due to the influence of the determination mechanism and the system response time, the corresponding resonance signal has exceeded the maximum value at this time, so the PZT drive voltage is slightly reduced, corresponding to the spectrum range of the previous determination. At this time, the system will detect the zero value point position of the resonance error signal stored in the FPGA again, and then start the PID feedback control system and set the feedback parameters. The PID feedback control system feeds back the calculation results to the PZT in real time, and the length of the resonance cavity changes slightly with the PZT, thereby locking the resonance signal to the error signal zero point (corresponding to the resonance signal peak value).

[0070] In one embodiment of the present invention, preferably, in the step S3, the FPGA chip in the FPGA unit generates a digital ramp signal, the digital ramp signal is directly input into the acousto-optic Q-switch driver, and the acousto-optic Q-switch driver generates a Q-switch signal, and dynamically adjusts the time of t3 so that t1+t2+t3=A, where A is a constant.

[0071] After the resonant error signal stabilizes near the zero point, the system automatically calculates the time required for each previous stage, dynamically adjusts the opening time of the Q switch, and strictly ensures that the time interval between the two giant pulses is fixed, so that the generated single-frequency pulse laser has extremely high time repeatability.

[0072] According to one aspect of the present invention, in step S4, in order to achieve pulse repetition frequency stability, the compensation time t5 is dynamically adjusted so that t1+t2+t3+t4+t5=T (T is the pulse period). At the same time, the system automatically calculates the steady-state holding time of the PID in the t3 time to ensure that the time interval of the giant pulses generated by the two scanning cycles before and after is the set period.

[0073] In one embodiment of the present invention, preferably, in step S4, the steady-state holding time of the PID in time t3 is automatically calculated so that the time interval of the giant pulses generated in the two preceding and succeeding scanning cycles is the set period.

[0074] like Figure 5 , Figure 6 As shown, in one embodiment of the present invention, preferably, a five-segment state machine is used to design the FPGA unit, including:

[0075] State G0 is used to prevent the influence caused by the unstable light output of the system;

[0076] State G1, continuously increase the PZT driving voltage, scan the resonant cavity, and record the scanning step lengths of the two scanning cycles before and after, respectively, value_pre and value. When the peak detection module of the system determines the peak point of the resonant signal, it jumps to state G2;

[0077] In the state G2, the PZT driving voltage is slightly reduced, so that the system re-detects the peak point stored at the last moment, and then starts the PID feedback control system, and after a period of time, jumps to the state G3;

[0078] In the state G3, the step length of the G2 segment of the two scanning cycles before and after is recorded as thr and hold_time. The speed at which the PZT voltage drops is affected by the characteristics of the piezoelectric ceramics used. When it drops to zero, it jumps to the state G4;

[0079] In state G4, the descending step length is the same as the step length of the G0 segment. The corresponding two scanning cycles before and after are value_pre and value respectively. The G4 state holding time needs to compensate for the duration of each state. The control scanning cycle is strictly the set cycle. The G4 segment step lengths of the two scanning cycles before and after are recorded as cntG4 and cntG4_pre.

[0080] In one embodiment of the present invention, preferably, each state step length in the front and back scanning cycles of the FPGA unit needs to satisfy:

[0081] cntG0+2value_pre+thr+cntG4_pre=1 / f

[0082] value_pre+cntG4_pre+cntG0+value+hold_time=1 / f.

[0083] The invention discloses a high-precision single-frequency laser seed injection locking method, which comprises the following steps: step S1, generating a resonant pulse signal based on an FPGA unit and a piezoelectric ceramic, monitoring the resonant pulse signal collected by an ADC unit, and recording the time t1 required from the start of the ramp voltage to the appearance of an error signal; step S2, after the error signal is monitored, slowly adjusting the ramp voltage, detecting the center position of an S-shaped waveform of a resonant cavity spectrum range corresponding to a plurality of resonant pulse signals by a peak detection module, starting a PID feedback control program, and recording the time t2; step S3, after the error signal is stabilized at the center 0 point position of the S-shaped waveform, maintaining the time t3, turning on the Q switch signal and disconnecting the PID feedback control at the same time, the Q switch signal is closed after being maintained for t4 time, and recording the digital quantity corresponding to the ramp voltage at this time; step S4, controlling the ramp voltage to drop to 0V, maintaining it for a period of time, and recording the overall time of step S4 as t5; the frequency jitter and unlocking problems caused by factors such as the hysteresis and creeping effect of the piezoelectric ceramic, mechanical vibration and ambient temperature are avoided, and the method has the advantages of adjustable repetition frequency, high time stability and extremely high frequency stability.

[0084] It should be noted that, in this article, the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, article or terminal device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or terminal device. In the absence of further restrictions, the elements defined by the sentence "comprises a ..." do not exclude the existence of other identical elements in the process, method, article or terminal device including the elements.

[0085] Finally, it should be noted that the above is a preferred embodiment of the present invention. It should be pointed out that although the preferred embodiment of the present invention has been described, for those skilled in the art, once the basic creative concept of the present invention is known, several improvements and modifications can be made without departing from the principles of the present invention, and these improvements and modifications should also be regarded as the protection scope of the present invention. Therefore, the attached claims are intended to be interpreted as including the preferred embodiment and all changes and modifications that fall within the scope of the embodiments of the present invention.

Claims

1. A high-precision single-frequency laser seed injection locking method, characterized in that: The following steps are involved: Step S1, generating a resonant pulse signal based on the FPGA unit and the piezoelectric ceramic, monitoring the resonant pulse signal collected by the ADC unit, and recording the time t1 required from the start of the ramp voltage to the appearance of the error signal; Step S2, after the error signal is monitored, the ramp voltage is slowly adjusted, based on the detection of the center position of the S-shaped waveform of the resonant cavity spectrum range corresponding to the multiple resonant pulse signals by the peak detection module, the PID feedback control program is started, and the time t2 is recorded; Step S3, after the error signal stabilizes at the center of the S-shaped waveform, it is kept for t3 time, the Q switch signal is turned on and the PID feedback control is disconnected, the Q switch signal is kept for t4 time and then turned off, and the digital value corresponding to the ramp voltage at this time is recorded; Step S4, control the ramp voltage to drop to 0V and keep it for a period of time, and record the total time of step S4 as t5.

2. The high-precision single-frequency laser seed injection locking method according to claim 1, characterized in that: Also includes: Step S5, repeatedly executing the steps S1 to S4, cyclically generating single-frequency injection-locked laser.

3. The high-precision single-frequency laser seed injection locking method according to claim 2, characterized in that: The step S1 specifically includes: Step S11, the FPGA chip in the FPGA unit generates a digital ramp signal, and the digital ramp signal is converted into an analog signal by the first DAC chip. At the same time, the digital ramp signal generates a high-voltage analog ramp signal after passing through the first DAC chip and the voltage amplifier to drive the piezoelectric ceramic in the laser cavity to move and scan the laser cavity. When the injected seed laser and the cavity length meet the resonance condition, an electrical pulse signal is generated; Step S12: Using the resonant light output mirror, the photodetector, and the resonant pulse signal collected by the ADC unit, monitor the resonant pulse signal collected by the ADC unit, first asynchronously synchronize the collected signal s1(t), and then derive Convert the pulse signal into an error signal and record the time t1 from the start of the ramp voltage to the appearance of the error signal.

4. The high-precision single-frequency laser seed injection locking method according to claim 3, characterized in that: In step S2, based on the detection of the center position of the S-shaped waveform of the resonant cavity spectrum range corresponding to the resonant pulse signal by the peak detection module, the PID feedback control process is started, which specifically includes: Step S21, storing in real time the waveforms of the resonant cavity spectrum range corresponding to the multiple resonant pulse signals; Step S22, when the peak detection module first determines the center position of the second S-shaped waveform in the resonant cavity spectrum range corresponding to the continuous plurality of resonant pulse signals, the ramp voltage is slightly reduced to correspondingly drive the piezoelectric ceramic to retreat; Step S23, during the retreat of the piezoelectric ceramic, the peak detection module of the FPGA detects the center position of the waveform just stored again, and immediately starts the PID feedback control program; Step S24, setting the proportional, integral and differential parameters, and loading the feedback control signal on the basis of the ramp voltage.

5. The high-precision single-frequency laser seed injection locking method according to claim 1, characterized in that: In step S3, the FPGA chip in the FPGA unit generates a digital ramp signal, which is directly input into the acousto-optic Q-switch driver, and the acousto-optic Q-switch driver generates a Q-switch signal, and dynamically adjusts the time of t3 so that t1+t2+t3=A, where A is a constant.

6. The high-precision single-frequency laser seed injection locking method according to claim 5, characterized in that: In the step S4, the compensation time t5 is dynamically adjusted so that t1+t2+t3+t4+t5=T, wherein T is the pulse period.

7. The high-precision single-frequency laser seed injection locking method according to claim 4, characterized in that: In step S4, the steady-state holding time of the PID in time t3 is automatically calculated so that the time interval of the giant pulses generated in the two preceding and succeeding scanning cycles is the set period.

8. The high-precision single-frequency laser seed injection locking method according to claim 1, characterized in that: The FPGA unit is designed using a five-stage state machine, including: State G0 is used to prevent the influence caused by the unstable light output of the system; State G1, continuously increase the PZT driving voltage, scan the resonant cavity, and record the scanning step lengths of the two scanning cycles before and after, respectively, value_pre and value. When the peak detection module of the system determines the peak point of the resonant signal, it jumps to state G2; In the state G2, the PZT driving voltage is slightly reduced, so that the system re-detects the peak point stored at the last moment, and then starts the PID feedback control system, and after a period of time, jumps to the state G3; In the state G3, the step length of the G2 segment of the two scanning cycles before and after is recorded as thr and hold_time. The speed at which the PZT voltage drops is affected by the characteristics of the piezoelectric ceramics used. When it drops to zero, it jumps to the state G4; In state G4, the descending step length is the same as the step length of the G0 segment. The corresponding two scanning cycles before and after are value_pre and value respectively. The G4 state holding time needs to compensate for the duration of each state. The control scanning cycle is strictly the set cycle. The G4 segment step lengths of the two scanning cycles before and after are recorded as cntG4 and cntG4_pre.

9. The high-precision single-frequency laser seed injection locking method according to claim 8, characterized in that: The state step lengths of the FPGA unit in the forward and backward scanning cycles must satisfy: CntG0+2value_pre+thr+cntG4_pre=1 / f value_pre+cntG4_pre+cntG0+value+hold_time=1 / f.

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