Gate drive circuit, motor drive device using same, and electronic apparatus

Abstract

The invention provides a gate drive circuit which suppresses through current and transient caused by reverse recovery current of a freewheel diode. The first current source (CS1) is configured so as to generate a first current (Ix) that can be switched between a first current amount (Ia) and a second current amount (Ib) that is less than the first current amount (Ia). The first current mirror circuit (CM1) has an input node connected to a first current source (CS1), and is configured so as to turn back a first current (Ix) and supply the first current (Ix) to a gate of a power transistor (MH). The on-fixed switch (SW2) is connected between the gate of the power transistor (MH) and a high-level line (412) that generates a high voltage (VH) corresponding to the high level of the gate voltage of the power transistor (MH). The control circuit (210) is configured so as to control the conduction of the fixed switch (SW2) and the first current source (CS1).

Description

Technical Field

[0001] The present disclosure relates to a gate drive circuit. Background Art

[0002] In motor drive circuits, DC / DC converters, power conversion devices, and the like, a half-bridge circuit, an H-bridge circuit, or a three-phase bridge circuit (hereinafter collectively referred to as a bridge circuit) using power transistors is often used.

[0003] Figure 1 1 is a circuit diagram of a bridge circuit 10. The bridge circuit 10 includes an upper arm 12 and a lower arm 14 which are connected in series between a power supply terminal and a ground terminal. The upper arm 12 includes a high-side transistor MH and a freewheeling diode Di connected in parallel. The lower arm 14 includes a low-side transistor ML and a freewheeling diode Di connected in parallel. An inductor (coil) L1 as a load is connected to the output terminal of the bridge circuit 10.

[0004] The bridge circuit 10 can be in a state where both the high-side transistor MH and the low-side transistor ML are turned off (high impedance state). The high-side transistor MH is on and the low-side transistor ML is off (high output state) The high-side transistor MH is off and the low-side transistor ML is on. (Low output state). About each state There are two types of currents I discharged from the bridge circuit 10. OUT (flowing to the right in the figure) and the bridge circuit 10 absorbs the current I OUT The current sinking state (flowing to the left in the figure).

[0005] [Prior art literature]

[0006] [Patent Document]

[0007] Patent Document 1: Japanese Patent Application Publication No. 2018-82575 Summary of the invention

[0008] The inventors Figure 1 The following issues were identified as a result of research on bridge circuits.

[0009] Consider switching from a high impedance state in the current sourcing state To high output state In the state In the output current I OUT The current is supplied to the load via the flyback diode Di of the lower arm 14 (current source). The output voltage V OUT -V F . V FIt is the forward voltage of the freewheeling diode Di.

[0010] In Status In the example, the output current I of the bridge circuit 10 is OUT Flows in the high-side transistor MH. In addition, in the flyback diode Di of the lower arm 14 on the opposite side, the reverse recovery current I rc Flows from the cathode to the anode. Therefore, in the high-side transistor MH, the output current I OUT and reverse recovery current I rc This state is equivalent to the case where the through current flows. If the through current flows, the output voltage V of the bridge circuit 10 OUT Becoming unstable can produce transients, which are undesirable because they can be the cause of unwanted emissions.

[0011] The present disclosure has been made in view of the above problems, and one exemplary object of one embodiment thereof is to provide a gate drive circuit capable of suppressing a through current and a transient caused by a reverse recovery current of a freewheeling diode on the opposite side.

[0012] One embodiment of the present disclosure relates to a gate drive circuit that drives an N-type power transistor that constitutes a switch circuit. The gate drive circuit includes: an on-circuit configured to pull current to the gate of the power transistor; an off-circuit configured to sink current from the gate of the power transistor; and a control circuit that controls the on-circuit and the off-circuit. The on-circuit includes: a first current source configured to generate a first current that can be switched between a first current amount and a second current amount that is less than the first current amount; a first current mirror circuit having an input node connected to the first current source and configured to fold back the first current and supply it to the gate of the power transistor; and an on-fixed switch connected between the gate of the power transistor and a high-level line that generates a high voltage equivalent to the high level of the gate voltage of the power transistor. The control circuit is configured to control the conduction fixed switch and the first current source. The control circuit is configured to: in response to an indication that the power transistor becomes conductive, (i) during a first period, set the first current to a first current amount and turn off the conduction fixed switch; (ii) during a second period, set the first current to a second current amount and turn off the conduction fixed switch; and (iii) during a third period, turn on the conduction fixed switch.

[0013] In addition, any combination of the above-described constituent elements and any substitution of constituent elements and expressions in methods, apparatuses, systems, and the like of the present disclosure may also be additional modes of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 It is the circuit diagram of a bridge circuit.

[0015] Figure 2 1 is a circuit diagram of a switch circuit according to an embodiment.

[0016] Figure 3 is a circuit diagram of a gate drive circuit according to an embodiment.

[0017] Figure 4 yes Figure 3 The operation waveform of the gate drive circuit.

[0018] Figure 5 This is a circuit diagram of a drive circuit including a gate drive circuit.

[0019] Figure 6 It is a circuit diagram showing a configuration example of a conduction circuit.

[0020] Figure 7 is the circuit diagram of the driving circuit.

[0021] Figure 8 1 is an operation waveform diagram of the driving circuit of sequence variation 1.

[0022] Fig. 9 This is an operation waveform diagram of the driving circuit of sequence variation 2.

[0023] Fig.10 This is a circuit diagram of a motor drive device including a switching circuit according to an embodiment. DETAILED DESCRIPTION

[0024] (Overview of Embodiments)

[0025] This is a summary of several exemplary embodiments of the present disclosure. This summary serves as a prelude to the detailed description that will be described later. It is intended to provide a basic understanding of the embodiments and simplifies several concepts of one or more embodiments. It does not limit the breadth of the invention or disclosure. For convenience, "one embodiment" is sometimes used as a term to indicate one embodiment (example, variation) or multiple embodiments (example, variation) disclosed in this specification.

[0026] This summary is not a comprehensive summary of all conceivable embodiments, nor is it intended to identify the important elements of all embodiments or to delineate the scope of some or all embodiments. Its only purpose is to serve as a prelude to a more detailed description that will be provided later, and to provide several concepts of one or more embodiments in a simplified form.

[0027] A gate drive circuit according to one embodiment drives an N-type power transistor constituting a switch circuit. The gate drive circuit includes: an on-circuit configured to pull current to the gate of the power transistor; an off-circuit configured to sink current from the gate of the power transistor; and a control circuit that controls the on-circuit and the off-circuit. The on-circuit includes: a first current source configured to generate a first current that can be switched between a first current amount and a second current amount that is less than the first current amount; a first current mirror circuit having an input node connected to the first current source and configured to fold back the first current and supply it to the gate of the power transistor; and an on-fixed switch connected between the gate of the power transistor and a high-level line that generates a high voltage equivalent to the high level of the gate voltage of the power transistor. The control circuit is configured to control the conduction fixed switch and the first current source. The control circuit is configured to: in response to an indication that the power transistor becomes conductive, (i) during a first period, the first current is set to a first current amount and the conduction fixed switch is turned off; (ii) during a second period, the first current is set to a second current amount and the conduction fixed switch is turned off; and (iii) during a third period, the conduction fixed switch is turned on.

[0028] According to this method, before the power transistor is turned on, a driving current of a first current amount is supplied to the gate of the power transistor to increase the gate voltage. Then, after the power transistor is turned on and the reverse recovery current can flow in the freewheeling diode of the opposite arm, the driving current supplied to the gate of the power transistor is reduced during the second period, and the power transistor is slowly turned on while keeping the on-resistance of the power transistor relatively large. Thus, the through current or transient caused by the reverse recovery current of the freewheeling diode of the opposite arm can be suppressed. Then, in the third period when the possibility of reverse recovery current flowing is low, the on-time of the power transistor can be shortened by increasing the current amount supplied to the gate compared to the second period, and the power consumption can be reduced. Furthermore, in both the first period and the second period, the first current mirror circuit operates to switch the amount of input current of the first current mirror circuit, so when switching to the second period, the current supplied to the gate changes slowly. Thus, the power consumption can be further reduced.

[0029] In one embodiment, the current supplied to the gate of the power transistor in the third period may be greater than the current supplied to the gate of the power transistor in the first period and the second period. After the influence of the reverse recovery characteristics of the freewheeling diode of the opposite arm is reduced, the on-resistance of the power transistor can be reduced in a short time by increasing the current supplied to the gate of the power transistor, thereby improving the efficiency of the bridge circuit.

[0030] In one embodiment, the on-state fixed switch may include a plurality of transistors arranged in a plurality of parallel paths, and the number of transistors in operation may be variable. The impedance of the on-state fixed switch may be adjusted according to the number of transistors in operation.

[0031] In one embodiment, the control circuit may turn on some of the plurality of transistors in the first period. This can increase the rising speed of the gate voltage of the power transistor in the first period and shorten the on time.

[0032] In one embodiment, the control circuit may turn on all of the plurality of transistors in a fourth period following the third period. In this way, the power transistor can be fixed in an on state. The switch for fixing the power transistor in an on state may also serve as a turn-on circuit.

[0033] In one embodiment, the control circuit may further include a first enable switch connected between the output node of the first current mirror circuit and the gate of the power transistor. The first current mirror circuit can be enabled or disabled according to the state of the first enable switch, and power consumption can be reduced by setting the first current mirror circuit to a disabled state.

[0034] In one embodiment, the control circuit may turn on the first enable switch in the first period and the second period, and turn off the first enable switch in a fourth period following the third period.

[0035] In one embodiment, the control circuit may turn on the first enable switch in the third period. When the second period is shifted to the third period, since the first current mirror circuit continues to operate, discontinuity of the current generated by the current mirror circuit can be suppressed.

[0036] In one embodiment, the control circuit may turn off the first enable switch during the third period.

[0037] In one embodiment, the control circuit may turn on the fixed-conduction switch in a fourth period following the third period.

[0038] In one embodiment, the first current mirror circuit may further include a second output node. The cutoff circuit may also include: a second current mirror circuit including an input node and an output node connected to the second output node of the first current mirror circuit; a second enable switch connected between the output node of the second current mirror circuit and the gate of the power transistor; and a cutoff fixed switch connected between the gate of the power transistor and a low-level line generating a low voltage equivalent to the low level of the gate voltage of the power transistor.

[0039] In one embodiment, the first current source may also include: an output node; a first constant current circuit connected to the output node; a first switch and a second constant current circuit connected in series between the output node and ground; and a second switch and a third constant current circuit connected in series between the output of the second constant current circuit and ground. Since the current generated by the first constant current circuit is always supplied to the first current mirror circuit, the operating point of the first current mirror circuit when the first enable switch is off can be maintained near the operating point in the operation when the first enable switch is on. Thus, when the first enable switch is switched from off to on, the first current mirror circuit can quickly start to operate.

[0040] In one embodiment, the gate drive circuit may also include a first sensor that compares the gate-source voltage of the power transistor with the first threshold voltage. The control circuit may also shift to the second period in response to the output change of the first sensor during the first period. By monitoring the gate-source voltage of the power transistor, the magnitude of the drive current can be changed in conjunction with the transition of the power transistor from the off state to the on state. The first threshold voltage may be equal to the gate threshold of the MOSFET, may be higher than the threshold, or may be lower than the threshold.

[0041] In one embodiment, the first sensor may be used together with a high-side cutoff sensor for detecting the cutoff of the high-side transistor. Thus, the driving current can be reduced before the high-side transistor becomes conductive, and an increase in the circuit area can be suppressed.

[0042] In one embodiment, the gate drive circuit may further include a second sensor that compares the output voltage of the switch circuit with the second threshold voltage. The control circuit may also shift to the third period in response to the output change of the second sensor during the second period. By monitoring the output voltage, it can be detected that the influence of the reverse recovery characteristics of the freewheeling diode of the opposite arm is reduced.

[0043] In one embodiment, the gate drive circuit may further include a third sensor that compares the output voltage of the switch circuit with a third threshold voltage. The control circuit may shift to the fourth period in response to a change in the output of the third sensor during the third period.

[0044] In one embodiment, the gate drive circuit may also be integrated on a semiconductor substrate. "Integrated" includes the case where all components of the circuit are formed on a semiconductor substrate, the case where the main components of the circuit are integrated, and in order to adjust the circuit constant, a part of the resistor or capacitor may also be provided outside the semiconductor substrate. By integrating the circuit on a chip, the circuit area can be reduced, and the characteristics of the circuit elements can be uniformly maintained.

[0045] A motor drive circuit in one embodiment comprises: a bridge circuit including a high-side transistor and a low-side transistor; a high-side driver, which is a gate drive circuit of any one of the above items for driving the high-side transistor as a power transistor; and a low-side driver, which is a gate drive circuit of any one of the above items for driving the low-side transistor as a power transistor.

[0046] An electronic device according to one embodiment includes a motor and the above-mentioned motor driving device for driving the motor.

[0047] (Implementation Method)

[0048] The preferred embodiments are described below with reference to the accompanying drawings. The same or equivalent components, members, and processes shown in the drawings are marked with the same reference numerals, and repeated descriptions are appropriately omitted. In addition, the embodiments do not limit the invention but are merely illustrative, and all the features and combinations thereof described in the embodiments are not necessarily the essential contents of the invention.

[0049] In this specification, "the state in which component A and component B are connected" includes not only the case in which component A and component B are directly physically connected, but also the case in which component A and component B are indirectly connected via other components that do not substantially affect their electrical connection state or do not impair the functions and effects exerted by their combination.

[0050] Similarly, "the state in which component C is arranged between component A and component B" includes, in addition to the case in which component A and component C or component B and component C are directly connected, the case in which they are indirectly connected via other components that do not substantially affect their electrical connection state or do not impair the functions and effects exerted by their combination.

[0051] Figure 2 1 is a circuit diagram of a switching circuit 100 according to an embodiment. The switching circuit 100 includes a bridge circuit 110 and a drive circuit 200. Here, only a one-phase configuration of the switching circuit 100 is shown, but the switching circuit 100 may be a three-phase circuit or an H-bridge circuit.

[0052] The bridge circuit 110 includes an upper arm 112 disposed between a power line (input line) 102 and an output terminal (output line) 104, and a lower arm 114 disposed between the output line 104 and a ground line 106. The upper arm 112 includes a high-side transistor MH and a flyback diode (return diode) Di connected in parallel. The lower arm 114 includes a low-side transistor ML and a flyback diode Di connected in parallel. In the present embodiment, the high-side transistor MH and the low-side transistor ML are N-channel MOSFETs, and their respective body diodes also serve as the flyback diode Di.

[0053] The drive circuit 200 controls the upper arm 112 and the lower arm 114 of the bridge circuit 110. The drive circuit 200 can switch the high impedance state in which both the upper arm 112 and the lower arm 114 are disconnected. High output state where the upper arm 112 is on and the lower arm 114 is off and a low output state in which the upper arm 112 is disconnected and the lower arm 114 is connected These three states. About the output current I OUT The direction of current flowing from the output line 104 of the bridge circuit 110 toward the inductor L1 as the load is defined as positive, and the opposite direction is defined as negative. There is an output current I OUT Positive (current source) state And the output current I OUT Negative (current sinking) state

[0054] The drive circuit 200 includes a control circuit 210, a high-side drive circuit 220, and a low-side drive circuit 260, and is a functional IC integrated on a semiconductor substrate. The control circuit 210 selects a state according to the state of the load of the bridge circuit 110. Generation and each state The corresponding control signals HGCTL and LGCTL. In the state, both the high-side control signal HGCTL and the low-side control signal LGCTL are at the cut-off level (e.g., low). In the state, the high-side control signal HGCTL is at the on level (eg, high), and the low-side control signal LGCTL is at the off level. In the embodiment, the high-side control signal HGCTL is at a cut-off level, and the low-side control signal LGCTL is at a cut-off level.

[0055] The high-side driving circuit 220 receives the high-side control signal HGCTL at the input node IN, and the output node OUT is connected to the gate of the high-side transistor MH via the high-side gate pin HG. If the high-side control signal HGCTL changes from the off level to the on level, the high-side driving circuit 220 supplies a driving current I to the gate of the high-side transistor MH. HG_ON , so that the gate-source voltage V GS In addition, if the high-side control signal HGCTL changes from the on level to the off level, the high-side drive circuit 220 draws the drive current I from the gate of the high-side transistor MH. HG_OFF , so that the gate-source voltage V GS decreases, causing the high-side transistor MH to be cut off.

[0056] The high-side driver circuit 220 can select a plurality of operation modes when the high-side transistor MH is turned on, one of which is referred to as the first mode. In the first mode, the high-side driver circuit 220 supplies a drive current I to the gate of the high-side transistor MH according to the state of the bridge circuit 110. HG_ON Changes in multiple stages.

[0057] In the first mode, the high-side driving circuit 220 outputs a driving current I1 of a first current amount during a first period T1 after the high-side control signal HGCTL changes from an off level to an on level. HG_ON In the second period T2 immediately following the first period T1, a driving current I having a second current I2 which is smaller than the first current I1 is output. HG_ON Then, in the third period T3 following the second period T2, a driving current I having a third current amount I3 greater than the first current amount I1 and the second current amount I2 is output. HG_ON .

[0058] The high-side driving circuit 220 is configured to be operable in a second mode in addition to the first mode. In the second mode, the driving current I generated by the high-side driving circuit 220 HG_ON The waveform of the drive current I is different from that of the first mode. Specifically, in the second mode, during the period from when the high-side control signal HGCTL changes from the off-level to the on-level to when the state transition of the bridge circuit 110 is completed, the drive current I HG_ON The fixed amount Ic is larger than the second current amount I2. The fixed amount Ic may be larger than any one of the first current amount I1 to the third current amount I3.

[0059] The low-side drive circuit 260 receives the low-side control signal LGCTL at the input node IN, and the output node OUT is connected to the gate of the low-side transistor ML via the low-side gate pin LG. If the low-side control signal LGCTL changes from the off level (e.g., low) to the on level (high), the low-side drive circuit 260 supplies a drive current I to the gate of the low-side transistor ML. LG_ON , so that the gate-source voltage V GS In addition, if the low-side control signal LGCTL changes from the on level to the off level, the low-side drive circuit 260 draws the drive current I from the gate of the low-side transistor ML. LG _ OFF , so that the gate-source voltage V GS decreases, causing the low-side transistor ML to become cut off.

[0060] Similar to the high-side drive circuit 220 , the low-side drive circuit 260 is configured to be switchable between the first mode and the second mode.

[0061] In the first mode, the low-side drive circuit 260 supplies a drive current I to the gate of the low-side transistor ML according to the state of the bridge circuit 110. LG _ ON Changes in multiple stages.

[0062] In the first mode, the low-side driving circuit 260 outputs a driving current I of a fourth current amount I4 in a fourth period T4 after the low-side control signal LGCTL changes from an off level to an on level. LG _ ON In the fifth period T5 immediately following the fourth period T4, a driving current I having a fifth current amount I5 which is less than the fourth current amount I4 is output. LG_ON Then, in the sixth period T6 immediately following the fifth period T5, a driving current I having a sixth current amount I6 greater than the fourth current amount I4 and the fifth current amount I5 is output. LG _ ON .

[0063] In the second mode, the driving current I generated by the low-side driving circuit 260 LG _ ON The waveform of the drive current I is different from that of the first mode. Specifically, in the second mode, during the period from when the low-side control signal LGCTL changes from the off-level to the on-level until the state transition of the bridge circuit 110 is completed, the drive current I LG _ ON The fixed amount Id is larger than the fifth current amount I5. The fixed amount Id may be larger than any one of the fourth current amount I4 to the sixth current amount I6.

[0064] The above is the configuration of the switch circuit 100. Next, its operation will be described.

[0065] First, the operation of the high-side drive circuit 220 will be described. The high-side drive circuit 220 operates in the first mode when a reverse recovery current can be generated for the flyback diode of the lower arm 114, and operates in the second mode when a reverse recovery current is not generated for the flyback diode of the lower arm 114.

[0066] Specifically, the high-side drive circuit 220 turns off the high-side transistor MH and the low-side transistor ML, and pulls the current I through the freewheeling diode Di of the lower arm 114. OUT Status In the state where the high-side transistor MH is turned on (sourcerise), the operation is performed in the first mode.

[0067] In addition, the high-side driving circuit 220 turns off the high-side transistor MH, turns on the low-side transistor ML, and sinks the current I OUTIn the state where the high-side transistor MH is turned on (sink rise), the operation is performed in the second mode.

[0068] Figure 3 4 is a circuit diagram of a gate drive circuit 400 according to an embodiment. Figure 2 The high-side driving circuit 220 drives the high-side transistor MH forming the upper arm.

[0069] The conduction circuit 410 is configured to draw a conduction current I to the gate of the high-side transistor MH, which is an N-type power transistor. HG_ON The cutoff circuit 420 is configured to sink a current I from the gate of the high-side transistor MH. HG_OFF .

[0070] The conduction circuit 410 includes a first current source CS1 , a second current source CS2 , a first current mirror circuit CM1 , a first enabling switch SW1 , and a conduction fixing switch SW2 .

[0071] The first current source CS1 outputs the first current Ix in the on state. The first current source CS1 is configured so that the current amount of the first current Ix can be switched between a first current amount Ia and a second current amount Ib that is smaller than the first current amount Ia.

[0072] The first current source CS1 can make the first current Ix completely zero in the off state, but is preferably configured to output a very small current amount Ic.

[0073] The first current mirror circuit CM1 is connected to the first current source CS1 at the input node in. The first current mirror circuit CM1 folds back the first current Ix and outputs it from the first output node out1. The first enable switch SW1 is provided between the first output node out1 of the first current mirror circuit CM1 and the gate of the high-side transistor MH (i.e., the high-side gate pin HG).

[0074] The fixed switch SW2 is connected to the gate of the high-side transistor MH and generates a high voltage V corresponding to the high level of the gate voltage of the high-side transistor MH. H The high voltage V HIt can be a bootstrap voltage generated by a bootstrap circuit or a charge pump circuit. The on-fixed switch SW2 includes a plurality of transistors MP1 to MPn on a plurality of n (n≥2) parallel paths provided between the high level line 412 and the gate of the high-side transistor MH. The plurality of transistors MP1 to MPn can be controlled to be on and off respectively, so the impedance of the on-fixed switch SW2 can be controlled. The state in which all the plurality of transistors MP1 to MPn are off corresponds to the off state of the on-fixed switch SW2. The state in which at least one of the plurality of transistors MP1 to MPn is on corresponds to the on state of the on-fixed switch SW2. The state in which all the plurality of transistors MP1 to MPn are on is referred to as the fully on state of the on-fixed switch SW2.

[0075] The sizes of the plurality of transistors MP1 to MPn may all be equal, or may be weighted using binary. The size of a transistor is gate width / gate length (W / L).

[0076] The control circuit 210 generates a control signal HGCTL indicating the states of the conduction circuit 410 and the cutoff circuit 420. Specifically, the control circuit 210 is configured to control the first current source CS1, the first enable switch SW1, and the conduction fixing switch SW2 for the conduction circuit 410.

[0077] In the first mode, the control circuit 210 operates in the following sequence in response to an instruction to turn on the high-side transistor MH.

[0078] (i) Period 1 T1

[0079] The first current source CS1 is turned on. The first current Ix of the first current source CS1 is the first current amount Ia. In addition, the first enable switch SW1 is turned on, and the conduction fixing switch SW2 is turned off.

[0080] In the first period T1, a current I having a first current amount I1 is supplied to the gate of the high-side transistor MH. HG_ON When the mirror ratio of the first current mirror circuit CM1 is set to α, the first current amount I1 is expressed by the following equation.

[0081] I1=Ia×α

[0082] (ii) Second period T2

[0083] The first current source CS1 remains on, and the first current Ix is reduced to the second current Ib. The first enable switch SW1 remains on, and the conduction fixing switch SW2 remains off.

[0084] In the second period T2, a current I having a second current amount I2 is supplied to the gate of the high-side transistor MH. HG_ON The second current I2 is expressed by the following formula.

[0085] I2 = Ib × α

[0086] Since Ib < Ia, so I2 < I1.

[0087] (iii) Period T3

[0088] The first current source CS1 is turned on, the first current Ix maintains the second current amount Ib, and the first enable switch SW1 is turned on. The conduction fixed switch SW2 is switched to on. In the third period T3, at least one of the transistors MP1 to MPn constituting the conduction fixed switch SW2 is turned on.

[0089] In the third period T3, a current I of the third current amount I3 is supplied to the gate of the high-side transistor MH HG_ON . The transistors that are turned on in the third period T3 are selected in such a way that I3 > I1.

[0090] More preferably, the transistors that are turned on in the third period T3 are selected in such a way that the turned-on transistors operate in the saturation region.

[0091] (iv) Period T4

[0092] The first current source CS1 and the first enable switch SW1 are turned off, and the conduction fixed switch SW2 is turned on. All the transistors MP1 to MPn of the conduction fixed switch SW2 are turned on.

[0093] Figure 4 is Figure 3 The operation waveform diagram of the gate drive circuit 400. The control signal CTRL is a logic signal indicating the state of the bridge circuit 110. The current I MH represents the current flowing in the high-side transistor MH, and the current I ML represents the current flowing in the low-side transistor ML. The current is positive in the direction from the drain to the source. V LG is the gate voltage (gate-source voltage) of the low-side transistor ML. V HG is the gate voltage of the high-side transistor MH, and V OUT represents the output voltage. V HG and V OUT The potential difference of is the gate-source voltage of the high-side transistor MH.

[0094] Before the time t0, the control signal CTRL is at a low level, the high-side transistor MH is cut off, the low-side transistor ML is turned on, and the output voltage V OUT is at a low voltage (0V).

[0095] Figure 4 represents the operation in the sink current mode. Before the time t0, the negative current IML Flows in the low-side transistor ML.

[0096] At time t0, the control signal CTRL changes to a high level. As a result, the low-side driver circuit 260 causes the gate voltage V LG decreases, causing the low-side transistor ML to become cut off.

[0097] At time t1, if the gate voltage V LG When the voltage Vth4 is lower than the fourth threshold voltage Vth4, the high-side driving circuit 220 becomes active. In the first period T1, the conduction circuit 410 supplies a current I1 of the first current amount I1 to the gate of the high-side transistor MH. HG_ON .

[0098] Then, at time t2, if the gate-source voltage V HG -V OUT When the first threshold voltage Vth1 is exceeded, the second period T2 is entered. In the second period T2, the conduction circuit 410 supplies a current I of the second current amount I2 to the gate of the high-side transistor MH. HG_ON The second current amount I2 is smaller than the first current amount I1.

[0099] Then, at time t3, if the output voltage V OUT When the second threshold voltage Vth2 is exceeded, the transition to the third period T3 is made. In the third period T3, the conduction fixed switch SW2 is turned on, and the conduction circuit 410 supplies a current I of a third current amount I3 to the gate of the high-side transistor MH. HG_ON The third current I3 is greater than the first current I1 and the second current I2. In the third period T3, the drain-source voltage V of the transistors MP1 to MPn constituting the second enable switch SW3 is DS (=V H -V HG ) is about 9 V to 10 V, and operates in the saturation region. In the saturation region, since the drain current does not depend on the drain-source voltage, there is an advantage that the third current amount I3 in the third period T3 is easily controlled.

[0100] Then, at time t4, if the output voltage V OUT Exceeding the input voltage VI N When the third threshold voltage Vth3 set near the high-side transistor MH is reached, the gate voltage V HG The high-side transistor MH is fixed to a high-level voltage and is strongly fixed to an on state.

[0101] The above is the operation of the switch circuit 100 .

[0102] According to the switch circuit 100, the period until the high-side transistor MH is turned on is defined as the first period T1, and the drive current I1 having the first current amount I1 is supplied to the gate of the high-side transistor MH. HG_ON , so that the gate voltage V HG Then, in the second period T2 after the high-side transistor MH is turned on and the reverse recovery current can flow through the freewheeling diode of the lower arm, the drive current I supplied to the gate of the high-side transistor MH is HG_ON By reducing the current to the second current I2, the high-side transistor MH is slowly turned on while keeping the on-resistance of the high-side transistor MH large, thereby suppressing the through current or transient caused by the reverse recovery current of the freewheeling diode of the lower arm, which is the opposite side of the upper arm driven by the drive circuit 200.

[0103] Next, in the third period T3 in which the possibility of the reverse recovery current flowing is low, the drive current I supplied to the gate of the high-side transistor MH is increased. HG_ON By increasing the third current amount I3 which is larger than the second period T2 , the on-time of the high-side transistor MH can be shortened, thereby reducing power consumption.

[0104] Furthermore, in both the first period T1 and the second period T2, the first current mirror circuit CM1 operates to change the amount of the input current Ix of the first current mirror circuit CM1. Therefore, when switching from the first period T1 to the second period T2, the driving current I HG_ON The current is gradually changed from the first current amount I1 to the second current amount I2. This can further reduce power consumption.

[0105] Furthermore, in the third period T3, the driving current I supplied to the gate of the high-side transistor MH is HG_ON This is larger than the first current amount I1 in the first period T1. As a result, since the on-resistance of the high-side transistor MH can be reduced in a short time, the efficiency of the bridge circuit can be further improved.

[0106] Next, a configuration example of the cutoff circuit 420 will be described.

[0107] Figure 5 2 is a circuit diagram of a drive circuit 200A including a gate drive circuit 400A. The gate drive circuit 400A includes an on circuit 410A and an off circuit 420A.

[0108] The basic structure of the conduction circuit 410A is Figure 3 Similarly, it includes a first current source CS1, a first current mirror circuit CM1, a first enabling switch SW1, and an on-state fixing switch SW2.

[0109] The first current mirror circuit CM1 has a second output node out2. The first current mirror circuit CM1 folds back the current Ix and supplies the current Ix' to the cutoff circuit 420A.

[0110] The cutoff circuit 420A includes a second current mirror circuit CM2 , a second enable switch SW3 , and a cutoff fixing switch SW4 .

[0111] The input node in of the second current mirror circuit CM2 is connected to the second output node out2 of the first current mirror circuit CM1. The second current mirror circuit CM2 folds back the current Ix'. The second enable switch SW3 is provided between the output node out of the second current mirror circuit CM2 and the gate of the high-side transistor MH.

[0112] The cut-off fixed switch SW4 is connected between the gate source of the high-side transistor MH. The cut-off fixed switch SW4 is constructed in the same manner as the on-fixed switch SW2. Specifically, it includes a plurality of transistors MN1 to MNn on a plurality of n (n≥2) parallel paths between the gate source of the high-side transistor MH. The plurality of transistors MN1 to MNn can be controlled to be on and off respectively, so the impedance of the cut-off fixed switch SW4 can be controlled. The state in which all the plurality of transistors MN1 to MNn are cut off corresponds to the off state of the cut-off fixed switch SW4. The state in which at least one of the plurality of transistors MN1 to MNn is on corresponds to the on state of the cut-off fixed switch SW4. The state in which all the plurality of transistors MN1 to MNn are on is referred to as the fully on state of the cut-off fixed switch SW4. It is referred to as the fully on state of the cut-off fixed switch SW4. The sizes of the plurality of transistors MN1 to MNn can be all equal, or they can be weighted using binary.

[0113] The second enabling switch SW3 and the off-fixing switch SW4 of the off circuit 420 are controlled according to the control signal HGCTL generated by the control circuit 210 .

[0114] According to the cutoff circuit 420A, when the high-side transistor MH is turned off, the drive current I generated by the cutoff circuit 420A can be reduced to HG_OFF When the drive current I HG_ON Also changes in stages.

[0115] Next, a more specific configuration example of the conduction circuit 410 will be described.

[0116] Figure 6 : is a circuit diagram showing a configuration example of the conduction circuit 410. The first current source CS1 includes a first constant current circuit CCS1, a second constant current circuit CCS2, a third constant current circuit CCS3, a first switch SW7, and a second switch SW8.

[0117] The first constant current circuit CCS1 is connected to the output node of the first current source CS1. The first switch SW7 and the second constant current circuit CCS2 are connected in series between the output node and the ground. The second switch SW8 and the third constant current circuit CCS3 are connected in series between the output of the second constant current circuit CCS2 and the ground.

[0118] In the off state, the first switch SW7 of the first current source CS1 is off. In the on state, in the first period T1, the first switch SW7 and the second switch SW8 of the first current source CS1 are on. In the second period T2, the first switch SW7 is on and the second switch SW8 is off.

[0119] The first current source CS1 continuously outputs the output current of the first constant current circuit CCS1 as a current Ix of a small current amount in the off state. Thus, the variation of the operating point of the first current mirror circuit CM1 can be suppressed. The operating speed of the first current mirror circuit CM1 can be increased. Thus, the responsiveness of the conduction circuit 410 can be improved.

[0120] Figure 7 2 is a circuit diagram of the driving circuit 200 . The driving circuit 200 may include a first sensor 202 , a second sensor 204 , a third sensor 206 , and a low-side cutoff sensor 208 .

[0121] The low-side cutoff sensor 208 detects that the low-side transistor ML is turned off. The low-side cutoff sensor 208 compares the gate-source voltage of the low-side transistor ML with the fourth threshold voltage Vth4. If the control circuit 210 detects that the low-side transistor ML is turned off based on the output of the low-side cutoff sensor 208, it shifts to the first period t1.

[0122] The first sensor 202 measures the gate-source voltage V GS The first threshold voltage Vth1 is compared with the first threshold voltage Vth1. The first threshold voltage Vth1 is based on the threshold voltage V GS(th) Just decide.

[0123] In many cases, a high-side cutoff sensor for detecting the cutoff of the high-side transistor MH is provided in the driving circuit 200. The output of the high-side cutoff sensor is referred to by the control circuit 210. The control circuit 210 monitors the output of the high-side cutoff sensor, and after the high-side transistor MH is reliably cut off, the low-side control signal LGCTL is converted to the on level. In this way, it is possible to prevent the high-side transistor MH and the low-side transistor ML from being turned on at the same time, thereby preventing a through current.

[0124] When the driving circuit 200 includes a high-side cutoff sensor, the first sensor 202 can be used in common with the high-side cutoff sensor, thereby reducing the circuit area.

[0125] In the first period T1 of the high-side driving circuit 220, if the output of the first sensor 202 changes, that is, the gate-source voltage V GS When the first threshold voltage Vth1 is exceeded, the second period T2 is entered. When the first threshold voltage Vth1 is set higher than the threshold voltage V GS(th) When the high-side driving circuit 220 is low, the high-side driving circuit 220 can be shifted to the second period T2 before the high-side transistor MH is turned on. When the response delay is large, the high-side driving circuit 220 shifts to the second period T2 at the same time as or slightly later than the turning on.

[0126] By monitoring the gate-source voltage V of the high-side transistor MH GS , which can be linked with the high-side transistor MH changing from the off state to the on state to make the drive current I HG_ON size changes.

[0127] The second sensor 204 outputs the output voltage V OUT The high-side driver circuit 220 responds to the output change of the second sensor 204 during the second period T2 and shifts to the third period T3. By monitoring the output voltage V OUT , it can be detected that the influence of the reverse recovery characteristics of the freewheeling diode Di of the lower arm 114 is reduced.

[0128] In the driving circuit 200, in order to detect the output voltage V OUT The output voltage V is sometimes set to V OUT Ratio with input voltage V IN In this case, by using the voltage monitoring circuit also as the second sensor 204, an increase in circuit area can be suppressed.

[0129] The third sensor 206 outputs a voltage V OUT With the input voltage V IN The control circuit 210 refers to the output of the third sensor 206. If V OUT When it exceeds Vth3, it shifts to the fourth period T4.

[0130] Next, the configuration and operation of the low-side driving circuit 260 will be described. The low-side driving circuit 260 may be configured similarly to the high-side driving circuit 220 .

[0131] The low-side drive circuit 260 operates in the first mode when a reverse recovery current of the flyback diode of the upper arm 112 can be generated, and operates in the second mode when a reverse recovery current of the flyback diode of the upper arm 112 is not generated.

[0132] Specifically, the low-side drive circuit 260 injects the current I from the high-side transistor MH and the low-side transistor ML to the upper arm 112 via the freewheeling diode Di. OUT Status When the low-side transistor ML is turned on (sinkfall), the operation is performed in the first mode.

[0133] In addition, the low-side driving circuit 260 turns on the high-side transistor MH, turns off the low-side transistor ML, and draws the current I through the high-side transistor MH. OUT In the state of , the low-side transistor ML is turned on (source fall: pull-down), and the operation is performed in the second mode.

[0134] Next, a modification of the sequence of the driving circuit 200 will be described.

[0135] (Sequence Variation 1)

[0136] In the first sequence modification example, in the first period T1 , the control circuit 210 turns on a part of the transistors MP1 to MPn constituting the on-fixed switch SW2 . Other aspects are the same as those of the embodiment.

[0137] Figure 8 2 is an operation waveform diagram of the driving circuit 200 according to the sequence variation 1. Figure 8 The upper part of shows the voltage waveform of sequence variation 1. Figure 8 The lower part of the sequence shows the driving current I of the first modification example with a solid line. HG_ON '. For comparison, the dashed line is used Figure 4 The driving current I HG_ON .

[0138] In the first sequence variation, during the first period T1, the on-state fixed switch SW2 is turned on, so the drive current I HG_ON 'The current I1 is Figure 4 Therefore, due to the gate voltage V HG The rising speed of is accelerated, so the timing t2' of the transition to the second period T2' is also advanced. Figure 4 Compared with the action of , the conduction time of the high-side transistor MH can be shortened.

[0139] (Sequence Variation 2)

[0140] In the second sequence modification, in the third period T3, the control circuit 210 sets the conduction fixing switch SW2 to the fully-on state. Other aspects are the same as those of the embodiment.

[0141] Fig. 9 2 is an operation waveform diagram of the driving circuit 200 according to the second sequence variation. Fig. 9 The upper part of shows the voltage waveform of sequence variation 2. Fig. 9 The lower part of the sequence shows the driving current I of the second modification example with a solid line. HG_ON ". Dashed line I CM1 Indicates the driving current I HG_ON In the third period T3, by setting the conduction fixed switch SW2 to a fully turned-on state, the drive current I in the third period T3 can be further increased. HG_ON , which can shorten the conduction time.

[0142] (Sequence Variation 3)

[0143] Sequence modification example 3 is a combination of sequence modification example 1 and sequence modification example 2. That is, in the first period T1, the control circuit 210 turns on a part of the transistors MP1 to MPn constituting the conduction fixed switch SW2. In the third period T3, the control circuit 210 turns on the conduction fixed switch SW2 in a fully-conducted state. Other aspects are the same as those of the embodiment.

[0144] (Sequence Variation 4)

[0145] In the embodiment or the sequence modifications 1 to 3, the first enable switch SW1 may be turned off in the third period T3.

[0146] (use)

[0147] Next, description will be given of the use of the switch circuit 100. The switch circuit 100 can be suitably used in a drive circuit for a motor.

[0148] Fig.10 1 is a circuit diagram of a motor drive device 300 including the switching circuit 100 according to the embodiment. The motor drive device 300 drives a three-phase motor 302 as a load and controls the rotation state.

[0149] The motor driving device 300 includes a bridge circuit 110 and a driving circuit 200. The bridge circuit 110 is a three-phase inverter having bridge arms of U phase, V phase, and W phase, and each bridge arm of each phase has an upper arm and a lower arm.

[0150] The drive circuit 200 includes a control circuit 210 , high-side drive circuits 220U to 220W, and low-side drive circuits 260U to 260W. The control circuit 210 generates a control signal indicating the state of the six arms constituting the bridge circuit 110 based on the state of the three-phase motor 302 as a load.

[0151] The high-side driving circuits 220U to 220W are configured by the structure of the high-side driving circuit 220 described above. In addition, the low-side driving circuits 260U to 260W are configured by the structure of the low-side driving circuit 260 described above.

[0152] Here, a three-phase motor is taken as an example, but a single-phase motor may also be used. In this case, the bridge circuit 110 is an H bridge circuit.

[0153] Next, the purpose of the motor driving device 300 is described. The motor driving device 300 can be used to control the spindle motor of a hard disk or the lens driving motor of an imaging device. Alternatively, it can be used to drive the driving motor of a printer head or the paper feeding motor. Alternatively, the motor driving device 300 can be used to drive the motor of an electric vehicle, a hybrid vehicle, etc.

[0154] Those skilled in the art should understand that the embodiments are merely illustrative, and that the combinations of the constituent elements and the processing procedures may have various modifications, and such modifications are also within the scope of the present disclosure or the present invention. Such modifications are described below.

[0155] (Variant 1)

[0156] In the implementation, the bridge circuit 110 is composed of discrete components, but is not limited thereto. The bridge circuit 110 may also be integrated into the driving circuit 200 .

[0157] (Variant 2)

[0158] The upper arm 112 and the lower arm 114 may be formed of IGBTs (Insulated Gate Bipolar Transistors).

[0159] (Variant 3)

[0160] In the embodiment, both the high-side driving circuit 220 and the low-side driving circuit 260 can select a plurality of modes, but only one of them may be configured to be capable of mode control.

[0161] (Variant 4)

[0162] In the embodiment, the first enabling switch SW1 can be used to switch the enabling and disabling of the first current mirror circuit CM1, but the present disclosure is not limited thereto. For example, the first enabling switch SW1 can be connected between the gate source of the PMOS transistor constituting the first current mirror circuit CM1, and the first current mirror circuit CM1 can be disabled by turning on the first enabling switch SW1. Alternatively, the first enabling switch SW1 can be omitted. The same is true for the second enabling switch SW3.

[0163] (Variant 5)

[0164] The use of the switching circuit 100 is not limited to the motor drive device 300. For example, the switching circuit 100 can be suitably used in a switching regulator (DC / DC converter), various power conversion devices (inverters, converters), an inverter for lighting a discharge lamp, a digital audio amplifier, etc. Therefore, the switching circuit 100 can be used in civil equipment including electronic equipment and home appliances, automobiles and vehicle-mounted parts, industrial vehicles, and industrial machinery.

[0165] The embodiments described using specific terms merely illustrate the principles and applications of the present invention, and various modifications or changes in configuration may be made in the embodiments without departing from the spirit of the present invention defined in the claims.

[0166] (Note)

[0167] The following techniques are disclosed in this specification.

[0168] (Item 1)

[0169] A gate drive circuit is a gate drive circuit for driving an N-type power transistor constituting a switch circuit, comprising:

[0170] a conduction circuit configured to draw current to the gate of the power transistor,

[0171] a cutoff circuit configured to sink current from the gate of the power transistor, and

[0172] A control circuit for controlling the conduction circuit and the cutoff circuit;

[0173] The conduction circuit comprises:

[0174] a first current source configured to generate a first current switchable between a first current amount and a second current amount smaller than the first current amount,

[0175] a first current mirror circuit having an input node connected to the first current source and configured to fold back the first current and supply the first current to the gate of the power transistor; and

[0176] Turning on a fixed switch connected between the gate of the power transistor and a high level line generating a high voltage equivalent to the high level of the gate voltage of the power transistor;

[0177] The control circuit is configured to control the on-state fixed switch and the first current source;

[0178] The control circuit is configured to: in response to an instruction that the power transistor becomes conductive,

[0179] (i) in a first period, the first current is set to the first current amount, and the conduction fixed switch is turned off,

[0180] (ii) in a second period, the first current is set to the second current amount, and the conduction fixed switch is turned off,

[0181] (iii) During the third period, the conduction fixed switch is turned on.

[0182] (Item 2)

[0183] The gate drive circuit as described in item 1,

[0184] The current supplied to the gate of the power transistor in the third period is larger than the current supplied to the gate of the power transistor in the first period and the second period.

[0185] (Item 3)

[0186] A gate drive circuit as described in item 1 or 2,

[0187] The conduction fixed switch includes a plurality of transistors arranged on a plurality of paths connected in parallel, and the number of transistors in operation is variable.

[0188] (Item 4)

[0189] The gate drive circuit as described in item 3,

[0190] The control circuit turns on some of the plurality of transistors during the first period.

[0191] (Item 5)

[0192] A gate drive circuit as described in item 3 or 4,

[0193] The control circuit turns on all of the plurality of transistors in a fourth period following the third period.

[0194] (Item 6)

[0195] A gate drive circuit as described in any one of items 1 to 5,

[0196] A first enable switch connected between an output node of the first current mirror circuit and the gate of the power transistor is further provided.

[0197] (Item 7)

[0198] The gate drive circuit as described in item 6,

[0199] The control circuit turns on the first enable switch in the first period and the second period, and turns off the first enable switch in a fourth period following the third period.

[0200] (Item 8)

[0201] A gate drive circuit as described in item 6 or 7,

[0202] The control circuit turns on the first enable switch during the third period.

[0203] (Item 9)

[0204] A gate drive circuit as described in item 6 or 7,

[0205] The control circuit turns off the first enable switch during the third period.

[0206] (Item 10)

[0207] A gate drive circuit as described in any one of items 1 to 9,

[0208] The control circuit turns on the fixed-conduction switch in a fourth period following the third period.

[0209] (Item 11)

[0210] A gate drive circuit as described in any one of items 1 to 10,

[0211] The first current mirror circuit further has a second output node;

[0212] The cut-off circuit comprises:

[0213] a second current mirror circuit having an input node connected to the second output node of the first current mirror circuit and an output node,

[0214] a second enabling switch connected between the output node of the second current mirror circuit and the gate of the power transistor, and

[0215] A turn-off fixed switch is connected between the gate of the power transistor and a low-level line generating a low voltage corresponding to the low level of the gate voltage of the power transistor.

[0216] (Item 12)

[0217] A gate drive circuit as described in any one of items 1 to 11,

[0218] The first current source comprises:

[0219] Output node,

[0220] a first constant current circuit connected to the output node,

[0221] a first switch and a second constant current circuit connected in series between the output node and ground, and

[0222] A second switch and a third constant current circuit are connected in series between the output of the second constant current circuit and the ground.

[0223] (Item 13)

[0224] A gate drive circuit as described in any one of items 1 to 12,

[0225] further comprising a first sensor for comparing a gate-source voltage of the power transistor with a first threshold voltage;

[0226] The control circuit shifts to the second period in response to a change in the output of the first sensor during the first period.

[0227] (Item 14)

[0228] A gate drive circuit as described in any one of items 1 to 13,

[0229] further comprising a second sensor for comparing the output voltage of the switch circuit with a second threshold voltage;

[0230] The control circuit shifts to the third period in response to a change in the output of the second sensor during the second period.

[0231] (Item 15)

[0232] A gate drive circuit as described in item 5 or 7,

[0233] further comprising a third sensor for comparing the output voltage of the switch circuit with a third threshold voltage;

[0234] The control circuit shifts to the fourth period in response to a change in the output of the third sensor during the third period.

[0235] (Item 16)

[0236] A gate drive circuit as described in any one of items 1 to 15,

[0237] It is integrated on a semiconductor substrate.

[0238] (Item 17)

[0239] A motor drive device, comprising:

[0240] A bridge circuit including a high-side transistor and a low-side transistor,

[0241] a high-side driver, which is a gate drive circuit as described in any one of items 1 to 16 for driving the high-side transistor as the power transistor, and

[0242] A low-side driver is a gate drive circuit as described in any one of items 1 to 16, which drives the low-side transistor as the power transistor.

[0243] (Item 18)

[0244] An electronic device comprising:

[0245] Motor, and

[0246] A motor driving device as described in item 17 for driving the motor.

[0247] [Explanation of Reference Numerals]

[0248] 100 switch circuit

[0249] 102 power cord

[0250] 104 output lines

[0251] 106 ground wire

[0252] 110 bridge circuit

[0253] 112 Upper arm

[0254] 114 lower arm

[0255] MH high side transistor

[0256] ML low-side transistor

[0257] Di freewheeling diode

[0258] 200 drive circuit

[0259] 202 No.1 Sensor

[0260] 204 2nd sensor

[0261] 206 3rd sensor

[0262] 208 Low Side Cutoff Sensor

[0263] 210 control circuit

[0264] 220 high side drive circuit

[0265] 260 low side drive circuit

[0266] 300 motor drive

[0267] 302 three-phase motor

[0268] 400 gate drive circuit

[0269] 410 conduction circuit

[0270] 412 high level line

[0271] CS1 1st current source

[0272] CS2 Second current source

[0273] CM1 1st current mirror circuit

[0274] SW1 1st enable switch

[0275] SW2 is on and fixed switch

[0276] SW3 2nd enable switch

[0277] SW4 cut-off fixed switch

[0278] 420 cut-off circuit

[0279] 422 High Side Line

[0280] CM3 3rd current mirror circuit

[0281] CM4 4th current mirror circuit

[0282] CCS1 1st constant current circuit

[0283] CCS2 Second constant current circuit

[0284] CCS3 3rd constant current circuit

[0285] CCS4 4th constant current circuit

[0286] CCS5 No. 5 Constant Current Circuit

[0287] SW7 1st switch

[0288] SW8 2nd switch

[0289] SW9 9th switch.

Claims

1. A gate drive circuit is a gate drive circuit for driving an N-type power transistor constituting a switch circuit, comprising: a conduction circuit configured to draw current to the gate of the power transistor, a cutoff circuit configured to sink current from the gate of the power transistor, and A control circuit for controlling the conduction circuit and the cutoff circuit; The conduction circuit comprises: a first current source configured to generate a first current switchable between a first current amount and a second current amount smaller than the first current amount, a first current mirror circuit having an input node connected to the first current source and configured to fold back the first current and supply the first current to the gate of the power transistor; and Turning on a fixed switch connected between the gate of the power transistor and a high level line generating a high voltage equivalent to the high level of the gate voltage of the power transistor; The control circuit is configured to control the on-state fixed switch and the first current source; The control circuit is configured to: in response to an instruction of the power transistor to become conductive, (i) in a first period, the first current is set to the first current amount, and the conduction fixed switch is turned off, (ii) in a second period, the first current is set to the second current amount, and the conduction fixed switch is turned off, (iii) During the third period, the conduction fixed switch is turned on.

2. The gate drive circuit according to claim 1, The current supplied to the gate of the power transistor in the third period is larger than the current supplied to the gate of the power transistor in the first period and the second period.

3. The gate drive circuit according to claim 1 or 2, The conduction fixed switch includes a plurality of transistors arranged on a plurality of paths connected in parallel, and the number of transistors in operation is variable.

4. The gate driving circuit according to claim 3, The control circuit turns on some of the plurality of transistors during the first period.

5. The gate driving circuit according to claim 3, The control circuit turns on all of the plurality of transistors in a fourth period following the third period.

6. The gate drive circuit according to claim 1 or 2, A first enable switch connected between an output node of the first current mirror circuit and the gate of the power transistor is further provided.

7. The gate driving circuit according to claim 6, The control circuit turns on the first enable switch in the first period and the second period, and turns off the first enable switch in a fourth period following the third period.

8. The gate driving circuit according to claim 6, The control circuit turns on the first enable switch during the third period.

9. The gate driving circuit according to claim 6, The control circuit turns off the first enable switch during the third period.

10. The gate drive circuit according to claim 1 or 2, The control circuit turns on the fixed-conduction switch in a fourth period following the third period.

11. The gate drive circuit according to claim 1 or 2, The first current mirror circuit further has a second output node; The cut-off circuit comprises: a second current mirror circuit having an input node connected to the second output node of the first current mirror circuit and an output node, a second enabling switch connected between the output node of the second current mirror circuit and the gate of the power transistor, and A turn-off fixed switch is connected between the gate of the power transistor and a low-level line generating a low voltage corresponding to the low level of the gate voltage of the power transistor.

12. The gate drive circuit according to claim 1 or 2, The first current source comprises: Output node, a first constant current circuit connected to the output node, a first switch and a second constant current circuit connected in series between the output node and ground, and A second switch and a third constant current circuit are connected in series between the output of the second constant current circuit and the ground.

13. The gate drive circuit according to claim 1 or 2, further comprising a first sensor for comparing a gate-source voltage of the power transistor with a first threshold voltage; The control circuit shifts to the second period in response to a change in the output of the first sensor during the first period.

14. The gate drive circuit according to claim 1 or 2, further comprising a second sensor for comparing the output voltage of the switch circuit with a second threshold voltage; The control circuit shifts to the third period in response to a change in the output of the second sensor during the second period.

15. The gate driving circuit according to claim 5, further comprising a third sensor for comparing the output voltage of the switch circuit with a third threshold voltage; The control circuit shifts to the fourth period in response to a change in the output of the third sensor during the third period.

16. The gate drive circuit according to claim 1 or 2, It is integrated on a semiconductor substrate.

17. A motor drive device comprising: A bridge circuit including a high-side transistor and a low-side transistor, A high-side driver, which is the gate drive circuit according to claim 1 or 2 that drives the high-side transistor as the power transistor, and A low-side driver is the gate drive circuit according to claim 1 or 2, which drives the low-side transistor as the power transistor.

18. An electronic device comprising: Motor, and The motor driving device according to claim 17 drives the motor.

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