A dual half-bridge soft-switching converter and its control method and system

Abstract

The present application belongs to the field of power electronics technology, and specifically discloses a dual half-bridge soft-switching converter and its control method and system. Through the present application, voltage-dividing capacitors C1 and C2 are newly added to the input side. The voltage-dividing capacitors C1 and C2 provide energy under light load to charge and discharge the parasitic capacitance of the MOS tube. Therefore, under the fixed-frequency phase-shift PWM control, the leading switches Q1 and Q2 on the primary side of the transformer can achieve ZVS under light load conditions, thereby improving transmission efficiency. The control method and system provided by the present application have many advantages over traditional PWM phase-shift schemes. First, while achieving ZVS of the lagging bridge arm switch tube under light load conditions, it can also provide a high-precision output signal, allowing stable control of the power output of the device under different load conditions. Secondly, it has good real-time performance and can quickly respond to changes in the control signal. In addition, it can effectively reduce power loss and adjust the output average power by changing the phase shift angle.

Description

Technical Field

[0001] The present application belongs to the field of power electronics technology, and more specifically, relates to a dual half-bridge soft-switching converter and a control method and system thereof. Background Art

[0002] Traditional phase-shifted full-bridge converters are widely used in medium- and high-power applications. Their advantages lie in their simple topology, high power density, and ability to achieve zero-voltage switching (ZVS) by leveraging the device's inherent parasitic capacitance and inductance resonance. However, these converters still suffer from several serious issues, including limited soft-switching range under varying loads, circulating current losses, loss of secondary-side duty cycle, and parasitic oscillations in the rectifier bridge.

[0003] Achieving ZVS in the lagging leg of a phase-shifted full-bridge is determined by the energy stored in the transformer's leakage inductor. When the converter is lightly loaded or the resonant inductor is small, the resonant inductor is insufficient to provide the energy required to charge and discharge the switch's parasitic capacitance, and the lagging leg loses ZVS, increasing switching losses and reducing efficiency. By adding a larger external resonant inductor in series with the transformer or replacing the linear inductor with a saturable inductor, the conditions for achieving zero voltage switching in the converter can be optimized to a certain extent. However, the additional losses introduced by the presence of more or less auxiliary wiring components in the power circuit limit efficiency gains. Due to the limitations of the series auxiliary current source, the introduction of a boost capacitor can reduce circulating current losses, improving overall efficiency by approximately 1%. However, this solution requires an additional transformer, which imposes a size and cost penalty on the equipment, making it unsuitable for high-power applications. The full-bridge converter is combined into a symmetrical dual half-bridge converter, and the drives of the two half-bridges are phase-shifted to control the output voltage. Two resonant inductors are combined with the magnetizing inductance to achieve a wide range of ZVS for the converter. However, the ZVS of the leading bridge arm under light load conditions is still not solved. Summary of the Invention

[0004] In response to the defects of the existing technology, the purpose of this application is to provide a dual half-bridge soft-switching converter and its control method and system, aiming to solve the problem of limited soft switching range of the existing traditional phase-shifted full-bridge converter under load changes, especially the ZVS problem of the leading bridge arm under light load conditions.

[0005] A first aspect of the present application relates to a dual half-bridge soft switching converter, comprising: an input side of the converter consisting of two symmetrical half-bridge circuits, and the two half-bridge circuits share a first voltage-dividing capacitor and a second voltage-dividing capacitor; wherein,

[0006] The first half-bridge circuit includes a leading bridge arm, a primary winding of a first transformer and its primary leakage inductance, a first voltage-dividing capacitor and a second voltage-dividing capacitor.

[0007] The second half-bridge circuit includes a lagging bridge arm, a primary winding of a second transformer and a primary leakage inductance thereof, a first voltage-dividing capacitor and a second voltage-dividing capacitor;

[0008] The switch tubes in the leading bridge arm and the lagging bridge arm are both MOSFETs;

[0009] The output side of the converter includes two secondary windings of a transformer, a rectifier circuit, an output filter inductor and an output filter capacitor, and the two secondary windings are directly connected in series in the same direction as the input of the rectifier circuit.

[0010] In some embodiments, all MOSFET parasitic capacitors in the leading bridge arm and the lagging bridge arm have equal capacitances and satisfy:

[0011]

[0012] in, is the primary leakage inductance of the transformer, is the output filter inductor, is the output current, is the parasitic capacitance of MOSFET, is the input voltage of the converter.

[0013] It should be noted that the present application makes the above-mentioned specific design on the parasitic capacitance of MOSFET to ensure that enough energy is drawn away from the MOSFET to be turned on. The charge on the bridge arm is turned off and the MOS tube is turned off. Charging is performed to achieve zero voltage turn-on of the MOS tube.

[0014] In some embodiments, the first voltage-dividing capacitor and the second voltage-dividing capacitor have equal capacitances, which can ensure that the terminal voltages of the two voltage-dividing capacitors are both half of the input voltage.

[0015] A second aspect of the present application relates to a control method for a dual half-bridge soft-switching converter according to any embodiment of the present application, the control method comprising:

[0016] In the symmetrical half switching cycle, At this moment, Q1 in the leading bridge arm is turned on. Always turn on Q3 in the lagging bridge arm;

[0017] Among them, Q1 and Q2 are leading bridge arm switches, Q3 and Q4 are lagging bridge arm switches, and Q1 and Q2 are complementary turned on, Q3 and Q4 are complementary turned on, and Q1 is ahead of Q3;

[0018] The following conditions are met between each moment:

[0019]

[0020]

[0021]

[0022]

[0023] in, is the moment to turn off Q2, is the moment when the terminal voltage of the parasitic capacitor in Q1 drops to zero, is the moment to turn off Q4, is the moment when the terminal voltage of the parasitic capacitor in Q3 drops to zero, is the moment when the primary current of the transformer rises to zero, for and The length of time between for and The length of time between is the MOSFET parasitic capacitance, is the input voltage of the converter, is the primary current of the first transformer at the corresponding moment, is the primary leakage inductance of the first transformer.

[0024] In some embodiments, the dead time between the Q1 and Q2 drive signals Exceed .

[0025] In some embodiments, the dead time between the Q3 and Q4 drive signals Less than .

[0026] In some embodiments, the phase shift angle of Q1 ahead of Q3 is satisfy:

[0027]

[0028] in, is the switching period of phase-shift PWM control.

[0029] It should be noted that the present application implements the above-mentioned specific design, and controls the common conduction time of Q1 and Q4 (Q2 and Q3) by the phase shift angle, thereby achieving the adjustment of the voltage gain; and by designing the MOS tube turn-on moment, the ZVS of the converter MOS tube under light load conditions is achieved.

[0030] In general, the above technical solutions conceived by this application have the following beneficial effects compared with the existing technologies:

[0031] (1) This application proposes a dual half-bridge soft-switching converter. By adding voltage-dividing capacitors C1 and C2 on the input side, the voltage-dividing capacitors C1 and C2 provide energy under light load to charge and discharge the parasitic capacitance of the MOS tube. As a result, under fixed-frequency phase-shift PWM control, the transformer primary-side leading switches Q1 and Q2 can achieve ZVS under light load conditions, thereby improving transmission efficiency. Compared with the existing traditional full-bridge converter and dual half-bridge converter using fixed-frequency phase-shift PWM control, this application can achieve ZVS of the transformer primary-side lagging bridge arm switches Q3 and Q4 under lighter load conditions, thereby broadening the load range of soft switching.

[0032] (2) This application proposes a control method and system for a dual half-bridge soft-switching converter, which has many advantages over traditional PWM phase-shifting schemes. First, in addition to achieving ZVS of the lagging bridge arm switch tube under light load conditions, it can also provide a high-precision output signal, allowing stable control of the power output of the device under different load conditions. Second, it has good real-time performance and can quickly respond to changes in the control signal. In addition, it can effectively reduce power loss and adjust the average output power by changing the phase shift angle. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Figure 1 This is a schematic diagram of a dual half-bridge soft-switching converter circuit provided in an embodiment of the present application.

[0034] Figure 2 This is a typical working waveform diagram provided in the embodiment of the present application.

[0035] Figure 3 This is a current path diagram of mode 1 provided in an embodiment of the present application.

[0036] Figure 4 This is a current path diagram of mode 2 provided in an embodiment of the present application.

[0037] Figure 5 This is a current path diagram of mode three provided in an embodiment of the present application.

[0038] Figure 6 This is a current path diagram of mode four provided in an embodiment of the present application.

[0039] Figure 7 This is a current path diagram of mode five provided in an embodiment of the present application.

[0040] Figure 8 This is a current path diagram of mode six provided in an embodiment of the present application.

[0041] Figure 9 This is a current path diagram of mode seven provided in an embodiment of the present application.

[0042] Figure 10 This is an equivalent circuit diagram of the lagging bridge arm provided in an embodiment of the present application.

[0043] Figure 11 This is the waveform of the junction capacitance and leakage inductance current of the lagging bridge arm of the traditional phase-shifted full-bridge converter. The horizontal axis represents time (s), and the vertical axis represents voltage (V) and current (A) respectively.

[0044] Figure 12 This is a waveform diagram of the junction capacitance and leakage inductance current of the lagging bridge arm provided in an embodiment of the present application; the horizontal axis represents time (s), and the vertical axis represents voltage (V) and current (A) respectively.

[0045] Figure 13 This is a key waveform diagram provided by an embodiment of the present application when the load is 20%; the horizontal axis represents time (s), and the vertical axis represents voltage (V), current (A), current (A), and voltage (V) in sequence.

[0046] Figure 14 : This is a soft switching waveform diagram of the switch tube Q1 provided in an embodiment of the present application, where (a) corresponds to 20% load, (b) corresponds to 50% load, and (c) corresponds to full load; the horizontal axis represents time (s), and the vertical axis represents the drive signal, voltage (V), and current (A) of Q1 respectively.

[0047] Figure 15 These are the soft-switching waveforms of switch Q3 provided in an embodiment of the present application. (a) corresponds to 20% load, (b) corresponds to 50% load, and (c) corresponds to full load. The horizontal axis represents time (s), and the vertical axis represents Q3's drive signal, voltage (V), and current (A), respectively. DETAILED DESCRIPTION

[0048] In order to make the purpose, technical solutions and advantages of this application more clear, the following further describes this application in detail with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain this application and are not intended to limit this application.

[0049] The term "and / or" as used herein describes an association between related objects, indicating that three possible relationships exist. For example, "A and / or B" can represent: A exists alone, A and B exist simultaneously, or B exists alone. The symbol " / " as used herein indicates that the related objects are in an "or" relationship, for example, A / B means either A or B.

[0050] The terms "first" and "second" in this specification and claims are used to distinguish different objects rather than to describe a specific order of objects. For example, "first response message" and "second response message" are used to distinguish different response messages rather than to describe a specific order of response messages.

[0051] In the embodiments of this application, words such as "exemplary" or "for example" are used to indicate examples, illustrations, or descriptions. Any embodiment or design described as "exemplary" or "for example" in the embodiments of this application should not be interpreted as being preferred or advantageous over other embodiments or designs. Rather, the use of words such as "exemplary" or "for example" is intended to present the relevant concepts in a concrete manner.

[0052] In the description of the embodiments of the present application, unless otherwise specified, "multiple" means two or more, for example, multiple processing units means two or more processing units, etc.; multiple elements means two or more elements, etc.

[0053] The embodiments of the present application are described below in conjunction with the drawings in the embodiments of the present application.

[0054] like Figure 1 As shown, the present application provides a dual half-bridge soft switching converter, the input side of which is mainly composed of two symmetrical half-bridge circuits connected in parallel. r1 and T r2 ) The primary side is placed in parallel, and the rectifier circuit on the secondary side of the transformer is composed of a full-bridge rectifier circuit. The first half-bridge circuit consists of two switching tubes Q1 and Q2, the first transformer T r1 The primary winding and its primary leakage inductance L r1 , two input voltage dividing capacitors C1 and C2, the second half-bridge circuit consists of two switch tubes Q3 and Q4, the second transformer T r2 The primary winding and its primary leakage inductance L r2 , two input voltage divider capacitors C1 and C2, two input voltage divider capacitors C1 and C2 are used to divide the input voltage. Q1~Q4 are all MOSFETs (including their own body diodes D b1 ~ D b4 and parasitic capacitance C oss1 ~ C oss4 ), the gate of Q1 and the drain of Q2 are connected to the same-name terminal of transformer Tr1, the gate of Q3 and the drain of Q4 are connected to the same-name terminal of transformer Tr2, the drains of Q1 and Q3 are connected to the input positive bus together with C1, and the gates of Q2 and Q4 are connected to the input positive bus together with C2; and the two half-bridge circuits share C1 and C2.

[0055] Its output side includes two secondary windings of transformers, four rectifier diodes D R1 ~ D R4 Among them, D R1 Anode, D R2 The cathode of Tr1 is connected to the same end of the secondary winding. R3 Anode, D R4 The cathode of Tr2 is connected to the opposite end of the secondary winding, D R1 and D R3 and output filter inductor L o One end is connected to the output filter capacitor C o Positive electrode and L o The other end is connected to C o Negative electrode and D R1 and D R3 The anode of the transformer is connected, and the two secondary winding ends of the transformer are directly connected in series in the same direction as the rectifier circuit D R1 ~ D R4 input.

[0056] The present application provides a control method for a dual half-bridge soft switching converter. The converter adopts fixed-frequency phase-shift PWM control with a switching period of T s , the driving of the first switch tube Q1 and the second switch tube Q2 in the leading bridge arm has the same duty cycle D c , D c =0.5 (including dead time), and the phase difference between the two is 0.5T s The driving duty cycle of the third switch Q3 and the fourth switch Q4 in the lagging bridge arm are both 0.5 (including dead time), and the phase difference between the two is 0.5T. s The driving of switches Q3 and Q4 in the lagging bridge arm lags behind that of the leading bridge arm, Q1, and Q2, respectively. By controlling the phase shift angle θ (0° < θ < 180°) between the leading and lagging bridge arms, the combined on-time of switches Q1 (Q2) and Q4 (Q3) varies accordingly, thereby regulating the overall converter's transmission power and output voltage.

[0057] The driving duty cycle of Q1 through Q4 is 0.5 (including dead time), and Q1 and Q2 (Q3 and Q4) are complementary. Furthermore, the phase shift angle between Q1 and Q3 is θ, with Q1 leading Q3. Therefore, Q1 and Q2 are leading-arm switches, while Q3 and Q4 are lagging-arm switches. Before analyzing the operating principle of the converter proposed in this application in detail, the following assumptions can be made:

[0058] 1) Output filter inductor L o Large enough, the output can be regarded as a constant current source I o ;

[0059] 2) The voltage divider capacitors C1 and C2 are equal and large enough, so the terminal voltages V1 and V2 of both are the input voltage V in Half of V1=V2=V in / 2;

[0060] 3) The parasitic capacitance of the four MOSFETs is equal, that is, C oss1 =C oss2 =C oss3 =C oss4 =C oss ;

[0061] 4)T r1 and T r2 The ratio of the number of secondary turns to the number of primary turns is n, and n is less than 1.

[0062] The typical operating waveform corresponding to the dual half-bridge soft switching converter is as follows: Figure 2 As shown. Among them, t 0~ t 7 is half a complete switching cycle, and half a switching cycle includes 7 switching modes. According to the symmetry of the main circuit topology and working principle of this application, only the first half switching cycle is analyzed below. t 0~ t The five working modes in 7 correspond to Figures 3 to 9 , where node A represents the midpoint of the leading bridge arm, node B represents the midpoint of the lagging bridge arm, and node C represents the midpoint of the voltage divider capacitors C1 and C2:

[0063] Mode 1 [before time t0]: The current path of this mode is as follows Figure 3 In this mode, Q2 and Q4 are in the on state (under phase-shifted fixed-frequency PWM control, refer to the working waveform to determine the on state), T r1 and T r2 The primary current i p1 and i p2 All flow out from the positive electrode of C2 and flow through T r1 The primary winding, L r1 , Q2 and T r2 The primary winding, L r2 , Q4 returns to the negative terminal of C2, so the voltage v between nodes A and C AC , the voltage v between nodes B and C BC All are –V in / 2. From this we can see that the magnetizing inductance L m1 and L m2 The current i Lm1 and i Lm2 is decreasing linearly. At the same time, T r1 and T r2 The secondary winding voltage Vs1 and V s2 All are –nV in / 2, so D R2 and D R3 Natural conduction, rectified output voltage V rec -nV in , that is, v s1 and v s2 Obviously, in this mode, D R2 The current i DR2 For I o , after converting it to the original side, we can get i p1 and i p2 The expression is (ignoring the voltage drop on the leakage inductance, v AC and v BC All added to the magnetizing inductance):

[0064]

[0065] in, I 1 represents the primary current at time t1.

[0066] Mode 2 [t0, t1]: The current path of this mode is as follows Figure 4 As shown. Time t0 corresponds to the moment when Q2 is turned off, i p2 The current path remains unchanged, and i p1 Then give C oss2 While charging, it also charges C oss1 Discharge. Due to the existence of C1 and C2, the secondary side in this mode still has only D R2 and D R3 conduction, which can be equivalent to L r1 and L o Connect in series to C oss2 and C oss1 Therefore, the charging and discharging of the two parasitic capacitors can be completed in a very short time (the magnitude and direction of all currents can be considered unchanged), that is, C oss2 The terminal voltage rises from zero to V in , and C oss1 The terminal voltage is determined by V in drops to zero. Therefore, v AC Also from –V in / 2 becomes V in / 2, and v BC Then keep –V in / 2 remains unchanged.

[0067] Mode 3 [t1, t3]: The current path of this mode is as follows Figure 5 As shown. Since at time t1 C oss1 The terminal voltage drops to zero, so i p1The current flowing through the body diode D of Q1 b1 Without loss of generality, time t2 corresponds to the moment when Q1 is turned on. Obviously, ZVS turn-on of Q1 can be achieved. In this mode, v AC V in / 2 and v BC -V in / 2, so that v s1 and v s2 nV respectively in / 2 and –nV in / 2, and V rec is zero. Therefore, the four rectifier diodes in this mode are turned on at the same time. Similarly, ignoring the voltage drop on the leakage inductance, v AC and v BC If all of them are added to the magnetizing inductance, we can get i p1 and i p2 satisfy:

[0068]

[0069] It can be seen that due to i p1 and i p2 The actual change is not big, and the current change converted to the secondary side is even smaller, so in this mode, it can be considered that i DR2 Approximately I o , and D R1 The current i DR1 Approximately zero.

[0070] Mode 4 [t3, t4]: The current path of this mode is as follows Figure 6 As shown. Time t3 corresponds to the moment when Q4 is turned off, i p1 The current path remains unchanged, and i p2 Then give C oss4 While charging, it also charges C oss3 Discharge. Due to the presence of C1 and C2, there is no need for L r2 Providing energy can quickly achieve C oss4 and C oss3 The charge and discharge, that is, C oss4 The terminal voltage rises from zero to V in , and C oss3 The terminal voltage is determined by V in drops to zero. Therefore, v BC Also from –V in / 2 becomes V in / 2, and v AC Then keep V in / 2 remains unchanged.

[0071] Mode 5 [t4, t6]: The current path of this mode is as follows Figure 7 As shown. Time t4 corresponds to Coss3 The terminal voltage is determined by V in The moment when v drops to zero. Although the four diodes are turned on at the same time in the previous mode, the actual commutation process is not carried out. In this mode, v s1 and v s2 are all zero, which means that L m1 and L m2 The voltage across both ends is also zero, so L r1 and L r2 The voltage at both ends is V in / 2, resulting in i p1 and i p2 It rises rapidly and can be expressed as:

[0072]

[0073] in i p1 and i p2 Under the rapid linear change of the secondary side, i DR2 Rapid linear decline, and i DR1 Rapid linear rise. At t6, i p1 and i p2 Therefore, Q3 must be turned on before time t6 to achieve ZVS. For example, if Q3 is turned on at time t5, then time t5 corresponds to a time before t6.

[0074] Mode 6 [t6, t7]: The current path of this mode is as follows Figure 8 In this mode, i p1 and i p2 Continue to rise rapidly, D R1 and D R2 The commutation continues, and time t7 indicates the time when the commutation is completed. Figure 2 When the current in the secondary diode becomes stable, the commutation is completed.

[0075] Mode 7 (t7 to the start of the next cycle): The current path of this mode is as follows Figure 9 In this mode, Q1 and Q3 are in the on state, i p1 and i p2 All flow out from the positive electrode of C1 and flow through Q1 and L r1 、T r1 The primary winding and Q3, L r2 、T r2 The primary winding of the capacitor returns to the negative terminal of C1, so v AC and v BC Both are V in / 2. From this we can see that i Lm1 and i Lm2is linearly increasing. At the same time, v s1 and v s2 All nV in / 2, so the secondary rectifier diode is only D R1 and D R4 On, V rec nV in .

[0076] This application controls the phase shift time between the leading bridge arm and the lagging bridge arm by adjusting the opening time of t2 (equal to ), which can realize the regulation of converter transmission power and boost ratio.

[0077] The following is an example to illustrate the technical solution of this application:

[0078] At t1, the voltage across Q1 in the leading bridge arm decreases to zero. At this time, the parasitic diode of Q1 is turned on, and the leading bridge arm switch can achieve ZVS conduction. In the period [t1-t3], it can be divided into C oss2 with C oss1 Linear charge and discharge and LC resonance process. Output filter inductor L o Equivalent to connecting the transformer T in series r1 On the primary side, due to the output filter inductor L o Very large and related to the transformer primary leakage inductance L r When connected in series, it can be equivalent to a constant current source to charge and discharge the junction capacitance, and the energy can easily satisfy the following formula:

[0079]

[0080] At this time, the leakage inductance L r and output filter inductor L o There is enough energy to pump away C oss1 and give the same bridge arm C oss2 Charging, when C oss1 When the voltage across the two ends is zero, the parasitic diode of Q1 is turned on, and the leading bridge arm switch can achieve ZVS conduction. The time of this mode is:

[0081]

[0082] In order to ensure that the leading tube Q1 can be turned on at zero voltage, the dead time t between the Q1 and Q2 drive signals needs to be met. d(lead) >t 01 ,Right now:

[0083]

[0084] In order to simplify the model and facilitate analysis, the lagging bridge arms of the traditional full-bridge converter and the converter proposed in this application are equivalent to the following: Figure 10 The simulation parameters of the circuits shown in (a) and (b) are set as follows: Input voltage V in =320V, transformer leakage inductance L r = 5.6μH, parasitic capacitance C oss3 、C oss4 、C oss5 and C oss6 Both are 65pF, and the voltage divider capacitors C1 and C2 are both 3mF.

[0085] For the traditional full-bridge converter, during the switching process of the lagging bridge arm, the secondary side of the transformer is short-circuited, and the corresponding primary side voltage is all added to the leakage inductance L. r On. Figure 10 The equivalent circuit of the lagging bridge arm of the traditional shifted full-bridge converter shown in (a) is shown in Figure 1. The input power supply voltage is V in , the parasitic capacitance of the lagging bridge arm is C oss5 and C oss6 , the capacitance is In C oss5 From V in In the process of falling to zero, the current flowing out of the power supply is C oss5 du / dt, the energy W1 released by the power supply can be expressed as:

[0086]

[0087] It is known that W1 is a negative number, which means that W1 is the energy absorbed by the power supply. Due to the law of conservation of energy, it is known that in C oss5 with C oss6 During the discharge and charge process, this energy needs to be transferred by the leakage inductance L r Provided, the maximum energy W2 that the leakage inductance can provide is:

[0088]

[0089] The equivalent circuit is simulated by PLECS software to analyze the parasitic capacitance C of the lagging bridge arm switch tube. oss5 and C oss6 and leakage inductance L r The resonance situation is simulated and verified under light load conditions. Given L r The initial current is 0.5A, C oss5 and C oss6 The voltage waveform and leakage inductance L r The current waveform is as follows Figure 11 shown.

[0090] Under light load conditions, the filter inductor L o It is not connected in series with the original side, and it is difficult to satisfy W2>|W1|, and C will appear oss5The voltage has not yet risen to V in , C oss6 The voltage has not dropped to zero, but the primary current has already decreased to zero. If C is turned on at this time, oss6 For the corresponding switch tube, zero voltage turn-on cannot be achieved.

[0091] At t3, when Q4 is turned off, the output rectifier circuit is in the commutation process, V rec The voltage is clamped at zero, then the transformer secondary side V s1 and V s2 The voltage is zero, so the primary voltage of the transformer is also zero, V BC The voltage is all added to the leakage inductance L r Above, such as Figure 10 (b) is the equivalent circuit of the lagging bridge arm of the converter proposed in this application, where C1 and C oss3 and leakage inductance L r In the circuit composed of C oss3 From V in In the process of falling to zero, the current flowing out of C1 is I2=C oss3 du / dt, the energy W3 released by C1 can be expressed as:

[0092]

[0093] Similarly, in C2 and C oss4 and leakage inductance L r In the circuit composed of C oss4 From zero to V in In the process, the current flowing out of C2 is I3=C oss4 du / dt, the energy W4 released by C2 can be expressed as:

[0094]

[0095] In the entire loop of the equivalent circuit, the sum of the energy absorbed by C1 and the energy released by C2 is zero, satisfying the law of conservation of energy. At this time, the leakage inductance L r As a resonant inductor only, even under light load conditions, two voltage divider capacitors can still be used to achieve C oss3 with C oss4 The process of discharging and charging can achieve ZVS in the full range of loads.

[0096] When the energy is sufficient, it is necessary to select a suitable moment to turn on the lagging bridge arm switch tube, such as at time t6, i p1 and i p2 Therefore, Q3 must be turned on before time t6 to achieve ZVS. From formula (3), we can see that i p1 The time required for (t4) to rise to zero is:

[0097]

[0098] In order to ensure that the hysteresis tube Q3 can be turned on at zero voltage, the dead time t between the Q3 and Q4 drive signals needs to be met. d(lag) <t 46 ,Right now:

[0099]

[0100] The equivalent circuit simulation is also performed by PLECS software to analyze the parasitic capacitance C of the lagging bridge arm switch tube of the converter proposed in this application. oss3 and C oss4 and leakage inductance L r The resonance situation is simulated and verified under light load conditions. Given L r The initial current is 0A to verify the full range load ZVS function of the converter proposed in this application, where C oss5 and C oss6 The voltage waveform and leakage inductance L r The current waveform is as follows Figure 12 As shown. The energy of W1 and W2 cancels out, and the leakage inductance L r As a resonant inductor only, it can still achieve zero voltage switching of the lagging bridge arm under light load conditions. When the voltage across Q3 in the lagging bridge arm decreases to zero, the parasitic diode of Q3 is turned on, and the lagging bridge arm switch can achieve ZVS conduction.

[0101] The converter proposed in this application is simulated and analyzed in PLECS. Table 1 lists the specifications of simulation parameters in an embodiment shown. Figure 13 The key waveforms of the converter proposed in this application at 20% full load are shown. It can be seen that at 20% of full load, v AC and v BC The value of i p1 and i p2 The values ​​of are almost the same. Therefore, the power transferred by both transformers is roughly the same.

[0102] Table 1 Experimental parameters

[0103]

[0104] Figure 14 The gate drive, voltage and current of the leading bridge arm switch Q1 under different load powers are shown. According to the analysis in Section 2, the realization condition of ZVS in Q1 is determined by the output filter inductor L oTherefore, Q1 can easily achieve ZVS under different loads. Similarly, Q2's operating state is the same as Q1, so Q2 can also achieve ZVS at the same time.

[0105] The ZVS of the lagging bridge arm switch Q3 is implemented as follows: Figure 15 As shown in Figure 1, it shows the gate drive, voltage and current of switch Q3 under different load powers. By zooming in on the waveform, it can be seen that ZVS turn-on is clearly achieved under different loads. In addition, due to v C1 and v C2 The peak value of Q3 does not change at different powers, and the voltage peak value of Q3 is almost the same at different loads. Figure 14 and Figure 15 Looking at the voltage waveforms of Q1 and Q3, we can see that they have the same voltage peak.

[0106] It should be understood that the above-mentioned device is used to execute the method in the above-mentioned embodiment. The implementation principle and technical effect of the corresponding program module in the device are similar to those described in the above-mentioned method. The working process of the device can refer to the corresponding process in the above-mentioned method and will not be repeated here.

[0107] Based on the method in the above embodiment, an embodiment of the present application provides a computer-readable storage medium, which stores a computer program. When the computer program runs on a processor, the processor executes the method in the above embodiment.

[0108] Based on the method in the above embodiment, an embodiment of the present application provides a computer program product. When the computer program product runs on a processor, the processor executes the method in the above embodiment.

[0109] It is understood that the processor in the embodiments of the present application may be a central processing unit (CPU), other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), field programmable gate arrays (FPGA), other programmable logic devices, transistor logic devices, hardware components, or any combination thereof. The general-purpose processor may be a microprocessor or any conventional processor.

[0110] The method steps in the embodiments of the present application can be implemented by hardware or by a processor executing software instructions. The software instructions can be composed of corresponding software modules, which can be stored in random access memory (RAM), flash memory, read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), registers, hard disks, mobile hard disks, CD-ROMs, or any other form of storage medium known in the art. An exemplary storage medium is coupled to the processor so that the processor can read information from the storage medium and write information to the storage medium. Of course, the storage medium can also be an integral part of the processor. The processor and storage medium can be located in an ASIC.

[0111] The above embodiments can be implemented in whole or in part using software, hardware, firmware, or any combination thereof. When implemented using software, they can be implemented in whole or in part in the form of a computer program product. The computer program product comprises one or more computer instructions. When loaded and executed on a computer, the computer program instructions fully or partially produce the processes or functions described in the embodiments of this application. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium or transmitted via the computer-readable storage medium. The computer instructions can be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via wired (e.g., coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) means. The computer-readable storage medium can be any available medium accessible by a computer or a data storage device such as a server or data center that integrates one or more available media. The available medium can be magnetic media (e.g., floppy disk, hard disk, tape), optical media (e.g., DVD), or semiconductor media (e.g., solid-state drive (SSD)).

[0112] It will be understood that the various numerical numbers involved in the embodiments of the present application are merely distinctions for the convenience of description and are not intended to limit the scope of the embodiments of the present application.

[0113] It is easy for those skilled in the art to understand that the above is only a preferred embodiment of the present application and is not intended to limit the present application. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present application should be included in the scope of protection of the present application.

Claims

1. A control method for a dual half-bridge soft-switching converter, characterized in that: The input side of the dual half-bridge soft-switching converter is composed of two symmetrical half-bridge circuits, and the two half-bridge circuits share a first voltage-dividing capacitor and a second voltage-dividing capacitor; wherein the first half-bridge circuit includes a leading bridge arm, a primary winding of a first transformer and its primary leakage inductance, a first voltage-dividing capacitor and a second voltage-dividing capacitor, and the second half-bridge circuit includes a lagging bridge arm, a primary winding of a second transformer and its primary leakage inductance, a first voltage-dividing capacitor and a second voltage-dividing capacitor; wherein Q1 and Q2 are leading bridge arm switches, Q3 and Q4 are lagging bridge arm switches, and Q1 and Q2 are complementary turned on, Q3 and Q4 are complementary turned on, and Q1 is ahead of Q3; the switches in the leading bridge arm and the lagging bridge arm are both MOSFETs; the output side of the dual half-bridge soft-switching converter includes the secondary windings of two transformers, a rectifier circuit, an output filter inductor and an output filter capacitor, and the two secondary windings are directly connected in series in the same direction as the input of the rectifier circuit. The control method includes: In the symmetrical half switching cycle, At this moment, Q1 in the leading bridge arm is turned on. Always turn on Q3 in the lagging bridge arm; The following conditions are met between each moment: in, is the moment to turn off Q2, is the moment when the terminal voltage of the parasitic capacitor in Q1 drops to zero, is the moment to turn off Q4, is the moment when the terminal voltage of the parasitic capacitor in Q3 drops to zero, is the moment when the primary currents of the two transformers rise to zero. for and The length of time between for and The length of time between is the MOSFET parasitic capacitance, is the input voltage of the dual half-bridge soft-switching converter, is the primary current of the first transformer at the corresponding moment, is the primary leakage inductance of the first transformer.

2. The control method according to claim 1, wherein: Dead time between Q1 and Q2 drive signals Exceed .

3. The control method according to claim 1, wherein: Dead time between Q3 and Q4 drive signals Less than .

4. The control method according to claim 1, wherein: The phase shift angle of Q1 leads that of Q3 satisfy: in, is the switching period of phase-shift PWM control.

5. The control method according to claim 4, wherein: The output voltage of the dual half-bridge soft-switching converter is adjusted by controlling the phase shift angle, thereby adjusting the transmission power and / or the boost ratio.

6. A control system for a dual half-bridge soft-switching converter, characterized in that: comprising at least one processor and at least one memory; The at least one memory is configured to store computer instructions; The at least one processor is configured to execute at least part of the computer instructions to implement the control method according to any one of claims 1 to 5.

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