Bias voltage circuit, duty ratio calibration circuit, starting method, chip and equipment

Abstract

The invention belongs to the field of electronic circuits, and particularly relates to a bias voltage circuit for a duty ratio calibration circuit, the duty ratio calibration circuit, a starting method, a chip and electronic equipment. The bias voltage circuit comprises a bias main body circuit and an acceleration circuit, and the acceleration circuit is connected with the bias main body circuit; the bias main body circuit is used for providing bias voltage; the acceleration circuit is used for reducing the RC time constant of the bias main body circuit in the starting stage of the bias main body circuit. According to the bias voltage circuit, the acceleration circuit is additionally arranged, so that the RC time constant of the bias main body circuit is reduced in the starting stage of the bias main body circuit, the response speed of the circuit is improved, the bias voltage rising speed of the bias voltage circuit is improved, and the time for the bias voltage to reach a specified voltage value is shortened.

Description

Technical Field

[0001] The present application belongs to the field of electronic circuits, and specifically relates to a bias voltage circuit for a duty cycle calibration circuit, a duty cycle calibration circuit and a startup method, a chip and an electronic device. Background Art

[0002] Duty cycle calibration circuits are widely used in various types of circuits. Usually, duty cycle calibration circuits have a reset function. When the duty cycle calibration circuit enters the reset state, the bias voltage will slowly rise to a specific voltage value, while helping the circuit to establish a suitable operating point. When the circuit switches from the reset state to the bias state, the appropriate bias voltage can enable the operational amplifier in the duty cycle calibration circuit to quickly enter the bias state, reducing the possibility of errors caused by inappropriate operating points.

[0003] In the existing duty cycle calibration circuit, the bias voltage is mostly generated by the bias voltage circuit based on the voltage division method, and is sent to the input end of the operational amplifier after passing through the RC (Resistor Capacitor) filter. Generally, the bias voltage is quickly raised to a specific voltage value by short-circuiting the resistor in the filter by waiting for multiple clock cycles. When the clock speed is high, the reset time will become shorter after waiting for a fixed clock cycle. Since the bias voltage load is heavy, this method will cause the bias voltage to rise slowly, making it difficult to reach a specific suitable voltage value, which may cause the duty cycle calibration circuit to be difficult to start. Summary of the invention

[0004] In view of this, the purpose of the present application is to provide a bias voltage circuit, a duty cycle calibration circuit and a startup method, a chip and an electronic device for a duty cycle calibration circuit, so as to improve the problem that the bias voltage of the existing bias voltage circuit rises slowly under high-speed clock conditions and is difficult to reach the specified voltage value.

[0005] The embodiment of the present application is implemented as follows:

[0006] In a first aspect, an embodiment of the present application provides a bias voltage circuit, comprising: a bias main circuit and an acceleration circuit, wherein the acceleration circuit is connected to the bias main circuit; the bias main circuit is used to provide a bias voltage; and the acceleration circuit is used to reduce the RC time constant of the bias main circuit during the startup phase of the bias main circuit.

[0007] In the above embodiment, an acceleration circuit is added to the bias voltage circuit so as to reduce the RC time constant of the bias main circuit during the startup phase of the bias main circuit, thereby improving the response speed of the circuit, thereby increasing the bias voltage rising speed of the bias voltage circuit, and shortening the time for the bias voltage to reach a specified voltage value.

[0008] In combination with a possible implementation manner of the embodiment of the first aspect, the bias main circuit includes a voltage divider circuit, the acceleration circuit is connected in parallel with at least some devices in the voltage divider circuit, the equivalent impedance of the acceleration circuit is less than or equal to the equivalent impedance of the voltage divider circuit, and the acceleration circuit includes a switch; when the bias voltage circuit is in a startup stage, the switch of the acceleration circuit is in a closed state; when the bias voltage circuit is in a bias stage, the switch of the acceleration circuit is in an open state.

[0009] In the above embodiment, since the equivalent impedance of the acceleration circuit is less than or equal to the equivalent impedance of the voltage divider circuit, when the acceleration circuit is connected in parallel with the bias main circuit, the equivalent impedance of the entire circuit will be reduced, thereby reducing the RC time constant of the circuit. At the same time, since the acceleration circuit includes a switch, it is possible to select whether to enable the acceleration circuit by controlling the closing or opening of the switch. For example, when the bias voltage circuit is in the startup stage, the switch of the acceleration circuit is in a closed state, and at this time, the acceleration circuit is enabled; when the bias voltage circuit is in the bias stage, the switch of the acceleration circuit is in an open state, and at this time, it is equivalent to that the acceleration circuit is inoperative.

[0010] In combination with a possible implementation manner of the embodiment of the first aspect, the voltage-dividing circuit includes a first switch branch and a second switch branch connected in series, and the connecting end of the first switch branch and the second switch branch is a voltage-dividing end; one end of the first switch branch is connected to a power supply, and one end of the second switch branch is grounded; the acceleration circuit includes a third switch branch and a fourth switch branch, a first end of the third switch branch is connected to the power supply, a second end of the third switch branch is connected to the first switch branch, and the third switch branch is connected in parallel with at least some of the devices in the first switch branch; a first end of the fourth switch branch is grounded, a second end of the fourth switch branch is connected to the second switch branch, and the fourth switch branch is connected in parallel with at least some of the devices in the second switch branch.

[0011] In the above embodiment, by connecting the third switch branch in parallel with at least part of the devices in the first switch branch, the equivalent impedance of the first switch branch and the third switch branch can be reduced, and by connecting the fourth switch branch in parallel with at least part of the devices in the second switch branch, the equivalent impedance of the second switch branch and the fourth switch branch can be reduced. In this way, the equivalent impedance of the entire circuit can be reduced, thereby reducing the RC time constant of the circuit. At the same time, the above-mentioned acceleration circuit has a relatively simple structure, low cost, and does not require too much area.

[0012] In combination with a possible implementation manner of the embodiment of the first aspect, the third switch branch and the fourth switch branch are connected in series, the second end of the third switch branch is connected to the voltage divider end of the first switch branch, and the second end of the fourth switch branch is connected to the voltage divider end of the second switch branch; or, the second end of the third switch branch is connected to an internal endpoint in the first switch branch, and the second end of the fourth switch branch is connected to an internal endpoint in the first switch branch.

[0013] In the above embodiment, when the second end of the third switch branch is connected to the voltage-dividing end of the first switch branch, and the second end of the fourth switch branch is connected to the voltage-dividing end of the second switch branch, at this time, the third switch branch is connected in parallel with all the devices in the first switch branch, and the fourth switch branch is connected in parallel with all the devices in the second switch branch. Without introducing a new connection point, the RC time constant of the circuit can be reduced, and at the same time, the RC time constant of the circuit can be reduced to a greater extent; or, when the second end of the third switch branch is connected to the internal endpoint in the first switch branch, and the second end of the fourth switch branch is connected to the internal endpoint in the first switch branch, at this time, the third switch branch is connected in parallel with some devices in the first switch branch, and the fourth switch branch is connected in parallel with some devices in the second switch branch. This method can also reduce the RC time constant of the circuit and increase the flexibility of the scheme selection.

[0014] In combination with a possible implementation manner of the embodiment of the first aspect, a voltage division ratio of the first equivalent resistor and the second equivalent resistor is consistent with a voltage division ratio of the first switch branch and the second switch branch, wherein the first equivalent resistor is the equivalent resistor after the third switch branch is connected in parallel with the first switch branch; and the second equivalent resistor is the equivalent resistor after the fourth switch branch is connected in parallel with the second switch branch.

[0015] In the above embodiment, the voltage division ratio of the first equivalent resistor and the second equivalent resistor is consistent with the voltage division ratio of the first switch branch and the second switch branch, which reduces the influence of the acceleration circuit on the circuit bias voltage, does not change the voltage division ratio, and thus does not change the magnitude of the bias voltage, thereby reducing the need for subsequent process design to correct the bias voltage due to changes in the voltage division ratio.

[0016] In combination with a possible implementation manner of the embodiment of the first aspect, the third switch branch and the fourth switch branch both include a switch tube and a resistor connected in series.

[0017] In the above embodiment, the acceleration circuit only needs a few switching tubes and small resistors, which is low in cost, does not require much area, and does not require changes to the original circuit, thereby minimizing the impact of the acceleration circuit on the circuit bias main circuit.

[0018] In combination with a possible implementation manner of the embodiment of the first aspect, the bias voltage circuit also includes a control circuit, which is connected to the bias main circuit and the switching tube in the acceleration circuit, and the control circuit is used to control the state of the switching tube.

[0019] In the above embodiment, a control circuit is added to control the state of the switch tube in the bias main circuit and the acceleration circuit, so that the acceleration circuit only works when the bias voltage circuit is started, and enters the reset state at the initial startup, which greatly reduces the equivalent impedance of the voltage divider node, thereby reducing the RC time constant, and can quickly pull the bias voltage to the desired voltage value, saving startup time. When the bias voltage is stable, the acceleration circuit will be turned off to reduce power consumption.

[0020] In combination with a possible implementation manner of the embodiment of the first aspect, the bias main circuit includes a voltage divider circuit and an output circuit; the output circuit is connected to the voltage divider end of the voltage divider circuit; the output circuit includes: a switching tube and a filter resistor, and the switching tube is connected in parallel with the filter resistor; when the bias voltage circuit is in the startup stage, the switching tube is in a closed state; when the bias voltage circuit is in the bias stage, the switching tube is in a disconnected state.

[0021] In the above embodiment, the charging and discharging time of the Vref node (output bias voltage) is further changed by controlling the closing or opening of the switch tube. For example, when the bias voltage circuit is in the startup stage, the switch tube is turned on to short-circuit the filter resistor, thereby further reducing the charging and discharging time of the Vref node. Therefore, the bias voltage Vref can be quickly pulled up to a specific voltage value; and when the bias voltage circuit is in the bias stage, the switch tube is turned off, and the equivalent impedance at the Vref node is large, which can reduce the impact on the subsequent circuit.

[0022] In a second aspect, an embodiment of the present application further provides a duty cycle calibration circuit, comprising a bias voltage circuit as provided in the above-mentioned first aspect embodiment and / or any possible implementation method in combination with the first aspect embodiment.

[0023] In a third aspect, an embodiment of the present application further provides a chip, comprising: a duty cycle calibration circuit as provided in the embodiment of the second aspect above.

[0024] In a fourth aspect, an embodiment of the present application further provides a method for starting a duty cycle calibration circuit, wherein the duty cycle calibration circuit includes a bias voltage circuit as provided in the above-mentioned first aspect embodiment and / or any possible implementation method in combination with the first aspect embodiment, and the method includes: in a startup phase, controlling the bias main circuit to provide a bias voltage; controlling the acceleration circuit to reduce the RC time constant of the bias main circuit.

[0025] In a fifth aspect, an embodiment of the present application further provides an electronic device, comprising: a chip as provided in the embodiment of the third aspect above.

[0026] Other features and advantages of the present application will be described in the following description. The purpose and other advantages of the present application can be realized and obtained through the structures specifically pointed out in the written description and the drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For those of ordinary skill in the art, other drawings can also be obtained based on these drawings. The above and other purposes, features and advantages of the present application will be more clearly shown in the drawings.

[0028] Figure 1 A schematic structural diagram of a bias voltage circuit for a duty cycle calibration circuit provided in an embodiment of the present application is shown.

[0029] Figure 2 A circuit diagram of a bias main body circuit provided in an embodiment of the present application is shown.

[0030] Figure 3a A schematic diagram showing the connection between a voltage divider circuit and an acceleration circuit provided in an embodiment of the present application is shown.

[0031] Figure 3b A schematic diagram showing the connection between another voltage divider circuit and an acceleration circuit provided in an embodiment of the present application is shown.

[0032] Figure 4a A circuit diagram of a bias voltage circuit provided in an embodiment of the present application is shown.

[0033] Figure 4b A circuit diagram of another bias voltage circuit provided in an embodiment of the present application is shown.

[0034] Figure 5 A schematic structural diagram of an electronic device provided in an embodiment of the present application is shown. DETAILED DESCRIPTION

[0035] The technical solutions in the embodiments of the present application will be described below in conjunction with the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all of the embodiments. The following embodiments can be used as examples to more clearly illustrate the technical solutions of the present application, and cannot be used to limit the scope of protection of the present application. It will be appreciated by those skilled in the art that, in the absence of conflict, the features in the following embodiments and embodiments can be combined with each other.

[0036] It should be noted that similar numbers and letters represent similar items in the following figures, so once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures. At the same time, in the description of this application, relational terms such as "first", "second", etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "comprise", "include" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device.

[0037] Furthermore, the term "and / or" in this application is merely a term used to describe the association relationship between associated objects, indicating that three relationships may exist. For example, A and / or B may represent three situations: A exists alone, A and B exist at the same time, and B exists alone.

[0038] In the description of the embodiments of the present application, unless otherwise clearly specified or limited, the technical term "connection" may refer to a direct connection or an indirect connection through an intermediate medium.

[0039] In view of the short reset duration under high-speed clock, the bias voltage of the existing bias voltage circuit for duty cycle calibration circuit is difficult to reach the specified voltage value. The embodiment of the present application provides a solution for quickly starting the bias voltage circuit, which can improve the response speed of the bias voltage circuit, improve the bias voltage rising speed of the bias voltage circuit, and shorten the time for the bias voltage to reach the specified voltage value.

[0040] Combine the following Figure 1 The circuit structure shown is used to illustrate the bias voltage circuit for the duty cycle calibration circuit provided in the embodiment of the present application. The bias voltage circuit provided in the embodiment of the present application includes: a bias main circuit and an acceleration circuit, and the acceleration circuit is connected to the bias main circuit.

[0041] The bias main circuit is used to provide a bias voltage. The acceleration circuit is used to reduce the RC time constant of the bias main circuit during the startup phase of the bias main circuit. The present application increases the response speed of the circuit by adding an acceleration circuit so as to reduce the RC time constant of the bias main circuit during the startup phase of the bias main circuit, thereby increasing the bias voltage rise speed of the bias voltage circuit and shortening the time for the bias voltage to reach a specified voltage value.

[0042] In a possible implementation manner, the bias main circuit includes: a voltage divider circuit and an output circuit, and the output circuit is connected to the voltage divider end of the voltage divider circuit.

[0043] The voltage divider circuit includes a first switch branch and a second switch branch connected in series, one end of the first switch branch is connected to a power supply, one end of the second switch branch is grounded, and the connection end of the first switch branch and the second switch branch is a voltage divider end, such as the voltage divider end represented by a Vrt node. In one implementation, the first switch branch and the second switch branch both include a switch tube and a resistor connected in series.

[0044] The output circuit may include: a switch tube and a filter resistor, the switch tube and the filter resistor are connected in parallel. When the bias voltage circuit is in the startup phase (reset state), the switch tube is in a closed state; when the bias voltage circuit is in the bias phase (bias state), the switch tube is in an open state. In one embodiment, the output circuit may also include a filter capacitor connected in series with the filter resistor.

[0045] In one possible implementation, the circuit schematic diagram of the bias main circuit is as follows: Figure 2 As shown, R0 is a filter resistor and M0 is a switch tube in the output circuit. Resistor R2 and switch tube M2 are included in the first switch branch, and switch tube M1 and resistor R1 are included in the second switch branch. When the bias main circuit is in the reset state, M1, M0, and M2 are all turned on, that is, they are in a closed state. M0 is turned on to achieve a short circuit for R0, further reducing the charging and discharging time of the Vref node. When the bias main circuit is in the bias state, M1 and M2 are turned on, and M0 is not turned on, that is, it is in a disconnected state. The VDD voltage is divided by resistors R1 and R2 and sent to Vref to play a biasing role.

[0046] Understandably, Figure 2 M1, M0, and M2 all act as switches, and their implementation is not limited to Figure 2 In addition, in some possible implementations, the switch tubes in the first switch branch and the second switch branch may be omitted, and in this case, the voltage divider circuit may only include resistors R1 and R2.

[0047] The RC time constant is the product of resistance (R) and capacitance (C). When reducing the RC time constant of the bias main circuit, the resistance value (R) of the bias main circuit can be reduced, or the capacitance value (C) of the bias main circuit can be reduced. In different implementations, the circuit structure of the acceleration circuit is different.

[0048] In one possible implementation, the acceleration circuit is connected in parallel with at least part of the devices in the voltage divider circuit of the bias main circuit, and the equivalent impedance of the acceleration circuit is less than or equal to the equivalent impedance of the voltage divider circuit. Since the equivalent impedance of the acceleration circuit is less than or equal to the equivalent impedance of the voltage divider circuit, when the acceleration circuit is connected in parallel with the bias main circuit, the equivalent impedance of the entire circuit will be reduced, thereby reducing the RC time constant of the circuit. The acceleration circuit includes a switch, and whether to enable the acceleration circuit can be selected by controlling the closing or opening of the switch. For example, when the bias voltage circuit is in the startup stage, the switch of the acceleration circuit is in a closed state, at which time the acceleration circuit is enabled; when the bias voltage circuit is in the bias stage, the switch of the acceleration circuit is in an open state, at which time it is equivalent to the acceleration circuit not working.

[0049] In an AC circuit, impedance refers to the resistance of a component or circuit to AC current. It includes the combined effects of resistance, capacitance and inductance. Resistance is the real part of impedance, which represents the part of the circuit that consumes power. In a DC circuit, resistance is the impedance of the circuit, because the effects of capacitance and inductance can be ignored.

[0050] Among them, the main structure of the acceleration circuit is consistent with the main structure of the voltage divider circuit in the bias main circuit, both of which include a switch tube and a resistor, and the switch tube can act as a switch. In a possible implementation, the acceleration circuit includes a third switch branch and a fourth switch branch, the first end of the third switch branch is connected to the power supply, the second end of the third switch branch is connected to the first switch branch, and the third switch branch is connected in parallel with at least some of the devices in the first switch branch; the first end of the fourth switch branch is grounded, the second end of the fourth switch branch is connected to the second switch branch, and the fourth switch branch is connected in parallel with at least some of the devices in the second switch branch.

[0051] In the above implementation, the third switch branch can be connected in parallel with all devices in the first switch branch, or it can be connected in parallel with some devices in the first switch branch; similarly, the fourth switch branch can be connected in parallel with all devices in the second switch branch, or it can be connected in parallel with some devices in the second switch branch.

[0052] For example, in one embodiment, Figure 3a As shown, the third switch branch and the fourth switch branch are connected in series, at this time, the second end of the third switch branch is connected to the voltage-dividing end of the first switch branch, and the second end of the fourth switch branch is connected to the voltage-dividing end of the second switch branch. In this embodiment, the third switch branch is connected in parallel with all devices in the first switch branch, and the fourth switch branch is connected in parallel with all devices in the second switch branch.

[0053] In another embodiment, Figure 3bAs shown, the third switch branch and the fourth switch branch are not connected in series. In this case, the second end of the third switch branch is connected to an internal endpoint in the first switch branch, such as point X, and the second end of the fourth switch branch is connected to an internal endpoint in the first switch branch, such as point Y. The line between the internal endpoint and the voltage divider terminal includes at least one device. In this embodiment, the third switch branch is connected in parallel with some devices in the first switch branch, and the fourth switch branch is connected in parallel with some devices in the second switch branch.

[0054] In a possible implementation manner, the first switch branch, the second switch branch, the third switch branch, and the fourth switch branch may all include a switch tube and a resistor connected in series. Figure 3a The circuit schematic diagram of the embodiment shown is as follows Figure 4a As shown, Figure 3b The circuit schematic diagram of the embodiment shown is as follows Figure 4b shown.

[0055] The switch tube M4 and the resistor R4 are included in the third switch branch, and the switch tube M3 and the resistor R3 are included in the fourth switch branch. Figure 4a In the example shown, the third switch branch is connected in parallel with all devices in the first switch branch, and the fourth switch branch is connected in parallel with all devices in the second switch branch. Figure 4b In the example shown, the third switch branch is connected in parallel only with the resistor R2 in the first switch branch, and the fourth switch branch is connected in parallel only with the resistor R1 in the second switch branch.

[0056] In one possible implementation, the equivalent impedance of the first switch branch is consistent with the equivalent impedance of the second switch branch, the equivalent impedance of the third switch branch is consistent with the equivalent impedance of the fourth switch branch, the equivalent impedance of the third switch branch is less than or equal to the equivalent impedance of the first switch branch, and the equivalent impedance of the fourth switch branch is less than or equal to the equivalent impedance of the second switch branch. In this implementation, the size of the switch tube M1 is consistent with the size of the switch tube M2, the resistance value of the resistor R1 is consistent with the resistance value of the resistor R2, and at this time, the voltage divider voltage of the voltage divider circuit is VDD / 2. The size of the switch tube M3 is consistent with the size of the switch tube M4, and the resistance value of the resistor R3 is consistent with the resistance value of the resistor R4. The resistance values ​​of the resistors R3 and R4 are less than or equal to the resistance values ​​of the resistors R1 and R2.

[0057] In one possible implementation, the introduction of the acceleration circuit will not change the voltage dividing ratio of the voltage divider circuit. In this implementation, the voltage dividing ratio of the first equivalent resistor and the second equivalent resistor is consistent with the voltage dividing ratio of the first switch branch and the second switch branch, wherein the first equivalent resistor is the equivalent resistor of the third switch branch connected in parallel with the first switch branch; the second equivalent resistor is the equivalent resistor of the fourth switch branch connected in parallel with the second switch branch.

[0058] For example, assuming that the voltage division ratio of the first switch branch and the second switch branch is 1:1, assuming that the impedance of the first switch branch is 10 ohms, the impedance of the second switch branch is 10 ohms, assuming that the impedance of the third switch branch is 10 ohms, and the impedance of the fourth switch branch is 10 ohms, then the impedance of the third switch branch after being connected in parallel with the first switch branch is 5 ohms. Similarly, the impedance of the fourth switch branch after being connected in parallel with the second switch branch is 5 ohms. After parallel connection, the voltage division ratio of the first switch branch and the second switch branch is still 1:1, but the resistance value is reduced.

[0059] In order to facilitate the control of the above-mentioned switch tube, in a possible implementation, the bias voltage circuit may further include a control circuit, the control circuit is connected to the bias main circuit and the switch tube in the acceleration circuit, and the control circuit is used to control the state of the switch tube. The control circuit may be a control circuit commonly used in the market to control the state of the switch tube.

[0060] In some other implementations, the switch tube in the bias voltage circuit may also be controlled by receiving an external control signal.

[0061] In order to achieve the rapid startup of the bias voltage circuit, an acceleration circuit is added on the basis of the bias main circuit. The acceleration circuit only works when the bias voltage circuit is started, and enters the reset state at the initial startup, reducing the equivalent impedance of the voltage divider node, thereby reducing the RC time constant, and can quickly pull the bias voltage to the desired voltage value, saving startup time. When the bias voltage is stable, the acceleration circuit will be turned off to reduce power consumption. At the same time, the acceleration circuit only needs a few MOS tubes and small resistors, which is low in cost and does not require too much area; there is no need to modify the original circuit, which minimizes the impact of the acceleration circuit on the circuit bias main circuit; there is no need to change the digital control logic in exchange for a longer waiting time, which can further save cost and time.

[0062] When the circuit is working normally, the voltage divider resistor of the bias main circuit and the equivalent impedance of the MOS tube are large, which are used to generate a suitable bias voltage while keeping the impact on the load circuit small, which can help the operational amplifier in the duty cycle calibration circuit establish a suitable operating point. The voltage divider resistor of the acceleration circuit and the equivalent impedance of the MOS tube are small, which are used to quickly pull up the bias voltage to a suitable voltage value during the circuit reset period (i.e., the startup phase).

[0063] The principle of the bias voltage circuit provided in the embodiment of the present application is as follows:

[0064] 1. When the bias voltage circuit enters the reset state (start-up phase), the switch tubes in the voltage divider circuit and the acceleration circuit are in the on state and the switch tube M0 is turned on. At this time, at least some of the devices in the acceleration circuit and the voltage divider circuit are in a parallel relationship. Since the impedance of the MOS tubes (M3, M4) in the on state is relatively small, and the resistance values ​​of the resistors R3 and R4 are relatively small, after being connected in parallel with the voltage divider circuit, the equivalent impedance at the Vrt node will be very small, so the time constant RC is greatly reduced, and Vrt can be quickly pulled up to a specific voltage value. On the other hand, at this time, the MOS tube M0 is turned on to short-circuit the resistor R0, further reducing the charging and discharging time of the Vref node, so the bias voltage Vref can be quickly pulled up to a specific voltage value.

[0065] 2. When the bias voltage circuit enters the bias state (bias stage), M1 and M2 in the voltage divider circuit remain in the on state, and M3 and M4 in the acceleration circuit are turned off. At this time, the MOS tube of the acceleration circuit acts as a switch and is in the off state. Since the impedance of the MOS tubes M3 and M4 in the off state is much greater than the resistance value of the resistors R3 and R4, the equivalent impedance of the acceleration circuit is infinite at this time. After being connected in parallel with the voltage divider circuit, the impedance is still close to the original impedance of the voltage divider circuit, so the impact on the voltage divider circuit and the output circuit is small. On the other hand, at this time, the MOS tube M0 is turned off, and the equivalent impedance at the Vref node is very large, which can reduce the impact on the subsequent circuit.

[0066] It is understandable that the above-mentioned acceleration circuit is mainly illustrated by reducing the RC time constant of the bias main circuit by reducing the resistance value R of the bias main circuit. In other embodiments, the acceleration circuit can also reduce the RC time constant of the bias main circuit by reducing the capacitance value C of the bias main circuit. In this embodiment, the circuit structure of the acceleration circuit is different from the circuit structure of the acceleration circuit shown above.

[0067] Based on the same inventive concept, the embodiment of the present application also provides a duty cycle calibration circuit, which includes the above-mentioned bias voltage circuit. The duty cycle calibration circuit is usually used to adjust and calibrate the duty cycle of a pulse width modulation (PWM) signal to ensure the accuracy and stability of the signal. The bias voltage circuit is an important component of the duty cycle calibration circuit, which provides a stable reference voltage for the circuit to ensure the accuracy of the calibration.

[0068] The bias voltage circuit provided in the duty cycle calibration circuit embodiment has the same implementation principle and technical effects as those in the aforementioned bias voltage circuit embodiment. For the sake of brief description, for matters not mentioned in the duty cycle calibration circuit embodiment, reference may be made to the corresponding contents in the aforementioned bias voltage circuit embodiment.

[0069] Based on the same inventive concept, an embodiment of the present application also provides a method for starting a duty cycle calibration circuit, which is the above-mentioned duty cycle calibration circuit, and the method includes: in the startup phase, controlling the bias main circuit to provide a bias voltage; controlling the acceleration circuit to reduce the RC time constant of the bias main circuit. For example, in the startup phase, the switch tubes in the bias main circuit and the acceleration circuit are controlled to be in the on state. The method also includes: when the circuit is working normally or entering the bias state, controlling the switch tube in the acceleration circuit to be in the off state, at which time, the switch tube in the bias main circuit is still in the on state.

[0070] Based on the same inventive concept, the embodiment of the present application further provides a chip, including the above-mentioned duty cycle calibration circuit, or, in some embodiments, the chip may include the above-mentioned bias voltage circuit. The chip may be various chips including the above-mentioned duty cycle calibration circuit, including but not limited to a processor.

[0071] Based on the same inventive concept, the embodiment of the present application also provides an electronic device, which may include the above-mentioned chip. The above-mentioned electronic device includes but is not limited to mobile phones, tablets, notebooks, communication equipment, medical equipment, measuring equipment, wearable equipment, automotive electronics, etc.

[0072] In one possible implementation, Figure 5 As shown, Figure 5 A block diagram of an electronic device provided by an embodiment of the present application is shown. The electronic device includes: a transceiver, a memory, a communication bus and a chip. The chip may include the above-mentioned duty cycle calibration circuit. In some embodiments, the chip may be a processor.

[0073] The transceiver, memory, and chip components are electrically connected to each other directly or indirectly to achieve data transmission or interaction. For example, these components can be electrically connected to each other through one or more communication buses or signal lines. Among them, the transceiver is used to send and receive data. The memory is used to store computer programs, wherein the computer program includes at least one software function module that can be stored in the memory in the form of software or firmware (Firmware) or solidified in the operating system (OS) of the electronic device. The chip is used to execute the software function module or computer program stored in the memory.

[0074] Among them, the memory can be, but is not limited to, random access memory (Random Access Memory, RAM), read only memory (Read Only Memory, ROM), programmable read-only memory (Programmable Read-Only Memory, PROM), erasable programmable read-only memory (Erasable Programmable Read-Only Memory, EPROM), electrically erasable read-only memory (Electric Erasable Programmable Read-Only Memory, EEPROM), etc.

[0075] The chip may be a processor with the ability to process signals. The above-mentioned processor may be a general-purpose processor, including a central processing unit (CPU), a network processor (NP), a graphics processing unit (GPU), an accelerated processing unit (Accelerated Processing Unit), a multimedia application processor (MAP), a microprocessor, etc.; it may also be a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic devices, discrete gates or transistor logic devices, discrete hardware components. Or the processor may also be any conventional processor, etc.

[0076] It should be noted that the various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0077] In addition, the functional modules in the various embodiments of the present application may be integrated together to form an independent part, or each module may exist separately, or two or more modules may be integrated to form an independent part.

[0078] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. A bias voltage circuit for a duty cycle calibration circuit, characterized in that: include: A bias main circuit for providing a bias voltage; An acceleration circuit is connected to the bias main circuit, and the acceleration circuit is used to reduce the RC time constant of the bias main circuit during the startup phase of the bias main circuit.

2. The bias voltage circuit according to claim 1, characterized in that: The bias main circuit includes a voltage divider circuit, the acceleration circuit is connected in parallel with at least part of the components in the voltage divider circuit, the equivalent impedance of the acceleration circuit is less than or equal to the equivalent impedance of the voltage divider circuit, and the acceleration circuit includes a switch; When the bias voltage circuit is in the startup phase, the switch of the acceleration circuit is in a closed state; When the bias voltage circuit is in the bias stage, the switch of the acceleration circuit is in an off state.

3. The bias voltage circuit according to claim 2, characterized in that: The voltage divider circuit comprises a first switch branch and a second switch branch connected in series, wherein a connection end between the first switch branch and the second switch branch is a voltage divider end; one end of the first switch branch is connected to a power supply, and one end of the second switch branch is grounded; The acceleration circuit comprises a third switch branch and a fourth switch branch, a first end of the third switch branch is connected to the power supply, a second end of the third switch branch is connected to the first switch branch, and the third switch branch is connected in parallel with at least part of the components in the first switch branch; A first end of the fourth switch branch is grounded, a second end of the fourth switch branch is connected to the second switch branch, and the fourth switch branch is connected in parallel with at least part of the components in the second switch branch.

4. The bias voltage circuit according to claim 3, characterized in that: The third switch branch and the fourth switch branch are connected in series, the second end of the third switch branch is connected to the voltage dividing end of the first switch branch, and the second end of the fourth switch branch is connected to the voltage dividing end of the second switch branch; or, The second end of the third switch branch is connected to an internal endpoint in the first switch branch, and the second end of the fourth switch branch is connected to an internal endpoint in the first switch branch.

5. The bias voltage circuit according to claim 3, characterized in that: The voltage division ratio of the first equivalent resistance and the second equivalent resistance is consistent with the voltage division ratio of the first switch branch and the second switch branch, wherein the first equivalent resistance is the equivalent resistance of the third switch branch connected in parallel with the first switch branch; and the second equivalent resistance is the equivalent resistance of the fourth switch branch connected in parallel with the second switch branch.

6. The bias voltage circuit according to claim 3, characterized in that: The third switch branch and the fourth switch branch both include a switch tube and a resistor connected in series.

7. The bias voltage circuit according to claim 6, characterized in that: The bias voltage circuit also includes a control circuit, which is connected to the bias main circuit and the switch tube in the acceleration circuit, and is used to control the state of the switch tube.

8. The bias voltage circuit according to any one of claims 1 to 7, characterized in that: The bias main circuit includes a voltage divider circuit and an output circuit; the output circuit is connected to the voltage divider end of the voltage divider circuit; the output circuit includes: a switch tube and a filter resistor, the switch tube is connected in parallel with the filter resistor; When the bias voltage circuit is in the startup phase, the switch tube is in a closed state; When the bias voltage circuit is in the bias stage, the switch tube is in the disconnected state.

9. A duty cycle calibration circuit, characterized in that: Comprising a bias voltage circuit as claimed in any one of claims 1 to 8.

10. A chip, characterized in that: include: The duty cycle calibration circuit as claimed in claim 9.

11. An electronic device, characterized in that: include: The chip as claimed in claim 10.

12. A method for starting a duty cycle calibration circuit, characterized in that: The duty cycle calibration circuit comprises: a bias voltage circuit as claimed in any one of claims 1 to 8; the method comprises: During the startup phase, the bias main circuit is controlled to provide a bias voltage; The control speed-up circuit reduces the RC time constant of the bias body circuit.

Images