Settling acceleration circuit and image sensor reading circuit using the same

Abstract

To improve performance such as RC time constant reduction and slew rate improvement regarding analog signal settling.SOLUTION: A settling acceleration circuit comprises: a first transistor in which a gate electrode is connected to an output terminal where a capacitive component is present; a first capacitor connected to a source terminal of the first transistor; a first constant current source connected to the source terminal of the first transistor; a current mirror circuit that amplifies a current from a drain terminal of the first transistor to output the amplified current to an output node; a second constant current source connected to the output node; and a first switch arranged between the output terminal and the output node. After the end of a settling acceleration period in which the first switch is made conductive to accelerate the settling of the voltage of the output terminal, the first switch is cut off, and a read-out circuit connected to the output terminal reads out the voltage of the output terminal. The present technique can be applied, for example, to an image pickup device such as a CMOS image sensor.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present disclosure relates to a settling acceleration circuit and an image sensor readout circuit using the same, and in particular to a settling acceleration circuit that enables performance improvements such as shortening the RC time constant related to analog signal settling and improving the slew rate, and an image sensor readout circuit using the same. [Background technology]

[0002] Conventionally, for solid-state imaging devices such as CMOS (Complementary Metal-Oxide-Semiconductor) image sensors, there has been a demand for faster pixel signal readout speeds and higher resolution. As resolution and pixel count increase, the number of pixels connected to the vertical signal line (VSL) increases, resulting in an increase in the parasitic capacitance of the vertical signal line. This increase in parasitic capacitance of the vertical signal line hinders shortening the settling time of the voltage on the vertical signal line. Reducing the settling time is important for increasing the pixel signal readout speed.

[0003] Conventionally, in order to shorten the settling time of the voltage on the vertical signal line, an additional current has been supplied to the vertical signal line according to the amount of voltage fluctuation on the vertical signal line (see, for example, Patent Documents 1 and 2). By supplying an additional current to the vertical signal line according to the amount of voltage fluctuation on the vertical signal line, the RC time constant and slew rate of the vertical signal line can be improved, thereby shortening the settling time.

[0004] Furthermore, in order to shorten the settling time of the voltage on the vertical signal line, an additional current is supplied to the vertical signal line at the timing of reading out the pixel signal in synchronization with a signal (a reset control signal or a transfer control signal) that changes the voltage on the vertical signal line (see, for example, Patent Document 3 and Non-Patent Document 1). By supplying an additional current to the vertical signal line, the slew rate of the vertical signal line is improved, thereby shortening the settling time. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] Japanese Patent Application Laid-Open No. 2015-139081 [Patent Document 2] Japanese Patent Application Laid-Open No. 2011-234243 [Patent Document 3] Japanese Patent Application Publication No. 2017-118373 [Non-Patent Document 1] A 3.7M-pixel l300-fps CMOS Image Sensor with 5.0G-Pixel / s High-Speed Readout Circuit, Institute of Image Television Engineers 2014, https: / / www.jstage.jst.go.jp / article / itetr / 38.37 / 0 / 38.37_9 / _pdf / -char / ja Summary of the Invention [Problem to be solved by the invention]

[0006] The conventional techniques described in Patent Documents 1 and 2 can realize negative capacitance, reduce the large parasitic capacitance added to the vertical signal line, and shorten the RC time constant. However, if the overall settling time is dominated by settling after the voltage at the FD (Floating Diffusion: charge-voltage converter / charge detector) node fluctuates significantly due to feedthrough caused by voltage transitions on the pixel control line, the effect of shortening the settling time is small. Furthermore, even after the VSL settles and converges, elements (current sources, current mirror circuits, etc.) for realizing negative capacitance are still connected to the VSL. In this case, when the subsequent circuit reads the VSL voltage, there is a problem in that thermal noise and 1 / f noise introduced from these elements into the VSL have a significant impact.

[0007] When using the conventional technology described in Patent Document 3 or Non-Patent Document 1, even if the voltage of the vertical signal line settles, the gate-source voltage Vgs of the amplifying transistor constituting the source follower fluctuates when the supply of additional current is stopped. Then, when the gate-source voltage Vgs changes, it is necessary to wait again for the settling time determined by the RC delay equation of the parasitic wiring resistance R and parasitic capacitance C of the vertical signal line.

[0008] Therefore, the present disclosure has been made in consideration of such circumstances, and aims to more reliably shorten the settling time of the voltage of the vertical signal line and increase the readout speed of the pixel signal. [Means for solving the problem]

[0009] A settling acceleration circuit according to a first aspect of the present disclosure includes a first transistor having a gate electrode connected to an output terminal having a capacitive component, a first capacitor connected to the source terminal of the first transistor, a first constant current source connected to the source terminal of the first transistor, a current mirror circuit that amplifies a current from the drain terminal of the first transistor and outputs the amplified current to an output node, a second constant current source connected to the output node, and a first switch disposed between the output terminal and the output node. After a settling acceleration period in which the first switch is turned on to accelerate the settling of the voltage at the output terminal ends, the first switch is turned off and a readout circuit connected to the output terminal reads out the voltage at the output terminal.

[0010] In a first aspect of the present disclosure, a settling acceleration circuit includes: a first transistor having a gate electrode connected to an output terminal having a capacitive component; a first capacitor connected to a source terminal of the first transistor; a first constant current source connected to the source terminal of the first transistor; a current mirror circuit that amplifies a current from a drain terminal of the first transistor and outputs the amplified current to an output node; a second constant current source connected to the output node; and a first switch disposed between the output terminal and the output node. After a settling acceleration period in which the first switch is turned on to accelerate settling of the voltage at the output terminal ends, the first switch is turned off, and the voltage at the output terminal is read out by a readout circuit connected to the output terminal.

[0011] A settling acceleration circuit according to a second aspect of the present disclosure includes a first transistor having a gate electrode connected to an output terminal having a capacitive component, a first capacitor connected to the source terminal of the first transistor, a first constant current source connected to the source terminal of the first transistor, a current mirror circuit that amplifies a current from the drain terminal of the first transistor and outputs the amplified current to the output terminal, a third constant current source that supplies a current to the current mirror circuit, and a fifth switch that connects the third constant current source and the current mirror circuit, and the fifth switch is turned on to improve the slew rate of the voltage at the output terminal during a slew rate acceleration period.

[0012] In a second aspect of the present disclosure, a settling acceleration circuit includes: a first transistor having a gate electrode connected to an output terminal having a capacitance component; a first capacitor connected to a source terminal of the first transistor; a first constant current source connected to the source terminal of the first transistor; a current mirror circuit that amplifies a current from a drain terminal of the first transistor and outputs the amplified current to the output terminal; a third constant current source that supplies a current to the current mirror circuit; and a fifth switch that connects the third constant current source and the current mirror circuit. The fifth switch is turned on to improve the slew rate of the voltage at the output terminal during a slew rate acceleration period.

[0013] An image sensor readout circuit according to a third aspect of the present disclosure includes a first transistor having a gate electrode connected to an output terminal having a capacitance component, a first capacitor connected to the source terminal of the first transistor, a first constant current source connected to the source terminal of the first transistor, a current mirror circuit that amplifies a current from the drain terminal of the first transistor and outputs the amplified current to an output node, a second constant current source connected to the output node, and a first switch disposed between the output terminal and the output node, and uses a settling acceleration circuit that turns off the first switch after a settling acceleration period in which the first switch is turned on to accelerate settling of the voltage at the output terminal has ended, and a readout circuit connected to the output terminal reads out the voltage at the output terminal.

[0014] In a third aspect of the present disclosure, an image sensor readout circuit uses a settling acceleration circuit including: a first transistor having a gate electrode connected to an output terminal having a capacitance component, a first capacitor connected to a source terminal of the first transistor, a first constant current source connected to the source terminal of the first transistor, a current mirror circuit that amplifies a current from a drain terminal of the first transistor and outputs the amplified current to an output node, a second constant current source connected to the output node, and a first switch disposed between the output terminal and the output node. After a settling acceleration period in which the first switch is turned on to accelerate settling of the voltage at the output terminal ends, the first switch is turned off, and the voltage at the output terminal is read out by a readout circuit connected to the output terminal.

[0015] An image sensor readout circuit according to a fourth aspect of the present disclosure includes a first transistor having a gate electrode connected to an output terminal having a capacitance component, a first capacitor connected to the source terminal of the first transistor, a first constant current source connected to the source terminal of the first transistor, a current mirror circuit that amplifies a current from the drain terminal of the first transistor and outputs the amplified current to the output terminal, a third constant current source that supplies a current to the current mirror circuit, and a fifth switch that connects the third constant current source and the current mirror circuit, and uses a settling acceleration circuit that turns on the fifth switch to improve the slew rate of the voltage at the output terminal during a slew rate acceleration period.

[0016] In a fourth aspect of the present disclosure, an image sensor readout circuit includes: a first transistor having a gate electrode connected to an output terminal having a capacitance component; a first capacitor connected to a source terminal of the first transistor; a first constant current source connected to the source terminal of the first transistor; a current mirror circuit that amplifies a current from a drain terminal of the first transistor and outputs the amplified current to the output terminal; a third constant current source that supplies a current to the current mirror circuit; and a fifth switch that connects the third constant current source and the current mirror circuit. The fifth switch is turned on to improve the slew rate of the voltage at the output terminal during a slew rate acceleration period.

[0017] An image sensor readout circuit according to a fifth aspect of the present disclosure includes a pixel source follower circuit having a signal line that outputs a pixel signal from a pixel, and a transistor that serves as an acceleration current source, the signal line being connected to a gate terminal of the transistor via a capacitor.

[0018] In a fifth aspect of the present disclosure, an image sensor readout circuit includes a pixel source follower circuit having a signal line that outputs a pixel signal from a pixel, and a transistor that serves as an acceleration current source, and the signal line is connected to a gate terminal of the transistor via a capacitor. [Brief explanation of the drawings]

[0019] [Figure 1] 1 is a circuit diagram showing a configuration example of a first embodiment of an analog integrated circuit to which the present technology is applied. [Figure 2] 10A and 10B are diagrams illustrating operation timings and time waveforms. [Figure 3] FIG. 2 is a circuit diagram showing a first modified example of the analog integrated circuit of FIG. [Figure 4] FIG. 2 is a circuit diagram showing a second modified example of the analog integrated circuit of FIG. [Figure 5] FIG. 2 is a circuit diagram showing a third modified example of the analog integrated circuit of FIG. [Figure 6] 10 is a circuit diagram showing a configuration example of a second embodiment of an analog integrated circuit to which the present technology is applied. FIG. [Figure 7] 10A and 10B are diagrams illustrating operation timings and time waveforms. [Figure 8] FIG. 10 is a circuit diagram showing a configuration example of a third embodiment of an analog integrated circuit to which the present technology is applied. [Figure 9] 10A and 10B are diagrams illustrating operation timings and time waveforms. [Figure 10] FIG. 9 is a circuit diagram showing a first modified example of the analog integrated circuit of FIG. 8. [Figure 11] 10A and 10B are diagrams illustrating operation timings and time waveforms. [Figure 12] FIG. 9 is a circuit diagram showing a second modified example of the analog integrated circuit of FIG. 8. [Figure 13] 10A and 10B are diagrams illustrating operation timings and time waveforms. [Figure 14] 10 is a circuit diagram showing a configuration example of a fourth embodiment of an analog integrated circuit (image sensor) to which the present technology is applied. FIG. [Figure 15] 10A and 10B are diagrams illustrating operation timings and time waveforms. [Figure 16] 10 is a circuit diagram showing a configuration example of a fifth embodiment of an analog integrated circuit (image sensor) to which the present technology is applied. FIG. [Figure 17] 17 is a diagram for explaining driving of the analog integrated circuit (imaging element) in FIG. 16. FIG. [Figure 18] FIG. 1 is a block diagram illustrating an example of the configuration of an imaging device. [Figure 19] FIG. 1 is a diagram illustrating an example of use of an image sensor. DETAILED DESCRIPTION OF THE INVENTION

[0020] Specific embodiments to which the present technology is applied will be described in detail below with reference to the drawings.

[0021] <First Configuration Example of Analog Integrated Circuit> FIG. 1 is a circuit diagram showing a configuration example of a first embodiment of an analog integrated circuit to which the present technology is applied.

[0022] As shown in FIG. 1, an analog integrated circuit 11 is configured by a buffer section 12 and a settling acceleration circuit 13, an input terminal VIN is connected to the buffer section 12, and an output terminal VOUT is connected to the buffer section 12 through the settling acceleration circuit 13.

[0023] The output terminal VOUT has parasitic resistance and parasitic capacitance due to its wiring, etc., so there is an RC delay when settling the voltage at the output terminal VOUT. When the voltage at the input terminal VIN is indirectly read out through the output terminal VOUT, a settling time is required for the voltage at the output terminal VOUT to stabilize (become statically determined). The purpose of the settling acceleration circuit 13 is to accelerate and speed up the settling of the voltage at the output terminal VOUT, thereby shortening the settling time.

[0024] The buffer unit 12 is configured to include a voltage buffer 21, a resistor 22, and a capacitor 23. The settling acceleration circuit 13 is configured to include a P-type MOS (Metal-Oxide-Semiconductor) transistor 31, a constant current source 32, a capacitor 33, an N-type MOS transistor 34, an N-type MOS transistor 35, a constant current source 36, and a connection / disconnection switch 37. Here, the voltage buffer 21 refers to a voltage follower configured from a source follower or an operational amplifier.

[0025] When the impedance of the input terminal VIN is high, it is difficult to read the voltage directly. For example, to read the voltage of the FD node, a buffer circuit with high input impedance, such as a source follower, is required. The input terminal of the buffer circuit can be connected to the FD node to indirectly read the voltage. By using a buffer circuit with low output impedance, it is possible to transmit the voltage change of the FD node to VSL, which has large parasitic capacitance and parasitic wiring resistance, and to achieve settling in a short period of time. The settling acceleration circuit 13 is a circuit that assists in accelerating this settling and shortening the stabilization time.

[0026] The input terminal VIN is connected to the input terminal of a voltage buffer 21, the output terminal of which is connected to one terminal of a resistor 22, the other terminal of which is connected to the output terminal VOUT and to the ground terminal VSS via a capacitor 23. The resistor 22 and the capacitor 23 simulate the resistance and capacitance components due to parasitic elements or parasitic effects; for example, the resistor 22 represents the wiring resistance of the vertical signal line, and the capacitor 23 represents the wiring capacitance of the vertical signal line. If the parasitic effect is small and the resistance value is small, the resistor 22 may not be present, and the output terminal of the voltage buffer 21 may be directly connected to the capacitor 23.

[0027] The connection point between the resistor 22 and the capacitor 23 is an output terminal VOUT, which is connected to the gate terminal of a P-type MOS transistor 31 .

[0028] The source terminal of the P-type MOS transistor 31 is connected to a power supply terminal VDD via a parallel-connected constant current source 32 and a capacitor 33. The drain terminal of the P-type MOS transistor 31 is connected to a ground terminal VSS via an N-type MOS transistor 34.

[0029] The N-type MOS transistor 34 and the N-type MOS transistor 35 form a current mirror circuit, with their gate terminals connected to each other, and the N-type MOS transistor 34 has its gate terminal and drain terminal connected in common to form a diode-connected configuration. The drain terminal of the P-type MOS transistor 31 is connected to this connection point, and the current from the drain terminal of the P-type MOS transistor 31 is multiplied by M and output to a node VOUT_BST to which the drain terminal of the N-type MOS transistor 35 is connected.

[0030] The drain terminal of the N-type MOS transistor 35 is connected to the power supply terminal VDD via a constant current source 36. The source terminal of the N-type MOS transistor 35 is connected to the ground terminal VSS.

[0031] One terminal of the connection / disconnection switch 37 is connected to the output terminal VOUT, and the other terminal is connected to a node VOUT_BST between the N-type MOS transistor 35 and the constant current source 36. The node VOUT_BST is the output node of the settling acceleration circuit 13. The connection / disconnection switch 37 disconnects or connects the output terminal VOUT and the node VOUT_BST in accordance with the digital control signal DIN_FB.

[0032] [Explanation of operation timing and time waveform] 2 shows the voltage waveforms of the input terminal VIN and the output terminal VOUT, and the time waveform of the digital control signal DIN_FB that indicates the settling acceleration period. When the voltage of the input terminal VIN is constant or changes little, settling acceleration of the voltage of the output terminal VOUT is not necessary, so the digital control signal DIN_FB is set to LOW level. Because the output terminal VOUT is isolated from the settling acceleration circuit 13, the voltage of the output terminal VOUT exhibits settling characteristics determined by the characteristics of the voltage buffer 21, the resistance value of the resistor 22, and the capacitance value of the capacitor 23.

[0033] On the other hand, just before or at the moment when the voltage of the input terminal VIN drops, the digital control signal DIN_FB is changed from LOW level to HIGH level, and the disconnection switch 37 is made conductive. At this time, the node VOUT_BST and the output terminal VOUT are short-circuited, and the settling acceleration circuit 13 accelerates the settling of the output terminal VOUT, so that the voltage of the output terminal VOUT can be converged to the expected value in a shorter time. During the settling acceleration period when the digital control signal DIN_FB is at HIGH level, the voltage of the output terminal VOUT reaches a voltage V1-V close to the expected value V1. ERR The digital control signal DIN_FB is then returned to LOW level. The readout wait period is waited until the voltage at the output terminal VOUT stabilizes at the expected value V1. The next-stage circuit connected to the output terminal VOUT then reads out the voltage at the output terminal VOUT according to the timing indicated by the digital control signal DIN_SAMP.

[0034] The dotted line in Figure 2 shows the voltage waveform at the output terminal VOUT when settling is performed using a time constant determined by the voltage buffer circuit, resistors, and capacitors without using the settling acceleration circuit 13. Without the settling acceleration circuit 13, it takes time for the voltage at the output terminal VOUT to settle and stabilize after the voltage at the input terminal VIN starts to drop. Using the settling acceleration circuit 13 accelerates the settling of the output terminal VOUT, allowing the voltage to converge to the expected value in a short period of time, shortening the time from when the voltage at the input terminal VIN changes to when the voltage at the output terminal VOUT can be read.

[0035] [Improvement of settling parameters (RC time constant, slew rate)] The ability of the settling acceleration circuit 13 to improve the voltage settling characteristics of the output terminal VOUT will be explained using the RC time constant τ1 and slew rate SR1 of the output terminal VOUT. When the digital control signal DIN_FB is LOW, the connection / disconnection switch 37 is disconnected, so the RC time constant τ1 and slew rate SR1 of the output terminal VOUT are determined only by the characteristics of each element in the buffer unit 12, and are respectively expressed by the following equation (1).

[0036]

number

[0037] In equation (1), the resistance value of resistor 22 is R VSL , the capacitance value of the capacitor 23 is C VSL The output impedance of the voltage buffer 21 is set to R BUFF , the output current range of the voltage buffer 21 is ±IMAX BUFF Within this limit.

[0038] Next, consider the settling characteristics when the voltage of the VOUT terminal drops as shown in Figure 2. When the digital control signal DIN_FB is HIGH, the connection / disconnection switch 37 is conductive, so the RC time constant τ2 and slew rate SR2 of the output terminal VOUT are determined by the characteristics of each element in the buffer unit 12 and the settling acceleration circuit 13, and are each expressed by the following equation (2).

[0039]

number

[0040] Here, the current of the constant current source 36 is M times the current of the constant current source 32, and the capacitance value of the capacitor 33 is C BST As is clear from the RC time constant τ1 in the above equation (1) and the RC time constant τ2 in the above equation (2), the RC time constant τ2 is smaller than the RC time constant τ1. In particular, it can be seen that by increasing M, which is the ratio of the current mirror circuit, the RC time constant τ2 can be significantly shortened, and the settling characteristics can be improved.

[0041] Similarly, as is clear from the slew rate SR1 in the above formula (1) and the slew rate SR2 in the above formula (2), the absolute value |SR2| of the slew rate SR2 is larger than the absolute value |SR1| of the slew rate SR1 (the magnitude and absolute value of the slew rate are important for settling. For example, |SR| means the absolute value of SR). In particular, it can be seen that by increasing M, which is the ratio of the current mirror circuit, the absolute value |SR2| of the slew rate SR2 can be significantly increased, thereby improving the settling characteristics. In the above formula (2), C VSL -M.C. BST As the term indicates, the settling acceleration circuit can reduce the capacitance added to the output terminal VOUT, that is, the negative capacitance (-M C BST ) can be realized.

[0042] [Settling acceleration circuit noise (thermal noise, 1 / f noise), and readout wait period] In the transistors that make up the settling acceleration circuit 13, thermal noise and 1 / f noise currents are generated between their source and drain terminals. The constant current sources are also composed of transistors, and therefore generate the noise. In the settling acceleration circuit 13, noise from the constant current source 32, N-type MOS transistor 34, N-type MOS transistor 35, and constant current source 36 in particular is mixed into the output terminal VOUT via node VOUT_BST and the disconnection switch 37. As shown in FIG. 2, during the settling acceleration period when the disconnection switch 37 is conductive, the noise is mixed into the output terminal VOUT, and the voltage of the output terminal VOUT fluctuates randomly over time depending on the noise.

[0043] Furthermore, the characteristics of each transistor that constitutes the settling acceleration circuit 13 vary. For example, it is difficult to keep constant the current values of the constant current sources 32 and 36 and the ratio M of the current mirror circuit, and they vary from circuit to circuit. This variation causes an error in the voltage of the output terminal VOUT just before the end of the settling acceleration period.

[0044] V ERRrepresents the influence of the offset voltage generated by the element variations of the settling acceleration circuit 13 and the above noise (V ERR (It is preferable that V is close to zero.) ERR In order to mitigate the influence of the voltage at the output terminal VOUT, a read wait period is required in which the connection / disconnection switch 37 is turned off before reading out the voltage at the output terminal VOUT. ERR The influence of is mitigated, and the voltage of the output terminal VOUT converges to the expected value V1.

[0045] The settling acceleration circuit 13 exemplified in this embodiment is configured to be able to accelerate settling when the voltage of the output terminal VOUT drops. To accelerate settling when the voltage of the output terminal VOUT rises, this can be similarly achieved by replacing the P-type MOS transistors with N-type MOS transistors in the settling acceleration circuit 13 exemplified, and replacing the N-type MOS transistors with P-type MOS transistors, and by changing the circuit configuration complementarily with respect to the power supply terminal VDD and the ground terminal VSS.

[0046] The constant current source 32 and the constant current source 36 described in this embodiment are configured using transistors. Since they can be easily configured using a CMOS process, a description of their configuration will be omitted. The connection / disconnection switch 37 and the current cut-off switch 38 described in this embodiment are analog switches configured using transistors, and are assumed to operate in such a way that when a digital control signal that controls the switch state is HIGH, two nodes are short-circuited to establish conduction (ON state), and when the digital control signal is LOW, the two nodes are cut off (OFF state).

[0047] In this way, the analog integrated circuit 11 can significantly improve the voltage settling characteristics of the output terminal VOUT while reducing the influence of thermal noise from the settling acceleration circuit 13. That is, the RC time constant of the output terminal VOUT can be shortened and the slew rate of the output terminal VOUT can be improved.

[0048] Fig. 3 is a circuit diagram showing a first modified example of the analog integrated circuit 11. In the analog integrated circuit 11-a shown in Fig. 3, components common to the analog integrated circuit 11 of Fig. 1 are given the same reference numerals, and detailed description thereof will be omitted.

[0049] 3, the buffer unit 12 has the same circuit configuration as the buffer unit 12 in FIG. 1. The settling acceleration circuit 13-a includes a P-type MOS transistor 31, a constant current source 32, a capacitor 33, an N-type MOS transistor 34, an N-type MOS transistor 35, a constant current source 36, and a connection / disconnection switch 37, which have the same circuit configuration as the settling acceleration circuit 13 in FIG.

[0050] The settling acceleration circuit 13-a has a different configuration from the settling acceleration circuit 13 of FIG.

[0051] The current cutoff switch 38 has one terminal connected to the constant current source 36 and the other terminal connected to a node VOUT_BST to which the N-type MOS transistor 35 and the connection cutoff switch 37 are connected. The current cutoff switch 38 turns on / off the output of current from the constant current source 36 in accordance with the digital control signal DIN_FB.

[0052] Therefore, the analog integrated circuit 11-a controls the digital control signal DIN_FB to a LOW level during periods other than the settling acceleration period to turn off the connection cutoff switch 37 and turn off the current cutoff switch 38, thereby cutting off the current flowing from the constant current source 36 to the N-type MOS transistor 35. In other words, during the period when the node VOUT_BST is not connected to the output terminal VOUT, the settling acceleration circuit 13-a does not need to operate, and therefore, cutting off the current flowing from the constant current source 36 to the N-type MOS transistor 35 can reduce current consumption.

[0053] In this way, the analog integrated circuit 11-a can improve the performance of the analog integrated circuit 11 and also reduce current consumption.

[0054] Fig. 4 is a circuit diagram showing a second modified example of the analog integrated circuit 11. In the analog integrated circuit 11-b shown in Fig. 4, components common to the analog integrated circuit 11 of Fig. 1 are given the same reference numerals, and detailed description thereof will be omitted.

[0055] 4, the buffer unit 12 has the same circuit configuration as the buffer unit 12 in FIG. 1. The settling acceleration circuit 13-b includes a P-type MOS transistor 31, a constant current source 32, a capacitor 33, an N-type MOS transistor 34, an N-type MOS transistor 35, a constant current source 36, and a connection / disconnection switch 37, which have the same circuit configuration as the settling acceleration circuit 13 in FIG.

[0056] 1 in that it includes a current cutoff switch 39 and an inverter 40. The inverter 40 is a circuit that inverts the logic of the digital control signal DIN_FB and outputs the inverted signal, and details thereof will be omitted as it can be easily realized in a CMOS process.

[0057] One terminal of the current cutoff switch 39 is connected to the connection point between the gate terminals of the N-type MOS transistor 34 and the N-type MOS transistor 35 that form a current mirror circuit, and the other terminal is connected to the ground terminal VSS to which the source terminal of the N-type MOS transistor 34 is connected. The current cutoff switch 39 turns on / off the connection between the gate terminals of the N-type MOS transistor 34 and the N-type MOS transistor 35 and the ground terminal VSS in accordance with a digital control signal DIN_FB that is inverted and input via an inverter 40.

[0058] Therefore, when the analog integrated circuit 11-b controls the digital control signal DIN_FB to a low level to turn off the connection cutoff switch 37 during periods other than the acceleration period, a high level, which is an inversion of the digital control signal DIN_FB, is supplied to the current cutoff switch 39. This turns on the current cutoff switch 39, connecting the gate terminals of the N-type MOS transistor 34 and the N-type MOS transistor 35 to the ground terminal VSS, causing the voltage Vgs between the gate terminal and source terminal of the N-type MOS transistor 35 to become zero, and cutting off the current between the drain terminal and source terminal of the N-type MOS transistor 35. This makes it possible to cut off the current flowing from the constant current source 36 to the N-type MOS transistor 35. In other words, during periods when the node VOUT_BST is not connected to the output terminal VOUT, the settling acceleration circuit 13-b does not need to operate, and therefore current consumption can be reduced by cutting off the current flowing from the constant current source 36 to the N-type MOS transistor 35.

[0059] In this way, the analog integrated circuit 11-b can improve the performance of the analog integrated circuit 11 and also reduce current consumption.

[0060] Fig. 5 is a circuit diagram showing a third modified example of the analog integrated circuit 11. In the analog integrated circuit 11-c shown in Fig. 5, components common to the analog integrated circuit 11 of Fig. 1 are given the same reference numerals, and detailed description thereof will be omitted.

[0061] 5, the buffer unit 12 has the same circuit configuration as the buffer unit 12 in FIG. 1. The settling acceleration circuit 13-c includes a P-type MOS transistor 31, a constant current source 32, a capacitor 33, an N-type MOS transistor 34, an N-type MOS transistor 35, a constant current source 36, and a connection / disconnection switch 37, which have the same circuit configuration as the settling acceleration circuit 13 in FIG.

[0062] 1 in that it includes a current cutoff switch 41 and a comparator 42. The comparator 42 has a non-inverting input terminal, an inverting input terminal, and a digital output terminal, and outputs a HIGH level as a digital output when the voltage or current at the non-inverting input terminal is greater than the voltage or current at the inverting input terminal, and outputs a LOW level when the voltage or current at the non-inverting input terminal is smaller than the voltage or current at the inverting input terminal.

[0063] One terminal of the current cutoff switch 41 is connected to the connection point between the gate terminals of the N-type MOS transistor 34 and the N-type MOS transistor 35 that form a current mirror circuit, and the other terminal is connected to the ground terminal VSS to which the source terminal of the N-type MOS transistor 34 is connected. Then, the current cutoff switch 41 turns on / off the connection of the gate terminals of the N-type MOS transistor 34 and the N-type MOS transistor 35 to the ground terminal VSS in accordance with the output of the comparator 42.

[0064] The comparator 42 has an inverting input terminal connected to the junction between the gate terminals of the N-type MOS transistor 34 and the N-type MOS transistor 35, which form a current mirror circuit, and a non-inverting input terminal to which an externally set comparison voltage VBN_VGS is input. When the voltage of the input terminal VIN drops and the voltage of the output terminal VOUT is settling, the voltage at the junction between the gate terminals rises and becomes higher than the comparison voltage VBN_VGS. As the settling stabilizes, the voltage at the junction between the gate terminals drops and becomes lower than the comparison voltage VBN_VGS. At this time, the comparator 42 detects the voltage inside the settling acceleration circuit 13-c (the voltage at the junction between the gate terminals) and outputs a HIGH signal to turn on the current cutoff switch 41. Here, the fact that the voltage inside the settling acceleration circuit 13-c is lower than the comparison voltage VBN_VGS means that the voltage at the output terminal VOUT has converged and is nearing completion of settling. The voltage at the connection point between the gate terminals indicates the settling state of the voltage at the output terminal VOUT.

[0065] As a result, when the settling of the settling acceleration circuit 13-c converges and the voltage of the output terminal VOUT stabilizes, the gate terminals of the N-type MOS transistor 34 and the N-type MOS transistor 35 are connected to the ground terminal VSS, the voltage Vgs between the gate terminal and source terminal of the N-type MOS transistor 35 becomes zero, and the current between the drain terminal and source terminal of the N-type MOS transistor 35 is cut off. Therefore, the current flowing from the constant current source 36 to the N-type MOS transistor 35 can be cut off. In other words, the settling acceleration circuit 13-c monitors the voltage of an internal node, detects a settling state, particularly when settling has converged, and automatically cuts off the current flowing from the constant current source 36 to the N-type MOS transistor 35, thereby achieving low current consumption.

[0066] In this way, the analog integrated circuit 11-c can improve the performance of the analog integrated circuit 11 and also reduce current consumption.

[0067] <Second Configuration Example of Analog Integrated Circuit> Fig. 6 is a block diagram showing a configuration example of a second embodiment of an analog integrated circuit to which the present technology is applied. In the analog integrated circuit 11A shown in Fig. 6, components common to the analog integrated circuit 11 in Fig. 1 are denoted by the same reference numerals, and detailed description thereof will be omitted.

[0068] 6, the buffer unit 12 has the same circuit configuration as the buffer unit 12 in FIG. 1. The settling acceleration circuit 13A includes a P-type MOS transistor 31, a constant current source 32, a capacitor 33, an N-type MOS transistor 34, an N-type MOS transistor 35, and a connection / disconnection switch 37, which have the same circuit configuration as the settling acceleration circuit 13 in FIG.

[0069] 1 in that the settling acceleration circuit 13A includes a P-type MOS transistor 43, a capacitor 44, and an auto-zero switch 45. That is, in the settling acceleration circuit 13A, the constant current source 36 in FIG. 1 is configured by an auto-zero circuit including the P-type MOS transistor 43, the capacitor 44, and the auto-zero switch 45.

[0070] The P-type MOS transistor 43 has a source terminal connected to the power supply terminal VDD and a drain terminal connected to the node VOUT_BST. The capacitor 44 has one terminal connected to the power supply terminal VDD and the other terminal connected to the gate terminal of the P-type MOS transistor 43.

[0071] One terminal of the auto-zero switch 45 is connected to the connection point between the capacitor 44 and the gate terminal of the P-type MOS transistor 43, and the other terminal is connected to the node VOUT_BST. The auto-zero switch 45 turns on / off the connection between the gate terminal and drain terminal of the P-type MOS transistor 43 in accordance with the digital control signal DIN_AZ.

[0072] [Explanation of operation timing and time waveform] 7 shows the voltage waveforms of the input terminal VIN and the output terminal VOUT, the time waveforms of the digital control signal DIN_FB indicating the settling acceleration period, and the time waveforms of the digital control signal DIN_AZ indicating the auto-zero period. Only the points different from FIG. 2 showing the operation of the settling acceleration circuit 13 will be explained below.

[0073] When the voltage of the input terminal VIN is held at a constant value, the digital control signal DIN_FB is set to a LOW level. In other words, the connection / disconnection switch 37 is disconnected, so that the current flowing from the drain terminal of the N-type MOS transistor 35 flows to the drain terminal of the P-type MOS transistor 43. During this period, an auto-zero period is provided in which the digital control signal DIN_AZ is set to a HIGH level. The auto-zero switch 45 is turned on, and the gate terminal and drain terminal of the P-type MOS transistor 43 are short-circuited, forming a diode connection.

[0074] The voltage at the gate terminal of the P-type MOS transistor 43 converges to a certain value so that the current between the source terminal and drain terminal of the P-type MOS transistor 43 becomes equal to the current flowing from the drain terminal of the N-type MOS transistor 35. When the auto-zero period ends, the voltage at the gate terminal of the P-type MOS transistor 43 is held in the capacitor 44. Since the current between the source terminal and drain terminal of the P-type MOS transistor 43 can be made equal to the current flowing to the drain terminal of the N-type MOS transistor 35 (the current of the auto-zero circuit stores the current of the current mirror circuit output to the node VOUT_BST), the offset voltage V that occurs in the voltage of the output terminal VOUT immediately before the settling acceleration period ends ERR can be made smaller.

[0075] 1, the current values of the constant current source 32 and the constant current source 36, the mirror ratio of the current mirror circuit, and other element parameters vary, making it difficult to match the current flowing to the drain terminal of the N-type MOS transistor 35 with the current of the constant current source 36. This difference in current flows to the output terminal VOUT through the connection / disconnection switch 37, causing a large offset voltage V ERR This leads to deterioration of the settling characteristics.

[0076] Therefore, the analog integrated circuit 11A can use its auto-zero function to accurately match the drain current of the P-type MOS transistor 43 with the drain current of the N-type MOS transistor 35. The offset current, which is the difference between the drain current of the P-type MOS transistor 43 and the drain current of the N-type MOS transistor 35, can be set to zero. When the settling of the output terminal VOUT converges and the voltage stabilizes during the settling acceleration period, the offset current flowing from the settling acceleration circuit 13A to the output terminal VOUT can be reduced, and voltage fluctuations at the output terminal VOUT can be suppressed during the read wait period, shortening the read wait period or reducing voltage errors when the voltage at the output terminal VOUT is read.

[0077] In this way, the analog integrated circuit 11A not only improves the performance of the analog integrated circuit 11, but also reduces variations in elements through the auto-zero function, thereby further improving performance.

[0078] <Third Configuration Example of Analog Integrated Circuit> Fig. 8 is a block diagram showing a configuration example of a third embodiment of an analog integrated circuit to which the present technology is applied. In the analog integrated circuit 11B shown in Fig. 8, components common to the analog integrated circuit 11 in Fig. 1 are denoted by the same reference numerals, and detailed description thereof will be omitted.

[0079] 8, the buffer unit 12 has the same circuit configuration as the buffer unit 12 in Fig. 1. The settling acceleration circuit 13B includes a P-type MOS transistor 31, a constant current source 32, a capacitor 33, an N-type MOS transistor 34, and an N-type MOS transistor 35, which have the same circuit configuration as the settling acceleration circuit 13 in Fig. 1.

[0080] 1 in that it includes a constant current source 49 and a current connection / disconnection switch 50. It is preferable, but not essential, to provide the constant current source 36 and connection / disconnection switch 37 of FIG. 1 in the settling acceleration circuit 13B. The settling acceleration circuit 13B does not include the constant current source 36 and connection / disconnection switch 37, and the drain terminal of the N-type MOS transistor 35 is directly connected to the output terminal VOUT.

[0081] The current connection switch 50 has one terminal connected to the constant current source 49, and the other terminal connected to the connection point of the P-type MOS transistor 31 and the N-type MOS transistor 34. The current connection switch 50 turns on / off the connection of the constant current source 49 in accordance with the digital control signal DIN_SI.

[0082] Therefore, the analog integrated circuit 11B having such a circuit configuration can improve the slew rate of the output terminal VOUT by controlling the digital control signal DIN_SI to a HIGH level during the period when the voltage value of the output terminal VOUT drops, turning on the current connection switch 50 and connecting the constant current source 49 to the N-type MOS transistor 34.

[0083] [Explanation of operation timing and time waveform] FIG. 9 shows the voltage waveforms of the input terminal VIN and the output terminal VOUT, and the time waveform of the digital control signal DIN_SI indicating the slew rate acceleration period (SR acceleration period).

[0084] When the voltage of the input terminal VIN is constant or changes little, settling acceleration of the voltage of the output terminal VOUT is not necessary, so the digital control signal DIN_SI is set to LOW level. Because no connection / disconnection switch is provided between the settling acceleration circuit 13B and the output terminal VOUT, the voltage of the output terminal VOUT always exhibits settling characteristics determined by the characteristics of the settling acceleration circuit 13B in addition to the characteristics of the voltage buffer 21, the resistance value of the resistor 22, and the capacitance value of the capacitor 23. Just before or at the moment the voltage of the input terminal VIN drops, the digital control signal DIN_SI is transitioned from LOW level to HIGH level, causing the current connection switch 50 to become conductive (SR acceleration period).

[0085] During the SR acceleration period, the DC current of the constant current source 49 is input to the drain terminal of the N-type MOS transistor 34, and the current amplified according to the current mirror ratio is output from the drain terminal of the N-type MOS transistor 35 and flows to the output terminal VOUT. The settling acceleration circuit 13B accelerates the settling of the output terminal VOUT, allowing the voltage of the output terminal VOUT to converge to the expected value in a shorter time.

[0086] During the SR acceleration period, the voltage at the output terminal VOUT drops to a voltage close to the expected value V2. After that, the digital control signal DIN_SI is returned to the LOW level. The process waits until the voltage at the output terminal VOUT stabilizes at the expected value V2. After that, the next-stage circuit connected to the output terminal VOUT reads the voltage at the output terminal VOUT.

[0087] The dotted line in Figure 9 shows the voltage waveform at the output terminal VOUT when settling is performed using a time constant determined by the voltage buffer circuit, resistors, and capacitors without using the settling acceleration circuit 13B. Without the settling acceleration circuit 13B, it takes time for the voltage at the output terminal VOUT to settle and stabilize after the voltage at the input terminal VIN starts to drop. Using the settling acceleration circuit 13B accelerates the settling of the output terminal VOUT, allowing the voltage to converge to the expected value in a short period of time, shortening the time from when the voltage at the input terminal VIN changes to when the voltage at the output terminal VOUT is read.

[0088] When the SR acceleration period ends and the digital control signal DIN_SI is set to a low level, the voltage of the output terminal VOUT converges to V2, which is lower than V1. Here, V1 shown in FIGS. 2 and 9 is an expected value and convergence value determined by the configuration of the buffer unit 12 to which the settling acceleration circuit is not connected. Since the settling acceleration circuit 13B does not include the connection / disconnection switch 37 or the constant current source 36, the output current from the drain terminal of the N-type MOS transistor 35 flows to the output terminal VOUT, causing the voltage to converge to V2, which is lower than V1 (an offset voltage V2-V1 is generated). Furthermore, when the SR acceleration period ends and the digital control signal DIN_SI is set to a low level, the settling acceleration circuit 13B is directly connected to the output terminal VOUT, so thermal noise and 1 / f noise from the elements that make up the settling acceleration circuit 13B are directly superimposed on the output terminal VOUT. Note that if the offset voltage, thermal noise, etc. cannot be tolerated, it is preferable to provide a constant current source 36 and a connection / disconnection switch 37, as in the settling acceleration circuit 13 of FIG. 1.

[0089] [Improvement of settling parameters (slew rate)] The slew rate SR3 of the output terminal VOUT during the SR acceleration period is determined by the characteristics of each element of the buffer unit 12 and the settling acceleration circuit 13B, and is expressed by the following equation (3).

[0090]

number

[0091] Here, the DC currents of the constant current source 32 and the constant current source 49 are respectively expressed as I BST and I SI When comparing the slew rate SR1 in the above formula (1), the slew rate SR2 in the above formula (2), and the slew rate SR3 in the above formula (3), it is clear that the absolute value |SR3| of the slew rate SR3 is larger than the absolute value |SR1| of the slew rate SR1 and the absolute value |SR2| of the slew rate SR2. In particular, by increasing M, which is the ratio of the current mirror circuit, and by increasing the DC current ISI It can be seen that by increasing |SR3|, the absolute value of the slew rate SR3 can be significantly increased, thereby improving the settling characteristics.

[0092] In this way, the analog integrated circuit 11B can improve the performance of the analog integrated circuit 11 and also improve the slew rate of the output terminal VOUT.

[0093] Fig. 10 is a circuit diagram showing a first modified example of the analog integrated circuit 11B. In the analog integrated circuit 11B-a shown in Fig. 10, components common to the analog integrated circuit 11B of Fig. 8 are given the same reference numerals, and detailed description thereof will be omitted.

[0094] In the analog integrated circuit 11B-a shown in Fig. 10, the buffer unit 12 has the same circuit configuration as the buffer unit 12 in Fig. 8. The settling acceleration circuit 13B-a includes a P-type MOS transistor 31, a constant current source 32, a capacitor 33, an N-type MOS transistor 34, an N-type MOS transistor 35, a constant current source 49, and a current connection switch 50, which have the same circuit configuration as the settling acceleration circuit 13B in Fig. 8.

[0095] The settling acceleration circuit 13B-a has a different configuration from the settling acceleration circuit 13B of FIG. 8 in that it includes a constant current source 36, a current cutoff switch 51, and an inverter 52.

[0096] One terminal of the current cutoff switch 51 is connected to the constant current source 36, and the other terminal is connected to the output terminal VOUT. An inverted signal of the digital control signal DIN_SI is input to the current cutoff switch 51 via an inverter 52, and the current cutoff switch 51 turns on / off the connection between the constant current source 36 and the output terminal VOUT.

[0097] The analog integrated circuit 11B-a having such a circuit configuration can improve the slew rate of the output terminal VOUT by controlling the digital control signal DIN_SI to a HIGH level during the period when the voltage value of the output terminal VOUT drops, turning on the current connection switch 50 and connecting the constant current source 49 to the N-type MOS transistor 34.

[0098] [Explanation of operation timing and time waveform] 11 shows the voltage waveforms of the input terminal VIN and the output terminal VOUT, and the time waveform of the digital control signal DIN_SI indicating the slew rate acceleration period (SR acceleration period). Only the differences from FIG. 9 will be explained below.

[0099] During the SR acceleration period, the voltage at the output terminal VOUT drops to a voltage close to the expected value V'1. After that, the digital control signal DIN_SI is returned to a low level. When the SR acceleration period ends and the digital control signal DIN_SI is returned to a low level, the voltage at the output terminal VOUT converges to V'1. After that, the next-stage circuit connected to the output terminal VOUT reads the voltage at the output terminal VOUT.

[0100] In the settling acceleration circuit 13B-a, the current of the constant current source 36 is M×I BST When the voltage at the output terminal VOUT has converged and stabilized, the output current M×I from the drain terminal of the N-type MOS transistor 35 is BST does not flow to the output terminal VOUT but flows to the constant current source 36. Therefore, the convergence value V'1 of the voltage at the output terminal VOUT can be made close to the convergence value V1 determined only by the configuration of the buffer unit 12. In other words, the offset voltage V'1-V1 by the settling acceleration circuit 13B-a can be made small.

[0101] [Improvement of settling parameters (slew rate)] During the SR acceleration period, the constant current source 36 is disconnected from the output terminal VOUT, and therefore does not affect the slew rate of the output terminal VOUT. Therefore, the slew rate of the output terminal VOUT during the SR acceleration period is expressed by the slew rate SR3 in the above formula (3), similar to the analog integrated circuit 11B, and it can be seen that the settling characteristics can be improved as described above.

[0102] In this way, the analog integrated circuit 11B-a can further improve the slew rate of the output terminal VOUT in addition to improving the performance of the analog integrated circuit 11. Furthermore, compared to the analog integrated circuit 11B, the analog integrated circuit 11B-a can reduce the offset of the voltage of the output terminal VOUT to the convergence value caused by the settling acceleration circuit 13B-a.

[0103] Fig. 12 is a circuit diagram showing a second modified example of the analog integrated circuit 11B. In the analog integrated circuit 11B-b shown in Fig. 12, components common to the analog integrated circuit 11B of Fig. 8 are given the same reference numerals, and detailed description thereof will be omitted.

[0104] In the analog integrated circuit 11B-b shown in Fig. 12, the buffer unit 12 has the same circuit configuration as the buffer unit 12 in Fig. 8. The settling acceleration circuit 13B-b includes a P-type MOS transistor 31, a constant current source 32, a capacitor 33, an N-type MOS transistor 34, and an N-type MOS transistor 35, which have the same circuit configuration as the settling acceleration circuit 13B in Fig. 8.

[0105] The settling acceleration circuit 13B-b has a different configuration from the settling acceleration circuit 13B of FIG.

[0106] The capacitor 53 has one terminal connected to the connection point of the P-type MOS transistor 31 and the constant current source 32, and the other terminal to which the digital control signal DIN_SC is input.

[0107] The analog integrated circuit 11B-b having such a circuit configuration can improve the slew rate of the output terminal VOUT by transitioning the digital control signal DIN_SC from a LOW level to a HIGH level during the period when the voltage value of the output terminal VOUT drops, and supplying the charge accumulated in the capacitor 53 to the connection point of the constant current source 32.

[0108] [Explanation of operation timing and time waveform] The operation of the settling acceleration circuit 13B-b is basically the same as that of the settling acceleration circuit 13B, and only the differences will be explained.

[0109] Figure 13 shows the voltage waveforms of the input terminal VIN and the output terminal VOUT, and the time waveform of the digital control signal DIN_SC. When the voltage of the input terminal VIN is constant or changes little, there is no need to accelerate the settling of the voltage of the output terminal VOUT, so the digital control signal DIN_SC is set to low level. The digital control signal DIN_SC is transitioned from low level to high level just before or at the moment the voltage of the input terminal VIN drops. This transition period is the slew rate acceleration period (SR acceleration period). Here, to clearly explain the effect of improving the slew rate, a period is provided in which the digital control signal DIN_SC is changed from low level to high level, but it may also be transitioned from low level to high level instantaneously.

[0110] During the SR acceleration period, the digital control signal DIN_SC changes from LOW level to HIGH level at the slew rate SR SC When the voltage changes, the capacitor 53 is charged with I SC =SR SC ×C SC The current M×I is generated and flows through the source terminal and drain terminal of the P-type MOS transistor 31 to the drain terminal of the N-type MOS transistor 34. The current M×I is amplified according to the current mirror ratio. SCis output from the drain terminal of the N-type MOS transistor 35 and flows to the output terminal VOUT. The settling acceleration circuit 13B-b accelerates the settling of the output terminal VOUT, allowing the voltage of the output terminal VOUT to converge to the expected value in a shorter time. The rest of the description is the same as for the settling acceleration circuit 13B, so a description thereof will be omitted.

[0111] [Improvement of settling parameters (slew rate)] The slew rate SR4 of the output terminal VOUT during the SR acceleration period is determined by the characteristics of each element of the buffer unit 12 and the settling acceleration circuit 13B-b, and is expressed by the following equation (4).

[0112]

number

[0113] When comparing the slew rate SR1 in the above formula (1), the slew rate SR2 in the above formula (2), and the slew rate SR4 in the above formula (4), it is clear that the absolute value |SR4| of the slew rate SR4 is larger than the absolute value |SR1| of the slew rate SR1 and the absolute value |SR2| of the slew rate SR2. In particular, by increasing M, which is the ratio of the current mirror circuit, and by increasing the capacitance C of the capacitor 53, SC Increase the DC current I SC It can be seen that by increasing |SR4|, the absolute value of the slew rate SR4 can be significantly increased, thereby improving the settling characteristics. Here, an example is shown in which one terminal of the capacitor 53 is connected to the source terminal of the P-type MOS transistor 31, but the same effect can be obtained by connecting it to the junction of the gate terminal and drain terminal of the N-type MOS transistor 34.

[0114] In this way, the analog integrated circuit 11B-b can improve the performance of the analog integrated circuit 11 and also improve the slew rate of the output terminal VOUT.

[0115] As described above, the analog integrated circuit 11 of each of the above-described embodiments and modifications can be used in an image sensor readout circuit including an image sensor.

[0116] <Fourth Configuration Example of Analog Integrated Circuit> Fig. 14 is a block diagram showing a configuration example of a fourth embodiment of an analog integrated circuit to which the present technology is applied. In the analog integrated circuit 11C shown in Fig. 14, components common to the analog integrated circuit 11 in Fig. 1 and the analog integrated circuit 11B-a in Fig. 10 are denoted by the same reference numerals, and detailed description thereof will be omitted.

[0117] An analog integrated circuit 11C shown in FIG. 14 is an image sensor readout circuit including an image sensor, and is made up of a pixel signal readout unit 67, a constant current source 69, a buffer unit 14 made up of a capacitor 23 and a resistor 22, and a settling acceleration circuit 13C.

[0118] The pixel signal readout unit 67 is composed of a photodiode 61, a transfer transistor 62, an FD node 63, an amplification transistor 64, a selection transistor 65, and a reset transistor 66. The output terminal of the pixel signal readout unit 67 is connected to a vertical signal line 68 via a resistor 22. The vertical signal line 68 is connected to a ground terminal VSS via a constant current source 69 and a capacitor 23 connected in parallel. The vertical signal line 68 is then connected to the gate terminal of a P-type MOS transistor 31 in the settling acceleration circuit 13C. Here, the resistor 22 and the capacitor 23 represent the parasitic wiring resistance and parasitic capacitance of the vertical signal line 68, respectively. The amplification transistor 64 and the constant current source 69 form a source follower circuit, which transmits the voltage of the FD node 63 to the vertical signal line 68. This is the same as the voltage buffer 21 described above, with the FD node 63 corresponding to the input terminal VIN and the output terminal VOUT corresponding to the vertical signal line 68.

[0119] 10, the settling acceleration circuit 13C includes a P-type MOS transistor 31, a constant current source 32, a capacitor 33, an N-type MOS transistor 34, an N-type MOS transistor 35, a constant current source 36, a constant current source 49, a current connection switch 50, a current interruption switch 51, and an inverter 52. Furthermore, like the settling acceleration circuit 13 of FIG. 1, the settling acceleration circuit 13C includes a connection interruption switch 37.

[0120] [Explanation of operation timing and time waveform] 15 shows the voltage waveforms of the digital control signals RST, TRG, DIN_SI, DIN_FB, and DIN_SAMP, the voltage waveform of the FD node 63, which is an analog signal of an internal node, and the voltage waveform of the vertical signal line 68 (VSL). The settling acceleration period is when the digital control signal DIN_FB is at a high level, and the slew rate acceleration period is when the digital control signal DIN_SI is at a high level. The pixel selection signal SEL is at a high level.

[0121] During the FD node reset period of the P-phase period, the FD node 63 is connected to the power supply terminal VDD, and the FD node 63 is reset. When the digital control signal RST transitions from a high level to a low level, the voltage of the FD node 63 drops due to the influence of feedthrough from the reset transistor 66, and the voltage of the vertical signal line 68 drops following the change in the FD node 63. A next-stage circuit (not shown) connected to the vertical signal line 68 waits for the voltage of the vertical signal line 68 to stabilize, and then reads the voltage VSL of the vertical signal line 68 at the timing to read out the P-phase VSL voltage. 1P Read out.

[0122] During the pixel charge transfer period of the D-phase period, the charge accumulated in the photodiode 61 is transferred to the FD node 63. At this time, the voltage of the FD node 63 rises due to the influence of feedthrough of the transfer transistor 62. When the digital control signal TRG transitions from a high level to a low level, the voltage of the FD node 63 drops significantly due to the influence of feedthrough of the transfer transistor 62. A next-stage circuit (not shown) connected to the vertical signal line 68 waits for the voltage of the vertical signal line 68 to stabilize, and then reads the voltage VSL of the vertical signal line 68 at the timing of reading out the D-phase VSL voltage. 1D Read out.

[0123] During the P-phase period and the D-phase period, the digital control signal DIN_FB transitions from low to high just before or at the moment the voltage of the vertical signal line 68 drops, turning on the connection cutoff switch 37. At this time, the node VOUT_BST and the vertical signal line 68 are shorted, and the settling acceleration circuit 13C accelerates the settling of the vertical signal line 68, allowing the voltage of the vertical signal line 68 to converge to the expected value in a shorter time. Furthermore, during the D-phase period, the digital control signal DIN_SI transitions from low to high and is held at high for a certain period (slew rate acceleration period). During the slew rate acceleration period, the voltage of the vertical signal line 68 drops, but by cutting off the current supplied from the constant current source 36 to the node VOUT_BST, the rate at which the voltage of the vertical signal line 68 drops during this period can be further accelerated.

[0124] The voltage of the vertical signal line 68 immediately after the end of the P-phase settling acceleration period is V 1P -V ERR The voltage of the vertical signal line 68 immediately after the end of the D-phase settling acceleration period is V 1D -V ERR V ERR is the error voltage generated by the element variations and noise of the settling acceleration circuit 13C (V ERR is preferably close to zero).

[0125] The error between the expected value of the VSL voltage immediately after the P-phase settling acceleration period ends is VERR The error between the expected value of the VSL voltage immediately after the D-phase settling acceleration period ends is also the same as ERR After the P-phase and D-phase settling acceleration periods are completed, the voltage of the vertical signal line 68 settles with a time constant determined only by the characteristics of each element of the buffer unit 14. ERR The influence of V becomes smaller, and the expected value V 1P and V 1D The CDS output, V 1D -V 1P Well then, V ERR The resulting settling error voltage is cancelled out, reducing its effect.

[0126] It is preferable to set the P-phase readout WAIT period and the D-phase readout WAIT period to the same value. In this case, the offset error V ERR The impact of

[0127] Therefore, like the analog integrated circuit 11 in Fig. 1, the analog integrated circuit 11C having such a circuit configuration can significantly improve the settling characteristics of the vertical signal line (shortening the time constant of the vertical signal line and improving the slew rate of the vertical signal line) while reducing the influence of thermal noise in the settling acceleration circuit. Furthermore, like the analog integrated circuit 11B-a in Fig. 10, the slew rate of the vertical signal line can be improved. Therefore, in an image sensor including an imaging element, the readout time of pixel signals can be shortened and increased in speed.

[0128] <Fifth Configuration Example of Analog Integrated Circuit> Fig. 16 is a block diagram showing a configuration example of a fifth embodiment of an analog integrated circuit to which the present technology is applied. Similar to the analog integrated circuit 11C of Fig. 14, the analog integrated circuit 11D shown in Fig. 16 is an image sensor including a buffer unit 14 serving as a pixel source follower circuit and a settling acceleration circuit 13D.

[0129] 16, the buffer unit 14 has the same circuit configuration as the buffer unit 14 in Fig. 14, and a resistor 22 and a capacitor 23 respectively represent the parasitic wiring resistance and parasitic capacitance of the vertical signal line 68. The settling acceleration circuit 13D is configured to include an N-type MOS transistor 81, a P-type MOS transistor 82, a capacitor 83, a P-type MOS transistor 84, an N-type MOS transistor 85, an N-type MOS transistor 86, a capacitor 87, and an N-type MOS transistor 88.

[0130] The vertical signal line 68 of the buffer unit 14 is connected to the source terminal of an N-type MOS transistor 81, and the drain terminal of the N-type MOS transistor 81 is connected to the connection point of the P-type MOS transistor 82 and the N-type MOS transistor 85. The N-type MOS transistor 81 is driven in accordance with a drive signal PC_DN3. A parasitic capacitance 89 of several pF is provided at the connection point between the vertical signal line 68 of the buffer unit 14 and the N-type MOS transistor 81.

[0131] The drain terminal of the P-type MOS transistor 82 is connected to the power supply terminal VDD, and the source terminal is connected to the drain terminal of the N-type MOS transistor 85. The capacitor 83 has one terminal connected to the power supply terminal VDD and the other terminal connected to the gate terminal of the P-type MOS transistor 82. The P-type MOS transistor 84 has one terminal connected to the junction of the gate terminal of the P-type MOS transistor 82 and the capacitor 83, and the other terminal connected to the junction of the P-type MOS transistor 82 and the N-type MOS transistor 85, and is driven in accordance with the drive signal XPC_LMSH. In other words, the P-type MOS transistor 82, the capacitor 83, and the P-type MOS transistor 84 form a second current source with a self-bias function to compensate for the current flowing through the N-type MOS transistor 86, which serves as an acceleration current source. The self-bias function is provided by the P-type MOS transistor 82, which serves as a diode-connected switch, and the sample / hold capacitor 83.

[0132] The N-type MOS transistor 85 has a drain terminal connected to the P-type MOS transistor 82 and a source terminal connected to the N-type MOS transistor 86, and is driven in accordance with the drive signal PC_DN. The N-type MOS transistor 86 has a drain terminal connected to the N-type MOS transistor 85, a source terminal connected to the ground terminal VSS, and a gate terminal connected to the connection point of the capacitor 87 and the N-type MOS transistor 88.

[0133] One terminal of the capacitor 87 is connected to the drain terminal of the N-type MOS transistor 81, and the other terminal is connected to the gate terminal of the N-type MOS transistor 86 and the drain terminal of the N-type MOS transistor 88. The N-type MOS transistor 88 is driven in accordance with the drive signal PC_LMSH.

[0134] The settling acceleration circuit 13D is configured as described above. The acceleration circuit section, which is composed of the N-type MOS transistor 85, the N-type MOS transistor 86, the capacitor 87, and the N-type MOS transistor 88, has a sample-and-hold function of the bias voltage by the drive signal PC_LMSH, and a certain constant current I EN This prevents the acceleration N-type MOS transistor 86 from turning off at the end of the acceleration period, thereby preventing a sudden drop in acceleration capability.

[0135] Furthermore, when the bias voltage is sampled and held, the N-type MOS transistor 81 driven in accordance with the drive signal PC_DN3 is turned off, and the N-type MOS transistor 85 driven in accordance with the drive signal PC_DN is turned on. The gate electrode of the N-type MOS transistor 86 is connected to the vertical signal line 68 via a capacitor 87, and fluctuations in the vertical signal line 68 are directly input to the N-type MOS transistor 86 as fluctuations in the gate-source voltage, thereby enabling efficient acceleration of the vertical signal line 68.

[0136] In addition, the current compensation unit consisting of the P-type MOS transistor 82, the capacitor 83, and the P-type MOS transistor 84 controls the current I so that the current does not become zero in the bias state of the N-type MOS transistor 86 for acceleration. EN This allows a sufficient current to be supplied to the N-type MOS transistor 86 even during convergence, thereby maintaining high speed.

[0137] Then, when the acceleration period ends, the N-type MOS transistor 81 is turned off in accordance with the drive signal PC_DN3, and the acceleration circuit unit and the current compensation unit are disconnected from the vertical signal line 68. At this time, noise from the acceleration circuit unit and the current compensation unit is stored in the parasitic capacitance 89, but the noise is reduced by the convergence operation of the buffer unit 14 after the acceleration period.

[0138] 17, during the sample and hold period from time t0 to time t1, the bias voltage can be held in a capacitor 87 connected between the output end of the vertical signal line 68 and the gate terminal of the N-type MOS transistor 86. When the output of the vertical signal line 68 rises due to the feedthrough phenomenon during the transfer of pixel signals, the applied voltage EMHIZ applied to the gate terminal of the N-type MOS transistor 86 also rises, as shown in FIG. 17. This causes a large difference in the voltage between the gate and source of the N-type MOS transistor 86, which serves as an acceleration current source.

[0139] Furthermore, the analog integrated circuit 11D connects the drain terminal of the N-type MOS transistor 86, which serves as an acceleration current source, to the output terminal of the vertical signal line 68 when the transfer of the pixel signal is completed (time t4), thereby rapidly extracting charge from the parasitic capacitance 89 of the vertical signal line 68, and as a result, accelerating the output of the vertical signal line 68. Note that in Figure 17, the output of the vertical signal line in conventional settling is indicated by a dashed line.

[0140] Then, after the acceleration is completed (time t5), an N-type MOS transistor 81 is provided to disconnect the acceleration circuit unit and the current compensation unit from the vertical signal line 68, and as a result, at the time of convergence, the noise added from the acceleration circuit unit is reduced by the buffer unit 14, as shown in Fig. 17. In other words, it is possible to achieve lower noise than before.

[0141] As described above, the analog integrated circuit 11D does not depend on negative capacitance by inputting the voltage of the vertical signal line 68 to the acceleration current source via the capacitor 87, and therefore can achieve more efficient acceleration with a smaller area and less power consumption than conventional devices. Furthermore, the analog integrated circuit 11D can significantly reduce the circuit size compared to conventional devices, and can therefore contribute to improved performance without making the sensor size a limiting factor for the lower chip.

[0142] It should be noted that a circuit configuration in which the N-type MOS transistors and P-type MOS transistors used in the description of this embodiment are combined in reverse may also be employed.

[0143] <Example of electronic device configuration> The imaging element described above can be applied to various electronic devices, such as imaging systems such as digital still cameras and digital video cameras, mobile phones with imaging functions, and other devices with imaging functions.

[0144] FIG. 18 is a block diagram showing an example of the configuration of an imaging device mounted on an electronic device.

[0145] As shown in FIG. 18, an imaging device 101 includes an optical system 102, an imaging element 103, a signal processing circuit 104, a monitor 105, and a memory 106, and is capable of capturing still images and moving images.

[0146] The optical system 102 is configured to have one or more lenses, and guides image light (incident light) from a subject to the image sensor 103, forming an image on the light receiving surface (sensor section) of the image sensor 103.

[0147] The above-described image sensor is used as the image sensor 103. Electrons are accumulated in the image sensor 103 for a certain period of time in accordance with an image formed on the light receiving surface via the optical system 102. A signal corresponding to the electrons accumulated in the image sensor 103 is then supplied to the signal processing circuit 104.

[0148] The signal processing circuit 104 performs various types of signal processing on the pixel signals output from the image sensor 103. The image (image data) obtained by the signal processing performed by the signal processing circuit 104 is supplied to a monitor 105 to be displayed, or supplied to a memory 106 to be stored (recorded).

[0149] In the imaging device 101 configured in this way, by applying the above-described imaging element, for example, it is possible to capture images with higher image quality.

[0150] <Examples of using image sensors> FIG. 19 is a diagram showing an example of using the image sensor (imaging element) described above.

[0151] The image sensor described above can be used in various cases for sensing light such as visible light, infrared light, ultraviolet light, and X-rays, for example, as follows.

[0152] ·Digital cameras, mobile devices with camera functions, and other devices that take images for viewing purposes - Devices used for traffic purposes, such as in-vehicle sensors that take pictures of the front, rear, surroundings, and interior of a vehicle for safe driving such as automatic stopping, and for recognizing the driver's condition, surveillance cameras that monitor moving vehicles and roads, and distance measuring sensors that measure distances between vehicles. A device used in home appliances such as TVs, refrigerators, and air conditioners to capture user gestures and operate the appliances according to those gestures. -Medical and healthcare equipment, such as endoscopes and devices that take blood vessel images using infrared light - Security devices such as surveillance cameras for crime prevention and cameras for person authentication Cosmetic devices such as skin measuring devices that take pictures of the skin and microscopes that take pictures of the scalp Sports equipment such as action cameras and wearable cameras for sports purposes Agricultural equipment such as cameras for monitoring the condition of fields and crops

[0153] <Configuration combination example> The present technology can also be configured as follows. (1) a first transistor having a gate electrode connected to an output terminal where a capacitance component is present; a first capacitor connected to the source terminal of the first transistor; a first constant current source connected to the source terminal of the first transistor; a current mirror circuit that amplifies a current from the drain terminal of the first transistor and outputs the amplified current to an output node; a second constant current source connected to the output node; a first switch disposed between the output terminal and the output node; Equipped with After a settling acceleration period in which the first switch is turned on to accelerate the settling of the voltage at the output terminal ends, the first switch is turned off and a readout circuit connected to the output terminal reads out the voltage at the output terminal. Settling acceleration circuit. (2) a second switch connected between the output node and the second constant current source; Furthermore, The second switch is turned off during a period other than the settling acceleration period to cut off the current flowing through the second constant current source. The settling acceleration circuit according to (1) above. (3) the current mirror circuit includes a second transistor and a third transistor whose gate terminals are connected to each other; a third switch connected to the gate terminal; Furthermore, During a period other than the settling acceleration period, the potential of the gate terminal is changed through the third switch to cut off the current flowing from the second constant current source to the third transistor. The settling acceleration circuit according to (1) or (2) above. (4) further comprising a comparator; The internal voltage or current of the settling acceleration circuit is compared with an externally set reference voltage or current by the comparator, and the on / off state of the third switch is controlled depending on the output result. The settling acceleration circuit according to (3) above. (5) the second constant current source has an auto-zero circuit consisting of a fourth transistor, a second capacitor, and a fourth switch; During a period other than the settling acceleration period, the current of the auto-zero circuit stores the current of the current mirror circuit output to the output node. A settling acceleration circuit according to any one of (1) to (4) above. (6) a first transistor having a gate electrode connected to an output terminal where a capacitance component is present; a first capacitor connected to the source terminal of the first transistor; a first constant current source connected to the source terminal of the first transistor; a current mirror circuit that amplifies a current from the drain terminal of the first transistor and outputs the amplified current to the output terminal; a third constant current source that supplies a current to the current mirror circuit; a fifth switch connecting the third constant current source and the current mirror circuit; Equipped with The fifth switch is turned on to increase the slew rate of the voltage of the output terminal during a slew rate acceleration period. Settling acceleration circuit. (7) a fourth constant current source for supplying a current to the output terminal; a sixth switch connecting the output terminal and the fourth constant current source; Furthermore, During the slew rate acceleration period, the sixth switch is turned off so that the current of the fourth constant current source does not flow to the output terminal. The settling acceleration circuit according to (6) above. (8) a third capacitor connected to the source terminal or the drain terminal of the first transistor or the current mirror circuit; Furthermore, During the slew rate acceleration period, the charge held in the third capacitor is supplied as a current to the current mirror circuit, thereby improving the slew rate of the voltage at the output terminal. The settling acceleration circuit according to (6) above. (9) a first transistor having a gate electrode connected to an output terminal where a capacitance component is present; a first capacitor connected to the source terminal of the first transistor; a first constant current source connected to the source terminal of the first transistor; a current mirror circuit that amplifies a current from the drain terminal of the first transistor and outputs the amplified current to an output node; a second constant current source connected to the output node; a first switch disposed between the output terminal and the output node; Equipped with After a settling acceleration period in which the first switch is turned on to accelerate the settling of the voltage at the output terminal ends, the first switch is turned off and a readout circuit connected to the output terminal reads out the voltage at the output terminal. Image sensor readout circuit using a settling acceleration circuit. (10) a first transistor having a gate electrode connected to an output terminal where a capacitance component is present; a first capacitor connected to the source terminal of the first transistor; a first constant current source connected to the source terminal of the first transistor; a current mirror circuit that amplifies a current from the drain terminal of the first transistor and outputs the amplified current to the output terminal; a third constant current source that supplies a current to the current mirror circuit; a fifth switch connecting the third constant current source and the current mirror circuit; Equipped with The fifth switch is turned on to increase the slew rate of the voltage of the output terminal during a slew rate acceleration period. Image sensor readout circuit using a settling acceleration circuit. (11) a pixel source follower circuit having a signal line for outputting a pixel signal from the pixel; A transistor that acts as an acceleration current source Equipped with The signal line is connected to the gate terminal of the transistor via a capacitor. Image sensor readout circuit. (12) Further provided is a second current source having a self-bias function to compensate for the current flowing through the acceleration current source. The image sensor readout circuit according to (11) above. (13) The self-bias function is composed of a transistor that serves as a switch that configures a diode connection and a capacitance element for sample / hold. The image sensor readout circuit according to (12) above.

[0154] It should be noted that the present embodiment is not limited to the above-described embodiment, and various modifications are possible within the scope of the gist of the present disclosure. Furthermore, the effects described in this specification are merely examples and are not intended to be limiting, and other effects may also be obtained. [Explanation of symbols]

[0155] 11 Analog integrated circuit, 12 Buffer section, 13 Settling acceleration circuit, 14 Buffer section, 21 Voltage buffer, 21, 22 Resistor, 23 Capacitor, 31 P-type MOS transistor, 32 Constant current source, 33 Capacitor, 34 N-type MOS transistor, 35 N-type MOS transistor, 36 Constant current source, 37 Connection / disconnection switch, 38 Current disconnection switch, 39 Current disconnection switch, 40 Inverter, 41 Current disconnection switch, 42 Comparator, 43 P-type MOS transistor, 44 Capacitor, 45 Auto-zero switch, 46 Connection / disconnection switch, 47 Inverter, 48 Changeover switch, 49 Constant current source, 50 Current connection switch, 51 Current disconnection switch, 52 Inverter, 53 Inverter, 54 Capacitor

Claims

1. a first transistor having a gate electrode connected to an output terminal where a capacitance component is present; a first capacitor connected to the source terminal of the first transistor; a first constant current source connected to the source terminal of the first transistor; a current mirror circuit that amplifies a current from the drain terminal of the first transistor and outputs the amplified current to an output node; a second constant current source connected to the output node; a first switch disposed between the output terminal and the output node; Equipped with After a settling acceleration period in which the first switch is turned on to accelerate the settling of the voltage at the output terminal is completed, the first switch is turned off and a readout circuit connected to the output terminal reads out the voltage at the output terminal. Settling acceleration circuit.

2. a second switch connected between the output node and the second constant current source; Furthermore, The second switch is turned off during a period other than the settling acceleration period to cut off the current flowing through the second constant current source.

2. The settling acceleration circuit of claim 1.

3. the current mirror circuit includes a second transistor and a third transistor whose gate terminals are connected to each other; a third switch connected to the gate terminal; Furthermore, During a period other than the settling acceleration period, the potential of the gate terminal is changed through the third switch to cut off the current flowing from the second constant current source to the third transistor.

2. The settling acceleration circuit of claim 1.

4. further comprising a comparator; The internal voltage or current of the settling acceleration circuit is compared with an externally set reference voltage or current by the comparator, and the on / off state of the third switch is controlled depending on the output result.

4. The settling acceleration circuit of claim 3.

5. the second constant current source has an auto-zero circuit consisting of a fourth transistor, a second capacitor, and a fourth switch; During a period other than the settling acceleration period, the current of the auto-zero circuit stores the current of the current mirror circuit output to the output node.

2. The settling acceleration circuit of claim 1.

6. a first transistor having a gate electrode connected to an output terminal where a capacitance component is present; a first capacitor connected to the source terminal of the first transistor; a first constant current source connected to the source terminal of the first transistor; a current mirror circuit that amplifies a current from the drain terminal of the first transistor and outputs the amplified current to the output terminal; a third constant current source that supplies a current to the current mirror circuit; a fifth switch connecting the third constant current source and the current mirror circuit; Equipped with The fifth switch is made conductive to increase the slew rate of the voltage of the output terminal during a slew rate acceleration period. Settling acceleration circuit.

7. a fourth constant current source for supplying a current to the output terminal; a sixth switch connecting the output terminal and the fourth constant current source; Furthermore, During the slew rate acceleration period, the sixth switch is turned off so that the current of the fourth constant current source does not flow to the output terminal.

7. The settling acceleration circuit of claim 6.

8. a third capacitor connected to the source terminal or the drain terminal of the first transistor or the current mirror circuit; Furthermore, During the slew rate acceleration period, the charge held in the third capacitor is supplied as a current to the current mirror circuit, thereby improving the slew rate of the voltage at the output terminal.

7. The settling acceleration circuit of claim 6.

9. a first transistor having a gate electrode connected to an output terminal where a capacitance component is present; a first capacitor connected to the source terminal of the first transistor; a first constant current source connected to the source terminal of the first transistor; a current mirror circuit that amplifies a current from the drain terminal of the first transistor and outputs the amplified current to an output node; a second constant current source connected to the output node; a first switch disposed between the output terminal and the output node; Equipped with After a settling acceleration period in which the first switch is turned on to accelerate the settling of the voltage at the output terminal is completed, the first switch is turned off and a readout circuit connected to the output terminal reads out the voltage at the output terminal. Image sensor readout circuit using a settling acceleration circuit.

10. a first transistor having a gate electrode connected to an output terminal where a capacitance component is present; a first capacitor connected to the source terminal of the first transistor; a first constant current source connected to the source terminal of the first transistor; a current mirror circuit that amplifies a current from the drain terminal of the first transistor and outputs the amplified current to the output terminal; a third constant current source that supplies a current to the current mirror circuit; a fifth switch connecting the third constant current source and the current mirror circuit; Equipped with The fifth switch is made conductive to increase the slew rate of the voltage of the output terminal during a slew rate acceleration period. Image sensor readout circuit using a settling acceleration circuit.

11. a pixel source follower circuit having a signal line for outputting a pixel signal from the pixel; A transistor that acts as an accelerating current source Equipped with The signal line is connected to the gate terminal of the transistor via a capacitor. Image sensor readout circuit.

12. Further provided is a second current source having a self-bias function to compensate for the current flowing through the acceleration current source.

12. The image sensor readout circuit of claim 11.

13. The self-bias function is composed of a transistor that serves as a switch that configures a diode connection and a capacitance element for sample / hold.

13. The image sensor readout circuit of claim 12.

Images