High-speed interface time sequence error correction device and error correction method based on FPGA (Field Programmable Gate Array)

Abstract

The invention provides a high-speed interface time sequence error correction device and method based on an FPGA, and belongs to the technical field of electronic information. The device comprises an ADC working state control module, a data receiving delay module, a serial-parallel conversion module, a phase-locked loop clock module and a delay parameter training module. The ADC working state control module is used for controlling the working state of the ADC module to output a test code; the data receiving delay module is used for performing delay alignment on the received data; the serial-to-parallel conversion module is used for converting the received serial data into parallel data; the phase-locked loop clock module provides required clock signals for the serial-parallel conversion module and the delay parameter training module; and the delay parameter training module is used for traversing all delay Delaytap values and calculating an optimal Delaytap value. According to the invention, multi-bit ADC data can be trained at the same time, available IDELAYTAP is trained without length requirements, and the method can be applied to a wider working environment.

Description

Technical Field

[0001] The present invention belongs to the technical field of FPGA data interface communication, and in particular relates to a high-speed interface timing error correction device and an error correction method based on FPGA. Background Art

[0002] With the development of modern electronic technology, electronic products have higher and higher requirements for data volume. High speed and high bandwidth have become technical terms that cannot be avoided in product design. As a high-speed interface communication technology, LVDS interface communication technology has the characteristics of low power consumption, low bit error rate, low crosstalk and low radiation. The maximum rate can reach 3.125Gbps. It is widely used in board-to-board, chip-to-chip and other connection methods. LVDS communication can ensure the stability and correctness of the sampled data, but due to the wiring difference between the transmitter and the receiver, when the receiver samples the data with the clock signal, the setup time may not be met or the setup time is too small, resulting in the inability to correctly collect data. In particular, the LVDS interface between the high-speed ADC and the FPGA has the characteristics of fast transmission rate and large bit width. Once a bit of data is metastable, it will seriously affect the sampling performance of the ADC.

[0003] At present, many timing trainings for LVDS interfaces have limitations. Some ignore whether the phase difference between the sampling clock and data is optimal. Some require training of three consecutive sets of TAP values ​​before the training is considered successful. Therefore, sufficient delay_tap values ​​must be trained to determine that the training is successful. Therefore, in harsh ambient temperatures, training failure is easily caused due to overly tight timing. Summary of the invention

[0004] The purpose of the present invention is to provide a high-speed interface timing error correction device and error correction method based on FPGA, which can simultaneously train multi-bit ADC data and train available IDELAY_TAP without length requirement, and can be applied in a wider working environment.

[0005] The above purpose is achieved through the following technical solutions: The present invention first provides a high-speed interface timing error correction device based on FPGA, which includes an ADC working state control module, a data receiving delay module, a serial-to-parallel conversion module, a phase-locked loop clock module, and a delay parameter training module; The ADC working state control module is used to control the ADC module working state to output a test code; The data receiving delay module is used to delay and align the received data; The serial-to-parallel conversion module is used to convert the received serial data into parallel data; The phase-locked loop clock module provides the required clock signal for the serial-to-parallel conversion module and the delay parameter training module; The delay parameter training module is used to traverse all delay Delay_tap values ​​and calculate the optimal Delay_tap value.

[0006] Another object of the present invention is to provide a method for performing high-speed interface timing error correction using the above-mentioned FPGA-based high-speed interface timing error correction device, the method comprising the following steps: Step 1, the phase-locked loop clock module outputs a clock signal to the serial-to-parallel conversion module and the delay parameter training module, and the ADC working state control module controls the FPGA to enter the training mode and outputs a test code; Step 2, the data receiving delay module and the serial-to-parallel conversion module respectively delay and serial-to-parallel convert the received data; Step 3, the delay parameter training module traverses all delay Delay_tap values ​​under normal test code reception conditions; Step 4, the delay parameter training module calculates the optimal Delay_tap value and assigns it to the delay Idelay module; Step 5: FPGA switches back to normal mode.

[0007] Furthermore, the specific method of step 2 is: The data receiving delay module converts the received serial differential data, including data and clock signals, into single-ended signals through IBUFDS differential conversion. The data and clock signals are delayed through the delay Idelay module inside the FPGA. The Idelay inside the FPGA is divided into fixed delay and dynamically allocated delay. The LVDS data branch passes through the dynamic allocation delay circuit; the clock signal passes through a circuit with a fixed delay parameter of 0 as a reference signal. During the subsequent signal transmission process, the fixed delay does not change. The data signal passes through a variable delay circuit. During the subsequent signal transmission process, the delay step is changed to adjust the relative relationship with the fixed delay path.

[0008] Furthermore, the specific method of step 3 is: automatically stepping the delay step value Delay_tap of the variable delay circuit of the data signal branch, the step range is 0~31, judging the test code obtained under each step value, and finding all Delay_tap values ​​under normal test code reception conditions.

[0009] Furthermore, the specific method of step 4 is: the optimal value is the middle value of the longest Delay_tap value interval under normal circumstances for all test codes to receive, and it is loaded into the IDELAY module to meet the optimal interface timing Compared with the prior art, the significant advantage of the present invention is that it can train multi-bit ADC data at the same time, and the available IDELAY_TAP trained has no length requirement, which can be applied in a wider working environment. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 A flow chart of the FPGA-based high-speed interface timing error correction method proposed by the present invention; Figure 2 It is a system structure diagram of the timing error correction method proposed by the present invention. DETAILED DESCRIPTION

[0011] The specific embodiments of the present invention are further described below in conjunction with the accompanying drawings. It should be noted again that the description of these embodiments is used to help understand the present invention, but does not constitute a limitation of the present invention.

[0012] The present invention provides Figure 1 The FPGA-based high-speed interface timing error correction method shown includes the following steps: Step 1: Control the FPGA to enter the training mode and control the high-speed ADC to output multiple parallel test codes. Taking 10-bit ADC as an example, the typical value is that after continuously sending 11 10-bit all-0 data, the 12th data is all-1, and it is sent cyclically in this way; Step 2: FPGA converts the received serial differential data into single-ended signals through the IBUFDS differential-to-single-ended primitive and processes them. The data and clock signals are delayed by the Idelay module inside the FPGA. The clock signal passes through the fixed delay circuit, and the data signal passes through the variable delay circuit. Then, they enter the serial-to-parallel conversion module inside the FPGA to convert the serial high-speed data into low-speed parallel data. Step 3, automatically step the delay step value Delay_tap of the variable delay circuit of the data signal branch, and the step range is 0 to 31. Sum the parallel test codes obtained under each step value to find out all Delay_tap values ​​under normal test code reception conditions; Step 4, calculate the intermediate value of the above Delay_tap value and assign it to the Idelay module; Step 5: FPGA switches back to normal mode.

[0013] Figure 2 The high-speed interface timing error correction device based on FPGA of the present invention comprises an ADC working state control module, a data receiving delay module, a serial-to-parallel conversion module, a phase-locked loop clock module, and a delay parameter training module; The ADC working state control module is used to control the ADC module working state to output a test code; The data receiving delay module is used to delay and align the received data; The serial-to-parallel conversion module is used to convert the received serial data into parallel data; The phase-locked loop clock module provides the required clock signal for the serial-to-parallel conversion module and the delay parameter training module; The delay parameter training module is used to traverse all delay Delay_tap values ​​and calculate the optimal Delay_tap value.

Claims

1. A high-speed interface timing error correction device based on FPGA, characterized in that: The device includes an ADC working state control module, a data receiving delay module, a serial-to-parallel conversion module, a phase-locked loop clock module, and a delay parameter training module; The ADC working state control module is used to control the ADC module working state to output a test code; The data receiving delay module is used to delay and align the received data; The serial-to-parallel conversion module is used to convert the received serial data into parallel data; The phase-locked loop clock module provides the required clock signal for the serial-to-parallel conversion module and the delay parameter training module; The delay parameter training module is used to traverse all delay Delay_tap values ​​and calculate the optimal Delay_tap value.

2. A method for performing high-speed interface timing error correction using the FPGA-based high-speed interface timing error correction device according to claim 1, characterized in that: The method comprises the following steps: Step 1, the phase-locked loop clock module outputs a clock signal to the serial-to-parallel conversion module and the delay parameter training module, and the ADC working state control module controls the FPGA to enter the training mode and outputs a test code; Step 2, the data receiving delay module and the serial-to-parallel conversion module respectively delay and serial-to-parallel convert the received data; Step 3, the delay parameter training module traverses all delay Delay_tap values ​​under normal test code reception conditions; Step 4, the delay parameter training module calculates the optimal Delay_tap value and assigns it to the delay Idelay module; Step 5: FPGA switches back to normal mode.

3. The FPGA-based high-speed interface timing error correction method according to claim 2, characterized in that: The specific method of step 2 is: The data receiving delay module converts the received serial differential data, including data and clock signals, into single-ended signals through IBUFDS differential conversion. The data and clock signals are delayed through the delay Idelay module inside the FPGA. The Idelay inside the FPGA is divided into two types: fixed delay and dynamically allocated delay. The LVDS data branch passes through the dynamic allocation delay circuit; the clock signal passes through a circuit with a fixed delay parameter of 0 as a reference signal. During the subsequent signal transmission process, the fixed delay does not change. The data signal passes through a variable delay circuit. During the subsequent signal transmission process, the delay step is changed to adjust the relative relationship with the fixed delay path.

4. The FPGA-based high-speed interface timing error correction method according to claim 2, characterized in that: The specific method of step 3 is: automatically step the delay step value Delay_tap of the variable delay circuit of the data signal branch, the step range is 0~31, judge the test code obtained under each step value, and find out all Delay_tap values ​​under normal test code reception.

5. The FPGA-based high-speed interface timing error correction method according to claim 2, characterized in that: The specific method of step 4 is: the optimal value is the middle value of the longest Delay_tap value interval under normal circumstances received by all test codes, and it is loaded into the IDELAY module to meet the optimal interface timing.

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