Passive drive capacitor array structure, gradual approximation type analog-to-digital converter and method
By adopting a passively driven capacitance array structure in the gradual approximation type analog-to-digital converter, and using the compensation capacitor array to compensate for charge loss, the high energy consumption and large-area occupation problems caused by the high switching frequency of the DAC capacitor array in traditional technology are solved, and efficient analog-to-digital conversion and low-power design are achieved.
Patent Information
- Application Number
- CN202411730102.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-11-28
- Publication Date
- 2025-03-25
AI Technical Summary
The high switching frequency requirements of the DAC capacitor array in traditional gradual approximation type analog-to-digital converters cause the reference voltage driving circuit to consume high energy or occupy a large area, making it difficult to achieve efficient analog-to-digital conversion.
The passively driven capacitance array structure is adopted, including a DAC capacitor array and a compensation capacitor array, passively driven by the first capacitor, and charge loss during the voltage conversion of the DAC capacitor array is compensated by a plurality of second capacitor groups to ensure that the target reference signal conforms to the binary relationship.
Through the passive driving capacitive array structure, the use of high-bandwidth active driver is avoided, which greatly saves power consumption and reduces the area overhead of the capacitive array.
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Figure CN119696586A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of integrated circuit technology, and in particular to a passively driven capacitor array structure, a successive approximation analog-to-digital converter and a method. Background Art
[0002] Successive Approximation Register Analog-to-Digital Converter (SAR ADC) is an analog-to-digital converter widely used in digitizing analog signals.
[0003] The architecture of the traditional SAR ADC is shown in the figure below. Figure 1 As shown, assuming that the initial reference voltage of the input is VR. In any conversion cycle, the DAC capacitor array will generate a series of voltage references: VR*C(N) / CT (N=1,2,3,4,5...) to compare with the input signal to implement the binary search method, where C(N) is the capacitance value switched in each step of the DAC capacitor array, and CT is the total capacitance value of the DAC capacitor array. Ideally, C(N)=2*C(N+1), VR and CT are constants, thus realizing the binary voltage search algorithm. For a SAR ADC with an M-bit resolution, the DAC capacitor array needs to be switched at least M-1 times in each conversion cycle, so the switching frequency of the DAC capacitor array is much higher than the SAR ADC operating frequency. This puts high demands on the reference voltage driving circuit of the DAC capacitor array: it needs to be stable in a very short time and provide a precise and constant reference voltage VR to the DAC capacitor array. This results in the reference voltage driving circuit often consuming a lot of energy or occupying a large chip area. Summary of the invention
[0004] Based on this, it is necessary to provide a passively driven capacitor array structure, a successive approximation analog-to-digital converter and method, and an electronic device to address the above technical issues.
[0005] In a first aspect, an embodiment of the present invention provides a passively driven capacitor array structure, which is applied to a successive approximation analog-to-digital converter, wherein the capacitor array structure includes a DAC capacitor array and a compensation capacitor array connected to the DAC capacitor array, wherein the DAC capacitor array outputs a target reference signal for comparison with an input signal, and the compensation capacitor array includes:
[0006] A first capacitor, connected to the DAC capacitor array, configured to follow an initial reference voltage and share a charge corresponding to the initial reference voltage with the DAC capacitor array;
[0007] A plurality of second capacitors are connected to the DAC capacitor array and are used to compensate for charge loss during voltage conversion of the DAC capacitor array, so that the target reference signal output by the DAC capacitor array conforms to a binary relationship.
[0008] In some embodiments, the compensation capacitor array includes:
[0009] N second capacitor groups arranged in sequence, each of the second capacitor groups includes two second capacitors connected in parallel, a lower plate of each second capacitor is connected to a common ground, and an upper plate is connected to the DAC capacitor array through a corresponding switch, and N represents the number of bits of a successive approximation analog-to-digital converter;
[0010] According to the comparison result of the target reference signal and the input signal last time, the second capacitor in the corresponding second capacitor group is controlled to be connected to compensate the charge loss of the DAC capacitor array during the voltage conversion process.
[0011] In some embodiments, the compensation capacitor array includes:
[0012] If, in the i-th comparison result, the target reference signal is smaller than the input signal, then controlling a second capacitor in the i-th group of the second capacitors to be connected to compensate for the charge loss of the DAC capacitor array during the voltage conversion process;
[0013] If the target reference signal is greater than the input signal in the i-th comparison result, another second capacitor in the i-th second capacitor group is controlled to be connected to compensate for the charge loss of the DAC capacitor array during the voltage conversion process.
[0014] In some embodiments, the bipartite relationship is:
[0015] |VDAC(i+1)-VDAC(i)|=2*|(VDAC(i+2)-VDAC(i+1))|
[0016] Among them, VDAC(i+1) represents the current target reference signal, VDAC(i+2) represents the next target reference signal, and VDAC(i) represents the previous target reference signal.
[0017] In some embodiments, the DAC capacitor array includes:
[0018] N third capacitors arranged in sequence, the lower plate of each of the third capacitors being connected to the compensation capacitor array or a common ground through a corresponding switch, and the upper plate being connected to a common end for outputting the target reference signal;
[0019] According to the comparison result of the target reference signal and the input signal last time, the corresponding third capacitor is controlled to be connected, and the charge is shared with the first capacitor and the corresponding second capacitor to output the target reference signal.
[0020] In some embodiments, if in the i-th comparison result, the target reference signal is smaller than the input signal, the lower plate of the i-th third capacitor is controlled to be connected to the common ground, and the lower plate of the first third capacitor is controlled to be connected to the compensation capacitor array;
[0021] If in the i-th comparison result, the target reference signal is greater than the input signal, the lower plate of the i-th third capacitor is controlled to be connected to the compensation capacitor array, and the lower plate of the first third capacitor is controlled to be connected to the common ground.
[0022] In a second aspect, an embodiment of the present invention provides a successive approximation analog-to-digital converter, comprising:
[0023] The capacitor array structure as described in the first aspect is used to output a target reference signal;
[0024] A sampling and holding circuit, connected to the capacitor array structure, for summing the received input signal with the target reference signal to obtain a comparison signal;
[0025] A comparator, connected to the sample-and-hold circuit, for comparing the comparison signal with a reference value to obtain a comparison result;
[0026] The logic circuit is connected to the capacitor array structure, and is used to feed back the comparison result to the capacitor array structure, and output the code value according to the successive comparison results.
[0027] In a third aspect, an embodiment of the present invention provides a control method for a successive approximation analog-to-digital converter, which is applied to the successive approximation analog-to-digital converter as described in the second aspect, comprising:
[0028] Controlling the connection of a second capacitor in the corresponding second capacitor group according to the comparison result of the target reference signal and the input signal last time, so as to compensate for the charge loss of the DAC capacitor array during the voltage conversion process; and
[0029] A corresponding third capacitor is controlled to be connected to share charges with the first capacitor and the corresponding second capacitor to output the target reference signal.
[0030] In some embodiments, if in the i-th comparison result, the target reference signal is less than the input signal, the lower plate of the i-th third capacitor is controlled to be connected to the common ground, the lower plate of the first third capacitor is controlled to be connected to the compensation capacitor array; and another second capacitor in the i-th group of the second capacitor group is controlled to be connected to compensate for the charge loss of the DAC capacitor array during the voltage conversion process;
[0031] If in the i-th comparison result, the target reference signal is greater than the input signal, then the lower plate of the i-th third capacitor is controlled to be connected to the compensation capacitor array, and the lower plate of the first third capacitor is controlled to be connected to the common ground; and one of the second capacitors in the i-th group of the second capacitors is controlled to be connected to compensate for the charge loss of the DAC capacitor array during the voltage conversion process.
[0032] In a fourth aspect, an embodiment of the present invention provides an electronic device, comprising the successive approximation analog-to-digital converter as described in the second aspect.
[0033] The passively driven capacitor array structure, the progressive approximation analog-to-digital converter and the method proposed in the present application can avoid the use of high-bandwidth active drive by passively driving the first capacitor, thereby greatly saving power consumption. At the same time, because the second capacitor is used as charge compensation, the first capacitor does not need to be very large, and the passively driven capacitor array structure only requires a small area cost. BRIEF DESCRIPTION OF THE DRAWINGS
[0034] Figure 1 A schematic diagram of the structure of a successive approximation analog-to-digital converter in the related art of this application;
[0035] Figure 2 A schematic structural diagram of a passively driven capacitor array structure in an embodiment provided in the present application;
[0036] Figure 3 A first connection diagram of a successive approximation analog-to-digital converter in an embodiment provided by the present application;
[0037] Figure 4 A second connection diagram of a successive approximation analog-to-digital converter in an embodiment provided by the present application;
[0038] Figure 5 A third connection diagram of a successive approximation analog-to-digital converter in an embodiment provided by the present application;
[0039] Figure 6 A fourth connection diagram of a successive approximation analog-to-digital converter in an embodiment provided by the present application;
[0040] Figure 7A schematic diagram of the structure of a successive approximation analog-to-digital converter in an embodiment provided in the present application;
[0041] Figure 8 A schematic flow chart of a control method of a successive approximation analog-to-digital converter in an embodiment provided in the present application. DETAILED DESCRIPTION
[0042] In order to make the purpose, technical solutions and advantages of the present application clearer, the present application is described and illustrated below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not intended to limit the present application. Based on the embodiments provided in the present application, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present application. In addition, it can also be understood that although the efforts made in this development process may be complex and lengthy, for ordinary technicians in the field related to the contents disclosed in the present application, some changes such as design, manufacturing or production based on the technical contents disclosed in the present application are only conventional technical means, and should not be understood as insufficient contents disclosed in the present application.
[0043] Reference to "embodiments" in this application means that a particular feature, structure, or characteristic described in conjunction with the embodiments may be included in at least one embodiment of the present application. The appearance of the phrase in various locations in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment that is mutually exclusive with other embodiments. It is explicitly and implicitly understood by those of ordinary skill in the art that the embodiments described in this application may be combined with other embodiments without conflict.
[0044] Unless otherwise defined, the technical terms or scientific terms involved in this application should be understood by people with ordinary skills in the technical field to which this application belongs. The words "one", "a", "a", "the" and the like involved in this application do not indicate a quantitative limitation, and may represent the singular or plural. The terms "include", "comprise", "have" and any of their variations involved in this application are intended to cover non-exclusive inclusions; for example, a process, method, system, product or device that includes a series of steps or modules (units) is not limited to the listed steps or units, but may also include steps or units that are not listed, or may also include other steps or units inherent to these processes, methods, products or devices. The words "connect", "connected", "coupled" and the like involved in this application are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. The "multiple" involved in this application refers to greater than or equal to two. "And / or" describes the association relationship of associated objects, indicating that there can be three relationships, for example, "A and / or B" can represent: A exists alone, A and B exist at the same time, and B exists alone. The terms "first", "second", "third" and the like involved in the present application are merely used to distinguish similar objects and do not represent a specific ordering of the objects.
[0045] Figure 2 A schematic diagram of a passively driven capacitor array structure in some embodiments provided in the present application, wherein the capacitor array structure includes a DAC capacitor array and a compensation capacitor array connected to the DAC capacitor array, wherein the DAC capacitor array outputs a target reference signal VDAC(i) for comparison with an input signal, and the compensation capacitor array is used to follow an initial reference signal VR to compensate for charge loss during voltage conversion of the DAC capacitor array.
[0046] like Figure 3 As shown, the compensation capacitor array includes: a first capacitor Cd, connected to the DAC capacitor array, used to follow the initial reference voltage VR and share the charge corresponding to the initial reference voltage with the DAC capacitor array; a plurality of second capacitors (Cc(0)...), connected to the DAC capacitor array, used to compensate for the charge loss in the voltage conversion process of the DAC capacitor array, so that the target reference signal output by the DAC capacitor array conforms to the binary relationship.
[0047] The first capacitor is used as a pre-charge capacitor, and the voltage across it is pre-charged to an initial reference voltage VR. In the signal following stage, it only needs to be connected to a low-power drive circuit. During the SAR ADC conversion process, the drive circuit does not need to be turned on, thereby greatly saving power consumption.
[0048] The second capacitors are used to compensate for the charge loss of the DAC capacitor array during each voltage conversion process. The value of each second capacitor can be calculated and selected in advance according to the law of conservation of charge.
[0049] In this embodiment, by passively driving the first capacitor, high-bandwidth active driving can be avoided, thereby greatly saving power consumption. At the same time, because the second capacitor is used as charge compensation, the first capacitor does not need to be very large, and this passively driven capacitor array structure only requires a small area overhead.
[0050] Specifically, the compensation capacitor array includes: N second capacitor groups arranged in sequence, each second capacitor group includes two second capacitors connected in parallel, the lower plate of each second capacitor is connected to a common ground, and the upper plate is connected to the DAC capacitor array through a corresponding switch, and N represents the number of bits of the successive approximation analog-to-digital converter.
[0051] like Figure 3 As shown, the second capacitors Cc(0) and Cc(1) form a second capacitor group, and the second capacitors Cc(00) and Cc(01) form a second capacitor group.
[0052] According to the comparison result of the target reference signal and the input signal last time, the second capacitor in the corresponding second capacitor group is controlled to be connected to compensate the charge loss of the DAC capacitor array during the voltage conversion process.
[0053] Specifically, if in the i-th comparison result, the target reference signal is smaller than the input signal, then one of the second capacitors in the i-th group of the second capacitors is controlled to be connected to compensate for the charge loss of the DAC capacitor array during the voltage conversion process;
[0054] If the target reference signal is greater than the input signal in the i-th comparison result, another second capacitor in the i-th second capacitor group is controlled to be connected to compensate for the charge loss of the DAC capacitor array during the voltage conversion process.
[0055] The DAC capacitor array includes: N third capacitors arranged in sequence, the lower board of each third capacitor is connected to the compensation capacitor array or the common ground through a corresponding switch, and the upper board is connected to the common end for outputting the target reference signal.
[0056] According to the comparison result of the target reference signal and the input signal last time, the corresponding third capacitor is controlled to be connected, and the charge is shared with the first capacitor and the corresponding second capacitor to output the target reference signal.
[0057] Specifically, if in the i-th comparison result, the target reference signal is smaller than the input signal, the lower plate of the i-th third capacitor is controlled to be connected to the common ground, and the lower plate of the first third capacitor is controlled to be connected to the compensation capacitor array;
[0058] If in the i-th comparison result, the target reference signal is greater than the input signal, the lower plate of the i-th third capacitor is controlled to be connected to the compensation capacitor array, and the lower plate of the first third capacitor is controlled to be connected to the common ground.
[0059] The working process of the capacitor array structure is described in detail below.
[0060] In the stage where the SAR ADC follows the input signal, such as Figure 3 As shown, the control switches Sd, S0, S1... are closed to precharge the first capacitor Cd and each second capacitor (Cc(0), Cc(1), Cc(00), Cc(01)...) in the compensation capacitor array to the initial reference voltage VR through a low-power reference voltage driving circuit. At the same time, the control switches Sg, S0(1), S0(2)... are closed to short-circuit the two ends of the DAC capacitor array to the ground.
[0061] After the following input signal phase is completed, Figure 4 As shown, first, the switches Sd, Sg, S0(1), S0, S1, S00, S01… are opened, and then the switch S1(1) is closed. At this time, the charge is shared between the first capacitor Cd and the third capacitor C(1), causing the voltage on the first capacitor Cd to drop to VR(1). At this time, the target reference signal output by the DAC capacitor array is:
[0062] VDAC(1)=VR(1)*C(1) / CT ①
[0063] The conversion phase then begins, comparing the input signal with the output VDAC(1) and determining the highest bit of the output code value based on the comparison result.
[0064] Next, the SAR ADC needs to generate VDAC(2) based on the comparison result of the highest bit. There are two cases:
[0065] 1) If the highest bit is 0, the DAC capacitor array needs to generate the target reference signal as:
[0066] VDAC(2)= VDAC(1)-VDAC(1) / 2 ②
[0067] like Figure 5As shown, the switches S1(1) and S0(2) are opened, and S0(1) and S1(2), S0 are closed. At this time, charge sharing occurs between the first capacitor Cd, the second capacitor Cc(0), and the third capacitors C(1) and C(2), so that the voltage on the first capacitor Cd is reduced to VR(2). At this time, the DAC capacitor array needs to generate the target reference signal:
[0068] VDAC(2)= -VR(1)*C(1) / CT+VR(2)*C(2) / CT ③
[0069] In this process, the charge that the DAC capacitor array needs to absorb from the first capacitor Cd can be expressed as QDAC(2). This part of the charge is provided by the first capacitor Cd and the second capacitor Cc(0). The charge on the second capacitor Cc(0) is used as compensation. According to the law of conservation of charge:
[0070] QDAC(2)+ QCd(2) + QCc(0)=0 ④
[0071] The charge QCd(2) and the charge QCc(0) are the charges provided by the first capacitor Cd and the second capacitor Cc(0) respectively. According to formulas ① to ④, the value of the second capacitor Cc(0) can be calculated and selected in advance so that formula ② is satisfied.
[0072] 2) If the highest bit is 1, the DAC capacitor array needs to generate the target reference signal as:
[0073] VDAC(2)= VDAC(1) + VDAC(1) / 2 ⑤
[0074] like Figure 6 As shown, switch S0(2) is opened, and switch S1(2) and S1 are closed. At this time, charge sharing occurs between the first capacitor Cd, the second capacitor Cc(1), and the third capacitors C(1) and C(2), so that the voltage on the first capacitor Cd is reduced to VR(2). At this time, the target reference signal generated by the DAC capacitor array is:
[0075] VDAC(2)= (VR(2) - VR(1))*C(1) / CT + VR(2)*C(2) / CT ⑥
[0076] In this process, the charge that the DAC capacitor array needs to absorb from the first capacitor Cd can be expressed as QDAC(2). This part of the charge is provided by the first capacitor Cd and the second capacitor Cc(1). The charge on the second capacitor Cc(1) is used as compensation. According to the law of conservation of charge:
[0077] QDAC(2)+ QCd(2) + QCc(1)=0 ⑦
[0078] The charge QCd(2) and the charge QCc(1) are the charges provided by the first capacitor Cd and the second capacitor Cc(1) respectively. According to formulas ①, ⑤ to ⑦, the value of the second capacitor Cc(1) can be calculated and selected in advance so that formula ⑤ is satisfied.
[0079] After the above steps are performed, the input signal is compared with the target reference signal VDAC(2) to determine the value of the second highest bit of the output code value.
[0080] The following conversion process is similar to the above process: after the i-th comparison, the capacitors of the DAC capacitor array need to be switched according to the comparison result to generate VDAC(i+1) for the next comparison. In order to ensure accurate binary division, it is necessary to ensure that:
[0081] |VDAC(i+1)-VDAC(i)|=2*|(VDAC(i+2)-VDAC(i+1))| ⑧
[0082] Among them, VDAC(i+1) represents the current target reference signal, VDAC(i+2) represents the next target reference signal, and VDAC(i) represents the previous target reference signal.
[0083] Based on the above capacitor array structure, the present application embodiment also proposes a successive approximation analog-to-digital converter, such as Figure 7 As shown, including:
[0084] The capacitor array structure as described in the above embodiment is used to output a target reference signal;
[0085] A sampling and holding circuit, connected to the capacitor array structure, for summing the received input signal with the target reference signal to obtain a comparison signal;
[0086] A comparator, connected to the sample-and-hold circuit, for comparing the comparison signal with a reference value to obtain a comparison result;
[0087] The logic circuit is connected to the capacitor array structure, and is used to feed back the comparison result to the capacitor array structure, and output the code value according to the successive comparison results.
[0088] In this embodiment, the sampling and holding circuit, the comparator, and the logic circuit are prior arts, and their solutions are not described in detail here.
[0089] By passively starting the capacitor array structure, high-bandwidth active driving is avoided, thereby greatly saving power consumption and reducing the area overhead of the successive approximation analog-to-digital converter.
[0090] Based on the above-mentioned successive approximation analog-to-digital converter, the embodiment of the present application further proposes a control method of the successive approximation analog-to-digital converter, such as Figure 8 As shown, the following steps are included:
[0091] S101: controlling a second capacitor in a corresponding second capacitor group to be connected according to a comparison result of the target reference signal and the input signal last time, so as to compensate for the charge loss of the DAC capacitor array during the voltage conversion process;
[0092] S102: Control a corresponding third capacitor to be connected to share charges with the first capacitor and the corresponding second capacitor to output the target reference signal.
[0093] Specifically, if in the i-th comparison result, the target reference signal is smaller than the input signal, the lower plate of the i-th third capacitor is controlled to be connected to the common ground, the lower plate of the first third capacitor is controlled to be connected to the compensation capacitor array; and another second capacitor in the i-th group of the second capacitor group is controlled to be connected to compensate for the charge loss of the DAC capacitor array during the voltage conversion process;
[0094] If in the i-th comparison result, the target reference signal is greater than the input signal, then the lower plate of the i-th third capacitor is controlled to be connected to the compensation capacitor array, and the lower plate of the first third capacitor is controlled to be connected to the common ground; and one of the second capacitors in the i-th group of the second capacitors is controlled to be connected to compensate for the charge loss of the DAC capacitor array during the voltage conversion process.
[0095] An embodiment of the present invention further provides an electronic device, comprising the successive approximation analog-to-digital converter in the above embodiment.
[0096] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.
[0097] The above embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the invention patent. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent of the present application shall be subject to the attached claims.
Claims
1. A passively driven capacitor array structure, applied to a successive approximation analog-to-digital converter, characterized in that: The capacitor array structure includes a DAC capacitor array and a compensation capacitor array connected to the DAC capacitor array, the DAC capacitor array outputs a target reference signal for comparison with an input signal, and the compensation capacitor array includes: A first capacitor, connected to the DAC capacitor array, configured to follow an initial reference voltage and share a charge corresponding to the initial reference voltage with the DAC capacitor array; A plurality of second capacitors are connected to the DAC capacitor array and are used to compensate for charge loss during voltage conversion of the DAC capacitor array, so that the target reference signal output by the DAC capacitor array conforms to a binary relationship.
2. The capacitor array structure according to claim 1, characterized in that: The compensation capacitor array comprises: N second capacitor groups arranged in sequence, each of the second capacitor groups includes two second capacitors connected in parallel, a lower plate of each second capacitor is connected to a common ground, and an upper plate is connected to the DAC capacitor array through a corresponding switch, and N represents the number of bits of a successive approximation analog-to-digital converter; According to the comparison result of the target reference signal and the input signal last time, the second capacitor in the corresponding second capacitor group is controlled to be connected to compensate the charge loss of the DAC capacitor array during the voltage conversion process.
3. The capacitor array structure according to claim 2, characterized in that: The compensation capacitor array comprises: If, in the i-th comparison result, the target reference signal is smaller than the input signal, then controlling a second capacitor in the i-th group of the second capacitors to be connected to compensate for the charge loss of the DAC capacitor array during the voltage conversion process; If the target reference signal is greater than the input signal in the i-th comparison result, another second capacitor in the i-th second capacitor group is controlled to be connected to compensate for the charge loss of the DAC capacitor array during the voltage conversion process.
4. The capacitor array structure according to any one of claims 1 to 3, characterized in that: The bipartite relationship is: |VDAC(i+1)-VDAC(i)|=2*|(VDAC(i+2)-VDAC(i+1))| Among them, VDAC(i+1) represents the current target reference signal, VDAC(i+2) represents the next target reference signal, and VDAC(i) represents the previous target reference signal.
5. The capacitor array structure according to claim 1, characterized in that: The DAC capacitor array comprises: N third capacitors arranged in sequence, the lower plate of each of the third capacitors being connected to the compensation capacitor array or a common ground through a corresponding switch, and the upper plate being connected to a common end for outputting the target reference signal; According to the comparison result of the target reference signal and the input signal last time, the corresponding third capacitor is controlled to be connected, and the charge is shared with the first capacitor and the corresponding second capacitor to output the target reference signal.
6. The capacitor array structure according to claim 5, characterized in that: If, in the i-th comparison result, the target reference signal is smaller than the input signal, the lower plate of the i-th third capacitor is controlled to be connected to the common ground, and the lower plate of the first third capacitor is controlled to be connected to the compensation capacitor array; If in the i-th comparison result, the target reference signal is greater than the input signal, the lower plate of the i-th third capacitor is controlled to be connected to the compensation capacitor array, and the lower plate of the first third capacitor is controlled to be connected to the common ground.
7. A successive approximation analog-to-digital converter, characterized in that: include: The capacitor array structure according to any one of claims 1 to 6, used to output a target reference signal; A sampling and holding circuit, connected to the capacitor array structure, for summing the received input signal with the target reference signal to obtain a comparison signal; A comparator, connected to the sample-and-hold circuit, for comparing the comparison signal with a reference value to obtain a comparison result; The logic circuit is connected to the capacitor array structure, and is used to feed back the comparison result to the capacitor array structure, and output the code value according to the successive comparison results.
8. A control method of a successive approximation analog-to-digital converter, applied to the successive approximation analog-to-digital converter as claimed in claim 7, characterized in that: include: Controlling the connection of a second capacitor in the corresponding second capacitor group according to the comparison result of the target reference signal and the input signal last time, so as to compensate for the charge loss of the DAC capacitor array in the voltage conversion process; and A corresponding third capacitor is controlled to be connected to share charges with the first capacitor and the corresponding second capacitor to output the target reference signal.
9. The control method according to claim 8, characterized in that: If, in the i-th comparison result, the target reference signal is smaller than the input signal, the lower plate of the i-th third capacitor is controlled to be connected to the common ground, the lower plate of the first third capacitor is controlled to be connected to the compensation capacitor array; and another second capacitor in the i-th group of the second capacitors is controlled to be connected to compensate for the charge loss of the DAC capacitor array during the voltage conversion process; If in the i-th comparison result, the target reference signal is greater than the input signal, then the lower plate of the i-th third capacitor is controlled to be connected to the compensation capacitor array, and the lower plate of the first third capacitor is controlled to be connected to the common ground; and one of the second capacitors in the i-th group of the second capacitors is controlled to be connected to compensate for the charge loss of the DAC capacitor array during the voltage conversion process.
10. An electronic device, characterized in that: It comprises the successive approximation analog-to-digital converter as claimed in claim 7.