Multi-bit quantization Sigma-Delta analog-to-digital converter architecture, extended counting structure and electronic component
By introducing multi-bit quantized Sigma-Delta analog-to-digital converter structure and Nyquist rate ADC into the Incremental Sigma-Delta analog-to-digital converter, the problem that the delay time and accuracy requirements in the prior art are not able to be met at the same time, and the analog-to-digital conversion effect with high precision and low latency is achieved.
Patent Information
- Application Number
- CN202411558415.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-11-04
- Publication Date
- 2025-03-25
AI Technical Summary
The existing Incremental Sigma-Delta analog-to-digital converters have a contradiction between meeting latency and accuracy requirements, and cannot achieve high precision and low latency at the same time.
The multi-bit quantized Sigma-Delta analog-to-digital converter structure is adopted, combined with the incremental SDM module, the extended counting module and the filter module, the high-bit conversion is performed through the incremental Sigma-Delta ADC, and the low-bit conversion is performed through the Nyquist rate ADC to output more accurate digital output codes.
It realizes improving the accuracy of the analog-to-digital converter without increasing the delay time, and while meeting high precision and low latency, it reduces the complexity and power consumption of the circuit design.
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Figure CN119696589A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of integrated circuits, and in particular to a multi-bit quantized Sigma-Delta analog-to-digital converter architecture, an extended counting structure and electronic components. Background Art
[0002] Analog to Digital Converter (ADC) is an electronic device that can convert analog signals that are continuous in time and amplitude into digital signals that are discrete in time and amplitude. Incremental Sigma-Delta Analog to Digital Converter (Incremental Sigma-Delta ADC) is a high-precision ADC. Incremental Sigma-Delta ADC uses oversampling and noise shaping techniques. After each signal conversion, the loop filter and digital extractor are reset. These features make Incremental Sigma-Delta ADC particularly efficient in low-frequency and high-resolution applications, such as sensor interfaces using switches and capacitor circuits and other occasions that require processing multiplexed low-frequency signals with high resolution.
[0003] The operation of the Incremental Sigma-Delta ADC is controlled by a reset pulse that clears the memory of the analog loop filter and the digital decimator after a number of clock cycles, where the number of oversampling clock cycles is given by the oversampling rate, commonly referred to as the conversion time period. N It takes 1 clock cycle to reach N effective number of bits (ENOB), which makes it impossible to meet the delay time (also called conversion time) and accuracy requirements at the same time. Summary of the invention
[0004] The purpose of the embodiment of the present invention is to provide a multi-bit quantized Sigma-Delta analog-to-digital converter structure, which can meet the requirements of delay time and accuracy at the same time.
[0005] In order to achieve the above-mentioned purpose, an embodiment of the present invention provides a multi-bit quantized Sigma-Delta analog-to-digital converter structure, which includes an incremental SDM module, an extended counting module and a filter module. The input interface is connected to the incremental SDM module, the output end of the incremental SDM module is connected to the extended counting module, and the output end of the incremental SDM module and the output end of the extended counting module are connected to the filter module; the incremental SDM module includes an incremental Sigma-Delta ADC structure, which is used to perform high-bit conversion on the input signal passing through the input interface; the extended counting module includes a Nyquist rate ADC structure, which is used to output the quantization error of the incremental SDM module to perform low-bit conversion on the input signal; the filter module is used to output the digital output code corresponding to the input signal.
[0006] Optionally, the Nyquist rate ADC structure includes a successive approximation ADC, a cyclic ADC or a flash ADC.
[0007] Optionally, the incremental Sigma-Delta ADC structure is an incremental multi-stage cascade Sigma-Delta ADC, and the incremental Sigma-Delta ADC structure includes a first-stage integrator, a second-stage integrator, and a third-stage integrator connected in sequence, the output end of the third-stage integrator is respectively connected to a quantizer and the extended counting module, and the output end of the quantizer is connected to the filter module.
[0008] Optionally, the incremental SDM module also includes a feedback DAC structure. When the incremental SDM module is a feedback cascade integrator structure, the feedback DAC structure is: the output end of the quantizer is respectively connected to the operational amplifier of the first-stage integrator, the operational amplifier of the second-stage integrator, and the operational amplifier of the third-stage integrator.
[0009] Optionally, the voltage connected to the input interface is V in , the voltage at the output of the first stage integrator is V O1 The voltage across the output of the second stage integrator is V O2 , the voltage at the output of the third stage integrator is V O3 , the value of the output of the quantizer is d, then the time domain relationship of the incremental SDM module is expressed by the following formula:
[0010]
[0011] Among them, n, l, k represent the clock cycle, λ1 represents the first-order coefficient, λ2 represents the second-order coefficient, λ3 represents the third-order coefficient, λ e represents the error term coefficient, and i represents the i-th clock cycle.
[0012] Optionally, the incremental SDM module also includes a feedback DAC structure. When the incremental SDM module is a feedforward cascade integrator structure, the feedback DAC structure is: the output end of the quantizer is connected to the operational amplifier of the first-stage integrator, and the output end of the first-stage integrator and the output end of the second-stage integrator are connected to the adder of the output end of the third-stage integrator.
[0013] Optionally, the voltage connected to the input interface is V in , the voltage at the output of the first stage integrator is V O1 The voltage across the output of the second stage integrator is V O2 , the voltage at the output of the third stage integrator is V O3 , the value of the output of the quantizer is d, then the time domain relationship of the incremental SDM module is expressed by the following formula:
[0014]
[0015] Among them, n, l, k represent the clock cycle, λ1 represents the first-order coefficient, λ2 represents the second-order coefficient, λ3 represents the third-order coefficient, λ e represents the error term coefficient, and i represents the i-th clock cycle.
[0016] Optionally, a control switch SW is configured between the output end of the third-stage integrator and the extended counting module. EC , to control the switch SW EC Control the extended counting module.
[0017] Optionally, the control switch SW EC The control of the extended counting module includes: when the incremental Sigma-Delta ADC structure is in a reset state, controlling the control switch SW EC Disconnecting the third-stage integrator, the extended counting module controls the timing Φ EC The multiplexing is used in the extended counting stage to re-quantize the residual voltage of the third-stage integrator at the end of the oversampling period.
[0018] An embodiment of the present invention further provides an electronic component, which includes the above-mentioned multi-bit quantized Sigma-Delta analog-to-digital converter architecture or the above-mentioned expansion counter analog-to-digital converter structure.
[0019] Through the above technical scheme, the embodiment of the present invention realizes downsampling and multi-rate incremental Sigma-Delta ADC based on the combination of incremental Sigma-Delta ADC structure and Nyquist rate ADC structure. The embodiment of the invention combines the advantages of high precision of Sigma-Delta ADC and high speed and low power consumption of Nyquist rate ADC. The incremental Sigma-Delta ADC structure converts analog input data samples at the end of each conversion cycle, thereby operating as a Nyquist rate ADC structure. Specifically, the embodiment of the present invention performs high-bit conversion on the input signal through the incremental Sigma-Delta ADC structure, and performs low-bit conversion on the input signal through the Nyquist rate ADC structure, so as to output a more accurate digital output code through the filter module, thereby achieving high-precision quantization output of the analog-to-digital converter and meeting the delay time (also referred to as conversion time) requirements.
[0020] Other features and advantages of the embodiments of the present invention will be described in detail in the subsequent detailed description. BRIEF DESCRIPTION OF THE DRAWINGS
[0021] The accompanying drawings are used to provide a further understanding of the embodiments of the present invention and constitute a part of the specification. Together with the following specific implementations, they are used to explain the embodiments of the present invention, but do not constitute a limitation on the embodiments of the present invention. In the accompanying drawings:
[0022] Figure 1 It is a structural schematic diagram of a multi-bit quantized Sigma-Delta analog-to-digital converter architecture provided by an embodiment of the present invention;
[0023] Figure 2 is a block diagram of an example multi-bit quantized Sigma-Delta analog-to-digital converter architecture;
[0024] Figure 3 is a block diagram of an example 3-stage CIFB incremental Sigma-Delta ADC;
[0025] Figure 4 yes Figure 3 Circuit diagram of the example;
[0026] Figure 5 is a schematic diagram of the structure of an example 3-stage CIFF incremental Sigma-Delta ADC;
[0027] Figure 6 yes Figure 5 Circuit diagram of the example;
[0028] Figure 7 is a schematic diagram of the structure of an example 3-level CIFB multiplexed incremental Sigma-DeltaADC;
[0029] Figure 8 is a block diagram of an example 3-stage CIFF multiplexed incremental Sigma-Delta ADC; and
[0030] Fig. 9 It is a timing diagram of the operation of the example extended counting analog-to-digital converter structure.
[0031] Description of Reference Numerals
[0032] 10 Incremental SDM module 20 Extended counting module 30 Filter module DETAILED DESCRIPTION
[0033] The specific implementation of the embodiment of the present invention is described in detail below in conjunction with the accompanying drawings. It should be understood that the specific implementation described here is only used to illustrate and explain the embodiment of the present invention, and is not used to limit the embodiment of the present invention.
[0034] It should be noted that if there are directional indications (such as up, down, left, right, front, back, etc.) involved in the embodiments of the present invention, the directional indication is only used to explain the relative position relationship, movement, etc. between the components under a certain specific posture (as shown in the drawings). If the specific posture changes, the directional indication will also change accordingly. For ease of description, spatial relative terms such as "under...", "below...", "lower part", "above...", "upper part" and the like can be used here to easily describe the relationship between one element or component and another (or other) elements or components as shown in the figure. In addition to the orientation shown in the figure, the spatial relative terms are intended to include different orientations of the device in use or operation. The device can be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used in the embodiments of the present invention can be interpreted accordingly. In addition, in the subsequent manufacturing process, there may be one or more additional operations in / between the described operations, and the order of operations can be changed. In the present disclosure, the phrase "one of A, B, and C" means "A, B, and / or C" (A, B, C, A and B, A and C, B and C, or A, B and C), and does not mean one element from A, one element from B, and one element from C unless otherwise specified. Materials, configurations, dimensions, processes, and / or operations described with respect to one embodiment may be adopted in other embodiments, and detailed descriptions thereof may be omitted.
[0035] In addition, if there are descriptions involving "first", "second", etc. in the embodiments of the present invention, the descriptions of "first", "second", etc. are only used for descriptive purposes and cannot be understood as indicating or suggesting their relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include at least one of the features. In addition, the technical solutions between the various embodiments can be combined with each other, but they must be based on the ability of ordinary technicians in the field to implement them. When the combination of technical solutions is contradictory or cannot be implemented, it should be deemed that such a combination of technical solutions does not exist and is not within the scope of protection required by this application.
[0036] Figure 1 This is a schematic diagram of the structure of a multi-bit quantized Sigma-Delta analog-to-digital converter architecture provided by an embodiment of the present invention. Please refer to Figure 1 , the multi-bit quantized Sigma-Delta analog-to-digital converter architecture may include an incremental SDM module 10, an extended counting module 20 and a filter module 30. The input interface is connected to the incremental SDM module 10, the output end of the incremental SDM module 10 is connected to the extended counting module 20, and the output end of the incremental SDM module 10 and the output end of the extended counting module 20 are connected to the filter module 30. The incremental SDM module 10 includes an incremental Sigma-Delta ADC structure for performing high-bit conversion on the input signal passing through the input interface; the extended counting module 20 includes a Nyquist rate ADC structure for outputting the quantization error of the incremental SDM module 10 to perform low-bit conversion on the input signal; the filter module 30 is used to output a digital output code corresponding to the input signal.
[0037] As mentioned above, the operation of the incremental Sigma-Delta ADC is controlled by a reset pulse that clears the memory of the analog loop filter and the digital decimator after a number of clock cycles, where the number of oversampling clock cycles is given by the oversampling rate, commonly referred to as the conversion time period. The incremental Sigma-Delta ADC requires 2 N The N-bit effective number of bits (ENOB) can only be achieved by 10 clock cycles, which makes it impossible to meet the delay time (also called conversion time) and accuracy requirements at the same time. Therefore, the embodiment of the present invention provides a more efficient analog-to-digital converter based on the combination of incremental Sigma-Delta ADC and Nyquist rate analog-to-digital converter technology, for example, a multi-step or extended counting structure.
[0038] The embodiment of the present invention is based on a combination of a sophisticated incremental SDM module (preferably, an incremental Sigma-Delta ADC structure) and an extended counting module (e.g., a Nyquist rate ADC structure) to realize a down-sampling multi-rate incremental Sigma-Delta ADC. The incremental Sigma-Delta ADC structure converts analog input data samples at the end of each conversion cycle, thereby operating as a Nyquist rate ADC structure. The input signal is converted to a high bit through the incremental Sigma-Delta ADC structure, and the input signal is converted to a low bit through the Nyquist rate ADC structure, so as to output a more accurate digital output code through the filter module, thereby realizing a high-speed, high-precision quantized output of the analog-to-digital converter.
[0039] Please refer to Figure 2 For example, the multi-bit quantized Sigma-Delta analog-to-digital converter structure may include a front-end stage (ie, a first stage @f s ) incremental Sigma-Delta ADC and back-end stage (i.e., second stage @f s / OSR) Nyquist rate ADC (used to digitize the residual voltage signal of the front-end incremental Sigma-Delta ADC). The extended counting method based on the multi-bit quantized Sigma-Delta analog-to-digital converter structure may include: the front-end stage performs the conversion of the high-bit part to produce the most significant bit (MSB) of the digitized signal, while the back-end stage performs the conversion of the low-bit part (LSB) to further quantize the residual voltage of the previous stage; the outputs of the two stages are digitally combined to provide a more accurate quantized output.
[0040] The Nyquist rate ADC structure preferably in the embodiment of the present invention may include a successive approximation ADC, a cyclic ADC or a flash ADC.
[0041] The incremental Sigma-Delta ADC structure preferably in the embodiment of the present invention may be an incremental multi-stage cascaded Sigma-Delta ADC, and the incremental Sigma-Delta ADC structure may include a first-stage integrator, a second-stage integrator, and a third-stage integrator connected in sequence. The output end of the third-stage integrator is respectively connected to a quantizer and the extended counting module, and the output end of the quantizer is connected to the filter module.
[0042] Further preferably, the extended counting module is used to improve the accuracy of the multi-bit quantized Sigma-Delta ADC; the input of the extended counting module can be the output analog voltage of the last stage integrator (for example, the third stage integrator) in the last cycle of the incremental SDM, that is, under the architecture of the embodiment of the present invention, the analog quantization error of the incremental SDM, and the output is the digital value of the quantization error of the incremental SDM after analog-to-digital conversion. Taking the Nyquist rate ADC structure as Flash ADC as an example, the incremental multi-stage cascaded Sigma-Delta ADC formed by the three-stage integrator can make the last stage integrator (for example, the third stage integrator) of the incremental SDM module output an analog voltage, which can be sent as an input signal to the multi-bit quantizer based on 5b FlashADC, and the analog voltage can be converted into a 24-bit digital output. After the quantization of the incremental SDM is completed, it enters the extended counting cycle. At this time, the 5b Flash ADC acts as an extended counting module (that is, as a residual quantization ADC), and the analog voltage outputted by the last stage is quantized again to obtain the digital output of the quantization error. The final output of the high-precision incremental SDM is obtained by adding the output of the extended counting module to the original output. Please refer to Figure 3 and Figure 4 The incremental SDM module preferably in the embodiment of the present invention may also include a feedback DAC structure. When the incremental SDM module is a feedback cascade integrator structure (CIFB), the feedback DAC structure may be: the output end of the quantizer is respectively connected to the operational amplifier of the first-stage integrator, the operational amplifier of the second-stage integrator and the operational amplifier of the third-stage integrator.
[0043] Please refer to Figure 3 and Figure 4 For example, the feedback DAC structure may also include a feedback capacitor and a feedback switch. Figure 4 This is an example circuit diagram of an incremental multi-stage cascade Sigma-Delta ADC according to an embodiment of the present invention. The embodiment of the present invention does not limit the order, structure, circuit structure, system parameters, etc. of the incremental multi-stage cascade Sigma-Delta ADC.
[0044] Preferably, the voltage connected to the input interface is V in , the voltage at the output of the first stage integrator is V O1 The voltage across the output of the second stage integrator is V O2 , the voltage at the output of the third stage integrator is V O3 , the value of the output end of the quantizer is d, then the time domain relationship of the incremental SDM module can be expressed by the following formula:
[0045]
[0046] Among them, n, l, k represent the clock cycle, λ1 represents the first-order coefficient, λ2 represents the second-order coefficient, λ3 represents the third-order coefficient, λ e represents the error term coefficient, and i represents the i-th clock cycle.
[0047] For example, for an ideal three-stage CIFB incremental Sigma-Delta ADC, if the input V in If it is an ideal DC signal with a fixed value, the output d can be uniquely determined at any cycle after reset. Therefore, the output voltage V O1 、V O2 、V O3 With V im Based on this, the embodiment of the present invention can obtain the transfer function of the incremental SDM module based on the time domain, and further implement the "decimation filtering" processing of the incremental multi-stage cascaded Sigma-DeltaADC code stream, that is, V in The quantitative results of D out Please combine Figure 3 and Figure 4 For example, determining the time domain relationship of the incremental SDM module may include:
[0048] 1) Set the analog domain signal V in 、V O1 、V O2 、V O3 The value range is, for example, [-1, 1], that is, V DD =1, V SS =-1, the reference voltage of the feedback signal V REF =1.
[0049] 2) The output value d of the quantizer is the quantization code value of its corresponding analog input, that is, it is equal to the output after passing through the ideal DAC. From the reset process, we can know that the initial state is:
[0050] V O1 [0]=0,V O2 [0]=0,V O3 [0] = 0 (2)
[0051] 3) After one cycle, the integrator is updated:
[0052] V O1 [1] = V O1 [0]+b1V in [0]-a1d[0]·Vref (3)
[0053] V O2 [1]=V O2[0]+c1V O1 [0]-a2d[0]·Vref (4)
[0054] V O3 [1]=V O3 [0]+c2V O2 [0]-a3d[0]·Vref (5)
[0055] 4) Iterate and derive:
[0056]
[0057] 5) Simplify the process, and we can get formula (1), where:
[0058]
[0059]
[0060]
[0061]
[0062] The coefficients b1, c1, and c2 in front of the error term as shown in formula (10) can determine the resolution of the residual quantization of the Nyquist rate ADC structure (e.g., Flash ADC). Preferably, for a 5-bit Flash ADC with multiplexed multi-bit quantization, the system parameters (a1, b1, c1, c2, etc.) can be designed to ensure that the amplification factor of the residual voltage by the coefficients in front of the error term does not exceed 5 bits.
[0063] Please refer to Figure 4 For example, the feedback capacitor and feedback switch of the incremental Sigma-Delta ADC in the figure can be divided into 31 equal parts, which can be quantized by N bits using 2 N -1 thermometer code corresponds to 2 N -1 Comparator characteristics determined.
[0064] Please refer to Figure 5 and Figure 6 The incremental SDM module preferably in the embodiment of the present invention may also include a feedback DAC structure. When the incremental SDM module is a feedforward cascade integrator structure (CIFF), the feedback DAC structure may be: the output end of the quantizer is connected to the operational amplifier of the first-stage integrator, and the output end of the first-stage integrator and the output end of the second-stage integrator are connected to the adder of the output end of the third-stage integrator.
[0065] Please refer to Figure 5 and Figure 6For example, the feedback DAC structure may also include a feedback capacitor and a feedback switch. Figure 6 This is an example circuit diagram of an incremental multi-stage cascade Sigma-Delta ADC according to an embodiment of the present invention. The embodiment of the present invention does not limit the order, structure, circuit structure, system parameters, etc. of the incremental multi-stage cascade Sigma-Delta ADC.
[0066] Preferably, the voltage connected to the input interface is V in , the voltage at the output of the first stage integrator is V O1 The voltage across the output of the second stage integrator is V O2 , the voltage at the output of the third stage integrator is V O3 , the value of the output of the quantizer is d, then the time domain relationship of the incremental SDM module is expressed by the following formula:
[0067]
[0068] Among them, n, l, k represent the clock cycle, λ1 represents the first-order coefficient, λ2 represents the second-order coefficient, λ3 represents the third-order coefficient, λ e represents the error term coefficient, and i represents the i-th clock cycle.
[0069] For example, for an ideal three-stage CIFF incremental Sigma-Delta ADC, if the input V in If it is an ideal DC signal with a fixed value, the output d can be uniquely determined at any cycle after reset. Therefore, the output voltage V O1 、V O2 、V O3 With V in Based on this, the embodiment of the present invention can obtain the transfer function of the incremental SDM module based on the time domain, and further implement the "decimation filtering" processing of the incremental multi-stage cascaded Sigma-DeltaADC code stream, that is, V in The quantitative results of D out Please combine Figure 5 and Figure 6 For example, determining the time domain relationship of the incremental SDM module may include:
[0070] 1) Set the analog domain signal V in 、V O1 、V O2 、V O3 The value range is, for example, [-1, 1], that is, V DD =1, V SS =-1, the reference voltage of the feedback signal V REF =1.
[0071] 2) The output value d of the quantizer is the quantization code value of its corresponding analog input, that is, it is equal to the output after passing through the ideal DAC. From the reset process, we can know that the initial state is:
[0072] V O1 [0]=0,V O2 [0]=0,V O3 [0] = 0 (12)
[0073] 3) After one cycle, the integrator is updated:
[0074] V O1 [1]=V O1 [0]+c1V in [0]-c1d[0]·Vref (13)
[0075] V O2 [1]=V O2 [0]+c2V O1 [0] (14)
[0076] V O3 [1]=V O3 [0]+c3V O2 [0] (15)
[0077] d[1]=a1V O1 [0]+a2V O2 [0]+a3V O3 [0] (16)
[0078] 4) Iterate and derive:
[0079]
[0080] 5) After simplification, we can get formula (11).
[0081] The coefficients c1, c2, and c3 in front of the error term as shown in formula (17) can determine the resolution of the residual quantization of the Nyquist rate ADC structure (e.g., Flash ADC). Preferably, for a 5-bit Flash ADC with multiplexed multi-bit quantization, the system parameters (a1, c1, c2, c3, etc.) can be designed to ensure that the amplification factor of the residual voltage by the coefficient in front of the error term does not exceed 5 bits.
[0082] Please refer to Figure 6 , the feedback capacitor and feedback switch of the incremental Sigma-Delta ADC in the figure can be divided into 31 equal parts, which can be quantized by N bits using 2 N -1 thermometer code corresponds to 2 NThe output of each integrator is sent to the adder through the feedforward path for summation. The adder interface can be implemented by a switch and capacitor circuit without an op amp. The signal summed by the adder is then used as the input of the 5-bit quantizer for calculation.
[0083] Preferably, a control switch SW is configured between the output end of the third-stage integrator and the extended counting module. EC , to control the switch SW EC Control the extended counting module.
[0084] Further preferably, the control switch SW EC The control of the extended counting module includes: when the incremental Sigma-Delta ADC structure is in a reset state, controlling the control switch SW EC Disconnecting the third-stage integrator, the extended counting module controls the timing Φ EC The multiplexing is used in the extended counting stage to re-quantize the residual voltage of the third-stage integrator at the end of the oversampling period.
[0085] Please refer to Figure 7 When the incremental Sigma-Delta ADC structure is a three-stage CIFB incremental Sigma-Delta ADC, the extended counting method may include: at this time, the front-stage integrators are all in a reset state, and the multi-bit quantized Flash ADC controls the switch SW EC Disconnecting the third-stage integrator, the Flash ADC controls the timing Φ EC It is reused in the extended counting stage to convert the residual voltage V of the third-stage integrator at the end of the oversampling period into O3 Re-quantization improves the accuracy of the modulator. Compared with the traditional extended count ADC, it not only reduces the complexity of circuit design, but also saves area and power consumption. The time-division multiplexing operation of the 5bflash ADC can re-quantize the residual voltage and add it to the final output, achieving both high accuracy and low power consumption (the advantage of Nyquist ADC).
[0086] Please refer to Figure 8 When the incremental Sigma-Delta ADC structure is a three-stage CIFF incremental Sigma-Delta ADC, the extended counting method may include: after the quantization phase of the incremental Sigma-Delta ADC structure is completed, the front-stage integrators are all in a reset state, and the multi-bit quantization Flash ADC is controlled by the switch SW EC Disconnecting from the adder, FlashADC controls the timing Φ ECMultiplexed for the extended counting stage. Among them, for the two structures of CIFB / CIFF incremental Sigma-Delta ADC, due to different system parameters, matching filter modules can be designed for use respectively.
[0087] The extended counting analog-to-digital converter structure preferably in the embodiment of the present invention may also include a clock generation module for generating a switch control signal required for the chip to work. Fig. 9 As shown, for example, it may include a two-phase non-overlapping clock, a multi-stage delayed switch control signal, etc.
[0088] Accordingly, the embodiment of the present invention realizes a down-sampling, multi-rate incremental Sigma-Delta ADC based on a combination of an incremental Sigma-Delta ADC structure and a Nyquist rate ADC structure. The embodiment of the invention combines the advantages of the high precision of the Sigma-Delta ADC and the high speed and low power consumption of the Nyquist rate ADC. The incremental Sigma-Delta ADC structure converts the analog input data samples at the end of each conversion cycle, thereby operating as a Nyquist rate ADC structure. Specifically, the embodiment of the present invention performs a high-bit conversion on the input signal through the incremental Sigma-Delta ADC structure, and performs a low-bit conversion on the input signal through the Nyquist rate ADC structure, so as to output a more accurate digital output code through the filter module, thereby achieving high-precision quantization output of the analog-to-digital converter and meeting the delay time (also referred to as conversion time) requirements.
[0089] Furthermore, the embodiment of the present invention improves the traditional extended counting ADC based on the multi-bit quantized Sigma-Delta analog-to-digital converter structure, performs time-division multiplexing on the multi-bit quantized Flash ADC, and uses multi-bit quantization technology and chopping technology to enable the ADC to maintain high precision, low noise and a certain speed while significantly reducing the overall power consumption and area.
[0090] An embodiment of the present invention further provides an electronic component, which may include the above-mentioned multi-bit quantized Sigma-Delta analog-to-digital converter structure or the above-mentioned expansion meter analog-to-digital converter structure.
[0091] It should also be noted that the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, commodity or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, commodity or device. In the absence of more restrictions, the elements defined by the sentence "comprises a ..." do not exclude the existence of other identical elements in the process, method, commodity or device including the elements.
[0092] The above are only embodiments of the present application and are not intended to limit the present application. For those skilled in the art, the present application may have various changes and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application should be included within the scope of the claims of the present application.
Claims
1. A multi-bit quantized Sigma-Delta analog-to-digital converter architecture, characterized in that: The multi-bit quantized Sigma-Delta analog-to-digital converter architecture includes an incremental SDM module, an extended counting module and a filter module. The input interface is connected to the incremental SDM module, the output end of the incremental SDM module is connected to the extended counting module, the output end of the incremental SDM module and the output end of the extended counting module are connected to the filter module, The incremental SDM module includes an incremental Sigma-Delta ADC structure, which is used to perform high-bit conversion on the input signal through the input interface. The extended counting module includes a Nyquist rate ADC structure for outputting the quantization error of the incremental SDM module to perform low-bit conversion on the input signal. The filter module is used to output a digital output code corresponding to the input signal.
2. The multi-bit quantized Sigma-Delta analog-to-digital converter architecture according to claim 1, characterized in that: The Nyquist rate ADC structure includes a successive approximation ADC, a cyclic ADC or a flash ADC.
3. The multi-bit quantized Sigma-Delta analog-to-digital converter architecture according to claim 1, characterized in that: The incremental Sigma-Delta ADC structure is an incremental multi-stage cascaded Sigma-Delta ADC, and the incremental Sigma-Delta ADC structure includes a first-stage integrator, a second-stage integrator, and a third-stage integrator connected in sequence. The output end of the third-stage integrator is respectively connected to the quantizer and the extended counting module, and the output end of the quantizer is connected to the filter module.
4. The multi-bit quantized Sigma-Delta analog-to-digital converter architecture according to claim 3, characterized in that: The incremental SDM module further includes a feedback DAC structure. When the incremental SDM module is a feedback cascade integrator structure, the feedback DAC structure is: The output end of the quantizer is respectively connected to the operational amplifier of the first stage integrator, the operational amplifier of the second stage integrator and the operational amplifier of the third stage integrator.
5. The multi-bit quantized Sigma-Delta analog-to-digital converter architecture according to claim 4, characterized in that: The voltage connected to the input interface is V in , the voltage at the output of the first stage integrator is V O1 The voltage across the output of the second stage integrator is V O2 , the voltage at the output of the third stage integrator is V O3 , the value of the output of the quantizer is d, then the time domain relationship of the incremental SDM module is expressed by the following formula: Among them, n, l, k represent the clock cycle, λ1 represents the first-order coefficient, λ2 represents the second-order coefficient, λ3 represents the third-order coefficient, λ e represents the error term coefficient, and i represents the i-th clock cycle.
6. The multi-bit quantized Sigma-Delta analog-to-digital converter architecture according to claim 3, characterized in that: The incremental SDM module further includes a feedback DAC structure. When the incremental SDM module is a feedforward cascade integrator structure, the feedback DAC structure is: The output end of the quantizer is connected to the operational amplifier of the first stage integrator, An adder is connected to the output end of the third stage integrator, and an output end of the first stage integrator and an output end of the second stage integrator.
7. The multi-bit quantized Sigma-Delta analog-to-digital converter architecture according to claim 6, characterized in that: The voltage connected to the input interface is V in , the voltage at the output of the first stage integrator is V O1 The voltage across the output of the second stage integrator is V O2 , the voltage at the output of the third stage integrator is V O3 , the value of the output of the quantizer is d, then the time domain relationship of the incremental SDM module is expressed by the following formula: Among them, n, l, k represent the clock cycle, λ1 represents the first-order coefficient, λ2 represents the second-order coefficient, λ3 represents the third-order coefficient, λ e represents the error term coefficient, and i represents the i-th clock cycle.
8. The multi-bit quantized Sigma-Delta analog-to-digital converter architecture according to claim 3, characterized in that: A control switch SW is configured between the output end of the third-stage integrator and the extended counting module. EC , to control the switch SW EC Control the extended counting module.
9. The expansion meter analog-to-digital converter structure according to claim 8, characterized in that: The control switch SW EC The control of the extended counting module includes: When the incremental Sigma-Delta ADC structure is in a reset state, the control switch SW is controlled EC Disconnecting the third-stage integrator, the extended counting module controls the timing Φ EC The multiplexing is used in the extended counting stage to re-quantize the residual voltage of the third-stage integrator at the end of the oversampling period.
10. An electronic component, characterized in that: The electronic component comprises a multi-bit quantized Sigma-Delta analog-to-digital converter architecture as described in any one of claims 1 to 7 Or the expansion meter analog-to-digital converter structure as described in claim 8 or 9.