LVDS (Low Voltage Differential Signaling) transmitter with pendulum control

Abstract

The invention relates to the technical field of integrated circuits, in particular to an LVDS (Low Voltage Differential Signaling) transmitter with pendulum control. According to the invention, by utilizing the characteristics of time delay of resistors and capacitors, a part of data signals output by an LVDS circuit are output after being subjected to time delay controlled by voltage swing control resistors (RD1 and RD2) and gate parasitic capacitors of switching tubes (M3 and M4), and the process can absorb reflection from an external load resistor RL so as to control the voltage swing of output signals (OUTN and OUTP); on one hand, the introduction of the pendulum control circuit does not increase additional power consumption of the circuit, and on the other hand, the introduction of the pendulum control circuit can improve the ringing phenomenon of the signal at the reversal position. And secondly, as the RCM1 and the RCM2 which are far greater than the RL are adopted, the current flowing through the internal matched resistor is prevented from being increased, and the power consumption of the transmitter is reduced. Finally, the power consumption of the LVDS transmitter is reduced while the ringing phenomenon is solved.

Description

Technical Field

[0001] The invention relates to the technical field of integrated circuits, and in particular to an LVDS transmitter with slew control. Background Art

[0002] LVDS (Low Voltage Differential Signaling) uses extremely low voltage swing to transmit data at high speed differentially, which can realize point-to-point or point-to-multipoint connection. It has the characteristics of low power consumption, low bit error rate, low crosstalk and low radiation.

[0003] In the process of signal transmission, due to the ringing phenomenon of square wave pulse at the signal inversion point, the ringing phenomenon is more prominent when transmitting high-frequency signals (GHz level), resulting in serious distortion of the output signal of the system when transmitting high-frequency signals, which easily reduces the transmission rate of the transmitter transmission signal. In the prior art, the ringing phenomenon is solved by connecting a resistor of the same size as the load in parallel inside the main driving circuit of the LVDS transmitter, which will cause the LVDS transmitter to consume higher power. Summary of the invention

[0004] In view of the above problems or shortcomings, the present invention provides an LVDS transmitter with slew control, aiming to solve the ringing phenomenon and reduce the power consumption of the LVDS transmitter.

[0005] A LVDS transmitter with slew control comprises an LVDS circuit and a slew control circuit.

[0006] The LVDS circuit includes a first switch tube M1, a second switch tube M2, a first current source tube M5, a second current source tube M6, a first common mode feedback resistor RCM1, a second common mode feedback resistor RCM2, a current source and an operational amplifier;

[0007] The gate terminal of the first switch tube M1 is connected to the positive input signal IN+, and the source terminal is connected to the current source; the drain terminal is connected to the drain terminal of the fourth switch tube M4, the drain terminal of the first current source tube M5 and one end of the first slew control resistor RD1, and serves as a reverse signal output terminal to output a signal OUTN.

[0008] The gate terminal of the second switch tube M2 is connected to the positive input signal IN-, and the source terminal is connected to the current source; its drain terminal is connected to the drain terminal of the third switch tube M3, the drain terminal of the second current source tube M6 and one end of the second slew control resistor RD2, and serves as a positive signal output terminal to output the signal OUTP.

[0009] The first common-mode feedback resistor RCM1 and the second common-mode feedback resistor RCM2 are connected in series and arranged between the forward signal output terminal and the reverse signal output terminal. The connection point between the first common-mode feedback resistor RCM1 and the second common-mode feedback resistor RCM2 is also connected to the forward input terminal of the operational amplifier.

[0010] The first switch tube M1 , the second switch tube M2 , the third switch tube M3 and the fourth switch tube M4 are NMOS tubes, and the first current source tube M5 and the second current source tube M6 are PMOS tubes.

[0011] The current source is connected to the source terminals of the first switch tube M1 , the second switch tube M2 , the third switch tube M3 and the fourth switch tube M4 .

[0012] Source terminals of the first current source tube M5 and the second current source tube M6 are both connected to the power supply voltage VDD, and gate terminals of both are connected to the output terminal of the operational amplifier.

[0013] The negative input of the operational amplifier is connected to a fixed voltage level V ref .

[0014] The slew control circuit includes a third switch tube M3, a fourth switch tube M4, a first slew control resistor RD1 and a second slew control resistor RD2.

[0015] The gate terminal of the third switch tube M3 is connected to the other end of the first slew control resistor RD1, and the gate terminal of the fourth switch tube M4 is connected to the other end of the second slew control resistor RD1; the source terminal of the third switch tube M3 is connected to the source terminal of the fourth switch tube M4, and is connected to the current source; the resistance value of the first slew control resistor RD1 is equal to that of the second slew control resistor RD2, and the sum of the two is equal to the external load resistor R L The resistance value is 100Ω.

[0016] Furthermore, the slew control circuit also includes a capacitor, one end of which is connected to the gate end of M3 and the other end of which is connected to the gate end of M4 to compensate for the insufficient parasitic capacitance of the MOS tubes M3 and M4.

[0017] Furthermore, the slew control circuit also includes two capacitors C1 and C2; one end of one capacitor C1 is connected to the gate terminal of M3, and the other end is connected to the power ground GND; one end of the other capacitor C2 is connected to the gate terminal of M4, and the other end is connected to the power ground GND, so as to compensate for the insufficient parasitic capacitance of the MOS tubes M3 and M4.

[0018] Furthermore, the first common-mode feedback resistor RCM1 and the second common-mode feedback resistor RCM2 detect the output common-mode voltage V comand forms a negative feedback control loop with the operational amplifier, the first current source tube M5 and the second current source tube M6; the sum of the resistance values ​​of the resistors RCM1 and RCM2 is ≥ 1000Ω, which is much larger than the external load resistance R L The resistance value is 100Ω.

[0019] Furthermore, the first switch tube M1, the second switch tube M2, the third switch tube M3 and the fourth switch tube M4 work in the linear region, and the first current source tube M5 and the second current source tube M6 work in the saturation region.

[0020] In summary, the present invention utilizes the characteristics of resistor and capacitor delay to output a portion of the data signal output by the LVDS circuit after a delay controlled by the slew control resistor (RD1 and RD2) and the gate parasitic capacitance of the switch tube (M3 and M4). This process absorbs the external load resistor R L The voltage swing of the output signal (OUTN and OUTP) is controlled by the reflection of the voltage swing control circuit. On the one hand, the introduction of the voltage swing control circuit does not increase the extra power consumption of the circuit. On the other hand, the introduction of the voltage swing control circuit can improve the ringing phenomenon of the signal at the inversion point. L RCM1 and RCM2 thus avoid increasing the current flowing through the internal matching resistor. Compared with the case where no voltage swing control circuit is added, the present invention is conducive to improving the quality of the output signal, reducing the degree of signal distortion, and increasing the rate at which the transmitter transmits the signal; compared with the traditional circuit structure for improving the ringing phenomenon, the LVDS transmitter of the present application can reduce the power consumption by half. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 It is a module block diagram of the present invention;

[0022] Figure 2 Schematic diagram of the circuit structure of the embodiment;

[0023] Figure 3 This is a simulation comparison diagram of the LVDS transmitter with and without slew control circuit;

[0024] Figure 4 is a schematic diagram of the circuit structure of an operational amplifier of an embodiment;

[0025] Figure 5 It is a schematic diagram of the LVDS circuit structure of the prior art. DETAILED DESCRIPTION

[0026] The present invention is further described in detail below with reference to the accompanying drawings and embodiments.

[0027] The structure of the existing LVDS circuit is as follows Figure 5 As shown, the feedback resistor RCM is set to a value equal to the receiving resistor at the receiving end (external load resistor RL ) value to solve the "ringing" phenomenon caused by impedance mismatch. However, this circuit solution is achieved by sacrificing the overall power consumption of the transmitter. Due to the existence of internal matching resistors, the power consumption of the overall circuit is 4 times the output current.

[0028] This embodiment provides an LVDS transmitter with slew control, referring to Figure 1 and Figure 2 :

[0029] Reference Figure 1 The LVDS circuit includes a forward signal input terminal, a forward signal output terminal, a reverse signal input terminal and a reverse signal output terminal. The forward signal input terminal (IN+) and the reverse signal input terminal (IN-) are used to receive input data signals IN+ and IN-, and the forward signal output terminal (OUTP) and the reverse signal output terminal (OUTN) are used to output data signals OUTP and OUTN.

[0030] In this embodiment, the LVDS circuit is provided with switch tubes M1 and M2, which are turned on or off according to the high or low levels of the received data signals IN+ and IN-, so that an output current with a positive or negative direction flows between the forward signal output terminal and the reverse signal output terminal, thereby realizing high level or low level transmission.

[0031] When the input data signal is high, the level signal connected to the positive signal input terminal (IN+) is high, and the level signal connected to the negative signal input terminal (NI-) is low. At this time, M2 is turned off, causing the current to flow out from the positive output terminal and flow through the external load resistor R L Then return; M1 is turned on, so that the current flows in from the reverse signal output terminal, forming a complete current loop. In this process, the current flows out from the forward signal output terminal through the external load resistor R L Then it flows into the reverse signal output terminal, so the level difference between the forward signal output terminal and the reverse signal output terminal is positive, and high level transmission is achieved.

[0032] When the input data signal is low, the level signal connected to the positive signal input terminal (IN+) is low, and the level signal connected to the reverse signal input terminal (NI-) is high. At this time, M1 is turned off, causing the current to flow out of the reverse output terminal and flow through the external load resistor R L Then return; M2 is turned on, so that the current flows in from the positive signal output terminal, forming a complete current loop. In this process, the current flows out from the reverse signal output terminal through the external load resistor R L Then it flows into the positive signal output terminal, so the level difference between the positive signal output terminal and the reverse signal output terminal is a negative value, thus realizing low level transmission.

[0033] Among them, M1, M2, M3 and M4 are NMOS tubes, M5 and M6 are PMOS tubes. M1, M2, M3 and M4 work in the linear region, and M5 and M6 work in the saturation region. The RCM1 and RCM2 detect the output common mode voltage and form a negative feedback control loop with the operational amplifier, M5 and M6.

[0034] In this embodiment, the operational amplifier structure used in the negative feedback control loop is as follows: Figure 4 As shown, V ip is the positive input terminal of the operational amplifier, V in is the inverting input terminal of the operational amplifier, V out_ap is the output terminal of the operational amplifier. When the common mode voltage V com When the voltage is reduced, the operational amplifier outputs a higher voltage, thereby reducing the gate voltage of M5 and M6, and the common-mode voltage V com Therefore, a negative feedback control loop is formed to achieve a common-mode voltage V com stability.

[0035] To this end, a slew control circuit is provided in this embodiment. The slew control circuit uses the fast changing characteristics of the high-frequency output data signal jump edge output by the LVDS circuit to short-circuit the slew control resistors RD1 and RD2 to the ground through the gate terminal parasitic capacitance of M3 and M4, and the sum of the resistance values ​​of the slew control resistors RD1 and RD2 is equal to the external load resistor R L , thereby eliminating the ringing phenomenon caused by impedance mismatch.

[0036] In this embodiment, when the positive input signal IN+ jumps from negative to positive and the reverse input signal IN- jumps from positive to negative, the positive output signal OUTP jumps from negative to positive and the reverse output signal OUTN jumps from positive to negative, and the direction of the output current flows from the positive signal output terminal to the reverse signal output terminal. Before the delay time, M3 is turned on and M4 is turned off. At this time, the slew control circuit absorbs a part of the output current (data current signal) and absorbs the reflected current signal caused by impedance mismatch; after the delay time, M3 is turned off and M4 is turned on to restore the complete output current.

[0037] On the contrary, when the positive input signal IN+ jumps from positive to negative and the reverse input signal IN- jumps from negative to positive, the positive output signal OUTP jumps from positive to negative and the reverse output signal OUTN jumps from negative to positive, and the direction of the output current flows from the reverse signal output end to the forward signal output end. Before the delay time, M3 is turned off and M4 is turned on. At this time, the slew control circuit absorbs part of the output current and absorbs the reflected current signal caused by impedance mismatch; after the delay time, M3 is turned on and M4 is turned off to restore the complete output current. The size of the output current signal and the reflected current signal can be adjusted by adjusting the size of M3 and M4; and the delay time is determined by the slew control resistor (RD1 and RD2) and the gate terminal parasitic capacitance of the switch tube (M3 and M4).

[0038] Figure 3 The LVDS transmitter with slew control according to the embodiment of the present invention is specifically provided. Figure 5 The simulation comparison diagram of the non-slew control circuit (existing technology) is shown in the figure, and the test condition is a 1GHz random data signal. It can be seen that the output waveform of the non-slew control circuit is due to the external load resistor R L The reflection of the LVDS transmitter produces ringing phenomenon, which makes the signal distortion more serious, the signal quality worse, and the limit frequency that can be achieved is lower; while the output waveform with the slew control circuit is greatly improved. In addition, the power consumption of the LVDS transmitter with slew control is twice the output current, which is 50% lower than the power consumption of the traditional structure to solve the ringing phenomenon.

[0039] It can be seen from the above embodiments and comparative examples that the present invention utilizes the characteristics of resistor and capacitor delay to output a portion of the data signal output by the LVDS circuit after a delay controlled by the slew control resistor (RD1 and RD2) and the gate parasitic capacitance of the switch tube (M3 and M4). This process will absorb the external load resistor R L The voltage swing of the output signal (OUTN and OUTP) is controlled by the reflection of the voltage swing control circuit. On the one hand, the introduction of the voltage swing control circuit does not increase the extra power consumption of the circuit. On the other hand, the introduction of the voltage swing control circuit can improve the ringing phenomenon of the signal at the inversion point. L RCM1 and RCM2 thus avoid increasing the current flowing through the internal matching resistor, thereby reducing the power consumption of the transmitter. Finally, the present invention achieves the goal of reducing the power consumption of the LVDS transmitter while solving the ringing phenomenon.

Claims

1. An LVDS transmitter with slew control, characterized in that: Including LVDS circuit and slew control circuit; The LVDS circuit includes a first switch tube M1, a second switch tube M2, a first current source tube M5, a second current source tube M6, a first common mode feedback resistor RCM1, a second common mode feedback resistor RCM2, a current source and an operational amplifier; The gate terminal of the first switch tube M1 is connected to the positive input signal IN+, and the source terminal is connected to the current source; Its drain terminal is connected to the drain terminal of the fourth switch tube M4, the drain terminal of the first current source tube M5 and one end of the first slew control resistor RD1, and serves as a reverse signal output terminal to output a signal OUTN; The gate terminal of the second switch tube M2 is connected to the positive input signal IN-, and the source terminal is connected to the current source; Its drain terminal is connected to the drain terminal of the third switch tube M3, the drain terminal of the second current source tube M6 and one end of the second slew control resistor RD2, and serves as a positive signal output terminal to output a signal OUTP; A first common-mode feedback resistor RCM1 and a second common-mode feedback resistor RCM2 are connected in series and arranged between the forward signal output terminal and the reverse signal output terminal, and a connection point between the first common-mode feedback resistor RCM1 and the second common-mode feedback resistor RCM2 is also connected to a forward input terminal of the operational amplifier; Among them, the first switch tube M1, the second switch tube M2, the third switch tube M3 and the fourth switch tube M4 are NMOS tubes, and the first current source tube M5 and the second current source tube M6 are PMOS tubes; The current source is connected to the source terminals of the first switch tube M1, the second switch tube M2, the third switch tube M3 and the fourth switch tube M4; The source terminals of the first current source tube M5 and the second current source tube M6 are both connected to the power supply voltage VDD, and the gate terminals of both are connected to the output terminal of the operational amplifier; The negative input of the operational amplifier is connected to a fixed voltage level V ref ; The slew control circuit includes a third switch tube M3, a fourth switch tube M4, a first slew control resistor RD1 and a second slew control resistor RD2; The gate terminal of the third switch tube M3 is connected to the other end of the first slew control resistor RD1, and the gate terminal of the fourth switch tube M4 is connected to the other end of the second slew control resistor RD1; the source terminal of the third switch tube M3 is connected to the source terminal of the fourth switch tube M4, and is connected to the current source; the resistance value of the first slew control resistor RD1 is equal to that of the second slew control resistor RD2, and the sum of the two is equal to the external load resistor R L The resistance value is 100Ω.

2. The LVDS transmitter with slew control as claimed in claim 1, characterized in that: The slew control circuit further includes a capacitor, one end of which is connected to the gate terminal of M3, and the other end of which is connected to the gate terminal of M4.

3. The LVDS transmitter with slew control as claimed in claim 1, characterized in that: The slew control circuit further includes two capacitors C1 and C2; one end of one capacitor C1 is connected to the gate of M3, and the other end is connected to the power ground GND; one end of the other capacitor C2 is connected to the gate of M4, and the other end is connected to the power ground GND.

4. The LVDS transmitter with slew control as claimed in claim 1, characterized in that: The first common mode feedback resistor RCM1 and the second common mode feedback resistor RCM2 detect the output common mode voltage V com and forms a negative feedback control loop with the operational amplifier, the first current source tube M5 and the second current source tube M6; the sum of the resistance values ​​of the resistors RCM1 and RCM2 is ≥1000Ω.

5. The LVDS transmitter with slew control as claimed in claim 1, characterized in that: The first switch tube M1 , the second switch tube M2 , the third switch tube M3 and the fourth switch tube M4 work in a linear region, and the first current source tube M5 and the second current source tube M6 work in a saturation region.

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