Time latching method based on function card

Abstract

The invention discloses a time latching method based on a functional card, which comprises the following steps: a time latch receives a trigger signal and latches a current time point; the current time point comprises coarse time service information and fine time service information; when the time latch is triggered, the fine time calculation unit multiplies the counting value of the counter unit by a second period to obtain time difference information serving as fine time service information. According to the invention, on the basis of the basic protocol time precision in the protocol transmission process, the local clocks of the functional cards are used for fine time calculation, independent counters are arranged in the clocks of the functional cards, counter reset command design is innovatively used, and nanosecond refresh counting is adopted, so that errors can be greatly reduced; the method and the device further improve the time precision of the time latch when the event occurs, and are particularly suitable for the technical field with high requirements on the time precision.

Description

Technical Field

[0001] The invention relates to the field of signal acquisition, and in particular to a time latching method based on a functional card. Background Art

[0002] Function cards, also commonly called industrial control cards or data acquisition / output cards, play an important role in the field of industrial automation and process control. One of their main functions is to be applied to event timestamps and event synchronization, ensuring that multiple acquisition devices can accurately record the time when an event occurs and achieve high-precision synchronization. For example: a switch quantity refers to a signal with two states (such as on / off, high / low, 1 / 0). In industrial automation, switch signals are often used to indicate the state of a device or control instructions. Through function cards, accurate timing and synchronization of switch events can be achieved. When the switch signal changes, the function card records the timestamp of the event and synchronizes with other acquisition devices to ensure that all devices can accurately record the time of the same event. Analog refers to continuously changing physical quantities such as voltage, current, temperature, pressure, etc. These signals are common in industrial processes and usually need to be accurately measured and recorded; function cards can collect analog signals and process them to obtain accurate timestamps. Similarly, they can also synchronize with other acquisition devices to ensure that the timestamps of all related events are consistent.

[0003] Function card time locking refers to locking and storing the time information on the function card (such as the data acquisition card) through specific technical means in the data acquisition system. This ensures that the time information will not change due to changes in the system clock or external interference during the data acquisition process, thereby ensuring the accuracy and consistency of the data. However, the time locking method of the function card in the prior art has the following problems: the function card in the prior art generally only synchronizes the current timestamp information (seconds) and the time synchronization code (pulse). The synchronization accuracy at this time mainly depends on the accuracy of the time synchronization code's own protocol. For example, when IRIG-G (DC) is used, the synchronization accuracy can be maintained at the microsecond level. However, in some technical fields, the synchronization accuracy needs to be required to be at the nanometer level, which cannot be achieved by the prior art solution. Summary of the invention

[0004] The purpose of the present invention is to overcome the deficiencies of the prior art and provide a time latching method based on a functional card.

[0005] The objective of the present invention is achieved through the following technical solutions:

[0006] A first aspect of the present invention provides a time latching method based on a functional card, comprising:

[0007] The time latch receives a trigger signal and latches the current time point; the current time point includes coarse time timing information and fine time timing information; the coarse time timing information is obtained by extracting the timestamp of the coarse time refreshed in each first cycle, and the first cycle corresponds to the IRIG-G (DC) protocol; the fine time timing information is obtained by extracting the fine time counted in each second cycle, and the second cycle corresponds to the local clock frequency;

[0008] The fine time timing information is specifically the time difference information generated by the local clock in each first cycle, the local clock includes a counter unit and a fine time calculation unit, the maximum count number of the counter unit is the first cycle divided by the second cycle, and the counter unit performs an addition operation every second cycle until the maximum count number is reached and a reset operation is performed;

[0009] When the time latch is triggered, the fine time calculation unit multiplies the count value of the counter unit by the second period to obtain time difference information as fine time timing information.

[0010] Furthermore, the coarse time timing information is coarse time timing information of a main controller card.

[0011] Further, the coarse time based on the coarse time timing information of the main controller card is overwritten and updated once every third period, and the overwriting and updating method includes:

[0012] The time information generator sends the generated time information pulse to the bus signal distributor every third cycle, and the bus signal distributor sends the time information pulse to the IRIG-G (DC) decoder;

[0013] The IRIG-G (DC) decoder processes the received time information pulse to obtain the coverage update time timing information, wherein the coverage update time timing information includes extracting the code element of the time information pulse by using the code element extraction module, and extracting the timing information and pulse of the time information pulse by using the timing information pulse extraction module;

[0014] The coarse time is updated by using the overlay update time timing information.

[0015] Further, the time information pulse generated by the time information generator is a relative time information pulse, the time information generator includes an IRIG-G (DC) encoder, and the IRIG-G (DC) encoder includes a code element generator, a time extraction pre-carry processing module and a time synchronizer;

[0016] The time information generator generates relative time information pulses, including:

[0017] The soft-core CPU sends the initial time information to the IRIG-G (DC) encoder via the AVALON bus, and the IRIG-G (DC) encoder starts timing based on the initial time information to obtain relative time information;

[0018] The code element generator of the IRIG-G (DC) encoder converts the relative time information into code elements, and then the time extraction pre-carry processing module and the time synchronizer convert the code elements into relative time information pulses, and send the relative time information pulses to the bus signal distributor.

[0019] Further, the time information pulse generated by the time information generator is a real time information pulse, and the time information generator includes a second CAT5e network port and a third MLVDS transceiver;

[0020] The time information generator generates real time information pulses, including:

[0021] The second CAT5e network port receives the real time information pulse sent by the external high-precision timing module, and forwards it to the bus signal distributor through the third MLVDS transceiver.

[0022] Furthermore, the IRIG-G (DC) decoder forms the timestamp of the coarse time refreshed in each first cycle as a synchronization pulse of the coarse time timing information of the functional daughter card, and sends it to the backplane timing bus through the first MLVDS transceiver.

[0023] Furthermore, the time information generator sends the generated time information pulse to the bus signal distributor every third period, and the bus signal distributor sends the time information pulse as cross-box coarse time synchronization information to the outside through the second MLVDS transceiver and the first CAT5e network port.

[0024] Further, the coarse time timing information is the coarse time timing information of the functional daughter card;

[0025] The coarse time timing information of the functional daughter card is obtained by receiving a synchronization pulse through the backplane timing bus of the fourth MLVDS transceiver every first cycle and sending it to the IRIG-G (DC) decoder for decoding.

[0026] Furthermore, the coarse time timing information is cross-box coarse time timing information; the coarse time based on which the cross-box coarse time timing information is updated once every third period, and the update mode includes:

[0027] The time information pulse as cross-box coarse time synchronization information sent externally is received through the third CAT5e network port every third period, and is sent to the IRIG-G (DC) decoder through the fifth MLVDS transceiver and the bus signal distributor. The IRIG-G (DC) decoder decodes and obtains the cross-box coverage update time synchronization information. The cross-box coverage update time synchronization information includes the code element of the time information pulse extracted by the code element extraction module, and the timing information and pulse of the time information pulse extracted by the timing information pulse extraction module;

[0028] The cross-box coverage update time synchronization information is used to cover and update the coarse time.

[0029] Further, the functional card comprises an automatic event trigger, an IRIG-G (DC) decoder and a soft-core CPU; the automatic event trigger comprises a signal preprocessing module, a multi-channel data source module, a data filter module, a threshold determination module and an event pulse generator; the IRIG-G (DC) decoder comprises a DMA data transmission module, a time latch, a time information register group and an event FIFO module;

[0030] Function card event trigger time records include:

[0031] The signal preprocessing module of the automatic event trigger receives the external trigger signal for digital quantity processing, and sends it to the data filter module and the threshold discrimination module in sequence through the multi-channel data source module for filtering and threshold screening. The screened data source directly triggers the event pulse generator to form a first code including the trigger channel and the trigger event;

[0032] The DMA data transmission module of the IRIG-G (DC) decoder receives the first code through the AVALON bus and triggers the time latch at the same time. The time latch puts the decoded current time point into the time information register group. The DMA data transmission module re-encodes the current time point and the first code taken out from the time information register group to form a second code including the trigger channel, the trigger time and the trigger event; and puts the second code into the event FIFO module for storage;

[0033] Function card event trigger time reading includes:

[0034] The soft-core CPU reads the current time point data from the time information register group of the IRIG-G (DC) decoder through the AVALON bus to obtain the time information of the current trigger event; and / or:

[0035] The soft-core CPU reads the second code from the event FIFO module of the IRIG-G (DC) decoder through the AVALON bus to obtain the time information of the historical event triggering.

[0036] The beneficial effects of the present invention are:

[0037] In an exemplary embodiment of the present invention, on top of the basic protocol time accuracy (coarse time accuracy, microsecond level) based on the protocol transmission process, the local clock of the functional card is used to perform fine time calculations, an independent counter is set inside the clock of each functional card and an innovative counter reset command design is used. The use of nanosecond refresh counts can greatly reduce errors and further improve the time accuracy of the time latch when an event occurs (i.e., to the nanosecond level), which is particularly suitable for technical fields that require very high time accuracy. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] Figure 1 A flow chart of a time latching method based on a functional card provided by an exemplary embodiment of the present invention;

[0039] Figure 2 A schematic diagram of an overlay update method of a coarse time based on the coarse time timing information of a main controller card provided by an exemplary embodiment of the present invention;

[0040] Figure 3 A schematic diagram of a time information pulse provided by an exemplary embodiment of the present invention;

[0041] Figure 4 A schematic diagram of a time information generator generating a relative time information pulse according to an exemplary embodiment of the present invention;

[0042] Figure 5 A schematic diagram of a time information generator providing a time information pulse generating a real time information pulse according to an exemplary embodiment of the present invention;

[0043] Figure 6 A schematic diagram of sending a synchronous pulse as coarse time timing information of a functional daughter card provided by an exemplary embodiment of the present invention;

[0044] Figure 7 A schematic diagram of sending time information pulses as cross-box coarse time synchronization information provided by an exemplary embodiment of the present invention;

[0045] Figure 8 A schematic diagram of obtaining the coarse time information of a functional daughter card provided by an exemplary embodiment of the present invention;

[0046] Fig. 9 A coarse time coverage update method based on coarse time timing information across boxes provided by an exemplary embodiment of the present invention;

[0047] Fig.10 A schematic diagram of the structure of a functional card provided by an exemplary embodiment of the present invention;

[0048] Fig.11An event triggering flow chart provided for an exemplary embodiment of the present invention;

[0049] Fig.12 An exemplary embodiment of the present invention is provided based on Fig.10 A schematic diagram of the architecture of the main controller card latch relative time of the functional card structure;

[0050] Fig.13 An exemplary embodiment of the present invention is provided based on Fig.10 A schematic diagram of the architecture of the main controller card of the functional card structure to lock the real time;

[0051] Fig.14 An exemplary embodiment of the present invention is provided based on Fig.10 A schematic diagram of the architecture of the functional daughter card latching time of the functional card structure;

[0052] Fig.15 A schematic diagram of an architecture for latching relative time in a chassis of a main controller card and a functional daughter card provided by an exemplary embodiment of the present invention;

[0053] Fig.16 A schematic diagram of an architecture for locking real time in a chassis of a main controller card and a functional daughter card provided by an exemplary embodiment of the present invention;

[0054] Fig.17 A schematic diagram of a structure for relative time locks of multiple chassis provided by an exemplary embodiment of the present invention;

[0055] Fig.18 A schematic diagram of an architecture for multiple chassis to lock real time is provided as an exemplary embodiment of the present invention. DETAILED DESCRIPTION

[0056] The technical solution of the present invention is described clearly and completely below in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0057] In the description of the present invention, it should be noted that the directions or positional relationships indicated by "center", "up", "down", "left", "right", "vertical", "horizontal", "inside", "outside", etc. are directions or positional relationships based on the drawings, which are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as limiting the present invention. In addition, "first" and "second" are only used for descriptive purposes and cannot be understood as indicating or implying relative importance.

[0058] In the description of the present invention, it should be noted that, unless otherwise clearly specified and limited, "installation", "connection" and "connection" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, or it can be the internal communication of two components. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0059] In addition, the technical features involved in the different embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other.

[0060] See also Figure 1 , Figure 1 A flow chart of a time latching method based on a functional card provided by an exemplary embodiment of the present invention is shown, comprising:

[0061] The time latch receives a trigger signal and latches the current time point; the current time point includes coarse time timing information and fine time timing information; the coarse time timing information is obtained by extracting the timestamp of the coarse time refreshed in each first cycle, and the first cycle corresponds to the IRIG-G (DC) protocol; the fine time timing information is obtained by extracting the fine time counted in each second cycle, and the second cycle corresponds to the local clock frequency;

[0062] The fine time timing information is specifically the time difference information generated by the local clock in each first cycle, the local clock includes a counter unit and a fine time calculation unit, the maximum count number of the counter unit is the first cycle divided by the second cycle, and the counter unit performs an addition operation every second cycle until the maximum count number is reached and a reset operation is performed;

[0063] When the time latch is triggered, the fine time calculation unit multiplies the count value of the counter unit by the second period to obtain time difference information as fine time timing information.

[0064] Specifically, in view of the problem that the time synchronization accuracy of the functional card in the prior art is not high, in this exemplary embodiment, when the time latch receives a trigger signal (i.e., an external event generates a trigger signal that requires latching time), the coarse time timing information and the fine time timing information are used to simultaneously latch the current time point, specifically:

[0065] For the coarse time timing information, it refers to obtaining the timestamp of the coarse time refreshed based on the first cycle (preferably 0.1ms, i.e. 100us) corresponding to the IRIG-G (DC) protocol, wherein the coarse time (the coarse time refresh module storage can be set separately) is refreshed every first cycle (the specific refresh method is detailed in the subsequent exemplary embodiments); when the time latch latches the current time point, the timestamp of the coarse time is obtained to obtain the coarse time timing information at the current time point; at this time, the event synchronization time of the functional card can be accurate to microseconds, for example: XXyears:XXdays:XXhours:XXminutes:XXseconds+100us.

[0066] For the fine time timing information, it refers to the fine time obtained by counting the second cycle corresponding to the local clock frequency of the functional card (for example, when the local clock frequency is 100Mhz, the clock cycle of the local clock, that is, the second cycle is 10ns). Taking the first cycle of 0.1ms (when matching the second cycle unit, the corresponding is 100000ns) and the second cycle of 10ns as an example, the time difference information and counting related contents are explained (other first cycles and second cycles are analogous): The maximum number of counts of the counter unit is the first cycle divided by the second cycle, that is, 100000ns / 10ns=10000 (times), that is, 10000 counts can be performed in each first cycle (coarse time), and the counter unit performs an increment operation every 10ns. Until the count reaches 10000; when the time latch latches the current time point, the count value of the counter unit is obtained, for example, the count value is 351, then the fine time calculation unit calculates the time difference information of 351*10ns=3510ns (that is, the count value of the above-mentioned counter unit multiplied by the second cycle) generated by the local clock operation of the functional card within a first cycle (0.1ms) after the current coarse time, and uses this information as the fine time timing information; at this time, the synchronization time of the functional card (based on the microsecond level of the coarse time timing information) can be accurate to the nanosecond level, for example: XXyears:XXdays:XXhours:XXminutes:XXseconds+100us+3510ns.

[0067] To summarize, in this exemplary embodiment, on top of the basic protocol time accuracy (coarse time accuracy, microsecond level) based on the protocol transmission process, the local clock of the functional card is used to perform fine time calculations, an independent counter is set inside the clock of each functional card and an innovative counter reset command design is used. The use of nanosecond refresh counts can greatly reduce errors and further improve the time accuracy of the time latch when an event occurs (i.e., to the nanosecond level), which is particularly suitable for technical fields that require very high time accuracy.

[0068] It should be noted that: according to actual needs, the function card can be divided into a main controller card and a function sub-card, wherein the main controller card provides coarse time (including relative time and real time, which will be explained later), and the function sub-card needs to obtain the coarse time from the main controller card. Both the main controller and the function sub-card are applicable to the time latching method based on the function card mentioned in this exemplary embodiment. There can be only one main controller card, or there can be a main controller card and at least one function sub-card connected to the main controller card. The following exemplary embodiments will be preferably expanded to explain more implementation methods of the time latching method mentioned in this exemplary embodiment for the main controller card and the function sub-card:

[0069] More preferably, in an exemplary embodiment, the coarse time timing information is the coarse time timing information of the main controller card. For this exemplary embodiment, it can be used for the main controller card.

[0070] More preferably, in an exemplary embodiment, the coarse time based on the main controller card coarse time timing information is updated once every third cycle, such as Figure 2 As shown, the coverage update methods include:

[0071] The time information generator sends the generated time information pulse to the bus signal distributor every third cycle, and the bus signal distributor sends the time information pulse to the IRIG-G (DC) decoder;

[0072] The IRIG-G (DC) decoder processes the received time information pulse to obtain the coverage update time timing information, wherein the coverage update time timing information includes extracting the code element of the time information pulse by using the code element extraction module, and extracting the timing information and pulse of the time information pulse by using the timing information pulse extraction module;

[0073] The coarse time is updated by using the overlay update time timing information.

[0074] Specifically, in this exemplary embodiment, with respect to the coarse time timing information of the main controller card (i.e., corresponding to the main controller card that generates the coarse time itself), in order to make the coarse time more accurate (reduce the error in the internal time calculation), the time information pulse generated by the time information generator every third cycle (for example, 0.01s, corresponding to 10ms) is used for overwriting and updating, wherein the time information pulse generated by the time information generator is accurate time information.

[0075] Specifically, the time information generator sends the generated time information pulse to the bus signal distributor every third cycle, the bus signal distributor sends the time information pulse to the IRIG-G (DC) decoder, the IRIG-G (DC) decoder processes the received time information pulse to obtain the coverage update time timing information, and finally uses the coverage update time timing information to cover and update the coarse time. The coverage update time timing information includes the code element of the time information pulse extracted by the code element extraction module, and the timing information and pulse of the time information pulse extracted by the timing information pulse extraction module.

[0076] In a specific exemplary embodiment, the time information pulse is as follows Figure 3 As shown, specifically: each frame pulse includes 100 bits of data, which are respectively allocated as year, day, hour, minute, second, 0.1 second, and 0.01 second as timing information; each bit of data is represented by 0 code element, 1 code element or P code element, 0 code element and 1 code element represent 0 and 1 in binary respectively, and P code element represents the cutoff of the corresponding bit. Among them, the 1st to 10th bits represent seconds, the 11th to 20th bits represent minutes, the 21st to 30th bits represent hours, the 31st to 45th bits represent days, the 46th to 50th bits represent 0.1 seconds, the 51st to 60th bits represent 0.01 seconds, the 61st to 70th bits represent years, and the 71st to 100th bits represent control functions. Figure 2 The time information pulses in the clock represent: 24 years, 304 days, 11 hours, 15 minutes, and 30.26 seconds. Figure 2 The “TIME FRAME” in the table means that the third period is 0.01 seconds, and the “INDEX COUNT” means that the first period is 0.1 ms.

[0077] More preferably, in an exemplary embodiment, the time information pulse generated by the time information generator is a relative time information pulse, such as Figure 4 As shown, the time information generator includes an IRIG-G (DC) encoder, and the IRIG-G (DC) encoder includes a symbol generator, a time extraction pre-carry processing module and a time synchronizer;

[0078] The time information generator generates relative time information pulses, including:

[0079] The soft-core CPU sends the initial time information to the IRIG-G (DC) encoder via the AVALON bus, and the IRIG-G (DC) encoder starts timing based on the initial time information to obtain relative time information;

[0080] The code element generator of the IRIG-G (DC) encoder converts the relative time information into code elements, and then the time extraction pre-carry processing module and the time synchronizer convert the code elements into relative time information pulses, and send the relative time information pulses to the bus signal distributor.

[0081] Specifically, in this exemplary embodiment, the time information pulse generated by the time information generator of the main controller card is a relative time information pulse, that is, when synchronization with the external real time is not required, the relative time is for the entire system, and at this time the time of the main controller card and the time sent by the main controller card to the functional daughter card are both relative times. The specific generation process of relative time is as follows:

[0082] The soft-core CPU sends the initial time information to the IRIG-G (DC) encoder through the AVALON bus. The IRIG-G (DC) encoder will start timing based on the initial time to obtain the relative time information, and the soft-core CPU will no longer be required. However, during the process, the soft-core CPU can obtain the current time of the IRIG-G (DC) encoder and correct it (the correction operation itself may introduce errors, so the correction operation should be a slow operation, such as once an hour or a day, or even no correction, because the accumulation of errors will not affect the accuracy of the relative time).

[0083] After the initial time information enters the IRIG-G (DC) encoder, the symbol generator converts the initial time information into symbols, and then the time extraction pre-carry processing module and the time synchronizer convert the symbols into relative time information pulses, and then the relative time information is transmitted to the bus signal distributor, and the relative time information pulse is generated. Subsequently, the bus signal distributor transmits the relative time information pulse to the IRIG-G (DC) decoder for decoding to obtain the coverage update time timing information (to achieve the relative time acquisition within the board), or transmits it to the second MLVDS transceiver and the first CAT5e network port to transmit pulses externally (to achieve the coarse time synchronization of other chassis, such as the subsequent cross-chassis exemplary embodiment).

[0084] More preferably, in an exemplary embodiment, the time information pulse generated by the time information generator is a real time information pulse, such as Figure 5 As shown, the time information generator includes a second CAT5e network port and a third MLVDS transceiver;

[0085] The time information generator generates real time information pulses, including:

[0086] The second CAT5e network port receives the real time information pulse sent by the external high-precision timing module, and forwards it to the bus signal distributor through the third MLVDS transceiver.

[0087] Specifically, in this exemplary embodiment, the time information pulse generated by the time information generator of the main controller card is a real time information pulse, that is, if synchronization with external real time is required, an external high-precision timing module (which can be a GPS / 5G / PTP high-precision timing module) needs to be connected, and the high-precision timing module sends the real time information pulse to the main controller card, specifically, the second CAT5e network port of the main controller card receives the external real time information pulse and transmits it to the third MLVDS transceiver, and the third MLVDS transceiver transmits the real time information pulse to the bus signal distributor, and the real time information pulse is generated. Subsequently, the bus signal distributor sends the real time information pulse to the IRIG-G (DC) decoder for decoding to obtain the coverage update time timing information (realizing the acquisition of the real time in the board), or transmits it to the second MLVDS transceiver and the first CAT5e network port to transmit pulses externally (realizing the coarse time synchronization of other chassis, such as the subsequent cross-chassis exemplary embodiment).

[0088] It should be noted that the latching process for latching real time and relative time is the same, which mainly depends on whether the main controller card uses an external high-precision timing module.

[0089] More preferably, in an exemplary embodiment, Figure 6 As shown, the IRIG-G (DC) decoder forms the timestamp of the coarse time refreshed in each first cycle as the synchronization pulse of the coarse time timing information of the functional daughter card, and sends it to the backplane timing bus through the first MLVDS transceiver.

[0090] Specifically, this exemplary embodiment is applicable to a main controller card that needs to send coarse time timing information to a functional sub-card. The main controller card sends the synchronization pulse of the coarse time timing information of the functional sub-card to the backplane timing bus through the first MLVDS transceiver every first cycle, wherein the coarse time timing information of the functional sub-card corresponds to the coarse time timing information of the main controller card; the functional sub-card connected to the backplane timing bus can obtain the coarse time timing information of the functional sub-card every first cycle.

[0091] In addition, the backplane timing bus in the chassis uses MLVDS technology, and its phase accuracy is much higher than the TTL level. The error generated during signal transmission is negligible compared to the nanosecond error of the above-mentioned clock synchronization delay.

[0092] More preferably, in an exemplary embodiment, Figure 7As shown, the time information generator sends the generated time information pulse to the bus signal distributor every third cycle, and the bus signal distributor sends the time information pulse as cross-box coarse time synchronization information to the outside through the second MLVDS transceiver and the first CAT5e network port.

[0093] Specifically, this exemplary embodiment is applicable to application scenarios that require multiple groups of chassis, each group of chassis includes a main controller card and preferably an external functional daughter card. No matter how many chassis there are in the entire system, only one chassis acts as a time generator to provide timing information for the entire system. The limitation of this exemplary embodiment corresponds to the main controller card of the chassis as a time generator. The bus signal distributor uses the time information pulse as the cross-chassis coarse time synchronization information, and sends it to other external chassis through the second MLVDS transceiver and the first CAT5e network port. The third CAT5e network port of the main controller card in the other chassis receives the time information pulse every third cycle, and sends it to the IRIG-G (DC) decoder through the fifth MLVDS transceiver to obtain the cross-chassis coverage update time timing information. The coverage method of the coverage update time timing information is the same as the coverage time in the box; the subsequent cross-chassis coarse time calculation refers to the coverage update time timing information.

[0094] In addition, this exemplary embodiment also provides high stability and long-distance timing capabilities: the timing bus uses MLVDS differential pairs for transmission, and the timing between chassis uses standard CAT5e interfaces and cables, which can improve the reliability of long-distance timing and further reduce errors. By reducing the pulse rising and falling edge times, the path is steeper and the slope is larger, reducing the error caused by the edge. Especially when the transmission path is very long, the error reduction is very considerable.

[0095] More preferably, in an exemplary embodiment, the coarse time timing information is the coarse time timing information of the function daughter card;

[0096] like Figure 8 As shown, the coarse time timing information of the functional daughter card is obtained by the fourth MLVDS transceiver receiving a synchronization pulse through the backplane timing bus every first cycle and sending it to the IRIG-G (DC) decoder for decoding.

[0097] Specifically, in this exemplary embodiment, this exemplary embodiment is applicable to the limitation of the functional daughter card. The functional daughter card itself does not have a time generating device. Therefore, the synchronization pulse sent by the main controller card is received by the fourth MLVDS transceiver connected to the backplane timing bus, and the synchronization pulse is sent to the IRIG-G (DC) decoder for decoding, thereby completing the coarse time synchronization of the functional daughter card.

[0098] More preferably, in an exemplary embodiment, the coarse time timing information is cross-box coarse time timing information; the coarse time based on which the cross-box coarse time timing information is overwritten and updated once every third period, and the overwriting and updating methods include:

[0099] like Fig. 9 As shown, the time information pulse sent externally as the cross-box coarse time synchronization information is received through the third CAT5e network port every third period, and is sent to the IRIG-G (DC) decoder through the fifth MLVDS transceiver and the bus signal distributor. The IRIG-G (DC) decoder decodes to obtain the cross-box coverage update time synchronization information. The cross-box coverage update time synchronization information includes the code element of the time information pulse extracted by the code element extraction module, and the timing information and pulse of the time information pulse extracted by the timing information pulse extraction module;

[0100] The cross-box coverage update time synchronization information is used to cover and update the coarse time.

[0101] Specifically, this exemplary embodiment is applicable to application scenarios that require multiple groups of chassis, each group of chassis includes a main controller card and preferably an external functional daughter card. No matter how many chassis there are in the entire system, only one chassis acts as a time generator to provide timing information for the entire system. The limitation of this exemplary embodiment corresponds to the main controller card in other chassis that receives the cross-chassis coarse time timing information sent by the chassis that acts as a time generator. The third CAT5e network port of the main controller card receives the time information pulse every third cycle, and sends it to the IRIG-G (DC) decoder through the fifth MLVDS transceiver for decoding to obtain the coverage update time timing information, thereby completing the coarse time coverage update of its own chassis.

[0102] More preferably, in an exemplary embodiment, Fig.10 As shown, the functional card includes an automatic event trigger, an IRIG-G (DC) decoder and a soft-core CPU; the automatic event trigger includes a signal preprocessing module, a multi-channel data source module, a data filter module, a threshold discrimination module and an event pulse generator; the IRIG-G (DC) decoder includes a DMA data transmission module, a time latch, a time information register group and an event FIFO module (in addition, in Fig.10 In the figure, the symbol extraction module and the timing information pulse extraction module in the aforementioned exemplary embodiment are also shown, and the coarse time refresh module and the fine time refresh module correspond to the coarse time timing information extraction and the fine time timing information extraction in the aforementioned exemplary embodiment respectively);

[0103] Function card event trigger time records include:

[0104] The signal preprocessing module of the automatic event trigger receives the external trigger signal for digital quantity processing, and sends it to the data filter module and the threshold discrimination module in sequence through the multi-channel data source module for filtering and threshold screening. The screened data source directly triggers the event pulse generator to form a first code including the trigger channel and the trigger event;

[0105] The DMA data transmission module of the IRIG-G (DC) decoder receives the first code through the AVALON bus and triggers the time latch at the same time. The time latch puts the decoded current time point into the time information register group. The DMA data transmission module re-encodes the current time point and the first code taken out from the time information register group to form a second code including the trigger channel, the trigger time and the trigger event; and puts the second code into the event FIFO module for storage;

[0106] Function card event trigger time reading includes:

[0107] The soft-core CPU reads the current time point data from the time information register group of the IRIG-G (DC) decoder through the AVALON bus to obtain the time information of the current trigger event; and / or:

[0108] The soft-core CPU reads the second code from the event FIFO module of the IRIG-G (DC) decoder through the AVALON bus to obtain the time information of the historical event triggering.

[0109] Specifically, in this exemplary embodiment, an event triggering mechanism applicable to both the main controller card and the function daughter card is disclosed, such as Fig.11 As shown:

[0110] S1: The external trigger signal (switch quantity, analog quantity, level signal or pulse, not limited) is transmitted to the signal preprocessing module of the automatic event trigger through the input terminal of the function card (converting the analog quantity into digital quantity);

[0111] S2: After preprocessing, a multi-channel data source module is connected to an automatic event trigger. The multi-channel data source module is divided into multiple data source channels (the number of channels is limited by the system's own internal resources). In one exemplary embodiment (such as Fig.10 As shown in the figure, 32 data source channels are set, namely CH1 data source, CH2 data source, CH3 data source..........CH32 data source;

[0112] S3: Transfer the data sources of different channels to the data filter module, and perform technical filtering according to the filtering rules set by the data filter module. The filtering length is adjustable. Specifically, when the input data is a switch quantity, the filtering rule is an "anti-jitter" filter. For example, when the input data is continuously collected as N 1s, the filter stage will output 1. The same is true when the input data is 0. The N value here can be set. When the input data is an analog quantity, the filtering rule is a "sliding average filter". For example, a 5-point sliding filter is performed on the input data to eliminate peak jitter and prevent false threshold judgment.

[0113] S4: The data source filtered by the data filter is transmitted to the threshold discrimination module. The threshold parameters of the threshold discrimination module are set by the soft-core CPU (transmitted through the AVALON bus). The determined value or upper and lower limits of the threshold parameters are set to filter the data source that meets the parameter setting.

[0114] S5: The data source screened by the threshold discrimination module directly triggers the event pulse generator. The event pulse generator encodes different data sources to form a first code. The encoding rule of the first code is: 1: trigger event; 2: trigger event; 3: trigger event........32: trigger event (different serial numbers represent different channel names. The trigger event refers to what rule triggers it, for example: rising edge or falling edge);

[0115] The above steps (S1~S5) are all executed in sequence by automatic event triggers.

[0116] S6: The event pulse generator sends the first code to the DMA data transmission module of the IRIG-G (DC) decoder through the AVALON bus. The DMA data transmission module triggers the time latch at the same time when receiving the code. The time latch executes as follows: Figure 1 After the latching step shown, the decoded current time point is put into the time information register group;

[0117] S7: The DMA data transmission module combines the current time point stored in the time information register group and the first code sent by the event pulse generator into a set of data for re-encoding to form a second code including the trigger channel, trigger time and trigger event. The second code setting rule is: trigger channel (serial number): trigger time (time): trigger event (trigger rule), for example 1: time: rising edge; 2: time: falling edge.......... (wherein the serial number represents the channel name, which is represented bit by bit in binary conversion; time represents the latched instantaneous time corresponding to the channel name, that is, the current time point; the trigger rule represents which rule triggers, for example: rising edge or falling edge)

[0118] S8: putting the second code into the event FIFO module for storage;

[0119] The above steps (S6-S8) are all executed in sequence by the IRIG-G (DC) decoder. The corresponding time points of the subsequent data sources are deduced in the same way, so that the specific time points when different data sources enter the input end of the function card can be obtained.

[0120] S9: The soft-core CPU reads the current time point data from the time information register group of the IRIG-G (DC) decoder through the AVALON bus to obtain the time information of the current trigger event;

[0121] S10: The soft-core CPU reads the second code from the event FIFO module of the IRIG-G (DC) decoder through the AVALON bus to obtain the time information of the historical event triggering.

[0122] The above steps (S9 and S10) are selected and executed by the soft-core CPU according to actual needs.

[0123] Among them, it should be noted that:

[0124] (1) The reason for storing the data group, i.e., the second code, in the event FIFO module is that the time information register group can only store the latest time data information, and the subsequent new time data information will overwrite the previous time data information. Therefore, only by storing the data group obtained in step S6 in the event FIFO module can the saving and reading of the historical time information in step S10 be realized; on the other hand, if only the time information of the current triggering event is needed, the soft-core CPU can directly read the latest data from the time information register group through the AVALON bus (as described in step S9).

[0125] (2) The DMA data transmission module acts as a coprocessor. When it is necessary to read the time point information of historical trigger events, the DMA can bypass the soft-core CPU and operate independently, thus reducing the burden on the soft-core CPU.

[0126] The specific benefits achieved by the DMA data transmission module in this exemplary embodiment include: ① Greatly improve time accuracy: If DMA is not used and the soft-core CPU is used for latching, a random error (ranging from a few microseconds to a few milliseconds) will be introduced, which will have a great impact on the system synchronization accuracy and cannot be eliminated; while using DMA will only introduce a fixed error at the nanosecond level, which is easier to eliminate in later applications. ② Independently handle the work of the soft-core CPU so that it can handle other matters, speed up the system operation efficiency and thus improve the overall system performance. ③ The event FIFO module can cache the latched historical instantaneous time information, which is convenient for the soft-core CPU to read at any time.

[0127] in addition, Figure 12 to Figure 18 A schematic diagram of a functional card architecture and a chassis architecture obtained by combining the above exemplary embodiments is shown, specifically:

[0128] Fig.12 Shown based on Fig.10 The schematic diagram of the architecture of the main controller card latching relative time of the functional card structure is as follows: the soft-core CPU sends the initial time information to the IRIG-G (DC) encoder through the AVALON bus, and the IRIG-G (DC) encoder starts timing based on the initial time; after the initial time information enters the IRIG-G (DC) encoder, Figure 4 As shown, the code generator inside the IRIG-G (DC) encoder converts the initial time information into code elements, and then the time extraction pre-carry processing module and the time synchronizer convert the code elements into relative time information pulses. The relative time information pulses are then transmitted to the bus signal distributor every third cycle (0.01s), and the bus signal distributor transmits the pulse signal to the IRIG-G (DC) decoder for decoding or to the second MLVDS transceiver and the first CAT5e network port to transmit pulses externally. When transmitted to the IRIG-G (DC) decoder, the IRIG-G (DC) decoder extracts code elements and timing information pulses from the relative time information pulses to obtain the coarse time for coverage and update, and then extracts the timestamp information once every first cycle (0.1ms) of the timing time (coarse time) (and sends it as the synchronization pulse of the coarse time timing information of the functional daughter card through the first MLVDS transceiver to the backplane timing bus and then to the functional daughter card. If there is a functional daughter card, such as Figure 6 As shown in the figure, the timing time (fine time) is refreshed every second cycle (10ns) to extract the time difference information generated by its own clock. Coarse time + fine time = current time point (the absolute time point at the current moment). The time point that is latched immediately after the time latch is triggered is this time point.

[0129] Fig.13 Shown based on Fig.10 The main controller card of the functional card structure latches the real time. The relevant process of the main controller card latching the real time includes: the high-precision timing module sends the real time information pulse to the main controller card, the second CAT5e network port of the main controller card receives the external pulse and transmits it to the bus signal distributor through the third MLVDS transceiver, and the bus signal distributor sends the real time information pulse to the IRIG-G (DC) decoder or transmits it to the outside through the second MLVDS transceiver. The rest of the time latch content is the same as Fig.12 The relevant processes described are the same and will not be repeated here.

[0130] Fig.14 Shown based on Fig.10The schematic diagram of the functional daughter card latching time of the functional card structure of the functional daughter card of the functional card component structure is shown in FIG. The relevant process of the functional daughter card latching time includes: receiving the synchronization pulse sent by the main controller card through the fourth MLVDS transceiver connected to the backplane timing bus, and sending the synchronization pulse to the IRIG-G (DC) decoder for decoding, completing the coarse time synchronization of the functional daughter card (corresponding to Figure 8 ). The rest of the time the contents are latched and Fig.12 The relevant processes described are the same and will not be repeated here.

[0131] Fig.15 and Fig.16 The schematic diagram of the architecture of latching relative time and real time in a chassis including a main controller card and a functional daughter card is shown, wherein Fig.15 The logic of Fig.12 Overlay Fig.14 The relevant logic is the same as Fig.16 The logic of Fig.13 Overlay Fig.14 The relevant logic is the same and will not be repeated here.

[0132] Fig.17 and Fig.18 The schematic diagram of the architecture of multiple chassis latching relative time and real time is shown. The functional daughter card is not shown in the figure. If there is a need, it can be used according to Fig.15 and Fig.16 The relevant contents are superimposed. Among them, the time information generator (relative time is generated by the IRIG-G (DC) encoder, and the real time is sent by the external high-precision timing module) sends the generated time information pulse to the bus signal distributor every third cycle. The bus signal distributor sends the time information pulse as the cross-box coarse time synchronization information through the second MLVDS transceiver and the first CAT5e network port to the main controller card of the cross-box device. The main controller card of the cross-box device receives the time information pulse sent externally as the cross-box coarse time synchronization information through the third CAT5e network port every third cycle, and sends it to the IRIG-G (DC) decoder through the fifth MLVDS transceiver and the bus signal distributor. The IRIG-G (DC) decoder decodes and obtains the cross-box coverage update time synchronization information ( Fig. 9 ). The rest of the time the contents are latched and Fig.12 The relevant processes described are the same and will not be repeated here.

[0133] Obviously, the above embodiments are merely examples for clear explanation, and are not intended to limit the implementation methods. For ordinary technicians in the relevant field, other different forms of changes or modifications can be made based on the above description. It is not necessary and impossible to list all the implementation methods here. The obvious changes or modifications derived from them are still within the protection scope of the invention.

Claims

1. A time latching method based on a functional card, characterized in that: include: The time latch receives the trigger signal and latches the current time point; the current time point includes coarse time timing information and fine time timing information; The coarse time timing information is obtained by extracting the timestamp of the coarse time refreshed in each first cycle, and the first cycle corresponds to the IRIG-G (DC) protocol; the fine time timing information is obtained by extracting the fine time counted in each second cycle, and the second cycle corresponds to the local clock frequency; The fine time timing information is specifically the time difference information generated by the local clock in each first cycle, the local clock includes a counter unit and a fine time calculation unit, the maximum count number of the counter unit is the first cycle divided by the second cycle, and the counter unit performs an addition operation every second cycle until the maximum count number is reached and a reset operation is performed; When the time latch is triggered, the fine time calculation unit multiplies the count value of the counter unit by the second period to obtain time difference information as fine time timing information.

2. The time latching method based on a functional card according to claim 1 is characterized in that: The coarse time timing information is the coarse time timing information of the main controller card.

3. The time latching method based on a functional card according to claim 2 is characterized in that: The coarse time based on the timing information of the main controller card is updated every third cycle. The update method includes: The time information generator sends the generated time information pulse to the bus signal distributor every third cycle, and the bus signal distributor sends the time information pulse to the IRIG-G (DC) decoder; The IRIG-G (DC) decoder processes the received time information pulse to obtain the coverage update time timing information, wherein the coverage update time timing information includes extracting the code element of the time information pulse by using the code element extraction module, and extracting the timing information and pulse of the time information pulse by using the timing information pulse extraction module; The coarse time is updated by using the overlay update time timing information.

4. The time latching method based on a functional card according to claim 3 is characterized in that: The time information pulse generated by the time information generator is a relative time information pulse, the time information generator comprises an IRIG-G (DC) encoder, and the IRIG-G (DC) encoder comprises a code element generator, a time extraction pre-carry processing module and a time synchronizer; The time information generator generates relative time information pulses, including: The soft-core CPU sends the initial time information to the IRIG-G (DC) encoder via the AVALON bus, and the IRIG-G (DC) encoder starts timing based on the initial time information to obtain relative time information; The code element generator of the IRIG-G (DC) encoder converts the relative time information into code elements, and then the time extraction pre-carry processing module and the time synchronizer convert the code elements into relative time information pulses, and send the relative time information pulses to the bus signal distributor.

5. The time latching method based on a functional card according to claim 3 is characterized in that: The time information pulse generated by the time information generator is a real time information pulse, and the time information generator includes a second CAT5e network port and a third MLVDS transceiver; The time information generator generates real time information pulses, including: The second CAT5e network port receives the real time information pulse sent by the external high-precision timing module, and forwards it to the bus signal distributor through the third MLVDS transceiver.

6. A time latching method based on a functional card according to any one of claims 2 to 5, characterized in that: The IRIG-G (DC) decoder forms the timestamp of the coarse time refreshed in each first cycle as the synchronization pulse of the coarse time timing information of the functional daughter card, and sends it to the backplane timing bus through the first MLVDS transceiver.

7. A time latching method based on a functional card according to any one of claims 3 to 5, characterized in that: The time information generator sends the generated time information pulse to the bus signal distributor every third cycle, and the bus signal distributor sends the time information pulse as cross-box coarse time synchronization information to the outside through the second MLVDS transceiver and the first CAT5e network port.

8. The time latching method based on a functional card according to claim 1, characterized in that: The coarse time timing information is the coarse time timing information of the functional daughter card; The coarse time timing information of the functional daughter card is obtained by receiving a synchronization pulse through the backplane timing bus of the fourth MLVDS transceiver every first cycle and sending it to the IRIG-G (DC) decoder for decoding.

9. The time latching method based on a functional card according to claim 1, characterized in that: The coarse time timing information is cross-box coarse time timing information; the coarse time based on which the cross-box coarse time timing information is based is updated once every third period, and the update mode includes: The time information pulse as cross-box coarse time synchronization information sent externally is received through the third CAT5e network port every third period, and is sent to the IRIG-G (DC) decoder through the fifth MLVDS transceiver and the bus signal distributor. The IRIG-G (DC) decoder decodes and obtains the cross-box coverage update time synchronization information. The cross-box coverage update time synchronization information includes the code element of the time information pulse extracted by the code element extraction module, and the timing information and pulse of the time information pulse extracted by the timing information pulse extraction module; The cross-box coverage update time synchronization information is used to cover and update the coarse time.

10. The time latching method based on a functional card according to claim 1, characterized in that: The functional card comprises an automatic event trigger, an IRIG-G (DC) decoder and a soft-core CPU; the automatic event trigger comprises a signal preprocessing module, a multi-channel data source module, a data filter module, a threshold discrimination module and an event pulse generator; the IRIG-G (DC) decoder comprises a DMA data transmission module, a time latch, a time information register group and an event FIFO module; Function card event trigger time records include: The signal preprocessing module of the automatic event trigger receives the external trigger signal for digital quantity processing, and sends it to the data filter module and the threshold discrimination module in sequence through the multi-channel data source module for filtering and threshold screening. The screened data source directly triggers the event pulse generator to form a first code including the trigger channel and the trigger event; The DMA data transmission module of the IRIG-G (DC) decoder receives the first code through the AVALON bus and triggers the time latch at the same time. The time latch puts the decoded current time point into the time information register group. The DMA data transmission module re-encodes the current time point and the first code taken out from the time information register group to form a second code including the trigger channel, the trigger time and the trigger event; and puts the second code into the event FIFO module for storage; Function card event trigger time reading includes: The soft-core CPU reads the current time point data from the time information register group of the IRIG-G (DC) decoder through the AVALON bus to obtain the time information of the current trigger event; and / or: The soft-core CPU reads the second code from the event FIFO module of the IRIG-G (DC) decoder through the AVALON bus to obtain the time information of the historical event triggering.

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