MOS device and method for manufacturing a MOS device

Abstract

The application discloses a MOS device and a preparation method thereof. The MOS device comprises at least one source trench structure arranged between two adjacent first side surfaces and in contact with a source region structure. The source trench structure comprises a first gate, a second gate, a first dielectric layer and a second dielectric layer. The first dielectric layer is arranged between the first gate and the second gate. The first gate, the second gate and the first dielectric layer form a first structure. The second dielectric layer is arranged on the side surface and the bottom surface of the first structure and is in contact with the source region structure and a drift layer. The first dielectric layer comprises at least a first material layer and a second material layer arranged in a second direction. The dielectric constant of the material of the first material layer is greater than the dielectric constant of the material of the second material layer. The second direction is a direction from a substrate to the source region structure. The problems of damage of the device caused by reverse leakage current between the source and the drain and large power consumption caused by large coupling area between the source and the drain in the related art are solved.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and more specifically, to a MOS device and a method for fabricating a MOS device. Background Technology

[0002] Silicon-based IGBTs dominate high-voltage, high-current applications, but they cannot withstand high-frequency operation and have high power consumption. SiC, on the other hand, with its high voltage and high temperature resistance, allows it to achieve the same voltage withstand capability as silicon-based IGBTs using simpler MOSFET devices, while avoiding their high energy consumption. Under the same conditions, silicon carbide MOSFETs reduce energy loss by 66% compared to silicon-based IGBTs of the same specifications, primarily due to a significant reduction in switching losses. In the new energy vehicle industry, SiC can be used in inverters for driving and controlling motors, on-board chargers, and fast-charging stations. In photovoltaic power generation, leading photovoltaic inverter companies have already adopted SiC power devices to replace silicon devices.

[0003] In power electronic systems, SiC MOSFETs primarily function as electronic switches. When the MOSFET is in the off state, there is a reverse leakage current between the drain and source. Without an anti-parallel diode, this leakage current could damage other components in the circuit. Furthermore, when SiC MOSFETs are used for AC circuit rectification, since the MOSFET can only conduct under forward voltage, an anti-parallel diode is needed to provide a conduction path under reverse voltage, thereby achieving current rectification. Therefore, an external anti-parallel diode or an internal diode is typically used to improve the performance of the SiC MOSFET's body diode, thereby increasing the SiC MOSFET's efficiency. However, an external anti-parallel diode increases the circuit footprint, raises the device's packaging cost, and introduces parasitic capacitance and inductance, leading to slower response speeds and poor reliability. Internally integrated heterojunction Schottky barrier diodes (SBDs) have excessively high turn-on voltages (2.7-3.0V), making it difficult to provide freewheeling protection for the MOSFET under reverse bias. Both methods require additional area. Integrated Schottky diodes have large reverse leakage current, and an excessively large SBD area can even affect the reverse breakdown voltage of the MOSFET. Furthermore, the large voltage drop of the Schottky diode at high currents results in significant voltage drop losses when the freewheeling current is large. When the SiC MOS device is in the off state, there is a reverse leakage current between the drain and source. Without adding a freewheeling path, this leakage current may damage other components in the circuit. Summary of the Invention

[0004] This application provides a MOS device and a method for fabricating a MOS device to solve the problems in related technologies, such as reverse leakage current between the source and drain damaging the device and large power consumption caused by the large coupling area between the source and drain.

[0005] According to one aspect of this application, a MOS device is provided, comprising a plurality of cells, each cell including a substrate and a drift layer located on one side of the substrate, the drift layer having a first surface facing away from the substrate, the cell further comprising: a plurality of source region structures, the plurality of source region structures being spaced apart along a first direction, adjacent two source region structures having mutually approaching first side surfaces and two mutually opposing second side surfaces in the first direction, wherein the region between two adjacent second side surfaces is a drift region, the drift region being a portion of the drift layer, the first direction being parallel to the first surface; a plurality of gate structures, the gate structures being located on the side of the drift region facing away from the substrate, and the gate structures being in contact with the source region structures located on both sides of the drift region respectively; at least one source trench structure, the source... The source trench structure is located between two adjacent first side surfaces and is in contact with the source region structure. The source trench structure includes a first gate, a second gate, a first dielectric layer, and a second dielectric layer. The first gate and the second gate are spaced apart along the first direction. The first dielectric layer is located between the first gate and the second gate. The first gate, the second gate, and the first dielectric layer constitute a first structure. The second dielectric layer is located on the side surface and the bottom surface of the first structure and is in contact with the source region structure and the drift layer. The second dielectric layer includes at least a first material layer and a second material layer stacked sequentially in a second direction. The dielectric constant of the material of the first material layer is greater than the dielectric constant of the material of the second material layer. The second direction is the direction from the substrate to the source region structure.

[0006] Optionally, the material of the first material layer includes a high-K material, and the material of the second material layer includes a low-K material.

[0007] Optionally, the first dielectric layer further includes a third material layer, which is located on the side of the second material layer opposite to the first material layer, and the material of the third material layer includes an insulating material with waterproof properties.

[0008] Optionally, the first material layer has a first thickness in the second direction, and the second material layer has a second thickness in the second direction, wherein the first thickness is less than the second thickness.

[0009] Optionally, the second dielectric layer includes a first gate oxide layer and a fourth material layer stacked together. The first gate oxide layer is located on the side and bottom surfaces of the first structure that are in contact with the drift layer, respectively. The fourth material layer is located above and inside the first gate oxide layer. The material of the fourth material layer includes a high-k material.

[0010] Optionally, the MOS device further includes: a shielding region located on the side of the source trench structure near the substrate, the shielding region having a different doping type from the drift layer, wherein the shielding region has a plurality of sub-shielding regions spaced apart along the first direction.

[0011] Optionally, a first spacing is provided between any two adjacent sub-shielding areas in the first direction, and m sub-shielding areas are provided along the first direction, wherein: if m is an even number, the first spacing between the m / 2th sub-shielding area and the (m / 2)+1th sub-shielding area in the first direction is greater than the remaining first spacing; if m is an odd number, the first spacing between the (m-1) / 2th sub-shielding area and the (m+1) / 2th sub-shielding area in the first direction is greater than the remaining first spacing, and / or the first spacing between the (m+1) / 2th sub-shielding area and the (m+3) / 2nd sub-shielding area is greater than the remaining first spacing.

[0012] Optionally, the MOS device further includes: a first conductive layer, which is located on the side of the source trench structure away from the substrate and is in contact with the first gate, the second gate, the first dielectric layer and the second dielectric layer respectively, and the first conductive layer is connected to the source region structure.

[0013] According to another aspect of this application, a method for fabricating a MOS device is provided. The MOS device includes a plurality of cells. The step of forming the cells includes: providing a substrate; forming a drift layer on one side of the substrate, the drift layer having a first surface facing away from the substrate; the cells further include: forming a plurality of source region structures in the drift layer, the plurality of source region structures being spaced apart along a first direction, two adjacent source region structures having first side faces that are close to each other and second side faces that are facing away from each other, wherein the region between two adjacent second side faces is a drift region, the drift region being a portion of the drift layer, the first direction being parallel to the first surface; forming a first trench between two adjacent source region structures, the sidewalls of the first trench exposing the first side faces of the source region structures; forming a source trench structure in the first trench; the source trench structure being... The structure includes a first gate, a second gate, a first dielectric layer, and a second dielectric layer. The first gate and the second gate are spaced apart along a first direction. The first dielectric layer is located between the first gate and the second gate. The first gate, the second gate, and the first dielectric layer constitute a first structure. The second dielectric layer is located on the side and bottom surface of the first structure and is in contact with the source region structure and the drift layer. The second dielectric layer includes at least a first material layer and a second material layer stacked sequentially in a second direction. The dielectric constant of the material of the first material layer is greater than the dielectric constant of the material of the second material layer. The second direction is the direction from the substrate to the source region structure. A plurality of gate structures are formed on the side of the drift region away from the substrate, and the gate structures are in contact with the source region structures located on both sides of the drift region.

[0014] Optionally, the step of forming the source trench structure includes: forming a second dielectric layer on the sidewall of the first trench, with the remaining first trench constituting a second trench; forming a gate material region in the second trench using a deposition process; etching a third trench in the gate material region, wherein the gate material regions are exposed on opposite sidewalls in the first direction, and the remaining gate material regions constitute the first gate and the second gate respectively; and forming the first material layer and the second material layer in the third trench using a multiple deposition process, wherein the first material layer and the second material layer constitute the first dielectric layer.

[0015] The present application provides a MOS device in which a source trench structure is formed between the first sides of the two source regions. The first gate and the second gate in the source trench structure are spaced apart, and a first dielectric layer is formed between the first gate and the second gate, giving the source trench structure a structure similar to a split gate. When the MOS device is in the forward state, the source trench structure and the source structure work together to reduce lateral leakage current. When the MOS device is in the reverse state, the first gate and the second gate will induce annular inversion layers around the source trench structure with the nearby source structure, thereby forming a freewheeling channel for current to flow from the source to the drain. The source trench structure results in a large coupling area between the source and drain, significantly increasing the feedback capacitance and source charge of the device and reducing the switching speed. The first dielectric layer between the first gate and the second gate has a first material layer and a second material layer. The dielectric constant of the first material layer is greater than that of the second material layer. The second material layer can shield the coupling area between the source and drain, reducing the feedback capacitance and source charge of the device, improving the switching speed and reducing the power consumption. The first material layer is located at the bottom of the first dielectric layer, which can protect the second material layer from breakdown, increasing the breakdown resistance of the bottom of the source trench structure, thereby improving the overall performance of the device. Attached Figure Description

[0016] The accompanying drawings, which form part of this application, are used to provide a further understanding of this application. The illustrative embodiments and descriptions of this application are used to explain this application and do not constitute an undue limitation of this application. In the drawings:

[0017] Figure 1 This is a cross-sectional structural schematic diagram of a MOS device according to an embodiment of this application;

[0018] Figure 2 This is a cross-sectional structural schematic diagram of another MOS device according to an embodiment of this application;

[0019] Figure 3 This is a cross-sectional structural schematic diagram of another MOS device according to an embodiment of this application;

[0020] Figure 4 This is a schematic diagram of the current flow direction of a MOS device in reverse conduction state according to an embodiment of this application;

[0021] Figure 5 This is a schematic diagram of the current flow direction of a MOS device in the forward conduction state according to an embodiment of this application;

[0022] Figure 6 A flowchart illustrating a method for fabricating a MOS device according to an embodiment of this application is shown;

[0023] Figure 7 The diagram shows a cross-sectional view of the substrate obtained in the first to fourth steps of a method for fabricating a MOS device according to an embodiment of this application.

[0024] Figure 8 This illustration shows a cross-sectional view of the substrate after the shielding region is formed in a method for fabricating a MOS device according to an embodiment of this application.

[0025] Figure 9 The diagram shows a cross-sectional view of the substrate obtained in steps 5 to 9 of a method for fabricating a MOS device according to an embodiment of this application.

[0026] Figure 10 The diagram shows a cross-sectional structure of the substrate obtained in steps 10 to 13 of a method for fabricating a MOS device according to an embodiment of this application.

[0027] The above figures include the following reference numerals:

[0028] 1. Cell; 10. Substrate; 20. Drift layer; 201. First surface; 202. Drift region; 30. Source region structure; 301. First side surface; 302. Second side surface; 31. Body region; 32. First doped region; 40. Gate structure; 41. Third gate; 42. Second gate oxide layer; 50. Source trench structure; 51. First gate; 511. Gate material region; 52. Second gate; 53. First dielectric layer; 531. First material layer; 532. Second material layer; 533. Third material layer; 54. Second dielectric layer; 541. Fourth material layer; 542. First gate oxide layer; 61. Gate electrode; 62. Gate dielectric layer; 70. Shielding region; 71. Sub-shielding region; 81. First conductive layer; 811. Ohmic metal layer; 82. Second conductive layer; 91. First trench; 92. Second trench; 93. Third trench. Detailed Implementation

[0029] It should be noted that, unless otherwise specified, the embodiments and features described in this application can be combined with each other. This application will now be described in detail with reference to the accompanying drawings and embodiments.

[0030] To enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present application, and not all embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative effort should fall within the scope of protection of the present application.

[0031] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate for the embodiments of this application described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0032] As described in the background section, in the prior art, when a SiC MOS device is in the off state, there is a reverse leakage current between the drain and the source. If a freewheeling path is not added, this leakage current may damage other devices in the circuit. This application provides a MOS device and a method for fabricating a MOS device.

[0033] According to one aspect of this application, a MOS device is provided, such as... Figures 1 to 5As shown, the system includes multiple cells 1, each cell 1 including a substrate 10 and a drift layer 20 located on one side of the substrate 10. The drift layer 20 has a first surface 201 facing away from the substrate 10. Cell 1 also includes: multiple source region structures 30, which are spaced apart along a first direction A. Adjacent source region structures 30 have mutually close first side surfaces 301 and two mutually opposing second side surfaces 302 along the first direction A. The region between two adjacent second side surfaces 302 is a drift region 202, which is a portion of the drift layer 20. The first direction A is parallel to the first surface 201. Multiple gate structures 40 are located on the side of the drift region 202 facing away from the substrate 10, and the gate structures 40 are in contact with the source region structures 30 located on both sides of the drift region 202. At least one source trench structure 50 is also included. The source trench structure 50 is located between two adjacent first side surfaces 301 and is in contact with the source region structure 30. The source trench structure 50 includes a first gate 51, a second gate 52, a first dielectric layer 53, and a second dielectric layer 54. The first gate 51 and the second gate 52 are spaced apart along a first direction A. The first dielectric layer 53 is located between the first gate 51 and the second gate 52. The first gate 51, the second gate 52, and the first dielectric layer 53 constitute a first structure. The second dielectric layer 54 is located on the side surface and the bottom surface of the first structure and is in contact with the source region structure 30 and the drift layer 20. The first dielectric layer 53 includes at least a first material layer 531 and a second material layer 532 stacked sequentially in a second direction B. The dielectric constant of the material of the first material layer 531 is greater than that of the material of the second material layer 532. The second direction B is the direction from the substrate 10 to the source region structure 30.

[0034] In the aforementioned MOS device, a source trench structure is formed between the first sides of the two source regions. The first gate and the second gate in the source trench structure are spaced apart, and a first dielectric layer lies between the first gate and the second gate, giving the source trench structure a structure similar to a split gate. When the MOS device is in the forward state, the source trench structure and the source structure work together to reduce lateral leakage current. When the MOS device is in the reverse state, the first gate and the second gate, together with the nearby source structure, induce annular inversion layers around the source trench structure, thereby forming a freewheeling path for current to flow from the source to the drain. However, the source trench structure results in a large coupling area between the source and drain, increasing the feedback capacitance and source charge of the device, and reducing the switching speed. The first dielectric layer between the first gate and the second gate has a first material layer and a second material layer. The dielectric constant of the first material layer is greater than that of the second material layer. The smaller the dielectric constant, the smaller the polarization charge, and the weaker the material's ability to influence the electric field. The second material layer has a smaller dielectric constant, which can shield the coupling area between the source and drain, reducing the feedback capacitance and source charge of the device, increasing the switching speed and reducing the power consumption. The first material layer is located at the bottom of the first dielectric layer, which can protect the second material layer from breakdown, increasing the breakdown resistance of the bottom of the source trench structure, and thus improving the overall performance of the device.

[0035] The depth of the source trench structure is 0.8μm to 1.5μm, the width is 0.15μm to 1.3μm, and the thickness of the second dielectric layer is 0.03μm to 0.08μm. Those skilled in the art can make reasonable selections according to actual needs, and this application does not make specific limitations.

[0036] In the above embodiments, the substrate and the drift layer have the same doping type, and the resistivity of the substrate is 0.016–0.24 Ωcm; the drift layer, as the main breakdown layer of the device, has a doping concentration of 1.0 × 10⁻⁶. 15 cm -3 ~1.0×10 16 cm -3 The thickness of the drift layer can be selected according to product requirements. For example, the drift layer thickness of a 1200V MOS device is 9μm to 11μm, and the drift layer thickness of a 650V MOS device is 5μm to 7μm.

[0037] In the above embodiments, such as Figures 1 to 5As shown, the source region structure 30 includes a body region 31 and a first doped region 32. The side of the first doped region 32 facing away from the drift region 202 is located in the first side 301. The body region 31 is located on the side of the first doped region 32 closest to the substrate 10 and the side of the first doped region 32 closest to the drift region 202. The gate structure 40 is in contact with the body region 31. The doping types of the body region 31 and the first doped region 32 are different. The first doped region 32 has the same doping type as the drift layer 20, and the doping concentration of the first doped region 32 is greater than that of the body region 31. The magnitude of the gate voltage applied to the gate structure 40 can control the formation of a current channel in the body region 31 in contact with the gate structure 40. When the MOS device is operating normally, i.e., when current is applied to the source, a current channel is formed in the body region 31 in contact with the source trench structure 50, thereby forming a freewheeling channel for current to flow from the source to the drain.

[0038] Specifically, the depth of the bulk region is 0.7 μm to 0.8 μm, and its doping concentration is 5.0 × 10⁻⁶. 16 cm -3 ~1.5×10 17 cm -3 The depth of the first doped layer is 0.2 μm to 0.3 μm, and its doping concentration is 1.0 × 10⁻⁶. 19 cm -3 ~1.0×10 20 cm -3 Those skilled in the art can make adjustments according to actual needs, and this application does not impose specific limitations.

[0039] In the above embodiments, such as Figures 1 to 5 As shown, the gate structure 40 includes a third gate 41 and a second gate oxide layer 42. The second gate oxide layer 42 is located on the side of the third gate 41 close to the substrate 10. The third gate 41 is in contact with the gate electrode 61. The third gate 41 and the gate electrode 61 are covered by the gate dielectric layer 62.

[0040] Specifically, by applying a gate voltage to the third electrode, a current channel is formed in the body region that is in contact with the gate structure. When the gate voltage is greater than the threshold, the current channel in the body region is opened and a current channel is formed. When the gate voltage is less than the threshold, no current is formed in the body region. At this time, no current is formed in the body region, and the gate structure forms a planar MOS structure. The thickness of the gate dielectric layer is 600nm to 1000nm.

[0041] In some alternative implementations, the material of the first material layer includes a high-K material, and the material of the second material layer includes a low-K material.

[0042] Specifically, high-k materials, or high-dielectric-constant materials, refer to materials with a dielectric constant higher than that of silicon dioxide. Silicon dioxide has a dielectric constant of approximately 3.9; therefore, materials with a dielectric constant greater than 3.9 are considered high-k materials. High-k materials have a higher charge storage capacity, meaning they can store more charge under the same electric field. Furthermore, high-k materials exhibit lower leakage current and higher breakdown voltage, contributing to improved device performance. Low-k materials, or low-dielectric-constant materials, refer to materials with a smaller dielectric constant, typically below 3.0. Low-k materials have lower capacitance effects and leakage current, reducing circuit power consumption and heat generation. Using a low-k material as the second material layer, with its lower capacitance effect, effectively reduces the device's feedback capacitance and source charge, improving switching speed and reducing power consumption. The high-k material layer further reduces leakage current while enhancing breakdown voltage. In addition, low-K materials have a multi-pore structure. The first and second gate materials are mostly doped polycrystalline silicon. The dopants in polycrystalline silicon are easy to diffuse into the pore structure of low-K materials, causing the second material layer to have the layer change of the capacitor dielectric. The first material layer composed of high-K materials is located at the bottom of the first dielectric layer and can play a good blocking role.

[0043] The low-k materials include fluorosilicate glass (FSG), porous organosilicon glass (P-OSG), fluorinated polyimide, benzocyclobutene (BCB), etc., while the high-k materials can be selected from one or more of HfO2, TiO2, HfZrO, HfSiNO, Ta2O5, ZrO2, ZrSiO2, Al2O3, La2O3, Y2O3, SrTiO3, and BaSrTiO. Those skilled in the art can make reasonable selections according to actual needs, and this application does not impose specific limitations.

[0044] In some alternative implementations, such as Figure 1 and Figures 3 to 5 As shown, the first dielectric layer 53 also includes a third material layer 533, which is located on the side of the second material layer 532 away from the first material layer 531. The material of the third material layer 533 includes an insulating material with waterproof properties.

[0045] Specifically, when the second material layer has a low dielectric constant, materials with low dielectric constants, especially low-k materials, often have a porous structure or hydrophilic groups in their chemical composition, resulting in easy water absorption. This water absorption and deformation during subsequent fabrication processes can affect the strength and adhesion of the second material layer, reducing the stability and reliability of the device. Furthermore, the water absorption of low-k materials reduces their capacitance and durability, impacting the overall performance of the device. Forming a waterproof insulating material, such as Si3N4, on top of the second material layer can effectively protect it from water absorption and deformation during subsequent processes. The thickness of the third material layer is 0.1 μm to 0.6 μm, and the specific thickness is not limited in this application.

[0046] In addition to Si3N4, the materials of the third material layer also include one or more of the following: metal oxides (such as alumina), polymer materials (such as polyimide, parylene and epoxy resin), hydrophobic materials (such as fluorinated polymers), carbon-based materials (such as graphene), and inorganic films (such as tantalum nitride, titanium nitride and silicon nitride oxide). This application does not limit the materials. These materials are mainly due to their low moisture permeability and good chemical stability, which can also effectively prevent changes in material properties or corrosion caused by moisture.

[0047] In some alternative implementations, the first material layer has a first thickness in the second direction, and the second material layer has a second thickness in the second direction, wherein the first thickness is less than the second thickness.

[0048] Specifically, in the first dielectric layer, the upper first material layer reduces the device's feedback capacitance and source charge, improves the device's switching speed, and reduces the device's power consumption. The lower second material layer enhances the protection of the second material layer from breakdown and increases the breakdown resistance of the bottom of the source trench structure. Therefore, increasing the thickness of the first material layer and decreasing the thickness of the second material layer, without affecting the source trench structure's forward operation (reducing lateral leakage) and reverse operation (forming a freewheeling path for current to flow from the source to the drain), enhances the shielding effect of the second material layer on the coupling area between the source and drain, further reducing the device's feedback capacitance and source charge, improving the device's switching speed, and reducing the device's power consumption.

[0049] The thickness of the first material layer is 0.02 μm to 0.1 μm, and the thickness of the second material layer is 0.7 μm to 1 μm. The specific thickness is not limited in this application.

[0050] In some alternative implementations, such as Figure 2 and Figure 3As shown, the second dielectric layer 54 includes a fourth material layer 541 and a first gate oxide layer 542 stacked together. The first gate oxide layer 542 is located on the side and bottom surfaces of the first structure that are in contact with the drift layer 20, respectively. The fourth material layer 541 is located above and inside the first gate oxide layer 542. The material of the fourth material layer 541 includes a high-K material.

[0051] Specifically, high-k materials have a high dielectric constant. If the first dielectric layer of the source trench structure uses a high-k material, it can enhance the control of channel charge, improve the control accuracy of the gate voltage over the channel current, and reduce the gate voltage requirement to achieve the same electric field strength. Simultaneously, high-k materials can help distribute the electric field around the trench more uniformly, reducing electric field concentration and thus improving the device's breakdown voltage. However, the interface state density between the high-k material and the drift layer material is relatively large. If the first dielectric layer uses only high-k material, while enhancing the device's breakdown voltage, it will also weaken the carrier mobility in the MOS device, affecting the device's forward conduction characteristics. In the above embodiment, the second dielectric layer contains a first gate oxide layer and a fourth material layer. The fourth material layer is made of a high-k material. A first gate oxide layer exists between the high-k material fourth material layer and the drift layer. The interface state density between the first gate oxide layer and the drift layer is relatively small and does not affect the carrier mobility in the MOS device. Therefore, the high-K material on the inner side forming the fourth material layer can improve the voltage withstand capability of the device, while the first gate oxide layer on the outer side will not affect the carrier mobility in the MOS device, thus improving the voltage withstand performance at the bottom of the source trench structure.

[0052] In some alternative implementations, such as Figures 1 to 5 As shown, the MOS device further includes a shielding region 70, which is located on the side of the source trench structure 50 near the substrate 10. The shielding region 70 has a different doping type from the drift layer 20. The shielding region 70 has a plurality of sub-shielding regions 71 spaced apart along a first direction A.

[0053] Specifically, the electric field concentration at the corners of the source trench structure leads to the breakdown of the second dielectric layer, causing the device to break down below its rated breakdown voltage. This severely impacts the device's forward blocking characteristics and long-term reliability. By implanting a shielding region at the bottom of the source trench structure, the electric field distribution at the bottom of the source trench can be effectively improved, reducing electric field concentration, especially at the corners. This significantly enhances the device's breakdown resistance, allowing it to operate normally at higher voltages without premature breakdown and improving long-term operational reliability. When the MOS device is in reverse bias, the shielding region acts as a freewheeling channel by inducing a ring-shaped inversion layer in the body region, allowing current to flow from the source to the drain under control, thereby avoiding unnecessary leakage current and reducing device power consumption.

[0054] In some specific implementations, the shielding area consists of multiple sub-shielding areas, and the sub-shielding areas are floating, that is, they are not in contact with the source trench structure.

[0055] Specifically, multiple sub-shields help improve device thermal management. Multiple sub-shields act as multiple thermal barriers, reducing heat transfer between the source and drain, decreasing heat buildup in high-frequency, high-current applications, and improving thermal stability. The floating sub-shields are electrically isolated from the source trench structure, reducing electric field concentration in the source trench structure, particularly avoiding high electric field strength at the bottom of the source trench, thus reducing the risk of oxide layer breakdown. Under forward or reverse bias conditions, the floating sub-shields can dynamically sense and control charge distribution, thereby forming a more uniform electric field, reducing charge carrier losses, and lowering device power consumption. If the sub-shields are in contact with the source trench structure, it can lead to additional charge dissipation paths in the forward blocking state, resulting in unnecessary leakage current. Floating sub-shields avoid this, ensuring good charge control in the off state. Even under non-ideal operating conditions (such as extreme temperatures and high-voltage environments), the device exhibits good anti-interference and self-protection capabilities, improving its robustness and adaptability.

[0056] In some optional implementations, there is a first spacing between any two adjacent sub-shielding areas in the first direction, and there are m sub-shielding areas along the first direction, where: m is an even number, and the first spacing between the m / 2th sub-shielding area and the (m / 2)+1th sub-shielding area in the first direction is greater than the remaining first spacing; m is an odd number, and the first spacing between the (m-1) / 2th sub-shielding area and the (m+1) / 2th sub-shielding area in the first direction is greater than the remaining first spacing, and / or the first spacing between the (m+1) / 2th sub-shielding area and the (m+3) / 2nd sub-shielding area is greater than the remaining first spacing.

[0057] In the above embodiments, in the first direction, the first spacing between the middle sub-shielding areas is greater than the first spacing between the sub-shielding areas on both sides. For example, if the first direction has an even number of m sub-shielding areas, where m is 4, then the first spacing between the 2nd and 3rd sub-shielding areas is greater than the first spacing between the 1st and 2nd sub-shielding areas, and simultaneously, the first spacing between the 2nd and 3rd sub-shielding areas is greater than the first spacing between the 3rd and 4th sub-shielding areas. In another example, if the first direction has an odd number of m sub-shielding areas, where m is 5, then the first spacing between the 2nd and 3rd sub-shielding areas is greater than the first spacing between the other sub-shielding areas; or, the first spacing between the 3rd and 4th sub-shielding areas is greater than the first spacing between the other sub-shielding areas; or, the first spacing between the 2nd and 3rd sub-shielding areas is equal to the first spacing between the 3rd and 4th sub-shielding areas and greater than the first spacing between the other sub-shielding areas.

[0058] Specifically, the denser the sub-shielding areas, the better the improvement in electric field distribution. By adjusting the spacing of multiple sub-shielding areas, making the spacing between the sub-shielding areas on both sides smaller than that in the middle, the denser sub-shielding areas on both sides more effectively disperse the electric field intensity at the corner of the source trench structure, reducing electric field concentration. This significantly improves the device's breakdown voltage and enhances its forward blocking characteristics and long-term reliability. Furthermore, a denser sub-shielding area below the corner of the source trench structure helps form a more effective heat dissipation path at the trench edge, facilitating rapid heat dissipation, reducing hot spots, and improving the device's thermal stability. Especially under high current and high-frequency operating conditions, this can significantly improve the device's durability and reliability.

[0059] The doping concentration of the sub-shielding region is greater than that of the drift layer; specifically, the doping concentration of the sub-shielding region is 5.0 × 10⁻⁶. 18 cm -3 ~1.5×10 19 cm -3 The injection depth of the sub-shielded region is 0.9 μm to 1.8 μm, the length of the sub-shielded region along the first direction is 0.3 μm to 0.6 μm, the width of the sub-shielded region along the second direction is 0.3 μm to 0.6 μm, the first spacing between adjacent sub-shielded regions is 0.2 μm to 0.5 μm, and the distance between the sub-shielded region and the bottom surface of the upper source trench structure is 0.2 μm to 1 μm. Those skilled in the art can make appropriate selections based on the performance of the product; this application does not impose specific limitations.

[0060] In some alternative implementations, such as Figures 1 to 5As shown, the MOS device further includes: a first conductive layer 81, which is located at least on the side of the source trench structure 50 away from the substrate and is in contact with the first gate 51, the second gate 52, the first dielectric layer 53 and the second dielectric layer 54 respectively. The first conductive layer 81 is connected to the source region structure 30.

[0061] Specifically, the first conductive layer is the source electrode of the MOS device. The first conductive layer contacts the first gate and the second gate in the source trench structure and forms a connection with the source region. When the MOS device is reverse-biased, the first gate and the second gate, which are in contact with the first conductive layer, induce inversion layers with the body regions in the source structure on both sides, forming a conductive channel from the drift layer to the body region and the first doped region in the source structure, and then back to the first conductive layer. This forms a freewheeling channel for current to flow from the source to the drain, serving a reverse freewheeling function. The current channel is as follows: Figure 4 The arrows shown indicate the direction of current flow. When the MOS device is forward-biased, a freewheeling path is formed in the body region in contact with the gate structure, allowing current to flow from the source to the drain. The current path is as follows: Figure 5 As shown by the arrows, the first conductive layer is connected to a negative potential, and the first and second gates can adjust the electric field of the source trench structure, making the electric field stronger in the vertical direction and weaker in the lateral direction. The charge carriers are confined to move in the vertical direction, reducing lateral leakage.

[0062] Furthermore, the electric field concentration at the corners of the source trench structure leads to breakdown of the thin oxide dielectric layer, causing the device to break down below the rated breakdown voltage. This severely affects the device's forward blocking characteristics and long-term reliability. Implanting a floating sub-shield region at the bottom of the source trench, designed with a small edge spacing and a large center spacing, further reduces the electric field concentration at the bottom of the source trench, enhancing breakdown resistance and improving device reliability. Additionally, employing a trench-split gate structure below the source can shield the coupling area between the source and drain, significantly reducing the device's feedback capacitance and source charge, and improving the device's switching speed.

[0063] In some alternative implementations, such as Figures 1 to 5 As shown, the MOS device further includes a second conductive layer 82, which is located on the side of the substrate 10 away from the drift layer 20, and serves as the drain electrode of the device.

[0064] To reduce the on-resistance of the device, in some embodiments, such as Figures 1 to 5 As shown, an ohmic metal layer 811 is formed between the source region structure 30 and the first conductive layer 81. The ohmic metal layer 811 forms an ohmic contact with the first doped region 32. The ohmic contact has a low on-resistance to reduce the on-resistance of the MOS device. The material of the ohmic metal layer 811 includes materials such as Ni and Ti.

[0065] According to another aspect of this application, a method for fabricating a MOS device is provided, used to fabricate any type of MOS device, such as... Figure 6 As shown, the MOS device comprises multiple cells, and the fabrication method includes:

[0066] Step S101: Provide a substrate;

[0067] Step S102: A drift layer is formed on one side of the substrate, the drift layer having a first surface facing away from the substrate;

[0068] Step S103: Multiple source region structures are formed in the drift layer. The multiple source region structures are spaced apart along the first direction. Two adjacent source region structures have a first side that is close to each other and a second side that is away from each other. The area between two adjacent second side is the drift region. The drift region is a part of the drift layer. The first direction is parallel to the first surface.

[0069] Step S104: A first trench is formed between two adjacent source region structures. The sidewalls of the first trench expose the first sidewall of the source region structure. A source trench structure is formed in the first trench. The source trench structure includes a first gate, a second gate, a first dielectric layer, and a second dielectric layer. The first gate and the second gate are spaced apart along a first direction. The first dielectric layer is located between the first gate and the second gate. The first gate, the second gate, and the first dielectric layer constitute a first structure. The second dielectric layer is located on the sidewall and bottom surface of the first structure and is in contact with the source region structure and the drift layer. The second dielectric layer includes at least a first material layer and a second material layer stacked sequentially in a second direction. The dielectric constant of the material of the first material layer is greater than that of the material of the second material layer. The second direction is the direction from the substrate to the source region structure.

[0070] Step S105: A plurality of gate structures are formed on the side of the drift region away from the substrate, and the gate structures are in contact with the source region structures located on both sides of the drift region respectively.

[0071] Using the fabrication method described in this application, a first trench is formed between the first sides of the two source regions, and a source trench structure is formed in the first trench. The first gate and the second gate in the source trench structure are spaced apart, and a first dielectric layer is placed between the first gate and the second gate, giving the source trench structure a structure similar to a split gate. When the MOS device is in the forward state, the source trench structure and the source structure work together to reduce lateral leakage current. When the MOS device is in the reverse state, the first gate and the second gate, together with the nearby source structure, induce annular inversion layers around the source trench structure, thereby forming a freewheeling channel for current to flow from the source to the drain. However, the source trench structure results in a large coupling area between the source and drain, increasing the feedback capacitance and source charge of the device, and reducing the switching speed. The first dielectric layer between the first gate and the second gate has a first material layer and a second material layer. The dielectric constant of the first material layer is greater than that of the second material layer. The smaller the dielectric constant, the smaller the polarization charge, and the weaker the material's ability to influence the electric field. The second material layer has a smaller dielectric constant, which can shield the coupling area between the source and drain, reducing the feedback capacitance and source charge of the device, increasing the switching speed and reducing the power consumption. The first material layer is located at the bottom of the first dielectric layer, which can protect the second material layer from breakdown, increasing the breakdown resistance of the bottom of the source trench structure, and thus improving the overall performance of the device.

[0072] Exemplary embodiments of the method for fabricating the power device according to this application will now be described in more detail with reference to the accompanying drawings. However, these exemplary embodiments may be implemented in many different forms and should be construed as being limited only to the embodiments set forth herein. It should be understood that these embodiments are provided so that the disclosure of this application is thorough and complete, and that the concept of these exemplary embodiments is fully conveyed to those skilled in the art.

[0073] First, proceed to step S101: as follows Figure 7 As shown in (a), a substrate 10 is provided.

[0074] Specifically, the substrate material includes, but is not limited to, silicon, silicon nitride, silicon carbide, gallium nitride, gallium oxide, aluminum oxide, and aluminum nitride. Those skilled in the art can make reasonable selections according to actual needs, and no specific restrictions are imposed without application.

[0075] After the step of providing the substrate, step S102 is performed; as follows: Figure 7 As shown in (b), a drift layer 20 is formed on the substrate 10.

[0076] Specifically, the drift layer material may include silicon, silicon nitride, silicon carbide, gallium nitride, gallium oxide, aluminum oxide, and aluminum nitride, etc. Those skilled in the art can make a reasonable selection according to actual needs; no specific limitation is imposed. For example, the drift layer material is silicon carbide, to address the issue that SiC diode devices do not show significant performance advantages in certain parameters.

[0077] In some optional embodiments, the process for forming the drift layer includes, but is not limited to, deposition and epitaxial growth processes. In epitaxial growth processes, the doping concentration of impurities is relatively easy to control, and the activation rate is relatively fixed, making it easy to achieve the target doping distribution. This is not only suitable for silicon-based power devices, but also avoids the implantation doping difficulties of silicon carbide power devices, improving the efficiency of their terminal structures. Deposition processes are relatively mature, simple to operate, and have low costs. Deposition processes include, but are not limited to, physical vapor deposition (PVD), chemical vapor deposition (CVD), and atomic layer deposition (ALD). Physical vapor deposition (PVD) includes, but is not limited to, magnetron sputtering, reactive sputtering, DC sputtering, AC sputtering, vacuum deposition, and arc evaporation. Chemical vapor deposition (CVD) includes, but is not limited to, plasma-enhanced chemical vapor deposition (PECVD), metal-organic chemical vapor deposition (MOCVD), and laser-induced chemical vapor deposition (LCVD). Those skilled in the art can make reasonable selections according to actual needs, without applying for or making specific limitations.

[0078] After the step of forming the drift layer, proceed to step S103: as follows Figure 7 As shown in (c), multiple source region structures 30 are formed.

[0079] Specifically, the steps to form the source region structure include: Figure 7 As shown in (c), firstly, a plurality of spaced-apart body regions 31 are formed in the drift layer 20, and the body regions 31 and the drift layer 20 have different doping types; then, a first doped region 32 is formed on the side of any two adjacent body regions 31 that are close to each other, wherein the first doped region 32 and the body region 31 have different doping types, and the doping concentration of the first doped region 32 is greater than the doping concentration of the body region 31.

[0080] The process of forming the bulk region and the first doped region includes ion implantation. Ion implantation allows for precise control of the implanted ion concentration and depth without high-temperature treatment, achieving accurate doping while avoiding damage and deformation of the material structure. Furthermore, the doping concentration in the first doped region must be greater than that in the bulk region, and the depth of the first doped region must be less than that of the bulk region. Ion implantation allows for precise control of the doping concentration and depth in both the first and bulk regions. Additionally, silicon carbide has high carbon-silicon bond energies, making it difficult for impurity atoms to diffuse within the material. Ion implantation involves adding a specific number and type of impurities into a semiconductor material to alter its electrical properties. Ion implantation offers advantages such as low implantation temperature, flexible and precise control of doping distribution, reduced damage from high temperatures to silicon carbide, and improved doping efficiency.

[0081] In some optional embodiments, the above preparation method further includes: such as Figure 7 As shown in (d), a first trench 91 is formed between two adjacent source region structures 30, and the sidewalls of the first trench 91 expose the first side surface of the source region structure 30; then, as Figure 8 As shown, after forming the first trench 91, a shielding region 70 is formed at the bottom of the first trench 91. The shielding region 70 has multiple sub-shielding regions 71, which can effectively improve the electric field distribution at the bottom of the source trench and reduce electric field concentration, especially at corners. This significantly enhances the device's breakdown resistance, allowing the device to operate normally at higher voltages without premature breakdown, and also improves the long-term operational reliability of the device. When the MOS device is in reverse bias, by inducing a ring-shaped inversion layer in the body region, the shielding region can act as a freewheeling channel, allowing current to flow from the source to the drain under control, thereby avoiding unnecessary leakage current and reducing the device's power consumption. The sub-shielding regions are floating, meaning they are not in contact with the source trench structure; the doping type of the sub-shielding regions is different from that of the drift layer, and the doping concentration of the sub-shielding regions is greater than that of the drift layer; the process for forming the sub-shielding regions 71 includes ion implantation.

[0082] Specifically, etching processes include, but are not limited to, dry etching, wet etching, deep etching, ion beam etching (IBE), and electrolytic etching. Dry etching includes physical etching, chemical vapor deposition, and plasma etching, while deep etching includes deep reactive ion etching and laser etching. Those skilled in the art can make reasonable selections according to actual needs, and no specific limitations are imposed without application.

[0083] After the source region structure is formed, step S104 is performed: forming the source trench structure.

[0084] Specifically, the steps to form the source trench structure include: First, as Figure 9 As shown in (a), a second dielectric layer 54 is formed on the sidewall of the first trench 91, and the remaining first trench 91 constitutes the second trench 92; then, as Figure 9 As shown in (b), a gate material region 511 is formed in the second trench 92 using a deposition process; then, as Figure 9 As shown in (c), a third trench 93 is formed by etching in the gate material region 511. The sidewalls of the third trench 93 opposite each other in the first direction expose the gate material regions, and the remaining gate material regions constitute the first gate 51 and the second gate 52, respectively; then, as Figure 9 As shown in (d), a first material layer 531, a second material layer 532, and a third material layer 533 are formed in the third trench 93 using a multiple deposition process. The first material layer 531, the second material layer 532, and the third material layer 533 constitute the first dielectric layer 53. The first gate 51, the second gate 52, the first dielectric layer 53, and the second dielectric layer 54 constitute the source trench structure 50. The dielectric constant of the material of the first material layer 531 is greater than that of the material of the second material layer 532. Specifically, the material of the first material layer 531 includes a high-k material, the material of the second material layer 532 includes a low-k material, and the material of the third material layer 533 includes a waterproof material.

[0085] Specifically, the processes for forming the first gate, the second gate, the first material layer, and the second material layer include, but are not limited to, deposition processes and epitaxial growth processes. The deposition processes include, but are not limited to, physical vapor deposition (PVD), chemical vapor deposition (CVD), and atomic layer deposition (ALD). Physical vapor deposition (PVD) includes, but is not limited to, magnetron sputtering, reactive sputtering, DC sputtering, AC sputtering, vacuum deposition, and arc evaporation. Chemical vapor deposition (CVD) includes, but is not limited to, plasma-enhanced chemical vapor deposition (PECVD), metal-organic chemical vapor deposition (MOCVD), and laser-induced chemical vapor deposition (LCVD). Those skilled in the art can make reasonable selections according to actual needs, and no specific limitations are imposed without application.

[0086] After forming the source trench structure, step S105 is performed: forming the gate structure.

[0087] Specifically, the steps for forming the gate structure include: first, as... Figure 10 As shown in (a), in Figure 9 In the structure shown in (d), a second gate oxide layer 42 is formed on the drift region 202 formed by the drift layer 20 away from the source trench structure 50, and the second gate oxide layer 42 is in contact with the body region 31 and part of the first doped region 32; then, as Figure 10As shown in (b), a third gate 41 is formed on the second gate oxide layer 42, and the second gate oxide layer 42 and the third gate 41 constitute the gate structure 40.

[0088] In some alternative implementations, after forming the gate structure, the method further includes: Figure 10 As shown in (c), firstly, a gate electrode 61 is formed on the third gate 41; then, a gate dielectric layer 62 is formed on the gate electrode 61, the third gate 41 and the sidewall of the gate structure 40.

[0089] In some optional embodiments, the above preparation method further includes: step S106: as Figure 1 As shown, a first conductive layer 81 is formed on a substrate including a source trench structure 50 and a gate structure 40; a second conductive layer 82 is formed on the side of the substrate away from the drift layer.

[0090] In one specific implementation, such as Figure 10 As shown in (d), before forming the first conductive layer 81, an ohmic metal layer 811 is formed. The ohmic metal layer 811 is located on the side of the first doped region 32 away from the substrate 10 and is in contact with the first doped region 32.

[0091] The following will describe in detail, with reference to the embodiments, the MOS device formed by the fabrication method of the MOS device of this application.

[0092] Example

[0093] Provide an N-type silicon carbide substrate 10, such as Figure 7 As shown in (a);

[0094] An N-type silicon carbide drift layer 20 is formed on a silicon carbide substrate 10 using an epitaxial growth process, such as... Figure 7 As shown in (b);

[0095] Multiple spaced P-type bulk regions 31 are formed in the drift layer 20 using an ion implantation process;

[0096] An N-type first doped region 32 is formed in the body region 31 using an ion implantation process. The body region 31 and the first doped region 32 constitute the source region structure 30. Figure 7 As shown in (c);

[0097] An etching process is used to form a first trench 91 between two adjacent source region structures 30. The sidewalls of the first trench 91 expose the first side surface of the source region structure 30, such as... Figure 7 As shown in (d);

[0098] Four P-type sub-shielding regions 71 are formed on the bottom surface of the first trench 91 using an ion implantation process. These four P-type sub-shielding regions 71 constitute a P-type shielding region 70. Figure 8 As shown;

[0099] A silicon oxide layer is formed on the sidewalls and bottom surface of the first trench 91 using a high-temperature thermo-oxidation process to form the second dielectric layer 54. The remaining first trench 91 constitutes the second trench 92, as shown below. Figure 9 As shown in (a);

[0100] An N-type polysilicon region is formed in the second trench 92 using a deposition process to form the gate material region 511, such as... Figure 9 As shown in (b);

[0101] A third trench 93 is formed by etching in the gate material region 511. The two opposite sidewalls of the third trench 93 in the first direction expose polysilicon regions, and the remaining polysilicon regions constitute the first gate 51 and the second gate 52, respectively. Figure 9 As shown in (c);

[0102] An HfO2 layer, a fluorosilicate glass layer, and a Si3N4 layer are deposited within the third trench 93 to form a first material layer 531, a second material layer 532, and a third material layer 533. These three layers constitute the first dielectric layer 53. Figure 9 As shown in (d);

[0103] A silicon oxide layer is deposited on the drift region 202 to form the second gate oxide layer 42, as shown. Figure 10 As shown in (a);

[0104] An N-type polysilicon layer is deposited on the second gate oxide layer 42 to form the third gate 41, as shown below. Figure 10 As shown in (b);

[0105] Copper is deposited on the third gate 41 to form the gate electrode 61, and silicon dioxide is deposited on the gate electrode 61, the third gate 41, and the sidewalls of the gate structure 40 to form the gate dielectric layer 62. Figure 10 As shown in (c);

[0106] A Ni layer is formed on the first doped region 32 to form an ohmic metal layer 811, such as Figure 10 As shown in (d);

[0107] A first conductive layer 81 is formed on a substrate including a source trench structure 50 and a gate structure 40 using a deposition process, and a second conductive layer 82 is deposited on the side of the substrate away from the drift layer, such as... Figure 1 As shown.

[0108] It should also be noted that the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0109] The above are merely embodiments of this application and are not intended to limit the scope of this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of the claims of this application.

Claims

1. A MOS device, characterized in that, The unit cell comprises a plurality of cells, each cell including a substrate and a drift layer located on one side of the substrate, the drift layer having a first surface facing away from the substrate, and the unit cell further comprising: Multiple source region structures are spaced apart along a first direction. Two adjacent source region structures have a first side that is close to each other and two second side that are opposite to each other in the first direction. The area between two adjacent second side is a drift region, which is a part of the drift layer. The first direction is parallel to the first surface. Multiple gate structures are provided, wherein the gate structures are located on the side of the drift region away from the substrate, and the gate structures are respectively in contact with the source region structures located on both sides of the drift region; At least one source trench structure is provided, the source trench structure being located between two adjacent first side surfaces and in contact with the source region structure. The source trench structure includes a first gate, a second gate, a first dielectric layer, and a second dielectric layer. The first gate and the second gate are spaced apart along a first direction. The first dielectric layer is located between the first gate and the second gate. The first gate, the second gate, and the first dielectric layer constitute a first structure. The second dielectric layer is located on the side surface and the bottom surface of the first structure, respectively, and in contact with the source region structure and the drift layer. The first dielectric layer includes at least a first material layer and a second material layer stacked sequentially in a second direction. The dielectric constant of the material of the first material layer is greater than the dielectric constant of the material of the second material layer. The second direction is the direction from the substrate to the source region structure.

2. The MOS device according to claim 1, characterized in that, The first material layer is made of a high-k material, and the second material layer is made of a low-k material.

3. The MOS device according to claim 2, characterized in that, The first dielectric layer further includes a third material layer, which is located on the side of the second material layer opposite to the first material layer, and the material of the third material layer includes an insulating material with waterproof properties.

4. The MOS device according to claim 1, characterized in that, The first material layer has a first thickness in the second direction, and the second material layer has a second thickness in the second direction, wherein the first thickness is less than the second thickness.

5. The MOS device according to claim 1, characterized in that, The second dielectric layer includes a first gate oxide layer and a fourth material layer stacked together. The first gate oxide layer is located on the side and bottom surfaces of the first structure that are in contact with the drift layer. The fourth material layer is located above and inside the first gate oxide layer. The material of the fourth material layer includes a high-k material.

6. The MOS device according to any one of claims 1 to 5, characterized in that, The MOS device further includes: The shielding region is located on the side of the source trench structure near the substrate. The shielding region has a different doping type from the drift layer. The shielding region has a plurality of sub-shielding regions spaced apart along the first direction.

7. The MOS device according to claim 6, characterized in that, There is a first spacing between any two adjacent sub-shielding areas in the first direction, and there are m sub-shielding areas along the first direction, wherein: m is an even number, and the first spacing between the m / 2th sub-shielding area and the (m / 2)+1th sub-shielding area in the first direction is greater than the remaining first spacing; If m is an odd number, the first spacing between the (m-1) / 2th sub-shielding area and the (m+1) / 2th sub-shielding area in the first direction is greater than the remaining first spacings, and / or the first spacing between the (m+1) / 2th sub-shielding area and the (m+3) / 2th sub-shielding area is greater than the remaining first spacings.

8. The MOS device according to claim 1, characterized in that, The MOS device further includes: a first conductive layer, which is located on the side of the source trench structure away from the substrate and is in contact with the first gate, the second gate, the first dielectric layer and the second dielectric layer respectively, and the first conductive layer is connected to the source region structure.

9. A method for fabricating a MOS device, characterized in that, The MOS device includes multiple cells, and the steps for forming the cells include: Provide substrate A drift layer is formed on one side of the substrate, the drift layer having a first surface facing away from the substrate, and the cell further includes: Multiple source region structures are formed in the drift layer, and the multiple source region structures are spaced apart along a first direction. Two adjacent source region structures have a first side that is close to each other and a second side that is away from each other. The area between two adjacent second side is a drift region, and the drift region is a part of the drift layer. The first direction is parallel to the first surface. A first trench is formed between two adjacent source region structures, the sidewalls of the first trench expose the first sidewalls of the source region structures, and a source trench structure is formed in the first trench. The source trench structure includes a first gate, a second gate, a first dielectric layer, and a second dielectric layer. The first gate and the second gate are spaced apart along the first direction. The first dielectric layer is located between the first gate and the second gate. The first gate, the second gate, and the first dielectric layer constitute a first structure. The second dielectric layer is located on the sidewalls and bottomwalls of the first structure and is in contact with the source region structures and the drift layer. The second dielectric layer includes at least a first material layer and a second material layer stacked sequentially in a second direction. The dielectric constant of the material of the first material layer is greater than the dielectric constant of the material of the second material layer. The second direction is the direction from the substrate to the source region structure. Multiple gate structures are formed on the side of the drift region away from the substrate, and the gate structures are in contact with the source region structures located on both sides of the drift region.

10. The preparation method according to claim 9, characterized in that, The steps for forming the source trench structure include: The second dielectric layer is formed on the sidewall of the first trench, and the remaining first trenches constitute the second trench; A gate material region is formed in the second trench using a deposition process; A third trench is etched in the gate material region, and the gate material region is exposed on the opposite sidewalls of the third trench in the first direction. The remaining gate material region constitutes the first gate and the second gate, respectively. The first material layer and the second material layer are formed in the third trench using a multiple deposition process, and the first material layer and the second material layer constitute the first dielectric layer.

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