SiC JEFT device for improving avalanche capability and manufacturing method thereof

Abstract

The invention relates to the technical field of semiconductors, in particular to a SiC JEFT device capable of improving the avalanche capability and a manufacturing method thereof, a source region and a gate region are arranged in a groove at the same time, and the depth of a second type doping region of the source region is different from that of a second type doping region of the gate region; wherein the junction depth of the second-type doped region of the source region is deeper than that of the second-type doped region of the gate region, so that the maximum electric field is located at the junction edge of the second-type doped region of the source region in a turn-off state, an avalanche current enters the source electrode through ohmic contact of the source region and does not pass through the gate electrode any more, and the reliability of avalanche is ensured.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a SiC JEFT device with improved avalanche capability and a manufacturing method thereof. Background Art

[0002] Compared with Si, wide bandgap semiconductor materials SiC and GaN have about 3 times the bandgap width, 10 times the critical breakdown electric field strength, and higher electron mobility. Therefore, SiC and GaN devices have advantages over Si devices such as higher withstand voltage, operating frequency, efficiency, and temperature resistance. Power electronic systems based on wide bandgap semiconductor materials SiC and GaN devices can not only reduce switching losses by more than half, but also make the equipment smaller in size, weight, and comprehensive cost advantages, which is the development direction of the new generation of power electronic systems.

[0003] Compared with the low channel mobility and gate reliability issues caused by the high MOS interface state of SiC MOSFET, there is no MOS gate structure in SiC junction field effect transistor (JFET), so the device is relatively simple and mature. Conventional SiC junction field effect transistor (JFET) is a trench structure, such as Figure 1 As shown. The gate is at the bottom of the trench, and the P+ region at the bottom of the trench is used to deplete the conductive channel, thereby achieving the shutdown of the device. However, in the conventional structure, since the P+ region is only electrically connected to the gate, when the device undergoes avalanche breakdown, the avalanche current directly enters the gate through the P+ region. The gate will pass a very large avalanche current, which will cause great pressure on the gate drive circuit and can easily burn the gate drive circuit directly. Therefore, in ordinary JFET devices, including conventional planar JFET devices and trench JFET devices, the avalanche current passes through the gate, which will damage the gate drive control chip, and the avalanche capability is very weak. The invention of a junction field effect transistor device with high avalanche capability is of great significance to power electronic systems that use junction field effect transistor devices. Summary of the invention

[0004] In view of this, an object of the present invention is to provide a SiC JFET device with improved avalanche capability and a manufacturing method thereof, so as to solve the problem of weak avalanche capability of conventional planar JFET devices and trench JFET devices.

[0005] Based on the above purpose, the present invention provides a SiC JEFT device with improved avalanche capability, comprising a drain, an N+ layer of a first doping type, an N+ buffer layer, an N-drift layer, an N-channel layer, a P+ region of a second doping type, a gate, and a source arranged in sequence from bottom to top, a groove structure is provided on the front side of the device, and a mesa is formed on the upper part of both sides of the groove, and a dielectric layer is provided in the middle of the bottom of the groove, and the two sides and the sidewalls of the bottom of the groove are isolated into two regions, one of which is a second type doping region connected to the source, that is, the second type doping region of the source region, and the other is a second type doping region connected to the gate, that is, the second type doping region of the gate region; On both sides of the bottom of the trench, the depths of the second type doping region of the source region and the second type doping region of the gate region are different, wherein the junction depth of the second type doping region of the source region is deeper than the junction depth of the second type doping region of the gate region, so that in the off state, the maximum electric field is at the junction edge of the second type doping region of the source region.

[0006] Preferably, the width of the dielectric layer in the middle of the trench is greater than the interval between the two second type doping regions at the bottom of the trench, that is, the dielectric layer covers both the second type doping region of the source region and the second type doping region of the gate region.

[0007] Preferably, the top of the mesa is an ohmic contact of the source region, and the ohmic contact of the source region at the top of the mesa is electrically connected to the ohmic contact of the source region at one side of the bottom of the trench.

[0008] Preferably, there is a certain distance between the second type doping region of the source region and the second type doping region of the gate region on both sides of the bottom of the trench, so that the two second type doping regions do not penetrate under the maximum specified gate-source voltage.

[0009] Preferably, a heavily doped first type doped layer is provided on the top of the mesa, overlapping with the dielectric layer on the sidewall of the gate region, that is, the bottom of the heavily doped first type doped layer on the top of the mesa is lower than the highest point of the sidewall dielectric layer, ensuring no short circuit between the gate and the source.

[0010] The present invention also provides a method for manufacturing a SiC JEFT device with improved avalanche capability, comprising the following steps: epitaxially growing a highly doped first doping type buffer layer and a low doped first type drift layer on a highly doped first doping type SiC substrate, wherein the concentration and thickness of the drift layer are determined according to the breakdown voltage of the device design; A highly doped first type doped region is formed by implanting on the surface of the active region, a dielectric mask is formed on the surface, and the SiC surface is etched by a plasma method to form a SiC groove; An ion implantation mask is formed on one side of the trench, and ions of a second type of doping are implanted on the other side, and the second type of doping ions are implanted at the bottom and the sidewall of the trench respectively; Remove all masks, perform RCA cleaning on the wafer, apply a carbon film protective layer on the wafer surface, perform high-temperature annealing to activate the implanted ions, repair the lattice loss caused by the implantation, perform sacrificial oxidation and remove the thin SiC layer on the surface; Thermal oxidation is performed to form a thin surface oxide layer, and a dielectric layer is formed by deposition and etching in the middle of the bottom of the trench; Deposit a dielectric layer, anisotropically etch and remove the dielectric layer on the mesa and the bottom of the trench, and slightly over-etch the SiC to ensure that there is no dielectric on the subsequent ohmic contact area of ​​the source and gate regions; Depositing metal and performing a silicide process to form source ohmic contacts on the mesa and in the trench and gate ohmic contacts in the trench. The source ohmic contacts on the mesa and in the trench are electrically connected in a subsequent metal process and connected to the source electrode pressing block metal, and the gate ohmic contacts are electrically connected to the gate electrode pressing block metal; The dielectric is deposited and etched back to cover the groove and expose the ohmic contact on the table. The source and gate block metals are deposited and etched for electrical connection with external circuits in chip applications. The dielectric layer is then deposited and etched to form a passivation layer, and a polyimide protective layer is further applied.

[0011] The back of the wafer is thinned to remove most of the substrate and retain only part of the supporting layer to further reduce the resistance of the substrate. Metal is deposited and laser annealed to form an ohmic contact, and then a thick block metal is made on the back of the wafer for electrical connection to the external circuit.

[0012] Preferably, the junction depth of the second type doped ions in the source region is greater than the junction depth of the second type doped ions in the gate region, which is achieved by etching a deeper trench in the source region implantation area or by implanting ions in the source region with higher energy.

[0013] Preferably, the width of the intermediate dielectric layer is greater than the spacing between the source region and the second doping type layer of the gate region, that is, one side of the dielectric layer covers the second doping type layer of the gate region, and the other side covers the second doping type layer of the source region.

[0014] Preferably, the heavily doped first type doped layer on the top of the mesa overlaps with the dielectric layer on the sidewall of the gate region to a certain extent, that is, the bottom of the heavily doped first type doped layer on the top of the mesa is lower than the highest point of the sidewall dielectric layer.

[0015] Beneficial effects of the present invention: The SiC JEFT device with improved avalanche capability and the manufacturing method thereof provided by the present invention have different depths of the second type doping region in the source region and the second type doping region in the gate region, wherein the junction depth of the second type doping region in the source region is deeper than the junction depth of the second type doping region in the gate region, so that in the off state, the maximum electric field is at the junction edge of the second type doping region in the source region, so that the avalanche current enters the source through the ohmic contact of the source region and does not pass through the gate again, thereby ensuring the reliability of the avalanche; By making the bottom of the heavily doped first type doped layer on the top of the mesa lower than the highest point of the sidewall dielectric layer, a short circuit between the gate and the source can be effectively avoided. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In order to more clearly illustrate the technical solutions in the present invention or the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings in the following description are only for the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0017] Figure 1 A schematic diagram of a trench structure of a conventional SiC junction field effect transistor (JFET) in the prior art; Figure 2 Schematic diagram of the structure of a SiC JEFT device with improved avalanche capability according to the present invention Figure 3 Schematic diagram of another SiC JEFT device structure with improved avalanche capability according to the present invention Figure 4 Schematic diagram of sequentially producing a buffer layer and an epitaxial layer structure on a substrate in Example 1 of the present invention Figure 5 Schematic diagram after trench etching in Example 1 of the present invention Figure 6 Schematic diagram of completing the first and second doping type ion doping in embodiment 1 of the present invention Figure 7 Schematic diagram of completing the trench sidewall protection dielectric layer in embodiment 1 of the present invention Figure 8 Schematic diagram of completing ohmic contact between source and gate regions and trench dielectric filling in embodiment 1 of the present invention Fig. 9 Schematic diagram of the structure after chip manufacturing is completed in Example 1 of the present invention Fig.10 Schematic diagram after trench etching is completed in Example 2 of the present invention Fig.11 Schematic diagram of completing the first and second doping type ion doping in embodiment 2 of the present invention Fig.12 A schematic diagram of the structure after chip manufacturing is completed in Example 2 of the present invention. DETAILED DESCRIPTION

[0018] In order to make the objectives, technical solutions and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with specific embodiments.

[0019] It should be noted that, unless otherwise defined, the technical terms or scientific terms used in the present invention should be understood by people with ordinary skills in the field to which the present invention belongs. The "first", "second" and similar words used in the present invention do not indicate any order, quantity or importance, but are only used to distinguish different components. "Include" or "comprise" and similar words mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. "Connect" or "connected" and similar words are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0020] The embodiments of this specification provide a SiC JEFT device with improved avalanche capability, the device structure is as follows Figure 2 and Figure 3 As shown, from bottom to top, there are drain, N+ layer of first doping type, N+ buffer layer, N- drift layer, N channel layer, P+ region of second doping type, gate, and source. There is a trench structure on the front of the device, and the bottom, both sides and sidewalls of the trench are second type doping regions, which are connected to the source and gate. The middle of the bottom of the trench is a dielectric layer, isolating the source and gate regions on both sides of the trench.

[0021] Furthermore, the doping depths of the second type doped regions in the source region and the gate region on both sides of the bottom of the trench are different, wherein the junction depth of the second type doped region connected to the source region is deeper than the junction depth of the second type doped region connected to the gate region, so that in the off state the maximum electric field is at the junction edge of the second type doped region connected to the source region.

[0022] Furthermore, the doping depth of the source region at the bottom of the trench is deeper than the doping junction depth of the gate region. One method is to use higher ion implantation energy when doping the source region, so that after ion implantation doping of the source region and the gate region at the bottom of the trench, the junction depth of the source region is deeper.

[0023] Furthermore, the doping depth of the source region at the bottom of the trench is deeper than the doping junction depth of the gate region. One method is to make the trench depth of the source region deeper so that after ion implantation doping is performed on the source region and the gate region at the bottom of the trench, the junction depth of the source region is deeper.

[0024] Furthermore, the width of the isolation medium in the middle of the trench is greater than the spacing between the second type doping regions of the source region and the gate region at the bottom of the trench, that is, the isolation medium simultaneously covers part of the second type doping region of the source region and the second type doping region of the gate region, ensuring that the ohmic contacts at the bottom are all within the second type doping region.

[0025] Furthermore, the top of the mesa is also an ohmic contact of the source region, and the ohmic contact of the source region at the top of the mesa is electrically connected with the ohmic contact of the source region at one side of the bottom of the trench.

[0026] Furthermore, the ohmic contact of the gate region at one side of the bottom of the trench and the second type of doped region are isolated from the source region, that is, they are not electrically connected. The gate ohmic contact region is isolated from the source region at the top by the dielectric in the trench.

[0027] Furthermore, there is a certain distance between the second type doped regions connected to the source region and the gate region on both sides of the bottom of the trench, and it is required that there is no punch-through between the two doped regions under the maximum specified gate-source voltage, ensuring that the breakdown voltage between the gate and the source meets the requirements of product design.

[0028] Furthermore, there is a certain thickness of heavily doped first type doped layer on the top of the mesa, which has a certain overlap with the dielectric layer on the side wall of the gate area, that is, the bottom of the heavily doped first type doped layer on the top of the mesa is lower than the highest point of the side wall dielectric layer, which can effectively avoid short circuit between the gate and the source.

[0029] Furthermore, the junction depth of the second doping type doping region in the source region at the bottom of the trench is greater than the junction depth of the second type doping region in the gate region. This is achieved by making the ion implantation energy in the source region greater than the energy implanted in the gate region. The depths of the bottom of the source and gate trenches can be the same or different.

[0030] Furthermore, the junction depth of the second doping type doping region in the source region at the bottom of the trench is greater than the junction depth of the second type doping region in the gate region. This is achieved by making the trench depth in the source region greater than the trench depth in the gate region. The ion implantation energies at the bottom of the trench in the source region and the gate region can be the same or different.

[0031] The first type and the second type described in the present invention are interchangeable. Specific embodiment 1:

[0033] A SiC JEFT device with improved avalanche capability and a method for manufacturing the same, comprising: A highly doped first doping type buffer layer 101 and a low doped first type drift layer 102 are epitaxially grown on a highly doped first doping type SiC substrate 100, such as Figure 4 The concentration and thickness of the drift layer are determined according to the breakdown voltage of the device design.

[0034] Further, a highly doped first type doped region 103 is formed by implantation on the surface of the active region. The first type doping ions are then implanted on the surface to increase the doping concentration of the channel region 102a, thereby reducing the resistance of the channel. A SiC etching mask is formed by depositing and etching a dielectric layer on the surface. The dielectric mask can be one or more layers of SiO2, SiN, polysilicon, etc. The thickness of the dielectric mask requires that the remaining mask thickness after etching the SiC trench can still block subsequent ion implantation.

[0035] The SiC surface is etched by plasma method to form SiC groove 20, such as Figure 5 As shown. The trench depth can generally be about 0.5 microns to 3 microns, and the trench spacing can generally be about 0.5 microns to 3 microns. It can form channel depletion pinch-off under gate control very well, and the trench will not be too deep to increase the channel resistance.

[0036] Further, a filling dielectric layer is deposited in the trench, and the dielectric layer of the gate region on the left side of the trench is etched away, and the dielectric layer on the right side of the trench is retained as an ion implantation mask, and ions are implanted at the bottom and the sidewall of the trench to form a second type of doped region 104. The second type of ion implantation in the gate region is completed. The ion implantation concentration at the bottom surface is relatively high, for example, greater than 1E18cm-3, which is conducive to forming an ohmic contact.

[0037] Further, the mask is removed. A filling dielectric layer is deposited in the trench again, and the dielectric layer in the source region on the right side of the trench is removed by etching, and the dielectric layer on the left side of the trench is retained as an ion implantation mask, and ions are implanted at the bottom and the sidewall of the trench to form a second type of doped region 105. The second type of ion implantation in the source region is completed. The ion implantation concentration at the bottom surface is relatively high, for example, greater than 1E18cm-3, which is conducive to the formation of ohmic contact.

[0038] The effect is the same whether the left or right side of the trench is selected as the gate region or the source region.

[0039] The junction depth of the second type of doped ions in the source region is greater than the junction depth of the second type of doped ions in the gate region. This can be achieved by injecting higher energy into the source region ions. In Embodiment 2 of the present invention, this is achieved by making the trench depth in the source region deeper than that in the gate region. In this way, as shown in the figure, the maximum electric field will appear between A or B in the source region, and the breakdown will first occur at point A or B. The avalanche current enters the source through the ohmic contact in the source region, and will no longer pass through the gate, thereby ensuring the reliability of the avalanche.

[0040] Further, all masks are removed and the wafer is cleaned by RCA. A carbon film protective layer is applied on the wafer surface and high temperature annealing is performed to activate the implanted ions and repair the lattice loss caused by the implantation. Sacrificial oxidation is performed to remove the thin SiC layer on the surface and improve the quality of the SiC surface.

[0041] Further, thermal oxidation is performed to form a thin surface oxide layer. Preferably, annealing is performed in a NO or N2O atmosphere after thermal oxidation to improve the quality of the dielectric layer. The dielectric layer is deposited and etched, and the dielectric layer 200 is retained in the middle of the bottom of the trench, such as Figure 6 As shown, the dielectric layer can be SiO2 or SiN, or a multi-layer composite. Preferably, the height of the dielectric layer is close to the height of the table, which is conducive to the subsequent trench filling and planarization process. At the same time, the width of the intermediate dielectric layer 200 plus the subsequent sidewall dielectrics 201a and 201b is greater than the spacing between the source region and the second doping type layer of the gate region. That is, one side of the dielectric layer covers the second doping type layer 104 of the gate region, and the other side covers the second doping type layer 105 of the source region.

[0042] Further, a dielectric layer is deposited, and the dielectric layer on the terrace and the bottom of the trench is removed by anisotropic etching, and the dielectric layer 201a of the gate region of the trench sidewall and the dielectric layer 201b of the source region are retained, as shown in FIG. Figure 7 As shown. The height of dielectric layers 201a and 201b is higher than the bottom of the first doping type layer 103. And slightly over-etch SiC to ensure that there is no dielectric on the subsequent ohmic contact area of ​​the source region and the gate region. The dielectric layer can be SiO2, etc. Metal is deposited, and a silicide process is performed to form a source ohmic contact 301 on the table, a source ohmic contact 302 in the groove, and a gate ohmic contact 303 in the groove. The source ohmic on the table and in the groove are electrically connected in the subsequent metal process.

[0043] Deposit dielectric and etch back, so that dielectric 202 covers the groove and exposes the ohmic contact on the mesa, such as Figure 8 The deposited and etched source and gate block metal 401 is used for electrical connection with external circuits in chip applications, and then the dielectric layer is deposited and etched to form a passivation. The block metal can be Al, AlCu, AlSiCu or NiAu, TiNiAg, etc. The passivation medium is preferably SiO2, SiN, SiON or a composite of several layers. Then a polyimide protective layer is applied.

[0044] Further, the back of the wafer is thinned to remove most of the substrate and only retain part of the support layer, further reducing the resistance of the substrate. Metal is deposited and laser annealed to form an ohmic contact. A thick block metal 402 is then made on the back of the wafer for electrical connection with the external circuit. The back metal can be NiPbAu or TiNiAg, etc. Fig. 9 .

[0045] The first doping type ions may be N+, P+, etc., and the second doping type ions may be Al+, B+, etc. Specific embodiment 2:

[0047] A SiC JEFT device with improved avalanche capability and a manufacturing method thereof. The other preparation methods are similar to those of Example 1. The difference from Example 1 is that two etching methods are used when etching the groove 20, so that the groove 20a of the source region is deeper than the left side 20b, such as Fig.10 In this way, even if the same energy ions are implanted in the source and gate regions in the trench, the junction depth of the doped region in the source region will still be deeper than that in the gate region. Fig.11 . Ensure that the maximum electric field is still at the edge A or B of the second type doping region in the source region, ensuring the avalanche capability. The final device structure diagram is shown in Fig.12 shown.

[0048] Those skilled in the art should understand that the discussion of any of the above embodiments is only exemplary and is not intended to imply that the scope of the present invention is limited to these examples; under the concept of the present invention, the technical features in the above embodiments or different embodiments can also be combined, the steps can be implemented in any order, and there are many other changes in different aspects of the present invention as described above, which are not provided in detail for the sake of simplicity. Any omissions, modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. A SiC JEFT device with improved avalanche capability, characterized in that: The device comprises a drain, an N+ layer of a first doping type, an N+ buffer layer, an N-drift layer, an N-channel layer, a P+ region of a second doping type, a gate, and a source arranged in sequence from bottom to top. A groove structure is provided on the front of the device, and a table is formed on the upper part of both sides of the groove. A dielectric layer is provided in the middle of the bottom of the groove, and the two sides and the sidewalls of the bottom of the groove are isolated into two regions, one of which is a second type doping region connected to the source, that is, a second type doping region of the source region, and the other is a second type doping region connected to the gate, that is, a second type doping region of the gate region; On both sides of the bottom of the trench, the depths of the second type doping region of the source region and the second type doping region of the gate region are different, wherein the junction depth of the second type doping region of the source region is deeper than the junction depth of the second type doping region of the gate region, so that in the off state, the maximum electric field is at the junction edge of the second type doping region of the source region.

2. The SiC JEFT device with improved avalanche capability according to claim 1, characterized in that: The width of the dielectric layer in the middle of the trench is greater than the interval between the two second type doping regions at the bottom of the trench, that is, the dielectric layer covers both the second type doping region of the source region and the second type doping region of the gate region.

3. The SiC JEFT device with improved avalanche capability according to claim 1, characterized in that: The top of the mesa is an ohmic contact of the source region, and the ohmic contact of the source region at the top of the mesa is electrically connected with the ohmic contact of the source region at one side of the bottom of the trench.

4. The SiC JEFT device with improved avalanche capability according to claim 1, characterized in that: There is a certain distance between the second type doping region of the source region and the second type doping region of the gate region on both sides of the bottom of the trench, so that the two second type doping regions do not penetrate under the maximum specified gate-source voltage.

5. The SiC JEFT device with improved avalanche capability according to claim 1, characterized in that: A heavily doped first type doping layer is provided on the top of the mesa, overlapping with the dielectric layer on the sidewall of the gate region, that is, the bottom of the heavily doped first type doping layer on the top of the mesa is lower than the highest point of the sidewall dielectric layer.

6. A method for manufacturing a SiC JEFT device with improved avalanche capability, characterized in that: The following steps are involved: epitaxially growing a highly doped first doping type buffer layer and a low doped first type drift layer on a highly doped first doping type SiC substrate, wherein the concentration and thickness of the drift layer are determined according to the breakdown voltage of the device design; A highly doped first type doped region is formed by implanting on the surface of the active region, a dielectric mask is formed on the surface, and the SiC surface is etched by a plasma method to form a SiC groove; An ion implantation mask is formed on one side of the trench, and ions of a second type of doping are implanted on the other side, and the second type of doping ions are implanted at the bottom and the sidewall of the trench respectively; Remove all masks, perform RCA cleaning on the wafer, apply a carbon film protective layer on the wafer surface, perform high-temperature annealing to activate the implanted ions, repair the lattice loss caused by the implantation, perform sacrificial oxidation and remove the thin SiC layer on the surface; Thermal oxidation is performed to form a thin surface oxide layer, and a dielectric layer is formed by deposition and etching in the middle of the bottom of the trench; Deposit a dielectric layer, anisotropically etch and remove the dielectric layer on the mesa and the bottom of the trench, and slightly over-etch the SiC to ensure that there is no dielectric on the subsequent ohmic contact area of ​​the source and gate regions; Depositing metal and performing a silicide process to form source ohmic contacts on the mesa and in the trench and gate ohmic contacts in the trench. The source ohmic contacts on the mesa and in the trench are electrically connected in a subsequent metal process and connected to the source electrode pressing block metal, and the gate ohmic contacts are electrically connected to the gate electrode pressing block metal; Deposit dielectric and etch back to cover the groove and expose the ohmic contact on the table. Deposit and etch the source and gate block metal for electrical connection with external circuits in chip applications. Then deposit and etch the dielectric layer to form passivation, and further apply a polyimide protective layer. The back of the wafer is thinned to remove most of the substrate and retain only part of the supporting layer to further reduce the resistance of the substrate. Metal is deposited and laser annealed to form an ohmic contact, and then a thick block metal is made on the back of the wafer for electrical connection to the external circuit.

7. The method for manufacturing a SiC JEFT device with improved avalanche capability according to claim 6, characterized in that: The junction depth of the second type doped ions in the source region is greater than the junction depth of the second type doped ions in the gate region, which is achieved by etching a deeper trench in the source region implantation area or by implanting ions in the source region with higher energy.

8. The method for manufacturing a SiC JEF device with improved avalanche capability according to claim 6, characterized in that: The width of the intermediate dielectric layer is greater than the interval between the source region and the second doping type layer of the gate region, that is, one side of the dielectric layer covers the second doping type layer of the gate region, and the other side covers the second doping type layer of the source region.

9. The method for manufacturing a SiC JEFT device with improved avalanche capability according to claim 6, characterized in that: The heavily doped first type doped layer on the top of the mesa overlaps with the dielectric layer on the sidewall of the gate region to a certain extent, that is, the bottom of the heavily doped first type doped layer on the top of the mesa is lower than the highest point of the sidewall dielectric layer, ensuring that there is no short circuit between the gate and the source.

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