Terminal structure of semiconductor device, preparation method thereof and semiconductor device

Abstract

The invention provides a terminal structure of a semiconductor device, a preparation method thereof and the semiconductor device. The terminal structure comprises a substrate; the epitaxial layer is positioned on one side of the substrate; the field oxide layer is at least located on the partial surface, away from the substrate, of the epitaxial layer; the interlayer dielectric layer is located on the surface, far away from the substrate, of the field oxide layer, the partial side wall of the field oxide layer and the partial surface, far away from the substrate, of the epitaxial layer; the at least one first groove is arranged in the interlayer dielectric layer which is not covered with the field oxide layer along a first direction, the first groove penetrates into the epitaxial layer, and the first direction is the thickness direction of the substrate; and the passivation layer is at least located in the first groove and on the surface, away from the substrate, of the interlayer dielectric layer. The problem that in the prior art, the service life of a planar silicon carbide MOSFET power chip is affected due to water vapor permeation caused by the difference of thermal expansion coefficients of different dielectric layers in a high-temperature and high-humidity environment is solved.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a terminal structure of a semiconductor device, a preparation method thereof, and a semiconductor device. Background Art

[0002] In the field of semiconductor manufacturing technology, silicon carbide (SiC) MOSFET (Metal-Oxide-SemiconductorField-Effect Transistor) power chips are widely used in power electronic devices due to their superior electrical properties, such as high breakdown voltage, low switching loss and high temperature working ability. At the same time, in the field of materials science, SiC, as a wide-bandgap semiconductor material, has higher thermal stability and better electrical conductivity than traditional silicon, making it an ideal choice for high power density and high efficiency power electronic applications. In addition, in the field of electronic equipment, the service life and reliability of SiC MOSFET power chips directly affect the performance and stability of the entire system.

[0003] Silicon carbide (SiC) MOSFET power chips can be divided into planar MOSFET and trench MOSFET according to different cell structures. Due to the advantages of low process difficulty and mature structural design of planar terminal structure, the terminal structure of silicon carbide MOSFET power chips is still mainly planar terminal structure. The main application areas of silicon carbide (SiC) MOSFET power chips are new energy vehicles, energy storage, wind power, photovoltaics, etc. These high-voltage and high-power components also require components to meet the requirements of stable operation under harsh conditions. The existing planar terminals cannot operate for a long time under high temperature difference and high water vapor working conditions. The thermal expansion coefficients of different dielectric layers in the planar terminal structure are different under high temperature difference, which may lead to water vapor penetration channels between layers. In comparison, the trench-type power chip terminal structure can effectively suppress this problem and enhance the service life of the device.

[0004] The terminal structure of the prior art adopts a planar junction terminal. The contact surfaces of the field oxide layer, the passivation layer, and the polyimide layer with the silicon carbide epitaxial layer are all at the same level. The existing structure takes into account the electrical isolation and water vapor resistance capabilities of the passivation layer / polyimide material itself. Therefore, in order to improve the life of the device, most silicon carbide power chip manufacturers will increase the thickness of the passivation layer / polyimide as much as possible. In the design of the junction terminal, the problem of cracks between different materials caused by the large temperature difference faced by the planar junction terminal is often ignored. The generation of cracks provides a path for water vapor to enter the interior of the chip, thereby causing the chip to fail during its service life.

[0005] The above information disclosed in the background technology section is only used to enhance the understanding of the background technology of the technology described in this article. Therefore, the background technology may contain certain information that does not form the prior art known in this country for those skilled in the art. Summary of the invention

[0006] The main purpose of the present application is to provide a terminal structure of a semiconductor device, a preparation method thereof and a semiconductor device, so as to solve the problem in the prior art that the planar silicon carbide MOSFET power chip is affected by water vapor penetration due to differences in thermal expansion coefficients of different dielectric layers in a high temperature and high humidity environment, thereby affecting the chip life.

[0007] In order to achieve the above-mentioned purpose, according to one aspect of the present application, a terminal structure of a semiconductor device is provided, comprising: a substrate; an epitaxial layer, located on one side of the substrate; a field oxide layer, located at least on a portion of the surface of the epitaxial layer away from the substrate; an interlayer dielectric layer, located on a surface of the field oxide layer away from the substrate, on a portion of the sidewall of the field oxide layer, and on a portion of the surface of the epitaxial layer away from the substrate; at least one first groove, arranged along a first direction in the interlayer dielectric layer not covering the field oxide layer, and the first groove penetrates into the epitaxial layer, the first direction being the thickness direction of the substrate; a passivation layer, located at least in the first groove and on a surface of the interlayer dielectric layer away from the substrate.

[0008] Optionally, the terminal structure also includes: a second groove, which is arranged along the first direction outside the interlayer dielectric layer, and the second groove penetrates into the epitaxial layer; the second groove has a first side wall and a second side wall relative to each other, the first side wall is in contact with the interlayer dielectric layer, and the second side wall is not in contact with the interlayer dielectric layer, and the passivation layer is located in the first groove, in the second groove, and on the surface of the interlayer dielectric layer away from the substrate.

[0009] Optionally, the terminal structure also includes: a third trench, which is arranged along the first direction outside the passivation layer and the third trench penetrates into the epitaxial layer; the third trench has opposite third side walls and fourth side walls, the third side wall is in contact with the passivation layer, and the fourth side wall is not in contact with the passivation layer; an insulating layer is located in the third trench, on the surface of the passivation layer away from the substrate, and on part of the side walls of the passivation layer.

[0010] Optionally, along the first direction, the distance between the bottom surface of the first trench and the surface of the epitaxial layer close to the substrate is a first depth, the distance between the bottom surface of the third trench and the surface of the epitaxial layer close to the substrate is a third depth, and the first depth is smaller than the third depth.

[0011] Optionally, along the first direction, the distance between the bottom surface of the first trench and the surface of the epitaxial layer close to the substrate is a first depth, the distance between the bottom surface of the second trench and the surface of the epitaxial layer close to the substrate is a second depth, and the first depth is equal to the second depth.

[0012] Optionally, there are a plurality of the first trenches, and the plurality of the first trenches are spaced apart in the second direction, all of the first trenches are located between the field oxide layer and the second trench, and the second direction is perpendicular to the first direction.

[0013] Optionally, the terminal structure also includes: a plurality of field limiting rings spaced apart in a predetermined direction, located in the epitaxial layer, the field oxide layer located on surfaces of the plurality of field limiting rings away from the substrate and on a portion of the surface of the epitaxial layer away from the substrate, the doping type of the field limiting rings is different from that of the epitaxial layer, and the predetermined direction is a direction perpendicular to the thickness of the substrate; and a back metal layer located on the surface of the substrate away from the epitaxial layer.

[0014] According to another aspect of the present application, a method for preparing a terminal structure of any one of the semiconductor devices is provided, comprising: providing a substrate; forming a preliminary epitaxial layer on one side of the substrate; forming a field oxide layer at least on a portion of the surface of the preliminary epitaxial layer away from the substrate; forming a preliminary interlayer dielectric layer on a surface of the field oxide layer away from the substrate, on a portion of the sidewalls of the field oxide layer, and on a portion of the surface of the preliminary epitaxial layer away from the substrate; removing a portion of the preliminary epitaxial layer and the preliminary interlayer dielectric layer to form at least one first groove, the remaining preliminary epitaxial layer forms an epitaxial layer, the remaining preliminary interlayer dielectric layer forms an interlayer dielectric layer, the first groove is arranged along the first direction in the preliminary interlayer dielectric layer not covering the field oxide layer, and the first groove penetrates into the preliminary epitaxial layer, the first direction is the substrate thickness direction; forming a passivation layer at least in the first groove and on a surface of the interlayer dielectric layer away from the substrate.

[0015] Optionally, part of the prepared epitaxial layer and the prepared interlayer dielectric layer is removed to form at least one first groove, including: removing part of the prepared epitaxial layer and the prepared interlayer dielectric layer to form a second groove and at least one first groove, the second groove is arranged along the first direction outside the prepared interlayer dielectric layer, and the second groove penetrates into the prepared epitaxial layer, the second groove has a first side wall and a second side wall relative to each other, the first side wall is in contact with the prepared interlayer dielectric layer, and the second side wall is not in contact with the prepared interlayer dielectric layer, and a passivation layer is formed at least in the first groove and on the surface of the interlayer dielectric layer away from the substrate, including: forming the passivation layer in the first groove, in the second groove, and on the surface of the interlayer dielectric layer away from the substrate.

[0016] Optionally, removing part of the prepared epitaxial layer and the prepared interlayer dielectric layer to form at least one first groove includes: removing part of the prepared epitaxial layer and the prepared interlayer dielectric layer to form at least one first groove and a third groove, the third groove is arranged outside the passivation layer along the first direction, and the third groove penetrates into the prepared epitaxial layer; the third groove has relative third side walls and fourth side walls, the third side walls are in contact with the passivation layer, and the fourth side walls are not in contact with the passivation layer, after forming a passivation layer at least in the first groove and on the surface of the interlayer dielectric layer away from the substrate, the method further includes: forming an insulating layer in the third groove, on the surface of the passivation layer away from the substrate, and on part of the side walls of the passivation layer.

[0017] According to another aspect of the present application, a semiconductor device is provided, comprising any one of the terminal structures of the semiconductor device, or a terminal structure of the semiconductor device prepared by any one of the methods for preparing the terminal structure of the semiconductor device.

[0018] By applying the technical solution of the present application, the terminal structure of the semiconductor device includes a substrate, an epitaxial layer located on one side of the substrate, a field oxide layer, an interlayer dielectric layer, at least one first trench and a passivation layer, wherein the field oxide layer is located at least on a portion of the surface of the epitaxial layer away from the substrate, the interlayer dielectric layer is located on a surface of the field oxide layer away from the substrate, on a portion of the sidewall of the field oxide layer and on a portion of the surface of the epitaxial layer away from the substrate, the first trench is arranged along a first direction in the interlayer dielectric layer not covered by the field oxide layer, and the first trench penetrates into the epitaxial layer, and the passivation layer is located at least in the first trench and on a surface of the interlayer dielectric layer away from the substrate. Compared with the problem in the prior art that planar silicon carbide MOSFET power chips in a high temperature and high humidity environment are affected by water vapor penetration due to differences in thermal expansion coefficients of different dielectric layers, the passivation layer of the present application is at least located in the first groove and on the surface of the interlayer dielectric layer away from the substrate, the first groove is arranged along the first direction in the interlayer dielectric layer not covered by the field oxide layer, and the first groove penetrates into the epitaxial layer, so that the contact area between the passivation layer and the epitaxial layer is increased, and the length of the path for water vapor to enter the chip from the external environment is increased, which effectively blocks water vapor from penetrating into the chip through tiny cracks or gaps on the surface, thereby improving the reliability and service life of the chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] The drawings constituting part of the present application are used to provide a further understanding of the present application. The exemplary embodiments and descriptions of the present application are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:

[0020] Figure 1 A schematic cross-sectional structure diagram of a terminal structure of a semiconductor device provided according to an embodiment of the present application is shown;

[0021] Figure 2 A schematic flow chart of a method for preparing a terminal structure of a semiconductor device provided according to an embodiment of the present application is shown.

[0022] The above drawings include the following reference numerals:

[0023] 10. Substrate; 11. Epitaxial layer; 12. Interlayer dielectric layer; 13. First trench; 14. Passivation layer; 15. Field oxide layer; 16. Second trench; 17. Third trench; 18. Insulating layer; 19. Field limiting ring; 20. Back metal layer. DETAILED DESCRIPTION

[0024] It should be noted that the following detailed descriptions are illustrative and are intended to provide further explanation of the present application. Unless otherwise specified, all technical and scientific terms used herein have the same meanings as those commonly understood by those skilled in the art to which the present application belongs.

[0025] It should be noted that the terms used herein are only for describing specific embodiments and are not intended to limit the exemplary embodiments according to the present application. As used herein, unless the context clearly indicates otherwise, the singular form is also intended to include the plural form. In addition, it should be understood that when the terms "comprise" and / or "include" are used in this specification, it indicates the presence of features, steps, operations, devices, components and / or combinations thereof.

[0026] It should be understood that when an element (such as a layer, film, region, or substrate) is described as being "on" another element, the element may be directly on the other element, or there may be intermediate elements. Moreover, in the specification and claims, when an element is described as being "connected" to another element, the element may be "directly connected" to the other element, or "connected" to the other element through a third element.

[0027] As introduced in the background technology, in the prior art, planar silicon carbide MOSFET power chips are subject to water vapor penetration due to differences in thermal expansion coefficients of different dielectric layers in a high temperature and high humidity environment, which affects the chip life. To solve the above problems, the embodiments of the present application provide a terminal structure of a semiconductor device, a preparation method thereof, and a semiconductor device.

[0028] The technical solutions in the embodiments of the present invention will be described clearly and completely below in conjunction with the accompanying drawings in the embodiments of the present invention.

[0029] The present application embodiment provides a terminal structure of a semiconductor device, such as Figure 1 As shown, including:

[0030] Substrate 10;

[0031] The epitaxial layer 11 is located on one side of the substrate 10;

[0032] A field oxide layer 15, at least located on a surface of the epitaxial layer 11 that is away from the substrate 10;

[0033] An interlayer dielectric layer 12 is located on a surface of the field oxide layer 15 away from the substrate 10, on a portion of the sidewall of the field oxide layer 15, and on a portion of the surface of the epitaxial layer 11 away from the substrate 10;

[0034] At least one first trench 13 is disposed in the interlayer dielectric layer 12 not covered with the field oxide layer 15 along a first direction, and the first trench 13 penetrates into the epitaxial layer 11, and the first direction is the thickness direction of the substrate 10;

[0035] The passivation layer 14 is at least located in the first trench 13 and on the surface of the interlayer dielectric layer 12 away from the substrate 10 .

[0036] Through this embodiment, the terminal structure of the semiconductor device includes a substrate, an epitaxial layer located on one side of the substrate, a field oxide layer, an interlayer dielectric layer, at least one first trench and a passivation layer, wherein the field oxide layer is at least located on a portion of the surface of the epitaxial layer away from the substrate, the interlayer dielectric layer is located on the surface of the field oxide layer away from the substrate, on a portion of the side wall of the field oxide layer and on a portion of the surface of the epitaxial layer away from the substrate, the first trench is arranged along a first direction in the interlayer dielectric layer not covered by the field oxide layer, and the first trench penetrates into the epitaxial layer, and the passivation layer is at least located in the first trench and on the surface of the interlayer dielectric layer away from the substrate. Compared with the problem in the prior art that planar silicon carbide MOSFET power chips in a high temperature and high humidity environment are affected by water vapor penetration due to differences in thermal expansion coefficients of different dielectric layers, the passivation layer of the present application is at least located in the first groove and on the surface of the interlayer dielectric layer away from the substrate, the first groove is arranged along the first direction in the interlayer dielectric layer not covered by the field oxide layer, and the first groove penetrates into the epitaxial layer, so that the contact area between the passivation layer and the epitaxial layer is increased, and the length of the path for water vapor to enter the chip from the external environment is increased, which effectively blocks water vapor from penetrating into the chip through tiny cracks or gaps on the surface, thereby improving the reliability and service life of the chip.

[0037] In addition, the present application adds a longitudinal shallow groove structure (ie, a first groove) to the planar power chip terminal structure. The shallow groove suppresses the interface stress of different materials under high temperature difference and reduces the generation of micro cracks inside the terminal.

[0038] In the present application embodiment, Figure 1 As shown, there is one first groove 13 .

[0039] Specifically, the terminal structure of the prior art adopts a planar junction terminal, and the contact surfaces of the field oxide layer, the passivation layer, and the polyimide layer with the silicon carbide epitaxial layer are all at the same horizontal plane. The existing structure takes into account more the electrical isolation and water vapor resistance capabilities of the passivation layer / polyimide material itself. Therefore, in order to improve the life of the device, most silicon carbide power chip manufacturers will increase the thickness of the passivation layer / polyimide as much as possible. In the design of the junction terminal, the problem of cracks between different materials caused by the large temperature difference faced by the planar junction terminal is often ignored, and the generation of cracks provides a path for water vapor to enter the interior of the chip, thereby causing the chip to fail within its service life. Based on this, the first groove of the present application is located in the interlayer dielectric layer and the epitaxial layer, and the passivation layer is located in the first groove. The passivation layer acts as a screw, which can inhibit the movement of the interlayer dielectric layer and the passivation layer under high temperature and high humidity environments, and reduce the probability of small cracks or gaps on the surface of the terminal structure, thereby reducing the probability of water vapor penetrating into the chip through small cracks or gaps on the surface, thereby improving the reliability and service life of the chip.

[0040] In one alternative, Figure 1 As shown, the terminal structure further includes: a second groove 16, which is arranged outside the interlayer dielectric layer 12 along the first direction, and the second groove 16 penetrates into the epitaxial layer 11; the second groove 16 has a first side wall and a second side wall opposite to each other, the first side wall is in contact with the interlayer dielectric layer 12, and the second side wall is not in contact with the interlayer dielectric layer 12, and the passivation layer 14 is located in the first groove 13, the second groove 16, and the surface of the interlayer dielectric layer 12 away from the substrate 10. In this embodiment, the passivation layer is located in the first groove, the second groove, and the surface of the interlayer dielectric layer away from the substrate. By providing the second groove, the contact area between the passivation layer and the epitaxial layer is further increased, the path length of water vapor entering the chip from the external environment is further increased, and water vapor is further blocked from penetrating into the chip through tiny cracks or gaps on the surface, further ensuring that the chip has a good water vapor resistance, thereby further improving the reliability and service life of the chip.

[0041] According to some exemplary embodiments of the present application, Figure 1 As shown, the terminal structure further includes: a third groove 17, which is arranged outside the passivation layer 14 along the first direction, and the third groove 17 penetrates into the epitaxial layer 11; the third groove 17 has a third side wall and a fourth side wall opposite to each other, the third side wall is in contact with the passivation layer 14, and the fourth side wall is not in contact with the passivation layer 14; an insulating layer 18 is located in the third groove 17, on the surface of the passivation layer 14 away from the substrate 10, and on part of the side wall of the passivation layer 14. In this embodiment, the use of the insulating layer can enhance the device's ability to block water vapor, especially in a high temperature and high humidity environment, the insulating layer can prevent water vapor from penetrating into the device, thereby extending the service life of the device; by setting the third groove, and setting the insulating layer in the third groove, the contact area between the insulating layer and the epitaxial layer is increased, the path length of water vapor entering the chip from the external environment is further increased, and water vapor is further blocked from penetrating into the chip through tiny cracks or gaps on the surface, further ensuring that the chip has a good ability to block water vapor, thereby further improving the reliability and service life of the chip.

[0042] Specifically, Figure 1 As shown, the second sidewall of the second trench 16 is in contact with the insulating layer 18 .

[0043] Specifically, in the present application, the structure of the shallow groove (i.e., the first groove, the second groove, and the third groove) is flexible, and can be matched with an unlimited number of shallow grooves with different depth-to-width ratios according to different production capacities and different use conditions. The present application does not limit the depth, width, and number of shallow grooves, but it should be noted that it is recommended not to increase the difficulty of the previous and next processes, such as the groove filling passivation layer, the metal etching removal in the groove, etc.; placing multiple shallow grooves also requires a larger terminal area, reducing the number of finished chips, which also requires weighing the pros and cons. The present application adopts the existing technology in the etching process, without increasing the additional processing cost, and realizes the precise control of the terminal structure, further improving its water vapor resistance. The present application can effectively prevent the penetration of water vapor under extreme working conditions, such as high temperature and high humidity environments, thereby maintaining the stability of chip performance and extending service life. The present application not only improves the water vapor resistance of SiC MOSFET power chips by optimizing the design of the terminal structure, but also enhances its working stability in high temperature and high humidity environments, and improves the performance and stability of the entire power electronic system.

[0044] Specifically, a passivation layer is filled in one or more first grooves to form a rivet bolt structure embedded in the silicon carbide epitaxial layer, which can suppress the generation of cracks caused by different expansion coefficients of different materials in a high temperature difference environment and enhance the stability of the device structure.

[0045] According to some other exemplary embodiments of the present application, along the first direction, the distance between the bottom surface of the first groove and the surface of the epitaxial layer close to the substrate is the first depth, the distance between the bottom surface of the third groove and the surface of the epitaxial layer close to the substrate is the third depth, and the first depth is less than the third depth. In this embodiment, the first depth is less than the third depth, which further ensures that the path length of water vapor from the external environment into the chip is relatively long, and further ensures that the chip has a good water vapor resistance.

[0046] Specifically, the second trench is located between the first trench and the third trench, and one sidewall of the second trench contacts one sidewall of the third trench.

[0047] Specifically, the insulating layer and the passivation layer are not on the same level, which further increases the contact surface with the epitaxial layer and further enhances the ability to resist water vapor penetration.

[0048] In other embodiments, along the first direction, the distance between the bottom surface of the first groove and the surface of the epitaxial layer close to the substrate is the first depth, the distance between the bottom surface of the second groove and the surface of the epitaxial layer close to the substrate is the second depth, and the first depth is equal to the second depth. In the present application, the depth of the first groove is the same as the depth of the second groove, so that the first groove and the second groove can be etched and formed in the same etching process, ensuring high device preparation efficiency.

[0049] Specifically, the first trench and the second shallow trench have the same depth, which meets the characteristic of equal etching amount in the same etching process.

[0050] Specifically, the width of the first groove and the width of the second groove may be equal or different, wherein the width represents the length of the groove in a predetermined direction.

[0051] In some other optional schemes of the present application, there are multiple first grooves, and the multiple first grooves are arranged at intervals in the second direction, all of the first grooves are located between the field oxide layer and the second groove, and the second direction is perpendicular to the first direction. In the present application, multiple first grooves are arranged, so that the contact area between the passivation layer and the epitaxial layer is further increased, and the length of the path for water vapor to enter the chip from the external environment is further increased, which further blocks water vapor from penetrating into the chip through tiny cracks or gaps on the surface, further ensuring that the chip has a good water vapor resistance, thereby further improving the reliability and service life of the chip.

[0052] In some other optional schemes of this application, such as Figure 1 As shown, the terminal structure further includes: a plurality of field limiting rings 19 arranged at intervals in a predetermined direction, located in the epitaxial layer 11, the field oxide layer 15 is located on the surface of the plurality of field limiting rings 19 away from the substrate 10 and on the partial surface of the epitaxial layer 11 away from the substrate 10, the doping type of the field limiting rings 19 is different from the doping type of the epitaxial layer 11, and the predetermined direction is a direction perpendicular to the thickness of the substrate 10; a back metal layer 20 is located on the surface of the substrate 10 away from the epitaxial layer 11. In this embodiment, by arranging a plurality of field limiting rings at intervals in a predetermined direction, the withstand voltage of the semiconductor device can be enhanced. The doping type of the field limiting rings is different from that of the epitaxial layer. This structural design helps to disperse the electric field, reduce the concentration of the electric field, and thus improve the breakdown voltage of the device; the back metal layer can provide good electrical connection, further enhancing the overall stability of the device.

[0053] In the present application embodiment, Figure 1 As shown, there is one first groove 13 and three field limiting rings 19 .

[0054] In the embodiment of the present application, the doping type of the field limiting ring is P type.

[0055] According to some further exemplary embodiments of the present application, the doping type of the substrate is the same as the doping type of the epitaxial layer, and the doping concentration of the substrate is greater than the doping concentration of the epitaxial layer. In this embodiment, by increasing the doping concentration of the substrate, the stability of the semiconductor device in a high voltage and high temperature environment can be enhanced.

[0056] In the embodiment of the present application, the doping type of the above-mentioned substrate and the above-mentioned epitaxial layer are both N-type. The resistivity of the N-type epitaxial layer is 0.015-0.025Ω·cm-1, the thickness is 5-15μm, and the specification of the epitaxial layer is related to the withstand voltage. The number of the above-mentioned field limiting rings is 2-30, and the doping concentration is 1×1017cm -3 ~1×1019cm -3 , which is related to the withstand voltage. The thickness of the field oxide layer is 0.5-1.5 μm. The passivation layer is silicon oxide, silicon nitride and a combination thereof, with a thickness of 0.5-2.0 μm.

[0057] Specifically, the lower surface of the field oxide layer is flush with the upper surface of the epitaxial layer. The lower surface of the interlayer dielectric layer contacts the upper surface of the field oxide layer, and at the same time, the lower surface of the interlayer dielectric layer is flush with the upper surface of the epitaxial layer. The lower surface of the passivation layer contacts the upper surface of the interlayer dielectric layer.

[0058] In other embodiments, the material of the insulating layer includes polyimide, the material of the passivation layer includes silicon nitride, the material of the interlayer dielectric layer includes silicon oxide, and the material of the epitaxial layer includes silicon carbide. In this embodiment, the polyimide material itself has the ability of electrical isolation and water vapor resistance, which further ensures that the chip has good water vapor resistance. Silicon nitride, as the material of the passivation layer, has good chemical stability and moisture resistance, which can further effectively prevent the intrusion of water vapor and other corrosive substances, further protect the semiconductor device from environmental influences, and further extend the service life of the device; silicon oxide, as the material of the interlayer dielectric layer, can reduce the loss in the signal transmission process due to its excellent dielectric properties and good compatibility with silicon-based materials, while maintaining the stability of the structure; silicon carbide, as the material of the epitaxial layer, has high thermal stability and excellent electron mobility, which enables the semiconductor device to work in a high temperature environment, while improving the switching speed and efficiency of the device.

[0059] Specifically, the material of the interlayer dielectric layer includes silicon oxide and doped B / P silicon oxide, and the thickness is 0.5-1.0 μm. The interlayer dielectric layer isolates the gate and the source, and plays an electrical isolation role.

[0060] Specifically, the number of first grooves can be set to 1 or more, and the junction terminal margin is sufficient to place multiple first grooves, the purpose of which is to increase the contact surface with the epitaxial layer and enhance the ability to resist water vapor penetration. The groove length / depth and number can be flexibly set, avoiding the high-precision requirements of the usual process, and can match most existing processing technologies, enhancing the feasibility of the embodiments of the present invention.

[0061] Specifically, in an embodiment of the present application, by adding a multi-level groove structure (i.e., a first groove, a second groove, and a third groove) to the existing silicon carbide power device terminal structure, the chip's resistance to water vapor can be improved by using existing processes without increasing the chip area, and operational stability can be maintained in extremely high-humidity working environments.

[0062] Specifically, the shapes of the first groove, the second groove and the third groove may be U-shaped, V-shaped, inverted trapezoidal and semicircular, and the present application does not impose any specific limitation on this.

[0063] Specifically, the trench terminal structure of the present application can be used for various power devices such as silicon carbide MOSFET, silicon carbide Schottky diode, silicon carbide superjunction MOSFET and silicon carbide MPS (Merged PiN Schottky, mixed PiN / Schottky diode), and the present application does not make specific restrictions on this.

[0064] It should be noted that the terminal structure of existing silicon carbide MOSFET power devices is mostly planar. In high temperature and high humidity working environments, different dielectric layers on the terminal structure have stresses between different materials due to different thermal expansion coefficients. The stress causes tiny gaps between the device epitaxial layer and the protective layer of different materials. Water vapor penetrates into the chip through the gaps, causing the device life to be shortened. Silicon carbide power devices are used in photovoltaics, new energy vehicles, energy storage and other application fields. The devices must have excellent performance even in harsh working conditions during use. The need to increase the service life of the device in harsh environments is critical. The terminal structure process route of the semiconductor device of the present application is simple, and does not increase additional manufacturing costs. A groove-type terminal structure can be realized by adding an additional exposure area on the mask. Multiple grooves can be arranged, and the passivation layer is filled in the first groove and the second groove. The polyimide protective layer (i.e., the insulating layer) is filled in the third groove, which can completely wrap the passivation layer. In a high-temperature environment, the groove structure can clamp the passivation layer and the epitaxial layer to produce a gap due to different thermal expansion coefficients, and the groove-type terminal increases the length of the path for water vapor to enter the chip, which can produce an additional water vapor blocking effect.

[0065] The present application also provides a method for preparing a terminal structure of a semiconductor device, such as Figure 2 As shown, the following steps are included:

[0066] Step S101: providing a substrate;

[0067] Step S102: forming a preliminary epitaxial layer on one side of the substrate;

[0068] Step S103: forming a field oxide layer at least on a portion of the surface of the prepared epitaxial layer away from the substrate;

[0069] Step S104: forming a preliminary interlayer dielectric layer on the surface of the field oxide layer away from the substrate, on part of the sidewall of the field oxide layer, and on part of the surface of the preliminary epitaxial layer away from the substrate;

[0070] Step S105: removing part of the above-mentioned prepared epitaxial layer and the above-mentioned prepared interlayer dielectric layer to form at least one first trench, the remaining above-mentioned prepared epitaxial layer forms an epitaxial layer, and the remaining above-mentioned prepared interlayer dielectric layer forms an interlayer dielectric layer, the above-mentioned first trench is arranged along the above-mentioned first direction in the above-mentioned prepared interlayer dielectric layer not covered with the above-mentioned field oxide layer, and the above-mentioned first trench penetrates into the above-mentioned prepared epitaxial layer, and the above-mentioned first direction is the thickness direction of the above-mentioned substrate;

[0071] Step S106: forming a passivation layer at least in the first trench and on the surface of the interlayer dielectric layer away from the substrate.

[0072] Through the above embodiment, a substrate is first provided, and then a preliminary epitaxial layer is formed on one side of the substrate, and a field oxide layer is formed on at least a portion of the surface of the preliminary epitaxial layer away from the substrate, and then a preliminary interlayer dielectric layer is formed on the surface of the field oxide layer away from the substrate, on a portion of the sidewall of the field oxide layer, and on a portion of the surface of the preliminary epitaxial layer away from the substrate, and a portion of the preliminary epitaxial layer and the preliminary interlayer dielectric layer are removed to form at least one first groove, the remaining preliminary epitaxial layer forms an epitaxial layer, and the remaining preliminary interlayer dielectric layer forms an interlayer dielectric layer, and finally a passivation layer is formed at least in the first groove and on the surface of the interlayer dielectric layer away from the substrate, wherein the first groove is arranged along a first direction in the preliminary interlayer dielectric layer not covered by the field oxide layer, and the first groove penetrates into the preliminary epitaxial layer. Compared with the problem in the prior art that planar silicon carbide MOSFET power chips in a high temperature and high humidity environment are affected by water vapor penetration due to differences in thermal expansion coefficients of different dielectric layers, the passivation layer of the present application is at least located in the first groove and on the surface of the interlayer dielectric layer away from the substrate, the first groove is arranged along the first direction in the interlayer dielectric layer not covered by the field oxide layer, and the first groove penetrates into the epitaxial layer, so that the contact area between the passivation layer and the epitaxial layer is increased, and the length of the path for water vapor to enter the chip from the external environment is increased, which effectively blocks water vapor from penetrating into the chip through tiny cracks or gaps on the surface, thereby improving the reliability and service life of the chip.

[0073] In an optional scheme, part of the above-mentioned prepared epitaxial layer and the above-mentioned prepared interlayer dielectric layer is removed to form at least one first groove, including: part of the above-mentioned prepared epitaxial layer and the above-mentioned prepared interlayer dielectric layer is removed to form a second groove and at least one of the above-mentioned first grooves, the above-mentioned second groove is arranged outside the above-mentioned prepared interlayer dielectric layer along the above-mentioned first direction, and the above-mentioned second groove penetrates into the above-mentioned prepared epitaxial layer, the above-mentioned second groove has opposite first side walls and second side walls, the above-mentioned first side walls are in contact with the above-mentioned prepared interlayer dielectric layer, and the above-mentioned second side walls are not in contact with the above-mentioned prepared interlayer dielectric layer, and a passivation layer is formed at least in the above-mentioned first groove and on the surface of the above-mentioned interlayer dielectric layer away from the above-mentioned substrate, including: the above-mentioned passivation layer is formed in the above-mentioned first groove, in the above-mentioned second groove, and on the surface of the above-mentioned interlayer dielectric layer away from the above-mentioned substrate. In this embodiment, the passivation layer is located in the first groove, the second groove and on the surface of the interlayer dielectric layer away from the substrate. By setting the second groove, the contact area between the passivation layer and the epitaxial layer is further increased, and the length of the path for water vapor to enter the chip from the external environment is further increased, which further blocks water vapor from penetrating into the chip through tiny cracks or gaps on the surface, further ensuring that the chip has good water vapor resistance, thereby further improving the reliability and service life of the chip.

[0074] In other embodiments, removing part of the above-mentioned prepared epitaxial layer and the above-mentioned prepared interlayer dielectric layer to form at least one first groove includes: removing part of the above-mentioned prepared epitaxial layer and the above-mentioned prepared interlayer dielectric layer to form at least one first groove and a third groove, the above-mentioned third groove is arranged outside the above-mentioned passivation layer along the above-mentioned first direction, and the above-mentioned third groove penetrates into the above-mentioned prepared epitaxial layer; the above-mentioned third groove has relative third side walls and fourth side walls, the above-mentioned third side walls are in contact with the above-mentioned passivation layer, and the above-mentioned fourth side walls are not in contact with the above-mentioned passivation layer, after forming the passivation layer at least in the above-mentioned first groove and on the surface of the above-mentioned interlayer dielectric layer away from the above-mentioned substrate, the above-mentioned method also includes: forming an insulating layer in the above-mentioned third groove, on the surface of the above-mentioned passivation layer away from the above-mentioned substrate, and on part of the side walls of the above-mentioned passivation layer. In this embodiment, the use of the insulating layer can enhance the device's ability to block water vapor, especially in a high temperature and high humidity environment, the insulating layer can prevent water vapor from penetrating into the interior of the device, thereby extending the service life of the device; by setting a third groove, and setting the insulating layer in the third groove, the contact area between the insulating layer and the epitaxial layer is increased, and the length of the path for water vapor to enter the chip from the external environment is further increased, further blocking water vapor from penetrating into the chip through tiny cracks or gaps on the surface, further ensuring that the chip has a good ability to block water vapor, thereby further improving the reliability and service life of the chip.

[0075] In order to enable those skilled in the art to more clearly understand the technical solution of the present application, the implementation process of the method for preparing the terminal structure of the semiconductor device of the present application will be described in detail below in combination with specific embodiments.

[0076] The present application relates to a specific method for preparing a terminal structure of a semiconductor device, comprising the following steps:

[0077] Step S1: Provide an N+ substrate, and form an N-type epitaxial layer on one side of the substrate, form a P+ field limiting ring and an oxide field oxide layer on the N-type epitaxial layer, and use mask deposition, patterning, ion implantation and ion activation processes to form a field limiting ring on the epitaxial layer. The size and number of the field limiting ring structures are related to the maximum voltage that the power device can withstand. The oxide field oxide layer covers the device active area and the terminal, and the lower surface of the oxide field oxide layer in the terminal area is flush with the upper surface of the epitaxial layer.

[0078] Step S2: growing a preliminary interlayer dielectric layer on the surface of the oxide field oxide layer, wherein in the terminal region, the lower surface of the preliminary interlayer dielectric layer contacts the upper surface of the oxide field oxide layer, and at the same time, the lower surface of the preliminary interlayer dielectric layer is flush with the upper surface of the epitaxial layer; forming a mask layer and patterning it by coating and photolithography, and obtaining a first groove and a first preliminary groove in the terminal region by etching and degumming processes, and the remaining preliminary interlayer dielectric layer forms an interlayer dielectric layer, wherein the first groove and the first preliminary groove have equal depths, and may have equal or unequal widths, and one side of the first preliminary groove is flush with the cross section of the interlayer dielectric layer, and the other side is flush with the scribe line S, and a gate metal connection structure is obtained in the source region.

[0079] Step S3: growing a preliminary passivation layer on the surface of the interlayer dielectric layer, wherein the lower surface of the preliminary passivation layer contacts the upper surface of the interlayer dielectric layer, and the preliminary passivation layer fills the first trench and the first preliminary trench.

[0080] Step S4: forming a mask layer and patterning it by coating and photolithography, and obtaining a second preliminary groove in the terminal area by etching and degumming processes. The second preliminary groove is closer to the epitaxial layer than the first groove. One side of the second preliminary groove is flush with the cross section of the second groove, and the other side is flush with the scribe line. The second preliminary groove is a polyimide (i.e., insulating layer) filling area. The second preliminary groove is closer to the epitaxial layer than the second groove. The polyimide and the passivation layer are not at the same level, thereby increasing the contact surface with the epitaxial layer and enhancing the ability to resist water vapor penetration. The second preliminary groove is closer to the epitaxial layer than the first preliminary groove. The second preliminary groove is obtained by re-exposure and etching after the passivation layer is filled in the first preliminary groove. The bottom surface of the second preliminary groove is not at the same level as the surface of the epitaxial layer close to the substrate. When the second preliminary groove is processed, the passivation layer of the source area is also opened, and the processing of the source area limits the depth of the second preliminary groove.

[0081] Step S5: forming a polyimide layer (ie, insulating layer) on the passivation layer, wherein the polyimide layer covers the terminal area and is flush with the scribe line, and the other side of the polyimide layer extends to the active area.

[0082] Specifically, the processing technology of the first groove, the second groove and the third groove are compatible with the existing technology, and the first groove, the second groove and the third groove are obtained at the same time when processing the active area. Of course, the present application does not limit the processing together, and the first groove, the second groove and the third groove can be obtained through additional exposure, etching and degumming processing.

[0083] Specifically, the terminal structure of the semiconductor device and the preparation method thereof provided in the present application have a simple process, a large process window and do not increase the chip size without increasing the difficulty of existing process technology, thereby increasing the chip's ability to block water vapor and extending the chip's service life.

[0084] An embodiment of the present application also provides a semiconductor device, comprising any terminal structure of the above-mentioned semiconductor device.

[0085] In the above embodiment, the semiconductor device includes a terminal structure, wherein the terminal structure includes a substrate, an epitaxial layer located on one side of the substrate, a field oxide layer, an interlayer dielectric layer, at least one first trench and a passivation layer, wherein the field oxide layer is at least located on a portion of the surface of the epitaxial layer away from the substrate, the interlayer dielectric layer is located on a surface of the field oxide layer away from the substrate, on a portion of the sidewall of the field oxide layer and on a portion of the surface of the epitaxial layer away from the substrate, the first trench is arranged along a first direction in the interlayer dielectric layer not covered by the field oxide layer, and the first trench penetrates into the epitaxial layer, and the passivation layer is at least located in the first trench and on the surface of the interlayer dielectric layer away from the substrate. Compared with the problem in the prior art that planar silicon carbide MOSFET power chips in a high temperature and high humidity environment are affected by water vapor penetration due to differences in thermal expansion coefficients of different dielectric layers, the passivation layer of the present application is at least located in the first groove and on the surface of the interlayer dielectric layer away from the substrate, the first groove is arranged along the first direction in the interlayer dielectric layer not covered by the field oxide layer, and the first groove penetrates into the epitaxial layer, so that the contact area between the passivation layer and the epitaxial layer is increased, and the length of the path for water vapor to enter the chip from the external environment is increased, which effectively blocks water vapor from penetrating into the chip through tiny cracks or gaps on the surface, thereby improving the reliability and service life of the chip.

[0086] It should be noted that, in the embodiment of the present application, the semiconductor device includes an active area (CELL), a terminal structure and a scribe line at the edge of the terminal structure, and the terminal structure includes a field oxide layer, a field limiting ring and a junction terminal.

[0087] From the above description, it can be seen that the above embodiments of the present application achieve the following technical effects:

[0088] In the terminal structure of the semiconductor device of the present application, the terminal structure includes a substrate, an epitaxial layer located on one side of the substrate, a field oxide layer, an interlayer dielectric layer, at least one first trench and a passivation layer, wherein the field oxide layer is at least located on a portion of the surface of the epitaxial layer away from the substrate, the interlayer dielectric layer is located on the surface of the field oxide layer away from the substrate, on a portion of the sidewall of the field oxide layer and on a portion of the surface of the epitaxial layer away from the substrate, the first trench is arranged along a first direction in the interlayer dielectric layer not covered by the field oxide layer, and the first trench penetrates into the epitaxial layer, and the passivation layer is at least located in the first trench and on the surface of the interlayer dielectric layer away from the substrate. Compared with the problem in the prior art that planar silicon carbide MOSFET power chips in a high temperature and high humidity environment are affected by water vapor penetration due to differences in thermal expansion coefficients of different dielectric layers, the passivation layer of the present application is at least located in the first groove and on the surface of the interlayer dielectric layer away from the substrate, the first groove is arranged along the first direction in the interlayer dielectric layer not covered by the field oxide layer, and the first groove penetrates into the epitaxial layer, so that the contact area between the passivation layer and the epitaxial layer is increased, and the length of the path for water vapor to enter the chip from the external environment is increased, which effectively blocks water vapor from penetrating into the chip through tiny cracks or gaps on the surface, thereby improving the reliability and service life of the chip.

[0089] The above description is only the preferred embodiment of the present application and is not intended to limit the present application. For those skilled in the art, the present application may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A terminal structure of a semiconductor device, characterized in that: include: substrate; an epitaxial layer, located on one side of the substrate; A field oxide layer, at least located on a portion of the surface of the epitaxial layer away from the substrate; An interlayer dielectric layer is located on a surface of the field oxide layer away from the substrate, on a portion of the sidewall of the field oxide layer, and on a portion of the surface of the epitaxial layer away from the substrate; At least one first trench is arranged in the interlayer dielectric layer not covering the field oxide layer along a first direction, and the first trench penetrates into the epitaxial layer, and the first direction is the thickness direction of the substrate; A passivation layer is located at least in the first trench and on a surface of the interlayer dielectric layer away from the substrate.

2. The terminal structure of the semiconductor device according to claim 1, characterized in that: The terminal structure also includes: A second groove is arranged along the first direction outside the interlayer dielectric layer, and the second groove penetrates into the epitaxial layer; the second groove has a first side wall and a second side wall opposite to each other, the first side wall is in contact with the interlayer dielectric layer, and the second side wall is not in contact with the interlayer dielectric layer, and the passivation layer is located in the first groove, in the second groove, and on the surface of the interlayer dielectric layer away from the substrate.

3. The terminal structure of the semiconductor device according to claim 1, characterized in that: The terminal structure also includes: a third trench, arranged outside the passivation layer along the first direction, and the third trench penetrates into the epitaxial layer; the third trench has a third sidewall and a fourth sidewall opposite to each other, the third sidewall contacts the passivation layer, and the fourth sidewall does not contact the passivation layer; An insulating layer is located in the third trench, on a surface of the passivation layer away from the substrate, and on a portion of the sidewall of the passivation layer.

4. The terminal structure of the semiconductor device according to claim 3, characterized in that: Along the first direction, the distance between the bottom surface of the first trench and the surface of the epitaxial layer close to the substrate is a first depth, the distance between the bottom surface of the third trench and the surface of the epitaxial layer close to the substrate is a third depth, and the first depth is smaller than the third depth.

5. The terminal structure of the semiconductor device according to claim 2, characterized in that: Along the first direction, the distance between the bottom surface of the first trench and the surface of the epitaxial layer close to the substrate is a first depth, the distance between the bottom surface of the second trench and the surface of the epitaxial layer close to the substrate is a second depth, and the first depth is equal to the second depth.

6. The terminal structure of the semiconductor device according to claim 2, characterized in that: There are a plurality of the first trenches, and the plurality of the first trenches are spaced apart in the second direction, and all of the first trenches are located between the field oxide layer and the second trench, and the second direction is perpendicular to the first direction.

7. A method for preparing a terminal structure of a semiconductor device according to any one of claims 1 to 6, characterized in that: include: providing a substrate; forming a preliminary epitaxial layer on one side of the substrate; forming a field oxide layer at least on a portion of the surface of the preliminary epitaxial layer away from the substrate; forming a preliminary interlayer dielectric layer on a surface of the field oxide layer away from the substrate, on a portion of the sidewall of the field oxide layer, and on a portion of the surface of the preliminary epitaxial layer away from the substrate; Removing part of the prepared epitaxial layer and the prepared interlayer dielectric layer to form at least one first trench, the remaining prepared epitaxial layer forms an epitaxial layer, the remaining prepared interlayer dielectric layer forms an interlayer dielectric layer, the first trench is arranged in the prepared interlayer dielectric layer not covered with the field oxide layer along the first direction, and the first trench penetrates into the prepared epitaxial layer, and the first direction is the thickness direction of the substrate; A passivation layer is formed at least in the first trench and on a surface of the interlayer dielectric layer away from the substrate.

8. The method for preparing a terminal structure of a semiconductor device according to claim 7, characterized in that: Removing part of the prepared epitaxial layer and the prepared interlayer dielectric layer to form at least one first trench, comprising: removing part of the prepared epitaxial layer and the prepared interlayer dielectric layer to form a second trench and at least one first trench, the second trench being arranged outside the prepared interlayer dielectric layer along the first direction, and the second trench penetrating into the prepared epitaxial layer, the second trench having a first sidewall and a second sidewall opposite to each other, the first sidewall being in contact with the prepared interlayer dielectric layer, and the second sidewall being not in contact with the prepared interlayer dielectric layer, Forming a passivation layer at least in the first trench and on the surface of the interlayer dielectric layer away from the substrate includes: forming the passivation layer in the first trench, in the second trench, and on the surface of the interlayer dielectric layer away from the substrate.

9. The method for preparing a terminal structure of a semiconductor device according to claim 7, characterized in that: Removing part of the prepared epitaxial layer and the prepared interlayer dielectric layer to form at least one first trench, comprising: removing part of the prepared epitaxial layer and the prepared interlayer dielectric layer to form at least one first trench and a third trench, wherein the third trench is arranged outside the passivation layer along the first direction and the third trench penetrates into the prepared epitaxial layer; the third trench has a third sidewall and a fourth sidewall opposite to each other, wherein the third sidewall contacts the passivation layer and the fourth sidewall does not contact the passivation layer, After forming a passivation layer at least in the first trench and on the surface of the interlayer dielectric layer away from the substrate, the method further includes: forming an insulating layer in the third trench, on the surface of the passivation layer away from the substrate and on part of the sidewall of the passivation layer.

10. A semiconductor device, characterized in that: A terminal structure of a semiconductor device comprising any one of claims 1 to 6, or a terminal structure of a semiconductor device prepared by the method for preparing a terminal structure of a semiconductor device according to any one of claims 7 to 9.

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