Mini / Micro LED synchronous etching method with high laser lift-off yield

Abstract

The invention provides a Mini / Micro LED synchronous etching method with high laser lift-off yield, which comprises the following steps of: firstly, accurately transferring a channel pattern to the surface of a chip by using an ISO (International Standardization Organization) photomask; secondly, carrying out partial pre-etching on the isolation epitaxial layer under an ICP etching condition, removing partial epitaxial layer thickness, and ensuring that etching does not touch a chip substrate; and then, depositing an SIO DBR layer, performing synchronous re-etching on the SIO DBR layer and the isolation epitaxial layer under an ICP condition, removing the SIO DBR layer at the bottom of the sapphire substrate, and meanwhile, retaining the SIO DBR layer on the side wall of the channel. By accurately controlling the ICP power, the gas flow and the etching time, the etching uniformity is controlled within + / -5nm, scraps are greatly reduced, and the laser lift-off yield is improved. In addition, through real-time dynamic feedback control and use of high-performance ICP equipment, process stability and repeatability are ensured.

Description

Technical Field

[0001] The present invention relates to the field of Mini / Micro LED chip manufacturing, and in particular to a Mini / Micro LED synchronous etching method with high laser lift-off yield. Background Art

[0002] In the manufacturing of Mini / Micro LED chips, laser lift-off technology is the key process for separating the GaN epitaxial layer from the sapphire substrate. However, this process faces severe challenges. When the SIO (Silicon Oxide) DBR (Distributed Bragg Reflector) layer remains at the bottom of the sapphire substrate trench, the laser lift-off process is prone to produce a large amount of debris, which not only leads to a significant decrease in the lift-off yield, but also has an adverse effect on the subsequent processing and performance stability of the chip.

[0003] The root of this problem lies in the residual SIO DBR layer. As an important optical film, SIO DBR plays a key role in LED chips, but its residue during the stripping process has become a thorny problem. The residual SIO DBR layer interferes with the transmission of laser energy, resulting in an uneven stripping process, which generates a large amount of debris. These debris not only contaminate the chip surface, but may also be embedded in the chip structure, affecting its electrical and optical performance.

[0004] Although the existing technology attempts to remove the SIO DBR layer through a single etching process, the effect is not ideal. This method often cannot completely avoid the residue of SIO DBR at the bottom of the sapphire substrate, resulting in the continued existence of the debris problem. The limitations of the single etching process are mainly reflected in the following aspects: first, the etching rate is difficult to accurately control, and it is easy to over-etch or under-etch; second, the etching uniformity is difficult to ensure, especially on large-area chips; finally, a single etching process is difficult to take into account both the removal of the SIO DBR layer and the protection of the channel sidewalls, which may cause damage to the chip structure or performance degradation.

[0005] In addition, existing technologies also face challenges when processing the isolation epitaxial layer (ISO epitaxial layer). The complete removal of the ISO epitaxial layer is crucial to chip performance, but the traditional one-time etching method is difficult to achieve precise control and is prone to over-etching or insufficient etching. This not only affects the electrical properties of the chip, but may also cause difficulties in subsequent process steps.

[0006] In view of the above problems, the existing technology needs to be improved urgently. Summary of the invention

[0007] The purpose of the present invention is to provide a Mini / Micro LED synchronous etching method with high laser lift-off yield and a partial pre-etching and synchronous re-etching method of the ISO epitaxial layer, which has the advantages of improving the laser lift-off yield, reducing debris generation, preventing chip short circuit, and improving etching accuracy and uniformity.

[0008] In order to achieve the above object, the present invention provides a Mini / Micro LED synchronous etching method with high laser lift-off yield, comprising the following steps: Channel pattern transfer: The channel pattern is transferred to the chip using an isolation mask (ISO mask), ensuring that the pattern is accurately aligned and evenly distributed.

[0009] Partial pre-etching of ISO epitaxial layer: Under ICP etching conditions, the ISO epitaxial layer is partially pre-etched to remove part of the thickness of the ISO epitaxial layer to ensure that the etching does not touch the chip substrate.

[0010] The pre-etching depth is controlled between 5% and 90% of the total thickness of the ISO epitaxial layer.

[0011] The ICP power is controlled between 800W and 1000W, the bias power is controlled between 100W and 150W, and the chamber pressure is controlled between 2mTorr and 10mTorr.

[0012] SIO DBR coating: A SIO DBR protective layer is plated on the chip surface, ensuring that its thickness is between 50nm and 200nm.

[0013] Synchronous re-etching: Under ICP conditions, the SIO DBR and ISO epitaxial layer in the channel are simultaneously re-etched to remove the SIO DBR residue at the bottom of the sapphire substrate while retaining the SIO DBR layer on the channel sidewall.

[0014] The etching uniformity is controlled within ±5nm.

[0015] The synchronous re-etching process achieves uniform re-etching of the SIO DBR and ISO epitaxial layers by precisely controlling the ICP power, gas flow and etching time, ensuring the consistency of etching depth and sidewall protection.

[0016] The gas components include fluorine-based gas and chlorine-based gas, and the gas flow ratio thereof is 1:4.

[0017] Process monitoring: During the synchronous re-etching process, dynamic feedback control is performed by real-time monitoring of the etching depth and the integrity of the sidewall protection layer to ensure the accuracy and controllability of the process.

[0018] Process equipment characteristics: The ICP etching equipment includes a dual power control module and a gas flow real-time monitoring module to ensure real-time feedback and control of process parameters.

[0019] Surface treatment: Before ISO mask pattern transfer, the chip surface is plasma cleaned to remove surface impurities and ensure the accuracy and stability of pattern transfer.

[0020] Epitaxial layer materials: The ISO epitaxial layer is made of GaN or AlGaN materials to ensure material properties and process stability.

[0021] Channel structure characteristics: The channel pattern is a longitudinal groove structure, and the groove width is controlled between 1μm and 10μm to ensure structural accuracy and repeatability.

[0022] Process effect: Through this method, the residual rate of the SIO DBR layer at the bottom of the sapphire substrate is less than 0.5%.

[0023] Continuous process: All steps are completed continuously in the same etching chamber to avoid secondary contamination and improve process stability.

[0024] Application areas: This method is suitable for manufacturing Mini LED or Micro LED chips and meets the process requirements for large-scale production.

[0025] The present invention realizes precise control of the SIO DBR layer and the ISO epitaxial layer through partial pre-etching of the ISO epitaxial layer and synchronous re-etching of the SIO DBR, combined with real-time dynamic feedback and high-precision ICP equipment, ensuring that there is no SIO DBR residue on the sapphire substrate and the SIO DBR layer on the channel sidewall is intact, significantly improving the laser lift-off yield, etching uniformity and process stability, and providing strong technical support for the industrial production of Mini / Micro LEDs. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 Schematic diagram of a partial pre-etching process of the ISO epitaxial layer of the present invention.

[0027] Figure 2 Schematic diagram of the SIO DBR coating process of the present invention.

[0028] Figure 3 Schematic diagram of the synchronous re-etching process of the present invention. DETAILED DESCRIPTION

[0029] The technical solutions in the present invention will be described clearly and completely below in conjunction with the drawings in the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. The components of the present invention generally described and shown in the drawings here can be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of the present invention provided in the drawings is not intended to limit the scope of the claimed invention, but only represents the selected embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without making creative work belong to the scope of protection of the present invention. It should be noted that similar numbers and letters represent similar items in the following drawings, so once an item is defined in one drawing, it does not need to be further defined and explained in the subsequent drawings. At the same time, in the description of the present invention, the terms "first", "second", etc. are only used to distinguish the description, and cannot be understood as indicating or implying relative importance. Example

[0030] Step 1: Use ISO mask to transfer the channel pattern to the chip surface Align the ISO mask to the LED chip and transfer the channel pattern to the chip surface.

[0031] Step 2: Partial pre-etching of the ISO epitaxial layer like Figure 1 As shown, a portion 210 of the chip including the sapphire substrate 100 and the ISO epitaxial layer 200 is partially pre-etched using an ICP device, and the parameters are as follows: ICP power: 800W Bias power: 100W Chamber pressure: 5mTorr Etching time: adjusted according to the thickness of 50% ISO epitaxial layer removed Step 3: SIO DBR coating like Figure 2 As shown, a SIO DBR film layer 300 is deposited on the surface of the chip epitaxial layer after pre-etching.

[0032] Step 4: Align using ISO mask again Align the ISO mask to the chip again to ensure the pattern is accurately aligned.

[0033] Step 5: Synchronous Re-etching like Figure 3 As shown, ICP equipment is used for synchronous re-etching, and the parameters are as follows: ICP power: 900W Bias power: 120W Chamber pressure: 7mTorr Remove the remaining ISO epitaxial layer and the SIO DBR at the bottom of the trench. Figure 3 The structure 400 in the dashed box is etched while retaining the SIO DBR layer on the sidewall of the channel.

[0034] The SEM was used to observe the etched channel. No SIO DBR remained at the bottom of the sapphire substrate. The laser stripping yield was significantly improved. The SIO DBR layer on the channel sidewall was intact without obvious breakage or shedding. The debris was reduced during the laser stripping process, and the risk of chip short circuit was reduced. The etched surface uniformity was within ±5nm.

[0035] The partial pre-etching synchronous etching method of the Mini / Micro LED ISO epitaxial layer with high laser stripping yield provided by the present invention significantly improves the laser stripping yield, reduces the generation of debris, prevents chip short circuit, and improves the etching accuracy and uniformity by accurately controlling the ICP etching process parameters and process flow. The method ensures that there is no SIO DBR coverage at the bottom of the sapphire substrate, effectively reduces the residue and debris during the laser stripping process, and retains the SIO DBR layer on the side wall of the channel to prevent current short circuit and ensure stable chip performance. The precisely controlled ICP process parameters significantly improve the etching accuracy, and the etching surface uniformity is within ±5nm. The overall process has high stability and repeatability, and can achieve consistent effects on different batches of LED chips, which is suitable for industrial mass production. This method not only improves process reliability and reduces production costs, but also provides key technical support for the large-scale production of high-performance Mini / Micro LED devices.

[0036] The above description is only an embodiment of the present invention and is not intended to limit the protection scope of the present invention. For those skilled in the art, the present invention may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A Mini / Micro LED synchronous etching method with high laser lift-off yield, characterized in that: The following steps are involved: (1) Use ISO mask to transfer the channel pattern to the chip; (2) Under ICP etching conditions, partially pre-etch the ISO epitaxial layer to remove part of the thickness of the ISO epitaxial layer, ensuring that the pre-etching does not touch the chip substrate; (3) After SIO DBR coating, the SIO DBR and ISO epitaxial layer in the channel are simultaneously re-etched to remove the SIO DBR residue at the bottom of the sapphire substrate while retaining the SIO DBR layer on the channel sidewall.

2. The method according to claim 1, characterized in that In step (2), the partial pre-etching depth of the ISO epitaxial layer is controlled to be between 30% and 70% of the total thickness of the ISO epitaxial layer.

3. The method according to claim 1, characterized in that The simultaneous re-etching in step (3) needs to ensure that the SIO DBR layer on the channel sidewall is retained.

4. The method according to claim 1, characterized in that The synchronous re-etching process achieves uniform re-etching of the SIO DBR and ISO epitaxial layers by controlling the ICP power and gas flow rate.

5. The method according to claim 1, characterized in that In step (2), the ICP power of the partial pre-etching of the ISO epitaxial layer is controlled between 500 W and 2000 W, the bias power is controlled between 100 W and 200 W, and the chamber pressure is controlled between 2 mTorr and 10 mTorr.

6. The method according to claim 1, characterized in that The gas used in the ICP etching includes a fluorine-based gas and a chlorine-based gas, and the gas flow ratio thereof is 1:

4.

7. The method according to claim 1, characterized in that The thickness of the SIO DBR layer is 50 nm to 200 nm.

8. The method according to claim 1, characterized in that The etching uniformity after synchronous re-etching in step (3) is controlled within ±5nm.

9. The method according to claim 1, characterized in that: The ISO epitaxial layer is made of GaN or AlGaN material.

10. The method according to claim 1, characterized in that The channel pattern is a longitudinal groove structure, and the groove width is controlled between 1 μm and 10 μm.

Images