Semiconductor light emitting device and manufacturing method thereof

Abstract

The embodiment of the invention relates to a semiconductor light emitting device and a manufacturing method thereof. The semiconductor light-emitting device includes a light-emitting layer, a semiconductor substrate, and a multilayer film portion. The semiconductor substrate includes cubic gallium arsenide (GaAs). The semiconductor substrate has a substrate lower surface and a substrate upper surface. The substrate upper surface is located between the light-emitting layer and the substrate lower surface, and is inclined with respect to the (100) plane of the cubic crystal. The multilayer film portion includes a first layer and a second layer. The first layer is located between the substrate upper surface and the light-emitting layer, and has a first surface extending along the substrate upper surface. The second layer is located between the first surface and the light-emitting layer, is in contact with the first surface, and has a second surface on the opposite side from the surface in contact with the first surface. The irregularities of the second surface are larger than the irregularities of the first surface. Light from the light-emitting layer is radiated after passing through the multilayer film portion.

Description

[0001] Related Applications

[0002] This application claims priority based on Japanese Patent Application No. 2023-148742 (filing date: September 13, 2023) and Japanese Patent Application No. 2024-14971 (filing date: February 2, 2024). This application incorporates the entire contents of the basic applications by reference. Technical Field

[0003] Embodiments of the present invention relate to a semiconductor light emitting device and a method for manufacturing the same. Background Art

[0004] Semiconductor light emitting devices that emit light from a light emitting layer through a substrate have been developed. In such semiconductor light emitting devices, improvement of light emitting characteristics is desired. Summary of the invention

[0005] The semiconductor light-emitting device of the embodiment includes a light-emitting layer, a semiconductor substrate and a multilayer film portion. The semiconductor substrate includes cubic gallium arsenide (GaAs). The semiconductor substrate has a substrate lower surface and a substrate upper surface. The substrate upper surface is located between the light-emitting layer and the substrate lower surface, and is inclined relative to the (100) plane of the cubic crystal. The multilayer film portion includes a first layer and a second layer. The first layer is located between the substrate upper surface and the light-emitting layer, and has a first surface extending along a plane parallel to the substrate upper surface. The second layer is located between the first surface and the light-emitting layer, in contact with the first surface, and has a second surface on the opposite side of the surface in contact with the first surface. The second surface has a larger concavoconvexity than the first surface. Light from the light-emitting layer is radiated after passing through the multilayer film portion.

[0006] According to the present embodiment, a semiconductor light emitting device capable of improving light emitting characteristics and a method for manufacturing the same can be provided. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 (a) and Figure 1 (b) is a schematic diagram illustrating a semiconductor light emitting device according to an embodiment.

[0008] Figure 2 is a schematic cross-sectional view illustrating a light-emitting layer of a semiconductor light-emitting device according to an embodiment.

[0009] Figure 3 (a) and Figure 3 (b) is a schematic diagram illustrating a multilayer film portion of a semiconductor light emitting device according to an embodiment.

[0010] Figure 4This is an image illustrating a portion of a semiconductor light emitting device according to an embodiment.

[0011] Figure 5 (a) and Figure 5 (b) is an image illustrating a part of the semiconductor light emitting device according to the embodiment.

[0012] Figure 6 This is a graph illustrating an example of light emission intensity distribution in a semiconductor light emitting device.

[0013] Figure 7 (a) and Figure 7 (b) is a schematic plan view illustrating the light emission intensity distribution in the semiconductor light emitting device.

[0014] Figure 8 (a) and Figure 8 (b) is a schematic cross-sectional view illustrating a semiconductor light emitting device according to an embodiment.

[0015] Fig. 9 is a schematic cross-sectional view illustrating a semiconductor light emitting device according to an embodiment.

[0016] Fig.10 (a)~ Fig.10 (e) is a schematic cross-sectional view illustrating a method for manufacturing a semiconductor light-emitting device according to an embodiment. DETAILED DESCRIPTION

[0017] Hereinafter, embodiments of the present invention will be described with reference to the drawings.

[0018] The accompanying drawings are schematic or conceptual drawings, and the relationship between the thickness and width of each part, the ratio of the size between the parts, etc. are not necessarily the same as in reality. Even when the same part is shown, the size or ratio may be shown differently according to the drawings.

[0019] In the present specification and each drawing, the same reference numerals are given to the same elements as those already described, and detailed description thereof will be appropriately omitted.

[0020] Figure 1 (a) and Figure 1 (b) is a schematic diagram illustrating a semiconductor light emitting device according to an embodiment.

[0021] Figure 1 (a) is a plan view of the semiconductor light emitting device 1 according to the embodiment as viewed from above. Figure 1 (b) Yes Figure 1 (a) is a cross-sectional view taken along line A1-A2.

[0022] like Figure 1As shown in (b), the semiconductor light emitting device 1 includes a semiconductor substrate 100, a first buffer layer 301-1, a multilayer film portion 310, a second buffer layer 301-2, an n-type cladding layer 102, a light emitting layer 103, a p-type cladding layer 104, a p-type contact layer 105, a p-side electrode 106, and an n-side electrode 107. The semiconductor light emitting device 1 is, for example, a light emitting diode.

[0023] The semiconductor substrate 100 includes cubic gallium arsenide (GaAs). The semiconductor substrate 100 is, for example, an n-type GaAs substrate. The semiconductor substrate 100 has a substrate lower surface 100s and a substrate upper surface 100t, which is a surface opposite to the substrate lower surface 100s. The substrate upper surface 100t is inclined at an inclination angle θ relative to the (100) plane of the cubic crystal of GaAs. That is, the inclination angle θ is the angle between the substrate upper surface 100t and the (100) plane of the cubic crystal of GaAs. The inclination angle θ is, for example, an offset angle. The semiconductor substrate 100 is, for example, an offset substrate having an offset angle of the inclination angle θ.

[0024] In the description of the embodiment, an XYZ orthogonal coordinate system is used. The direction from the semiconductor substrate 100 toward the light-emitting layer 103 is set as the Z direction. Two directions perpendicular to the Z direction and orthogonal to each other are set as the X direction (second direction) and the Y direction (third direction). The direction from the lower surface 100s of the substrate toward the upper surface 100t of the substrate is, for example, parallel to the Z direction. The direction perpendicular to the upper surface 100t of the substrate is, for example, parallel to the Z direction. In addition, for the sake of explanation, the direction from the semiconductor substrate 100 toward the light-emitting layer 103 is referred to as "up", and the opposite direction is referred to as "down". These directions are based on the relative positional relationship between the semiconductor substrate 100 and the light-emitting layer 103, and have nothing to do with the direction of gravity.

[0025] like Figure 1 As shown in (a), in a plan view, the p-side electrode 106 and the n-side electrode 107 are arranged in the X direction. In this example, the X direction is the length direction of the semiconductor light emitting device 1. That is, for example, the length of the semiconductor substrate 100 in the X direction is longer than the length of the semiconductor substrate 100 in the Y direction. In addition, for example, the length of the multilayer film portion 310 in the X direction is longer than the length of the multilayer film portion 310 in the Y direction. In addition, for example, the length of the light emitting layer 103 in the X direction is longer than the length of the light emitting layer 103 in the Y direction.

[0026] The area of ​​the p-side electrode 106 is larger than the area of ​​the n-side electrode 107. In this example, the p-side electrode 106 is 350 micrometers (μm)×150 μm, and the n-side electrode 107 is 130 μm×130 μm.

[0027] like Figure 1As shown in (b), the first buffer layer 301-1 is located between the p-side electrode 106 and the upper surface 100t of the substrate and between the n-side electrode 107 and the upper surface 100t of the substrate. The first buffer layer 301-1 is disposed on the upper surface 100t of the substrate in contact with the upper surface 100t of the substrate. The first buffer layer 301-1 is, for example, an n-type GaAs layer.

[0028] The multilayer film portion 310 is located between the p-side electrode 106 and the first buffer layer 301-1 and between the n-side electrode 107 and the first buffer layer 301-1. The multilayer film portion 310 is disposed on the first buffer layer 301-1 in contact with the first buffer layer 301-1. Regarding the structure of the multilayer film portion 310, Figure 3 It will be described later.

[0029] The second buffer layer 301-2, as Figure 1 shown in (b), includes a first buffer portion 101a and a second buffer portion 101b. The first buffer portion 101a and the second buffer portion 101b are arranged along the X direction and are continuous with the second buffer portion 101b. The first buffer portion 101a is located between the n-side electrode 107 and the multilayer film portion 310. The second buffer portion 101b is located between the p-side electrode 106 and the multilayer film portion 310. The second buffer layer 301-2 (the first buffer portion 101a and the second buffer portion 101b) is disposed on the multilayer film portion 310 in contact with the multilayer film portion 310. The second buffer layer 301-2 is, for example, an n-type GaAs layer.

[0030] The n-type cladding layer 102 is located between the second buffer portion 101b and the p-side electrode 106. The n-type cladding layer 102 is disposed on the second buffer portion 101b in contact with the second buffer portion 101b. The n-type cladding layer 102 contains aluminum gallium arsenide mixed crystal (hereinafter, AlGaAs) represented by the composition formula Al Y Ga 1-Y As (0 < Y < 1). For example, for the n-type cladding layer 102, Al 0.5 Ga 0.5 As can be used.

[0031] The light-emitting layer 103 (active layer) is located between the n-type cladding layer 102 and the p-side electrode 106. The light-emitting layer 103 is disposed on the n-type cladding layer 102 in contact with the n-type cladding layer 102. The position of the light-emitting layer 103 is higher than that of the multilayer film portion 310. That is, at least a part of the multilayer film portion 310 is located between the light-emitting layer 103 and the first buffer layer 301-1. Regarding an example of the structure of the light-emitting layer 103, Figure 2 It will be described later.

[0032] The p-type cladding layer 104 is located between the light emitting layer 103 and the p-side electrode 106. The p-type cladding layer 104 is provided on the light emitting layer 103 in such a manner as to be in contact with the light emitting layer 103. The p-type cladding layer 104 includes AlGaAs. For example, Al 0.5 Ga 0.5 As.

[0033] The p-type contact layer 105 is located between the p-type cladding layer 104 and the p-side electrode 106. The p-type contact layer 105 is provided on the p-type cladding layer 104 so as to be in contact with the p-type cladding layer 104. The p-type contact layer 105 is, for example, a p-type GaAs layer.

[0034] It should be noted that the n-type GaAs (semiconductor substrate 100, first buffer layer 301-1, second buffer layer 301-2) and n-type cladding layer 102 contain n-type impurities. For example, the n-type impurities include at least one of silicon (Si), selenium (Se), and germanium (Ge). The p-type cladding layer 104 and p-type contact layer 105 contain p-type impurities. For example, the p-type impurities include at least one of beryllium (Be), magnesium (Mg), and zinc (Zn).

[0035] The p-side electrode 106 is provided on the p-type contact layer 105 so as to be in contact with the p-type contact layer 105. The p-side electrode 106 is made of a metal material such as gold, titanium, aluminum, or copper.

[0036] The n-side electrode 107 is provided on the first buffer portion 101a so as to be in contact with the first buffer portion 101a. The n-side electrode 107 is made of a metal material such as gold, titanium, aluminum, or copper.

[0037] In this way, the p-side electrode 106 and the n-side electrode 107 are formed on the upper surface side of the semiconductor light emitting device 1. The semiconductor light emitting device 1 radiates light from the light emitting layer 103 from the surface opposite to the p-side electrode 106 and the n-side electrode 107. The lower surface of the semiconductor light emitting device 1 (substrate lower surface 100s) is a light extraction surface.

[0038] The p-side electrode 106 is, for example, an electrode for current injection. If a bias voltage is applied to the p-side electrode 106 and the n-side electrode 107, the current injected from the p-side electrode 106 flows into the light-emitting layer 103. As a result, the light-emitting layer 103 emits light. The light from the light-emitting layer 103 passes through the second buffer layer 301-2, the multilayer film portion 310, the first buffer layer 301-1, and the semiconductor substrate 100, and is radiated to the outside from the lower surface of the semiconductor light-emitting device 1. As described above, the embodiment is a semiconductor light-emitting device that performs light irradiation from a surface different from the surface on which the current injection electrode is formed.

[0039] Figure 2It is a schematic cross-sectional view of a light-emitting layer of a semiconductor light-emitting device illustrating an embodiment.

[0040] The light-emitting layer 103 has, for example, a multi-quantum well structure (Multi-Quantum Well: MQW). The light-emitting layer 103 includes a plurality of quantum well layers 103a and a plurality of barrier layers 103b. The quantum well layers 103a and the barrier layers 103b are alternately stacked in the Z direction. The quantum well layer 103a is located between adjacent barrier layers 103b.

[0041] The light-emitting layer 103 is, for example, an InGaAs / AlGaAsP-based MQW active layer. That is, the quantum well layer 103a contains, for example, indium gallium arsenide mixed crystal represented by the composition formula In X Ga 1-X As (0 < X < 1) (hereinafter, InGaAs). For example, for the quantum well layer 103a, In 0.2 Ga 0.8 As can be used. The barrier layer 103b contains, for example, aluminum gallium arsenide phosphide mixed crystal represented by the composition formula Al x Ga 1-x As 1-y P y (0 < x < 1, 0 < y < 1) (hereinafter, AlGaAsP). For example, for the barrier layer 103b, Al 0.15 Ga 0.85 As 0.9 P 0.1 .

[0042] For example, the light-emitting layer 103 is set to emit light with a wavelength of 950 nanometers (nm).

[0043] Figure 3 (a) and Figure 3 (b) are schematic views of a multilayer film portion of a semiconductor light-emitting device illustrating an embodiment.

[0044] Figure 3 (a) is a schematic cross-sectional view of the multilayer film portion 310. The multilayer film portion 310 includes a first semiconductor layer 310a and a second semiconductor layer 310b. Figure 3 (b) is a schematic plan view of one (second layer 20) of the second semiconductor layer 310b viewed from above. For example, a plurality of the first semiconductor layers 310a are provided, and a plurality of the second semiconductor layers 310b are provided.

[0045] Each first semiconductor layer 310a contains a first semiconductor material. The first semiconductor material is, for example, AlGaAs. Each second semiconductor layer 310b contains a second semiconductor material. The second semiconductor material is, for example, InGaAs. As Figure 3As shown in (a), the first semiconductor layer 310a is provided on the second semiconductor layer 310b in a manner of contacting the second semiconductor layer 310b. In this example, the first semiconductor layer 310a and the second semiconductor layer 310b are alternately stacked in the Z direction. The multilayer film portion 310 is, for example, an InGaAs / AlGaAs periodic layer in which InGaAs layers and AlGaAs layers are alternately (periodically) stacked.

[0046] like Figure 3 As shown in (a), the plurality of first semiconductor layers 310a include the first layer 10. In other words, the first layer 10 is one of the first semiconductor layers 310a. The first layer 10 is the layer located at the bottom of the plurality of first semiconductor layers 310a. The first layer 10 is provided on the first buffer layer 301-1 in such a manner as to be in contact with the first buffer layer 301-1. The first layer 10 has a first surface 10u. The first surface 10u is an upper surface on the opposite side of the lower surface in contact with the first buffer layer 301-1.

[0047] The plurality of second semiconductor layers 310b include the second layer 20. In other words, the second layer 20 is one of the second semiconductor layers 310b. The second layer 20 is provided on the first surface 10u of the first layer 10 in such a manner as to be in contact with the first surface 10u. That is, the second layer 20 is located between the first surface 10u of the first layer 10 and the light emitting layer 103. The second layer 20 has a second surface 20u. The second surface 20u is an upper surface on the opposite side of the lower surface 20s in contact with the first layer 10.

[0048] The first surface 10u is flatter than the second surface 20u. The first layer 10 is, for example, a flat layer. The second surface 20u has larger irregularities than the first surface 10u. The second layer 20 is, for example, a non-flat layer.

[0049] Large concavity (low flatness) corresponds to, for example, a large maximum height Rz or a large arithmetic mean roughness Ra. That is, for example, the maximum height Rz of the second surface 20u is greater than the maximum height Rz of the first surface 10u. It should be noted that the maximum height Rz is the distance along the Z direction between the highest position of the surface (the position closest to the light-emitting layer 103) and the lowest position of the surface (the position closest to the semiconductor substrate 100) within the observation range. Or, for example, the arithmetic mean roughness Ra of the second surface 20u is greater than the arithmetic mean roughness Ra of the first surface 10u.

[0050] like Figure 3 (a) and Figure 3As shown in (b), the upper surface f2 of the second semiconductor layer 310b (for example, the second surface 20u) has a plurality of first inclined surfaces 31 and a plurality of second inclined surfaces 32. The first inclined surfaces 31 and the second inclined surfaces 32 are arranged alternately in the X direction. The first inclined surface 31 is inclined relative to the X direction and the Z direction. The second inclined surface 32 is inclined relative to the X direction and the Z direction. The first inclined surface 31 and the second inclined surface 32 extend in the Y direction. For example, the first inclined surface 31 and the second inclined surface 32 are not inclined relative to the Y direction. Figure 3 As shown in (b), for example, the boundary region between the first inclined surface 31 and the second inclined surface 32 extends along the Y direction.

[0051] For example, the first inclined surfaces 31 are arranged in the X direction at a constant period P. The first inclined surfaces 31 are arranged with respect to the substrate upper surface 100t (see Figure 1 (b)) is tilted at an inclination angle φ.

[0052] like Figure 3 As shown in (a), by repeatedly arranging the first inclined surface 31 and the second inclined surface 32 in the X direction, the thickness (length along the Z direction) of the second semiconductor layer 310b changes in the X direction. On the other hand, the thickness of the first layer 10 does not substantially change along the X direction and is constant. The lower surface of the first layer 10 is flat in the same manner as the upper surface (first surface 10u) of the first layer 10. The lower surface and the upper surface of the first layer 10 extend in the XY plane, for example, substantially parallel to each other.

[0053] It should be noted that the size of the unevenness and the film thickness can be measured by using a transmission electron microscope (TEM). Figure 3 The evaluation is performed by observing a cross section including the direction (e.g., X direction) and the Z direction in which the first inclined surface 31 is repeatedly arranged as shown in (a). The width of the observation range for evaluation is set to a degree that at least one first inclined surface 31 and at least one second inclined surface 32 can be observed as a whole.

[0054] As such, the multilayer film portion 310 includes a first layer 10 (flat layer), and a second layer 20 (non-flat layer) stacked on the first layer 10 and having lower flatness than the first layer 10. That is, the second surface 20u of the second layer 20 has a larger unevenness than the first surface 10u of the first layer 10. By providing such a non-flat layer, the light from the light-emitting layer 103 is refracted and expanded when passing through the multilayer film portion 310. That is, the multilayer film portion 310 functions as a light diffusion layer, for example. Thus, the intensity distribution of light in the light extraction surface can be improved, and the luminous characteristics can be improved. For example, the area with high luminous intensity in the light extraction surface can be expanded, and the light extraction efficiency can be improved.

[0055] For example, the shapes of the flat layer (first layer 10) and the non-flat layer (second layer 20) can be formed by performing crystal growth using a semiconductor substrate having a substrate upper surface 100t inclined with respect to the (100) plane.

[0056] For example, the first buffer layer 301-1, the multilayer film portion 310, the second buffer layer 301-2, the n-type cladding layer 102, the light-emitting layer 103, the p-type cladding layer 104 and the p-type contact layer 105 can be manufactured through a single continuous process by using the semiconductor substrate 100 as a growth substrate and adopting crystal growth based on the metal organic vapor deposition (MOCVD) method.

[0057] In this case, the first layer 10 and the second layer 20 are, for example, single crystals. For example, when the cross section is observed using TEM as described above, the first layer 10 can be regarded as a single crystal when the crystal lattice is not interrupted by a crystal defect or a crystal grain boundary interface and the crystal is connected, and the second layer 20 can be regarded as a single crystal when the crystal lattice is not interrupted by a crystal defect or a crystal grain boundary interface and the crystal is connected. For example, the first surface 10u and the second surface 20u are crystal planes, and the surface orientation of the second surface 20u is different from the surface orientation of the first surface 10u. For example, the surface orientation of the first inclined surface 31 is different from the surface orientation of the first surface 10u. The surface orientation of the second inclined surface 32 is different from the surface orientation of the first surface 10u. In addition, the surface orientation of the first inclined surface 31 is different from the surface orientation of the second inclined surface 32.

[0058] The surface orientation of the first surface 10u may also be the same as the surface orientation of the substrate upper surface 100t of the semiconductor substrate 100. The inclination angle φ of the first inclined surface 31 of the second surface 20u depends on the surface orientation of the substrate upper surface 100t. For example, the first inclined surface 31 extends in a direction parallel to the (100) plane of the semiconductor substrate 100. For example, the inclination angle φ of the first inclined surface 31 is the same as the inclination angle θ of the substrate upper surface 100t. For example, the first inclined surface 31 is the (100) plane. It should be noted that Figure 3 (a) The following Figure 8 In (b), the tilt angle φ is shown enlarged for easier viewing.

[0059] (Example 1)

[0060] Figure 4 , Figure 5 (a) and Figure 5 (b) is an image illustrating a part of the semiconductor light emitting device according to the embodiment.

[0061] Figure 4The cross-sectional TEM image of the layer structure obtained by growing the first buffer layer 301-1, the multilayer film portion 310 (InGaAs / AlGaAs periodic layer), and the second buffer layer 301-2 using a semiconductor substrate 100 whose upper surface 100t, which is the crystal growth surface, is tilted 15° from the (100) plane to the

[011] direction. Here, the multilayer film portion 310 is configured as a five-layer structure of AlGaAs / InGaAs / AlGaAs / InGaAs / AlGaAs. In addition, the InGaAs in the multilayer film portion 310 is 1.5 times the InGaAs / AlGaAs / AlGaAs periodic layer. X Ga 1-X The In composition X of As is set to 0.1, Al Y Ga 1-Y The Al composition Y of As was set to 0.1.

[0062] Various raw materials used in the MOCVD growth of this layer structure can be used, for example, trimethylindium as a Group III raw material: (CH 3 ) 3 In: TMI, trimethylgallium: (CH 3 ) 3 Ga:TMG, trimethylaluminum: (CH 3 ) 3 Al: TMA, for example, arsine as a Group V raw material: AsH 3 , Phosphine: PH 3 In addition, as other growth conditions, the temperature can be set to 700° C. and the pressure can be set to 5 kPa.

[0063] like Figure 4 As shown in , it is known that in InGaAs (contrast white in the figure), the flatness of the film disappears and the film thickness distribution is seen, becoming a shape that depends on the tilt angle of the substrate. Furthermore, the shape that depends on the tilt angle of the substrate has a crystal plane, and this plane is periodically formed. In this way, the single crystallinity of the film in which the flatness disappears and the film thickness distribution is seen is maintained, and no crystal defects are seen in the InGaAs film and in the interface with the AlGaAs on it to damage the stacking of the upper layer. On the other hand, it is also known that although the flatness of AlGaAs is damaged, the film thickness is relatively uniform, and the second buffer layer 301-2 stacked as the upper layer can grow flat. According to the inventor's in-depth experiments, such a shape can be made by reducing the conditions for MOCVD growth, that is, the ratio of the supply amount of the V group raw material to the III group raw material (V / III ratio), and specifically, it can be made by setting the V / III ratio to less than 50.

[0064] Figure 5 (a) and Figure 5 (b) is Figure 4TEM image of a structure in which the inclination angle of the substrate upper surface 100t is changed from 15°. Figure 5 In (a), the inclination angle of the substrate upper surface 100t is 2°. Figure 5 In (b), the inclination angle of the substrate upper surface 100t is 5°.

[0065] It is known that the shape of the multilayer film portion 310 (InGaAs / AlGaAs periodic layer) changes depending on the tilt angle of the substrate. In this way, the shape of the multilayer film portion 310 can be adjusted by the tilt angle of the substrate.

[0066] Figure 6 This is a graph illustrating an example of light emission intensity distribution in a semiconductor light emitting device.

[0067] Figure 7 (a) and Figure 7 (b) is a schematic plan view illustrating the light emission intensity distribution in the semiconductor light emitting device.

[0068] exist Figure 6 , the emission intensity distribution of the semiconductor light emitting device 9 of the reference example and the emission intensity distribution of the semiconductor light emitting device 1a of the embodiment are shown. In the semiconductor light emitting device 9 of the reference example, the multilayer film portion 310 is not provided. Except for this, the semiconductor light emitting device 9 is the same as the semiconductor light emitting device 1 described above.

[0069] When a bias voltage is applied to the p-side electrode 106 and the n-side electrode 107, the current injected from the p-side electrode 106 flows into the light-emitting layer 103, and the light-emitting layer 103 emits light along the shape of the p-side electrode 106. Figure 6 , Figure 7 (a) and Figure 7 (b) shows the emission intensity distribution on the light extraction surface when a bias current of 5 mA is applied. Figure 6 It represents the luminous intensity distribution in the length direction (X direction) of the device structure, and the luminous intensity is normalized. It should be noted that Figure 6 “0” on the horizontal axis is the position of the end of the p-side electrode 106 on the n-side electrode 107 side. Figure 6 The solid line in represents the luminous intensity distribution in the semiconductor light-emitting device 9. In this way, light is emitted along the shape of the p-side electrode 106, but the intensity decreases toward the electrode end. This is because there are components of light emitted directly from the light-emitting layer 103 to the outside of the device and components emitted to the outside of the device after repeated multiple reflections inside the device structure. In addition to the distribution along the shape of the current injection electrode, the luminous intensity distribution on the light extraction surface is determined by the overlap of these light components. Figure 7 (a) is a bottom view of the semiconductor light emitting device 9 which is the light extraction side. Figure 7(a) shows a light emitting region R having a normalized light emission intensity of 0.9 or more. Even in a back-emitting device structure that takes light shielding by electrodes into consideration, the light extraction intensity distribution does not always have substantially the same area as the current injection electrode shape, and improvement is required.

[0070] In view of this, it is considered to process the shape of the light extraction surface, or to add a structure for light diffusion inside the device structure. However, adding these processes will complicate the process of device manufacturing. In addition, it is difficult to change the internal structure of the device through a single manufacturing process, which will increase the workload. Furthermore, as a structure for diffusing light, it is also considered to make a concave-convex shape layer between the light-emitting layer and the light extraction surface, for example, by mechanical processing. However, when crystal defects are generated by the concave-convex shape, it sometimes has an adverse effect on the characteristics of the light-emitting layer.

[0071] In view of this, the inventors conducted repeated and in-depth experiments and found that by using the same material as the device constituent layer and changing the formation method, a non-flat layer can be formed and can be made through a single MOCVD process, so it is useful as a light diffusion layer. Figure 4 As described above, the non-planar layer can be formed using the MOCVD method.

[0072] In About Figure 6 and Figure 7 The semiconductor light emitting device 1a of (b) is different from the semiconductor light emitting device 9 of the reference example in that a multilayer film portion 310 is formed between the first buffer layer 301-1 and the second buffer layer 301-2. In the semiconductor light emitting device 1a, a substrate whose crystal growth plane is inclined 15° from the (100) plane to the

[011] direction is used for the semiconductor substrate 100. Here, by setting the V / III ratio during the growth of the multilayer film portion 310 to 30 and the V / III ratio of the light emitting layer 103 using the same material system to 200, a non-flat layer can be formed in the multilayer film portion 310, and the second buffer layer 301-2 to be the upper layer is buried flatly, so that the light emitting layer 103 can be made into a flat layer. In addition, the number of periods of the multilayer film portion 310 (the number of repeatedly stacked InGaAs layers) is set to 10, and the total film thickness of the thick film portion of InGaAs (the total thickness (d) of the plurality of second semiconductor layers 310b) is set to 160nm.

[0073] The luminous intensity distribution on the light extraction surface when a bias current of 5 mA is applied to the semiconductor light emitting device 1a manufactured in this way is shown in FIG. Figure 6 middle. Figure 6 The dotted line in represents the light emission intensity distribution in the semiconductor light emitting device 1a. Figure 7 (b) is a bottom view of the semiconductor light emitting device 1a, which is the light extraction side. Figure 7(b) shows a light-emitting region R having a normalized light-emitting intensity of 0.9 or more.

[0074] As can be seen from the results, the light extraction area is expanded by adopting the multilayer film portion 310 in the structure. It is believed that this is because when the light emitted from the light-emitting layer 103 passes through the multilayer film portion 310 inside the device structure, the refraction state of the light is different from the structure of the reference example each time it passes through multiple reflections and diffuses. Therefore, in this embodiment, a non-flat layer (InGaAs / AlGaAs periodic layer) that can diffuse light can be made through a single MOCVD growth process, resulting in improved light extraction efficiency. Excellent effects can be obtained from the perspective of productivity and characteristic improvement.

[0075] For example, Figure 3 As shown in FIG. 1 , when a plurality of first semiconductor layers 310a and a plurality of second semiconductor layers 310b are stacked in the multilayer film portion 310, the total thickness of the plurality of second semiconductor layers 310b is greater than the thickness at which the light from the light emitting layer 103 is refracted. For example, when the total thickness of the plurality of second semiconductor layers 310b is set to d, the wavelength of the light from the light emitting layer 103 is set to λ, and the effective refractive index of the second layer 20 at the wavelength (λ) is set to n, it is preferred to satisfy the formula d≥λ / (2n). As a result, the light from the light emitting layer 103 is refracted in the multilayer film portion 310, and the light emitting area is easily expanded.

[0076] Here, if Figure 3 As shown in (a), the plurality of second semiconductor layers 310b include the lowest layer (second layer 20) of the second semiconductor layer 310b closest to the semiconductor substrate 100 and the highest layer (third layer 22) of the second semiconductor layer 310b closest to the light-emitting layer 103. In this case, the total thickness (d) of the plurality of second semiconductor layers 310b is set to be the length along the Z direction between the lower end of the lowest layer (the point of the second layer 20 closest to the substrate) and the upper end of the highest layer (the point of the third layer 22 closest to the light-emitting layer). The total thickness (d) of the plurality of second semiconductor layers 310b is as shown in Figure 3 As shown in (a), this is the thickness of the range including the first semiconductor layer 310a located between the second semiconductor layers 310b. The total thickness (d) of the plurality of second semiconductor layers 310b is, for example, 150 nm or more.

[0077] In the multilayer film portion 310 , the first semiconductor layer 310 a and the second semiconductor layer 310 b are alternately provided in plurality, thereby increasing the number of interfaces between the first semiconductor layer 310 a and the second semiconductor layer 310 b . This allows, for example, light from the light emitting layer 103 to be diffused by refraction at the interface.

[0078] In addition, as regards Figure 3(a) As described above, the second surface 20u of the second layer 20 has, for example, a crystal plane with a different plane orientation from the first surface 10u of the first layer 10. The second layer 20 is, for example, a single crystal. In addition, for example, the inclination angle φ of the first inclined surface 31 of the second layer 20 is Figure 3 (a)) depends on the inclination angle θ of the semiconductor substrate 100 ( Figure 1 (b)). For example, the tilt angle φ is the same as the tilt angle θ. Such shapes of the first layer 10 and the second layer 20 can be formed by crystal growth. Compared with the case where a concave-convex shape is made in the device by etching or machining, the generation of crystal defects can be suppressed.

[0079] (Example 2)

[0080] Figure 8 (a) and Figure 8 (b) is a schematic cross-sectional view illustrating a semiconductor light emitting device according to an embodiment.

[0081] Figure 8 (a) shows a semiconductor light emitting device 2 according to an embodiment. Figure 8 (b) shows the structure of the multilayer film portion 310 of the semiconductor light emitting device 2. The difference between the structure of the semiconductor light emitting device 2 and the semiconductor light emitting device 1 is that the multilayer film portion 310 (InGaAs / AlGaAs periodic layer) is made into a two-layer structure combining each single layer of AlGaAs / InGaAs, and the film thickness D of the thick film portion of the InGaAs layer is set to 150nm. That is, the multilayer film portion 310 in the embodiment can also be a two-layer structure having only two layers, the first layer 10 and the second layer 20. The film thickness D is the distance in the Z direction between the upper end and the lower end of the second layer 20 (InGaAs layer), that is, the maximum length in the Z direction.

[0082] In the semiconductor light emitting device 2, the number of interfaces of the non-flat surface is reduced compared to the semiconductor light emitting device 1. However, even in this case, compared with the semiconductor light emitting device 9 of the reference example, the light from the light emitting layer 103 is refracted through the non-flat layer, i.e., the second layer 20, and the effect of expanding the light emitting area in the light extraction surface can be obtained. It is further known that when the present structure is adopted, the structure becomes flat when only a single InGaAs layer is used, and sometimes no effect is obtained. Therefore, it is known that in order to obtain a non-flat layer, it is preferred to set a mixed crystal layer containing Al (here, an AlGaAs layer) as a substrate. It is believed that this is because, for example, the Al mixed crystal layer produced under growth conditions with a relatively low V / III ratio has the effect of transmitting the inclined state of the crystal surface orientation to the upper layer.

[0083] For example, when the multilayer film portion 310 is a two-layer structure of the first layer 10 and the second layer 20, when the thickness of the multilayer film portion 310 is set to d1, the wavelength of the light from the light-emitting layer 103 is set to λ, and the effective refractive index of the second layer 20 at the wavelength (λ) is set to n, it is preferable to satisfy the formula d1≥λ / (2n). Thus, the light from the light-emitting layer 103 is refracted in the multilayer film portion 310, and the light-emitting area is easily expanded.

[0084] Here, the thickness (d1) of the multilayer film portion 310 in the case of a two-layer structure is set to the length along the Z direction between the lower end of the first layer 10 (the point of the first layer 10 closest to the substrate) and the upper end of the second layer 20 (the point of the second layer 20 closest to the light-emitting layer). The thickness (d1) of the multilayer film portion 310 in the case of a two-layer structure is, for example, 150 nm or more.

[0085] It should be noted that the embodiments of the present invention are not limited to the above-described situations. The tilt direction of the surface orientation of the semiconductor substrate 100 is set to

[011] , but is not limited thereto, and the same effect can be obtained as long as it is an orientation equivalent thereto. For example, the substrate upper surface 100t of the semiconductor substrate 100 is tilted relative to the (100) face of the cubic crystal of GaAs toward any one of the

[011] direction, [01-1] direction, [0-1-1] direction, and [0-11] direction of the cubic crystal. For example, the direction perpendicular to the substrate upper surface 100t can be a direction in which the

[100] direction is tilted toward any one of the

[011] direction, [01-1] direction, [0-1-1] direction, and [0-11] direction by an inclination angle θ.

[0086] The tilt angle θ may be any angle at which the flatness of the InGaAs layer of the multilayer film portion 310 is impaired. Figure 4 , Figure 5 (a) and Figure 5 As shown in (b), the shape depending on the tilt angle can be adjusted. However, if the tilt angle θ exceeds 25°, for example, sometimes the crystal growth itself is adversely affected and defects are induced in the growth process of the device constituent layer, thereby degrading the characteristics. Therefore, the tilt angle θ is preferably greater than 1° and less than 25°. However, the embodiment is not necessarily limited to this.

[0087] Furthermore, in the above-described embodiment, the In composition of the InGaAs layer of the multilayer film portion 310 is set to 0.1, but this is not limited thereto, and a composition that becomes transparent to the light emitted from the light emitting layer 103 may be selected.

[0088] Fig. 9 is a schematic cross-sectional view illustrating a semiconductor light emitting device according to an embodiment.

[0089] Fig. 9The semiconductor light emitting device 3 of the embodiment shown in FIG. 1 is different from the semiconductor light emitting devices 1 and 2 described above in the configuration of the multilayer film portion 310. In the semiconductor light emitting device 3, no Figure 1 (b) and the like, a buffer layer 301 is provided instead of the first buffer layer 301 - 1 and the second buffer layer 301 - 2 . The multilayer film portion 310 is provided on the buffer layer 301 .

[0090] The buffer layer 301 is provided on the substrate upper surface 100t of the substrate 100 in such a manner as to be in contact with the substrate upper surface 100t. The buffer layer 301 is, for example, an n-type GaAs layer. The buffer layer 301 includes a first portion 301a provided between the substrate upper surface 100t and the n-side electrode 107 and a second portion 301b provided between the substrate upper surface 100t and the p-side electrode 106. The first portion 301a and the second portion 301b are arranged in the X direction. The second portion 301b is thicker than the first portion 301a. A height difference is provided on the upper surface of the buffer layer 301 (the surface on the opposite side to the substrate 100).

[0091] The multilayer film portion 310 is located between the second portion 301b of the buffer layer 301 and the p-side electrode 106. The multilayer film portion 310 is provided on the second portion 301b of the buffer layer 301 in such a manner as to be in contact with the second portion 301b. The multilayer film portion 310 is not provided between the buffer layer 301 and the n-side electrode 107. In other words, the multilayer film portion 310 is not provided on the first portion 301a.

[0092] The multilayer film portion 310 is related to Figure 3 (a) or Figure 8 (b) and the multilayer film portion 310 described above. That is, the multilayer film portion 310 is a first semiconductor layer 310a (see Figure 3 (a)) and the second semiconductor layer 310b (refer to Figure 3 (a)) is a structure formed by stacking layers. The multilayer film portion 310 includes a first layer 10 (see Figure 3 (a))) and the second layer 20 as a non-planar layer ((refer to Figure 3 (a))). However, in this example, the first layer 10 is stacked on the buffer layer 301.

[0093] The n-type cladding layer 102, the light emitting layer 103, the p-type cladding layer 104, and the p-type contact layer 105 are located between the multilayer film portion 310 and the p-side electrode 106. The n-type cladding layer 102 is provided on the multilayer film portion 310 in such a manner as to be in contact with the multilayer film portion 310. As in the above-mentioned semiconductor light emitting device 1, etc., the light emitting layer 103, the p-type cladding layer 104, the p-type contact layer 105, and the p-side electrode 106 are stacked on the n-type cladding layer 102. The n-side electrode 107 is provided on the first portion 301a of the buffer layer 301 in such a manner as to be in contact with the first portion 301a.

[0094] If a bias voltage is applied to the p-side electrode 106 and the n-side electrode 107, the current injected from the p-side electrode 106 flows into the light-emitting layer 103, and the light-emitting layer 103 emits light. The light from the light-emitting layer 103 passes through the multilayer film portion 310, the buffer layer 301, and the semiconductor substrate 100, and is radiated to the outside from the lower surface of the semiconductor light-emitting device 3.

[0095] In the semiconductor light emitting device 3, the buffer layer need not be stacked on the multilayer film portion 310. Therefore, in manufacturing the semiconductor light emitting device, the load on the device for forming the buffer layer can be reduced. For example, the manufacturing cost can be reduced.

[0096] The current injected from the p-side electrode 106 flows to the n-side electrode 107 via the light-emitting layer 103, the n-type cladding layer 102, the multilayer film portion 310, and the buffer layer 301. That is, the multilayer film portion 310 exists in the path of the current flowing between the p-side electrode 106 and the n-side electrode 107. Therefore, for example, n-type impurities are doped in the multilayer film portion 310. That is, in the semiconductor light-emitting device 3, the multilayer film portion 310 has n-type conductivity. Thus, the conductivity is ensured and the increase of the operating voltage is suppressed.

[0097] In the multilayer film portion 310, for example, an InGaAs layer and an AlGaAs layer are stacked. For example, the multilayer film portion 310 is an InGaAs / AlGaAs periodic layer formed by alternately stacking an InGaAs layer and an AlGaAs layer. It is effective to dope the InGaAs layer and the AlGaAs layer with a suitable n-type impurity concentration. That is, the activation rate of the doped impurities in the InGaAs layer and the AlGaAs layer is different due to the different band gaps. Therefore, in order to obtain the same effective carrier concentration, impurities of different concentrations are doped. Specifically, the impurity doping concentration in the AlGaAs layer with a large band gap is higher than the impurity doping concentration in the InGaAs layer with a small band gap.

[0098] For example, the concentration of n-type impurities contained in the InGaAs layer is 1×10 17 atoms / cm 3 Above, preferably 3×10 17 atoms / cm3 For example, the concentration of n-type impurities contained in the AlGaAs layer is 1×10 17 atoms / cm 3 Above, preferably 3×10 17 atoms / cm 3 As a result, the influence on the operating voltage can be suppressed. The n-type impurity is, for example, at least one of Si, Se, and Ge.

[0099] It should be noted that in Figure 1 In the structure described in (b), the current flowing between the p-side electrode 106 and the n-side electrode 107 passes through the light-emitting layer 103, the n-type cladding layer 102, and the second buffer layer 301-2. Figure 1 In the structure of (b), the current flowing between the p-side electrode 106 and the n-side electrode 107 may not pass through the multilayer film portion 310. In this case, the multilayer film portion 310 may not be doped with n-type impurities. Figure 1 In the structure of (b), the resistivity of the multilayer film portion 310 is higher than the resistivity of the second buffer layer 301-2, and higher than the resistivity of the substrate 100. Figure 1 In the structure (b), since the multilayer film portion 310 with a relatively high resistivity is arranged directly below the second buffer layer 301-2, when the second buffer layer 301-2 is thin, the path of the current in the second buffer layer 301-2 becomes narrower. As a result, the resistance between the p-side electrode 106 and the n-side electrode 107 becomes larger. On the other hand, in Fig. 9 In the structure, the substrate 100 is arranged directly below the buffer layer 301. A part of the current may flow between the p-side electrode 106 and the n-side electrode 107 via the substrate 100. Thus, for example, an increase in resistance between the p-side electrode 106 and the n-side electrode 107 can be suppressed. For example, an increase in the operating voltage of the semiconductor light emitting device can be suppressed.

[0100] Fig.10 (a)~ Fig.10 (e) is a schematic cross-sectional view illustrating a method for manufacturing a semiconductor light-emitting device according to an embodiment.

[0101] The method for manufacturing the semiconductor light-emitting devices 1 and 2 includes a stacking step of continuously forming a stacked body including a first buffer layer 301-1, a multilayer film portion 310, a second buffer layer 301-2, an n-type cladding layer 102, a light-emitting layer 103, a p-type cladding layer 104, and a p-type contact layer 105 on a semiconductor substrate 100 by a single MOCVD method. For example, the stacked body from the first buffer layer 301-1 at the lower layer to the p-type contact layer 105 at the upper layer is formed without taking the semiconductor substrate 100 out of the chamber.

[0102] The above-mentioned lamination process includes supplying a first raw material gas containing a group V element and a second raw material gas containing a group III element. For example, in the raw material gas containing the first raw material gas and the second raw material gas, a V / III ratio is defined. The V / III ratio is the ratio of the number of atoms of the group V element supplied per unit time to the number of atoms of the group III element supplied per unit time. Each layer is formed by appropriately changing the ratio of the raw material gas.

[0103] like Fig.10 As shown in (a), a first buffer layer 301-1 is formed on a semiconductor substrate 100. Fig.10 As shown in (b), the multilayer film portion 310 is formed in a state where the V / III ratio is reduced compared to when the first buffer layer 301-1 is formed. Fig.10 As shown in (c), the second buffer layer 301-2, the n-type cladding layer 102, the light-emitting layer 103, the p-type cladding layer 104 and the p-type contact layer 105 are stacked in sequence in a state where the V / III ratio is increased compared to when the multilayer film portion 310 is formed. Fig.10 (a)~ Fig.10 The steps up to (c) are performed as a single crystal growth using the MOCVD method. The raw materials and growth conditions in the MOCVD method are, for example, as described in Figure 4 As already described.

[0104] Afterwards, if Fig.10 As shown in (d), the n-type cladding layer 102, the light emitting layer 103, the p-type cladding layer 104, and a portion of the p-type contact layer 105 are removed by etching, for example, to expose the first buffer portion 101a of the second buffer layer 301-2. Fig.10 As shown in (e), an n-side electrode 107 is formed on the first buffer portion 101a, and a p-side electrode 106 is formed on the p-type contact layer 105, for example, by sputtering.

[0105] As such, the multilayer film portion 310 can be made by a single MOCDV continuous process that is the same as other device constituent layers. Thus, a light-emitting device with high productivity can be realized. In addition, for example, the light-emitting layer 103 and the multilayer film portion 310 (the first layer 10 and the second layer 20) are of the same material system. That is, for example, the light-emitting layer 103 contains the same group V element as the group V element contained in the second layer 20 and the same group III element as the group III element contained in the first layer 10. By using the same material system, productivity can be improved.

[0106] about Fig. 9The semiconductor light-emitting device 3 described above can also be formed by the same manufacturing method as described above. That is, the manufacturing method of the semiconductor light-emitting device 3 includes a stacking step of continuously forming a stacked body including a buffer layer 301, a multilayer film portion 310, an n-type cladding layer 102, a light-emitting layer 103, a p-type cladding layer 104, and a p-type contact layer 105 on a semiconductor substrate 100 by a single MOCVD method. In the manufacture of the semiconductor light-emitting device 3, a buffer layer 301 is formed on a semiconductor substrate 100. Thereafter, the multilayer film portion 310 is formed in a state where the V / III ratio is reduced compared to when the buffer layer 301 is formed. Thereafter, the n-type cladding layer 102, the light-emitting layer 103, the p-type cladding layer 104, and the p-type contact layer 105 are stacked in sequence in a state where the V / III ratio is increased compared to when the multilayer film portion 310 is formed. Thereafter, the multilayer film portion 310, the n-type cladding layer 102, the light-emitting layer 103, the p-type cladding layer 104, and a portion of the p-type contact layer 105 are removed, for example, by etching, to expose the first portion 301a of the buffer layer 301. An n-side electrode 107 is formed on the first portion 301a, and a p-side electrode 106 is formed on the p-type contact layer 105.

[0107] The embodiments may also include the following aspects.

[0108] (Solution 1) A semiconductor light emitting device comprising:

[0109] Luminescent layer;

[0110] A semiconductor substrate comprising cubic gallium arsenide (GaAs), having a substrate lower surface and a substrate upper surface located between the light emitting layer and the substrate lower surface and inclined relative to a (100) plane of the cubic crystal; and

[0111] A multilayer film portion, the multilayer film portion includes a first layer and a second layer, the first layer is located between the upper surface of the above-mentioned substrate and the above-mentioned light-emitting layer, and has a first surface, the second layer is located between the above-mentioned first surface and the above-mentioned light-emitting layer, is in contact with the above-mentioned first surface extending along a plane parallel to the upper surface of the above-mentioned substrate, and has a second surface on the opposite side of the surface in contact with the above-mentioned first surface, the concavity and convexity of the above-mentioned second surface is larger than that of the above-mentioned first surface, and light from the above-mentioned light-emitting layer is radiated after passing through the above-mentioned multilayer film portion.

[0112] (Scheme 2) A semiconductor light emitting device according to scheme 1, wherein:

[0113] The multilayer film portion comprises:

[0114] a plurality of first semiconductor layers, including the first layer, each comprising a first semiconductor material; and

[0115] A plurality of second semiconductor layers, which are alternately stacked with the plurality of first semiconductor layers, include the second layer and each include a second semiconductor material.

[0116] (Solution 3) The semiconductor light-emitting device according to Solution 1 or 2, wherein

[0117] The second surface has a crystal plane with a surface orientation different from that of the first surface.

[0118] (Solution 4) The semiconductor light-emitting device according to Solution 3, wherein

[0119] The second layer is a single crystal.

[0120] (Solution 5) The semiconductor light-emitting device according to any one of Solutions 1 to 4, wherein

[0121] The first layer contains at least aluminum,

[0122] The second layer contains indium gallium arsenide (InGaAs) represented by the composition formula In x Ga 1-x As (0 < x < 1).

[0123] (Solution 6) The semiconductor light-emitting device according to Solution 2, wherein

[0124] The plurality of second semiconductor layers include the lowermost layer closest to the semiconductor substrate among the plurality of second semiconductor layers and the uppermost layer closest to the light-emitting layer among the plurality of second semiconductor layers,

[0125] When the distance in the Z direction from the lower end of the lowermost layer to the upper end of the uppermost layer, along the direction from the semiconductor substrate toward the light-emitting layer, is set as d, the wavelength of the light from the light-emitting layer is set as λ, and the effective refractive index of the second layer at the above wavelength is set as n, the formula d ≥ λ / (2·n) is satisfied.

[0126] (Solution 7) The semiconductor light-emitting device according to Solution 1, wherein

[0127] The multilayer film portion has a two-layer structure of the first layer and the second layer,

[0128] When the thickness of the multilayer film portion is set as d1, the wavelength of the light from the light-emitting layer is set as λ, and the effective refractive index of the second layer at the above wavelength is set as n, the formula d1 ≥ λ / (2·n) is satisfied.

[0129] (Solution 8) The semiconductor light-emitting device according to any one of Solutions 1 to 7, wherein

[0130] The upper surface of the substrate is inclined toward any one of the

[011] direction, the [01-1] direction, the [0-1-1] direction, and the [0-11] direction of the cubic crystal relative to the (100) plane of the cubic crystal.

[0131] (Scheme 9) A semiconductor light emitting device according to any one of schemes 1 to 8, wherein:

[0132] The substrate upper surface is inclined at an angle of not less than 1° and not more than 25° relative to the (100) plane of the semiconductor substrate.

[0133] (Scheme 10) A semiconductor light emitting device according to any one of schemes 1 to 9, wherein:

[0134] The second surface has a first inclined surface inclined relative to the upper surface of the substrate,

[0135] An inclination angle of the first inclined surface relative to the upper surface of the substrate is the same as an inclination angle of the upper surface of the substrate relative to the (100) plane.

[0136] (Scheme 11) A method for manufacturing a semiconductor light emitting device,

[0137] The method comprises the following steps: forming a multilayer film portion and a light-emitting layer by a single metal organic vapor phase epitaxy method on an upper surface of a semiconductor substrate including cubic gallium arsenide (GaAs) and having an upper surface of the substrate inclined relative to a (100) plane of the cubic crystal;

[0138] The multilayer film portion includes a first layer and a second layer, wherein the first layer is located above the upper surface of the substrate and has a first surface extending along a plane parallel to the upper surface of the substrate, and the second layer is disposed on the first surface and in contact with the first surface and has a second surface on the opposite side of the surface in contact with the first surface.

[0139] The second surface has a larger concavity than the first surface.

[0140] The light emitting layer is located above the multi-layer film portion.

[0141] (Scheme 12) The manufacturing method according to Scheme 11, wherein

[0142] The second layer contains group V elements and group III elements.

[0143] The light emitting layer includes the same group V element as the group V element of the second layer and the same group III element as the group III element of the second layer.

[0144] (Scheme 13) The manufacturing method according to Scheme 11 or 12, wherein

[0145] The V / III ratio in the growth of the multilayer film portion is lower than the V / III ratio in the growth of the light-emitting layer.

[0146] According to the embodiment, a semiconductor light emitting device capable of improving light emitting characteristics can be provided.

[0147] In the present application specification, “perpendicular” and “parallel” do not only mean strictly perpendicular or strictly parallel, but also include, for example, variations in the manufacturing process, as long as they are substantially perpendicular or substantially parallel.

[0148] Several embodiments of the present invention are illustrated above, but these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other ways, and various omissions, substitutions, changes, etc. can be made without departing from the scope of the main purpose of the invention. These embodiments and their modifications are included in the scope and main purpose of the invention, and are also included in the invention described in the claims and their equivalents. In addition, the above-mentioned embodiments can be implemented in combination with each other.

[0149] Explanation of symbols

[0150] 1, 1a, 2, 3, 9: Semiconductor light-emitting device

[0151] 10: Layer 1

[0152] 10u: Side 1

[0153] 20: Layer 2

[0154] 20u: Side 2

[0155] 22: Layer 3

[0156] 31: 1st inclined surface

[0157] 32: Second inclined surface

[0158] 100: Semiconductor substrate

[0159] 100s: bottom surface of substrate

[0160] 100t: upper surface of substrate

[0161] 101a: 1st buffer section

[0162] 101b: 2nd buffer section

[0163] 102: n-type cladding

[0164] 103: Luminous layer

[0165] 103a: Quantum well layer

[0166] 103b: Barrier layer

[0167] 104: p-type cladding

[0168] 105: p-type contact layer

[0169] 106: p-side electrode

[0170] 107: n-side electrode

[0171] 301: Buffer layer

[0172] 301a: Part 1

[0173] 301b: Part 2

[0174] 301-1: 1st buffer layer

[0175] 301-2: 2nd buffer layer

[0176] 310: Multilayer Film Department

[0177] 310a: 1st semiconductor layer

[0178] 310b: Second semiconductor layer

[0179] D: film thickness

[0180] P: Period

[0181] R: Luminous area

[0182] f2: upper surface

[0183] θ: Tilt angle

[0184] φ: Tilt angle

Claims

1. A semiconductor light emitting device comprising: Luminescent layer; A semiconductor substrate comprising cubic gallium arsenide (GaAs), having a substrate lower surface and a substrate upper surface located between the light emitting layer and the substrate lower surface and inclined relative to the (100) plane of the cubic crystal; and A multilayer film portion, the multilayer film portion includes a first layer and a second layer, the first layer is located between the upper surface of the substrate and the light-emitting layer, and has a first surface extending along a plane parallel to the upper surface of the substrate, the second layer is located between the first surface and the light-emitting layer, is in contact with the first surface, and has a second surface on the opposite side of the surface in contact with the first surface, the second surface has a larger concave-convexity than the first surface, and light from the light-emitting layer is radiated after passing through the multilayer film portion.

2. The semiconductor light emitting device according to claim 1, wherein: The multilayer film portion comprises: a plurality of first semiconductor layers, including the first layer, each comprising a first semiconductor material; and The plurality of second semiconductor layers are alternately stacked with the plurality of first semiconductor layers, include the second layers, and each includes a second semiconductor material.

3. The semiconductor light emitting device according to claim 1 or 2, wherein: The second surface has a crystal plane having a different plane orientation from that of the first surface.

4. The semiconductor light emitting device according to claim 3, wherein: The second layer is single crystal.

5. The semiconductor light emitting device according to claim 1 or 2, wherein: The first layer contains at least aluminum, The second layer comprises a composition formula In x Ga 1-x Indium gallium arsenide represented by As is InGaAs. In the composition formula, 0 <x<1。 6. The semiconductor light emitting device according to claim 2, wherein: The plurality of second semiconductor layers include a lowermost layer among the plurality of second semiconductor layers that is closest to the semiconductor substrate and an uppermost layer among the plurality of second semiconductor layers that is closest to the light emitting layer. When the distance between the lower end of the lowermost layer and the upper end of the uppermost layer along the Z direction from the semiconductor substrate toward the light-emitting layer is set to d, the wavelength of light from the light-emitting layer is set to λ, and the effective refractive index of the second layer at the wavelength is set to n, the equation d≥λ / (2·n) is satisfied.

7. The semiconductor light emitting device according to claim 1, wherein: The multilayer film portion is a two-layer structure of the first layer and the second layer, When the thickness of the multilayer film portion is set to d1, the wavelength of light from the light emitting layer is set to λ, and the effective refractive index of the second layer at the wavelength is set to n, the equation d1≥λ / (2·n) is satisfied.

8. The semiconductor light emitting device according to claim 1 or 2, wherein: The upper surface of the substrate is inclined toward any one of the [011] direction, the [01-1] direction, the [0-1-1] direction, and the [0-11] direction of the cubic crystal relative to the (100) plane of the cubic crystal.

9. The semiconductor light emitting device according to claim 1 or 2, wherein: The upper surface of the substrate is inclined at a degree of not less than 1° and not more than 25° with respect to the (100) plane of the semiconductor substrate.

10. The semiconductor light emitting device according to claim 1 or 2, wherein: The second surface has a first inclined surface inclined relative to the upper surface of the substrate, An inclination angle of the first inclined surface relative to the upper surface of the substrate is the same as an inclination angle of the upper surface of the substrate relative to the (100) plane.

11. A method for manufacturing a semiconductor light-emitting device, comprising the steps of: forming a multilayer film portion and a light-emitting layer by a single metal organic vapor phase epitaxy method on an upper surface of a semiconductor substrate including cubic gallium arsenide (GaAs) and having an upper surface of the substrate inclined relative to a (100) plane of the cubic crystal; The multilayer film portion includes a first layer and a second layer, wherein the first layer is located above the upper surface of the substrate and has a first surface extending along a plane parallel to the upper surface of the substrate, and the second layer is disposed on the first surface and in contact with the first surface and has a second surface on the opposite side of the surface in contact with the first surface. The second surface has a larger concavity and convexity than the first surface, The light emitting layer is located above the multi-layer film portion.

12. The manufacturing method according to claim 11, wherein: The second layer contains a group V element and a group III element, The light emitting layer includes the same group V element as the group V element of the second layer and the same group III element as the group III element of the second layer.

13. The manufacturing method according to claim 11 or 12, wherein: The V / III ratio in the growth of the multilayer film portion is lower than the V / III ratio in the growth of the light-emitting layer.

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