An anti-polarity LED chip and a manufacturing method thereof

Abstract

The present invention relates to the field of semiconductor technology, and particularly relates to an inverted-polarity LED chip and a manufacturing method thereof. The inverted-polarity LED chip includes a patterned silicon substrate, a mirror covering layer, a silicon dioxide planarization layer, a transparent conductive adhesive layer, a window layer, a P-type stack, a light-emitting layer, and an N-type stack, which are sequentially arranged from bottom to top; the upper surface of the patterned silicon substrate has a plurality of frustum-shaped protrusions; the mirror covering layer covers the entire surface of the patterned silicon substrate on the side with the frustum-shaped protrusions, the lower surface of the silicon dioxide planarization layer is provided with a plurality of through holes, the through holes are sleeved with the convex surface parts of the mirror, and the upper end surface of the convex surface part of the mirror is in direct contact with the lower surface of the transparent conductive adhesive layer and forms an electrical connection. The manufacturing method of the inverted-polarity LED chip provided by the present application has simple manufacturing processes and low manufacturing costs, and the performance of the inverted-polarity LED chip is reliable and stable.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and particularly relates to an inverted-polarity LED chip and a manufacturing method thereof. Background Art

[0002] Inverted-polarity LED chips, designed with a flip-chip structure, can have higher luminous efficiency, and have advantages such as long service life, green energy conservation and environmental protection, and are widely used in daily life, such as initial lighting, traffic signal display, and later outdoor large-screen display and other fields. With the continuous expansion of the application scope and scenarios, higher requirements are put forward for the reliable performance of the chips. At the same time, it is hoped that the manufacturing process of the chips can be simplified as much as possible and the cost can be reduced to meet the customer's demand for low-cost and high-reliability inverted-polarity LED chip products. The present invention aims to realize the manufacture of inverted-polarity LED chips with simple processes, low cost and high reliability. Summary of the Invention

[0003] The purpose of the present invention is to provide an inverted-polarity LED chip and a manufacturing method thereof, which can effectively improve the reliability of the inverted-polarity LED chip, simplify the LED manufacturing process, and realize low-cost chip manufacturing.

[0004] In order to solve the above problems, the technical solution provided by the present invention is:

[0005] The present invention provides an inverted-polarity LED chip, including a patterned silicon substrate, a mirror covering layer, a silicon dioxide planarization layer, a transparent conductive adhesive layer, a window layer, a P-type stack, a light-emitting layer, and an N-type stack, which are sequentially arranged from bottom to top;

[0006] The upper surface of the patterned silicon substrate has a plurality of frustum-shaped protrusions;

[0007] The mirror covering layer covers the entire surface of the patterned silicon substrate on the side with the frustum-shaped protrusions, so that the mirror covering layer forms a mirror flat portion and a mirror convex portion on the patterned silicon substrate;

[0008] The silicon dioxide planarization layer has a plurality of through holes, and the through holes are sleeved with the mirror convex portions, and the upper surface of the silicon dioxide planarization layer is flush with the upper surface of the mirror flat surface;

[0009] The upper end surface of the mirror convex portion is in direct contact with the lower surface of the transparent conductive adhesive layer and forms an electrical connection.

[0010] Further, the chip further includes a front electrode and a back electrode. The front electrode is arranged in the middle of the upper surface of the N-type stack; the back electrode is arranged on the lower surface of the patterned silicon substrate;

[0011] The frustum-shaped protrusions are uniformly distributed around the outer periphery directly below the front electrode.

[0012] Further, the angle between the side wall of the frustum-shaped protrusion and the horizontal line is 30° to 60°.

[0013] Further, the number of the frustum-shaped protrusions is 4 to 20.

[0014] Further, the height of the frustum-shaped protrusion is 4 μm to 10 μm.

[0015] Further, the preparation materials of the mirror covering layer include Ti, Pt, Au, Ti, Pt, and Au which are sequentially evaporated from bottom to top;

[0016] The thickness of the mirror covering layer is 3 μm to 4 μm.

[0017] Further, the preparation materials of the mirror covering layer further include an alumina layer, and the alumina layer is disposed on the surface away from the patterned silicon substrate side; and at least part of the alumina layer is missing from the upper end surface of the frustum-shaped protrusion so that an electrical connection is formed between the mirror covering layer and the transparent conductive adhesive layer;

[0018] The thickness of the alumina layer is 80 Å to 100 Å.

[0019] Further, the preparation materials of the transparent conductive adhesive layer are selected from transparent polymer polyurethanes or polyacrylates containing conductive fillers, and the conductive filler is carbon nanotubes;

[0020] The thickness of the transparent conductive adhesive layer is 1 μm to 1.5 μm.

[0021] Further, the chip further includes a passivation layer, and the passivation layer is disposed to cover the surface of the chip dicing channel.

[0022] The present invention also provides a manufacturing method of the above-mentioned reverse-polarity LED chip, and the manufacturing method includes:

[0023] S1, providing a GaAs substrate as a growth substrate for the reverse-polarity epitaxial structure;

[0024] S2, sequentially growing an N-type stack layer, a light-emitting layer, a P-type stack layer, and a window layer on the GaAs substrate, where the N-type stack layer includes a roughening layer, a current spreading layer, and an N-type confinement layer, to obtain an epitaxial wafer;

[0025] S3, taking a patterned silicon substrate for organic cleaning, and completing the evaporation of the mirror covering layer materials by electron beam evaporation;

[0026] S4. Clean the surface of the mirror coating layer with an organic solution and deposit a SiO2 dielectric film by PECVD;

[0027] S5. Use the CMP method to grind and polish the SiO2 dielectric film until the Au metal is exposed, and complete the preparation of the silica planarization layer;

[0028] S6. Clean the epitaxial wafer with an acid-base solution and spin-coat a transparent conductive adhesive layer on the surface of the epitaxial wafer;

[0029] S7. Stick the transparent conductive adhesive layer of the epitaxial wafer and the Si wafer after CMP together and place them in a pressing fixture to complete the bonding of the two;

[0030] S8. Chemically etch the bonded wafer source to remove the GaAs substrate and expose the N-type stack;

[0031] S9. Complete the production of the front electrode by negative photoresist lithography in cooperation with lift-off and perform high-temperature fusion;

[0032] S10. Use positive photoresist to over-etch to produce the scribe line pattern and etch the scribe line by dry etching;

[0033] S11. Use positive photoresist to over-etch to produce the roughening protection pattern and roughen the surface of the N-type stack by wet etching;

[0034] S12. Deposit the passivation layer material by PECVD and complete the preparation of the passivation layer through photolithography and etching;

[0035] S13. Thin the patterned silicon substrate, fabricate the back electrode, perform laser cutting, and complete the production of the LED die through testing.

[0036] Compared with the prior art, the beneficial effects of the present invention are:

[0037] 1. The deposition of the mirror covering layer is completed by electron beam evaporation directly on the patterned silicon substrate. The pattern of the patterned silicon substrate is adapted to the required P-plane current conduction channel. The SiO2 dielectric film is deposited by PECVD, and then the SiO2 dielectric film is polished by CMP to expose the mirror covering layer on the upper end surface of the frustum-shaped protrusion until the surface Au layer is exposed. The above process does not require wet etching. While achieving surface planarization, the metal on the frustum-shaped protrusion is exposed. By using the spin coating method, a transparent conductive adhesive layer is coated on the surface of the epitaxial wafer, and the epitaxial wafer with the transparent conductive adhesive layer and the Si wafer after CMP are bonded together to complete their bonding. The above operation is simple. The epitaxial wafer and the Si wafer are combined through the transparent conductive adhesive layer to realize the electrical connection between the transparent conductive adhesive layer and the metal of the mirror covering layer. The manufacturing process provided by this application does not require multiple metal depositions, multiple solution corrosions, and wet etching processes in the traditional process, and the process is simple, reliable, and easy to implement.

[0038] 2. The reverse-polarity LED chip structure provided by this application utilizes a patterned silicon substrate with a frustum-shaped protrusion, covers a layer of mirror material according to the shape of the patterned silicon substrate to form a mirror covering layer, and then fills and levels it with a silica leveling layer. This structure uses a patterned silicon substrate covered with a mirror metal layer to achieve direct contact between the mirror covering layer and the transparent conductive adhesive layer. The P-plane current conduction effect is stable and reliable. This structure does not require wet etching for preparation. The interface flatness between the mirror covering layer and the silica leveling layer is high, which is conducive to improving the light reflection.

[0039] 3. In this application, the angle between the side wall of the frustum-shaped protrusion and the horizontal line is 30° to 60°, which is conducive to the uniform deposition of the mirror covering layer on the surface of the frustum-shaped protrusion, obtaining a highly reliable and stable P-plane current conduction effect, and ensuring the flatness of the metal layer on the surface of the frustum-shaped protrusion to ensure a good light reflection effect.

[0040] 4. The materials of the mirror covering layer in this application are selected from Ti, Pt, Au, Ti, Pt, Au, and Al2O3 deposited in sequence by evaporation. It not only has a good light reflection effect but also has stable and reliable performance. Al2O3 can play an adhesion role and enhance the bonding force between the silica leveling layer and the mirror metal material. The transparent conductive adhesive layer has transparency, conductivity, and good bonding effect. It can bond the epitaxial wafer and the Si wafer after CMP together through the transparent conductive adhesive layer to complete their bonding. The epitaxial wafer and the Si wafer are combined through the transparent conductive adhesive layer to realize electrical connection and have good light transmittance. Description of the Drawings

[0041] The accompanying drawings described herein are used to provide a further understanding of the present application and form a part of the present application. The schematic embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation of the present application. In the drawings:

[0042] Figure 1 Schematic diagram of the epitaxial structure of an inverted-polarity LED chip shown in some embodiments of the present application;

[0043] Figure 2 Schematic diagram of the patterned silicon substrate structure shown in some embodiments of the present application;

[0044] Figure 3 Schematic diagram of the structure with a mirror covering layer formed on the patterned silicon substrate shown in some embodiments of the present application;

[0045] Figure 4 Schematic diagram of the structure of another perspective of the mirror covering layer formed on the patterned silicon substrate shown in some embodiments of the present application;

[0046] Figure 5 Schematic diagram of the structure with a silicon dioxide dielectric film formed on the patterned silicon substrate shown in some embodiments of the present application;

[0047] Figure 6 Schematic diagram of the structure with a silicon dioxide planarization layer formed on the patterned silicon substrate shown in some embodiments of the present application;

[0048] Figure 7 Is Figure 6 Partial enlarged schematic diagram of part A in;

[0049] Figure 8 Schematic diagram of the inverted-polarity LED chip structure shown in some embodiments of the present application;

[0050] Figure 9 Schematic diagram of the structure of another perspective of the inverted-polarity LED chip shown in some embodiments of the present application;

[0051] Description of the drawings: 1. GaAs substrate; 2. N-type stack; 3. Light-emitting layer; 4. P-type stack; 5. Window layer; 6. Patterned silicon substrate; 61. Frustum-shaped protrusion; 7. Mirror covering layer; 71. Mirror flat part; 72. Mirror convex part; 73. Mirror metal layer; 74. Aluminum oxide layer; 8. Silicon dioxide planarization layer; 81. Through hole; 9. Transparent conductive adhesive layer; 10. Front electrode; 11. Passivation layer; 12. Back electrode. Detailed Description of the Invention

[0052] The following will clearly and completely describe the technical solutions in the embodiments of the present application with reference to the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. The following description of at least one exemplary embodiment is actually only illustrative and in no way limits the present application and its application or use. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative efforts belong to the scope of protection of the present application.

[0053] Unless otherwise specifically stated, the relative arrangements, numerical expressions, and numerical values of the components and steps set forth in these embodiments do not limit the scope of the present application. At the same time, it should be understood that for the sake of convenience of description, the sizes of the various parts shown in the drawings are not drawn in actual proportional relationships. Technologies, methods, and devices known to those of ordinary skill in the relevant art may not be discussed in detail, but where appropriate, the said technologies, methods, and devices should be regarded as part of the authorization specification. In all the examples shown and discussed here, any specific value should be construed as merely exemplary and not as a limitation. Therefore, other examples of the exemplary embodiments may have different values. It should be noted that like reference numerals and letters denote like items in the following drawings, and thus, once an item is defined in one drawing, it does not need to be further discussed in subsequent drawings.

[0054] In the description of the present application, it should be understood that the use of terms such as "first" and "second" to limit components is only for the convenience of distinguishing the corresponding components. Without further statement, the above terms have no special meanings and thus cannot be construed as limiting the scope of protection of the present application.

[0055] In the description of the present application, it should be understood that the orientation or positional relationships indicated by orientation words such as "front, back, up, down, left, right", "horizontal, vertical, perpendicular, horizontal", and "top, bottom" are usually based on the orientation or positional relationships shown in the drawings. It is only for the convenience of describing the present application and simplifying the description. Without contrary explanation, these orientation words do not indicate and imply that the device or element referred to must have a specific orientation or be constructed and operated in a specific orientation, and thus cannot be construed as limiting the scope of protection of the present application; the orientation words "inside, outside" refer to the inside and outside relative to the contour of each component itself.

[0056] The following further details the present application in conjunction with specific embodiments:

[0057] Embodiment 1

[0058] The reverse-polarity LED chip provided in this embodiment Figure 8 is a schematic structural diagram of the reverse-polarity LED chip shown in some embodiments of the present application;Figure 9 Another perspective structural schematic diagram of the reverse-polarity LED chip shown in some embodiments of the present application; specifically, the structure provided by the present application is as follows. Please refer to Figure 8 and Figure 9 , a reverse-polarity LED chip includes a patterned silicon substrate 6, a mirror covering layer 7, a silica planarization layer 8, a transparent conductive adhesive layer 9, a window layer 5, a P-type stack 4, a light-emitting layer 3, and an N-type stack 2 arranged in sequence from bottom to top; the upper surface of the patterned silicon substrate 6 has a plurality of frustum-shaped protrusions 61 (see Figure 9 shown by the dotted line); the mirror covering layer 7 is covered on the entire surface of the patterned silicon substrate 6 on the side with the frustum-shaped protrusions 61, so that the mirror covering layer 7 forms a mirror flat portion 71 and a mirror convex portion 72 on the patterned silicon substrate 6 (the structure of the mirror flat portion 71 and the mirror convex portion 72 can be further referred to Figure 3 and Figure 4 ); the silica planarization layer 8 has a plurality of through holes 81, the through holes 81 are sleeved with the mirror convex portion 72, and the upper surface of the silica planarization layer 8 is flush with the upper surface of the mirror convex portion 72 (the structure of the through holes 81 and the mirror convex portion 72 can be further referred to Figure 6 ); the upper surface of the mirror convex portion 72 is in direct contact with the lower surface of the transparent conductive adhesive layer 9 and forms an electrical connection.

[0059] For the reverse-polarity LED chip structure provided by the present application, by using the patterned silicon substrate 6 with frustum-shaped protrusions 61, a layer of mirror material is covered according to the shape of the patterned silicon substrate 6 to form the mirror covering layer 7, and then the silica planarization layer 8 is used for filling and planarizing so that the upper end surface of the mirror convex portion 72 is metal-exposed and thus directly contacts the lower surface of the transparent conductive adhesive layer 9, and is used as the P-plane current channel to realize P-plane current conduction. The P-side current conduction channel is directly realized through the patterned silicon substrate 6 covered with the mirror metal layer 73, without the need for wet etching preparation. The P-plane current conduction effect is stable and reliable, the interface flatness between the mirror covering layer 7 and the silica planarization layer 8 is high, and it is beneficial to improve the reflection of light.

[0060] According to some preferred embodiments, the chip further includes a front electrode 10 and a back electrode 12. The front electrode 10 is disposed in the middle of the upper surface of the N-type stack (the front electrode 10 covers a partial area of the upper surface of the N-type stack, the front electrode 10 is disposed at the exact center position of the upper surface of the N-type stack, the shape of the front electrode 10 can be circular, and the periphery outside the covered area of the front electrode 10 is a light-emitting area); the back electrode 12 is disposed on the lower surface of the patterned silicon substrate 6; the frustum-shaped protrusions 61 are evenly distributed around the outside of the lower surface of the front electrode 10, so as to facilitate the uniform distribution of current around the front electrode 10 and avoid the convergence of current below the front electrode 10.

[0061] According to some preferred embodiments, the included angle between the side wall of the frustum-shaped protrusion 61 and the horizontal line is 30° to 60°, so as to facilitate the uniform deposition of the mirror covering layer 7 on the surface of the frustum-shaped protrusion 61, obtain a highly reliable and stable P-side current conduction effect, and at the same time ensure the flatness of the metal layer on the surface of the frustum-shaped protrusion 61 to facilitate a good light reflection effect. As a specific implementation manner, the included angle between the side wall of the frustum-shaped protrusion 61 and the horizontal line is 45°.

[0062] According to some preferred embodiments, the number of the frustum-shaped protrusions 61 is 4 to 20. By setting an appropriate number of frustum-shaped protrusions 61, it is beneficial to obtain a relatively appropriate P-side current conduction effect. As some specific implementation manners, the number of the frustum-shaped protrusions 61 is 12.

[0063] According to some preferred embodiments, the height of the frustum-shaped protrusion 61 is 4 μm to 10 μm.

[0064] According to some preferred embodiments, the preparation materials of the mirror covering layer 7 include Ti, Pt, Au, Ti, Pt, and Au sequentially evaporated from bottom to top; the thickness of the mirror covering layer 7 is 3 μm to 4 μm. The mirror covering layer 7 is made by sequentially evaporating the above materials, which not only has a good light reflection effect but also has stable and reliable performance.

[0065] According to some preferred embodiments, please refer to Figure 7, the preparation material of the mirror covering layer 7 further includes an alumina layer 74, and the alumina layer 74 is disposed on the surface away from the patterned silicon substrate 6; and at least a part of the alumina layer 74 on the upper end surface of the frustum-shaped protrusion 61 is missing, so that an electrical connection is formed between the mirror covering layer 7 and the transparent conductive adhesive layer 9; further, the alumina layer 74 on the upper end surface of the frustum-shaped protrusion 61 is completely removed by grinding, and the thickness of the alumina layer 74 is 80 angstroms to 100 angstroms. In this application, the alumina layer 74 has an adhesion effect and can enhance the bonding force between the silica planarization layer 8 and the mirror metal material.

[0066] According to some preferred embodiments, the preparation material of the transparent conductive adhesive layer 9 is selected from transparent polymer polyurethanes or polyacrylates containing conductive fillers, and the conductive filler is carbon nanotubes. When in use, in order to enhance the plasticity of the transparent conductive adhesive layer 9, an appropriate amount of plasticizer can be further added. The transparent conductive adhesive layer 9 provided in this application has transparency, conductivity and good bonding effect, can bond the epitaxial wafer and the CMP'ed Si wafer together to complete the bonding of the two, realizes electrical connection after combining the epitaxial wafer and the Si wafer through the transparent conductive adhesive layer 9, and at the same time has good light transmittance.

[0067] The thickness of the transparent conductive adhesive layer 9 is 1 μm to 1.5 μm.

[0068] According to some preferred embodiments, the chip further includes a passivation layer 11, and the passivation layer 11 is disposed to cover the surface of the chip dicing lane. Preferably, the preparation material of the passivation layer 11 is selected from SiN, SiO or SiN / SiO composite materials. By using the above passivation materials, the edges and side walls of the chip can be protected and insulated, effectively avoiding leakage.

[0069] As can be seen from the above, the reverse-polarity LED chip provided by the embodiments of this application has the following advantages:

[0070] 1. The reverse-polarity LED chip structure provided in this application utilizes a patterned silicon substrate with a frustum-shaped protrusion, covers a layer of mirror material according to the shape of the patterned silicon substrate to form a mirror covering layer, and then fills and planarizes it with a silica planarization layer. This structure uses a patterned silicon substrate covered with a mirror metal layer to realize the direct contact between the mirror covering layer and the transparent conductive adhesive layer. The P-plane current conduction effect is stable and reliable. This structure does not need to be prepared by wet etching, and the interface flatness between the mirror covering layer and the silica planarization layer is high, which is beneficial to improving the reflection of light.

[0071] 2. In this application, the angle between the side wall of the frustum-shaped protrusion and the horizontal line is 30°C to 60°C, which is beneficial for the uniform deposition of the mirror covering layer on the surface of the frustum-shaped protrusion, obtaining a P-plane current conduction effect with high reliability and stability, and ensuring the flatness of the metal layer on the surface of the frustum-shaped protrusion to guarantee a good light reflection effect.

[0072] 3. The materials of the mirror covering layer in this application are selected from Ti, Pt, Au, Ti, Pt, Au, and Al2O3 deposited by sequential evaporation. It not only has a good light reflection effect but also has stable and reliable performance. Al2O3 can play an adhesion role and enhance the bonding force between the silica leveling layer and the mirror metal material. The transparent conductive adhesive layer has transparency, conductivity, and good bonding effect, and can bond the epitaxial wafer and the CMP'ed Si wafer together through the transparent conductive adhesive layer to complete the bonding of the two. Through the transparent conductive adhesive layer, the epitaxial wafer is combined with the Si wafer to achieve electrical connection and has good light transmittance.

[0073] Example 2

[0074] Please refer to Figures 1 to 9 , this embodiment provides a method for manufacturing an inverted-polarity LED chip. The manufacturing method includes:

[0075] Step 1: Please refer to Figure 1 , Figure 1 which is a schematic diagram of the inverted-polarity LED chip epitaxial structure shown in some embodiments of this application; provide a GaAs substrate 1 as the growth substrate for the inverted-polarity epitaxial structure; sequentially grow an N-type stack 2, a light-emitting layer 3, a P-type stack 4, and a window layer 5 on the GaAs substrate 1. The N-type stack 2 includes a roughening layer, a current spreading layer, and an N-type confinement layer to prepare an epitaxial wafer;

[0076] As some preferred embodiments, the window layer 5 uses GaP material with a thickness of 0.5 μm to 1.0 μm, and the surface doping thickness is about 0.3 μm;

[0077] Step 2: Please refer to Figures 2 to 4 , Figure 2 which is a schematic diagram of the patterned silicon substrate structure shown in some embodiments of this application; Figure 3 which is a schematic diagram of the structure of the mirror covering layer formed on the patterned silicon substrate shown in some embodiments of this application; Figure 4 which is another perspective structure schematic diagram of the mirror covering layer formed on the patterned silicon substrate shown in some embodiments of this application; take the prepared patterned silicon substrate 6 for organic cleaning, and complete the evaporation of the mirror covering layer 7 materials by electron beam evaporation; the thickness of the patterned silicon substrate 6 used in this application can be 200 μm to 300 μm, and the height of the frustum-shaped protrusions 61 provided on its surface is 4 μm to 10 μm;

[0078] As some preferred embodiments, the material of the mirror covering layer 7 is Ti / Pt / Au / Ti / Pt / Au / Al2O3 arranged in sequence, with a total thickness of 3 μm to 4 μm, and the thickness of Al2O3 is 100 angstroms;

[0079] Step Three: Please refer to Figure 5 , Figure 5 which is a schematic structural diagram of forming a silicon dioxide dielectric film on the patterned silicon substrate 6 shown in some embodiments of the present application; Clean the surface of the mirror covering layer 7 with an organic solution, and deposit a SiO2 dielectric film by PECVD. The deposited thickness of the SiO2 dielectric film is 8 μm to 10 μm;

[0080] Step Four: Please refer to Figure 6 and Figure 7 , Figure 6 which is a schematic structural diagram of forming a silicon dioxide planarization layer on the patterned silicon substrate shown in some embodiments of the present application; Figure 7 is Figure 6 a partial enlarged schematic diagram of part A in

[0081] For the following Steps Five to Twelve, please refer to Figure 8 and Figure 9 , Figure 8 which is a schematic structural diagram of a reverse-polarity LED chip shown in some embodiments of the present application; Figure 9 which is a schematic structural diagram of another perspective of the reverse-polarity LED chip shown in some embodiments of the present application;

[0082] Step Five: Clean the epitaxial wafer with an acid-base solution, and spin-coat a transparent conductive adhesive layer 9 on the surface of the epitaxial wafer. The specific method of spin-coating is to spin-coat on the surface of the epitaxial wafer at a speed of 1000 r / s for 5 seconds first, then at a speed of 3000 r / s for 30 seconds, and then perform post-baking in a nitrogen-filled furnace. The post-baking temperature is 100 °C, and the post-baking time is 15 min;

[0083] As some preferred embodiments, the thickness of the transparent conductive adhesive layer 9 is 1.0 μm to 1.5 μm;

[0084] Step Six: Bond the epitaxial wafer with the transparent conductive adhesive layer 9 and the Si wafer after CMP together, place them in a special bonding fixture, put them into a bonding machine platform, and complete the bonding of the two by the method of high temperature and low pressure at a high temperature of 350 °C and a low pressure of 2000 Kg;

[0085] Step Seven: Put the bonded wafer source into a mixed solution of ammonia water and hydrogen peroxide, and remove the GaAs substrate 1 by chemical etching to expose the N-type stack 2;

[0086] Step VIII: Through negative photoresist lithography, cooperate with lift-off to complete the fabrication of the front electrode 10 and perform high-temperature fusion at 300 °C;

[0087] Step IX: Use positive photoresist overlay to fabricate the scribe line pattern, and use dry etching to etch the scribe line until 2000 Å of the window layer 5 remains;

[0088] Step X: Use positive photoresist overlay to fabricate the roughening protection pattern, and through wet etching, roughen the surface of the N-type stack 2. The wet etching solution uses a phosphoric acid-based solution;

[0089] Step XI: Deposit the passivation layer 11 material by PECVD. The passivation layer 11 material is SiN, and through photolithography etching, complete the preparation of the passivation layer 11;

[0090] Step XII: Thin the patterned silicon substrate 6, fabricate the back electrode 12, perform laser cutting, and complete the fabrication of the LED die through testing.

[0091] As can be seen from the above, the manufacturing method of the reverse-polarity LED chip provided by the embodiment of the present application has the following advantages:

[0092] 1. By directly depositing the mirror covering layer on the patterned silicon substrate by electron beam evaporation, the pattern of the patterned silicon substrate is adapted to the required P-plane current conduction channel. Deposit the SiO2 dielectric film by PECVD, and then use the CMP method to grind and polish the SiO2 dielectric film to expose the mirror covering layer on the upper end surface of the frustum-shaped protrusion until the surface Au layer is exposed. The above process does not require wet etching. While achieving surface planarization, it also realizes the exposure of the metal on the frustum-shaped protrusion, providing convenience for subsequent electrical connection;

[0093] 2. In the present application, a transparent conductive adhesive layer is coated on the surface of the epitaxial wafer by spin coating, and the epitaxial wafer transparent conductive adhesive layer and the Si wafer after CMP are bonded together to complete the bonding of the two; the above operation is simple. The epitaxial wafer and the Si wafer are combined through the transparent conductive adhesive layer to realize the electrical connection between the transparent conductive adhesive layer and the metal of the mirror covering layer.

[0094] 3. The manufacturing process provided by the present application does not require multiple metal depositions, multiple solution corrosions, and wet etching processes in the traditional process, and the process is simple, reliable, and easy to implement.

[0095] Therefore, the method for preparing the reverse-polarity LED chip provided by this application has the advantages of simple manufacturing process and low manufacturing cost, and the prepared reverse-polarity LED chip has the advantages of reliable and stable performance. Since the reverse-polarity LED chip obtained by the manufacturing method of the reverse-polarity LED chip provided in the embodiment of this application is the reverse-polarity LED chip in Embodiment 1 above, it also has the advantages of the reverse-polarity LED chip in Embodiment 1 above, which will not be elaborated here.

[0096] Contents not described in this embodiment can be referred to the relevant descriptions in the remaining parts of this application.

[0097] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application and not to limit them; although this application has been described in detail with reference to the preferred embodiments, those of ordinary skill in the art should understand that it is still possible to modify the specific implementation manners of this application or perform equivalent replacements on some technical features, and they should all be covered by the scope of the technical solutions claimed in this application.

Claims

1. A reverse polarity LED chip, characterized in that: It includes a patterned silicon substrate, a reflector cover layer, a silicon dioxide leveling layer, a transparent conductive adhesive layer, a window layer, a P-type stack, a light-emitting layer and an N-type stack arranged in sequence from bottom to top; The upper surface of the patterned silicon substrate has a plurality of truncated cone-shaped protrusions; The reflector cover layer covers the entire surface of the patterned silicon substrate on the side having the truncated cone-shaped protrusion, so that the reflector cover layer forms a reflector plane portion and a reflector convex portion on the patterned silicon substrate; The silicon dioxide leveling layer has a plurality of through holes, the through holes are fitted with the convex portion of the reflector, and the upper surface of the silicon dioxide leveling layer is flush with the upper surface of the frustum of the reflector; The upper end surface of the convex portion of the reflector is in direct contact with the lower surface of the transparent conductive adhesive layer to form an electrical connection.

2. A reverse polarity LED chip according to claim 1, characterized in that: The chip further comprises a front electrode and a back electrode, wherein the front electrode is arranged at the middle of the upper surface of the N-type stack; and the back electrode is arranged at the lower surface of the patterned silicon substrate; The truncated cone-shaped protrusions are evenly distributed around the outer sides directly below the front electrode.

3. A reverse polarity LED chip according to claim 2, characterized in that: The angle between the side wall of the truncated cone-shaped protrusion and the horizontal line is 30° to 60°.

4. The reverse polarity LED chip according to claim 3, characterized in that: The number of the truncated cone-shaped protrusions is 4 to 20.

5. The reverse polarity LED chip according to claim 1, characterized in that: The height of the truncated cone-shaped protrusion is 4 μm to 10 μm.

6. The reverse polarity LED chip according to claim 1, characterized in that: The preparation material of the reflector cover layer includes Ti, Pt, Au, Ti, Pt and Au deposited sequentially from bottom to top; The thickness of the reflector cover layer is 3 μm to 4 μm.

7. The reverse polarity LED chip according to claim 6, characterized in that: The preparation material of the reflector cover layer also includes an aluminum oxide layer, and the aluminum oxide layer is arranged on the surface away from the patterned silicon substrate; and at least part of the aluminum oxide layer is missing from the upper end surface of the truncated cone-shaped protrusion, so that an electrical connection is formed between the reflector cover layer and the transparent conductive adhesive layer; The thickness of the aluminum oxide layer is 80 angstroms to 100 angstroms.

8. The reverse polarity LED chip according to claim 1, characterized in that: The transparent conductive adhesive layer is made of a material selected from transparent polymer polyurethane or polyacrylate containing conductive fillers, and the conductive fillers are carbon nanotubes; The thickness of the transparent conductive adhesive layer is 1 μm to 1.5 μm.

9. The reverse polarity LED chip according to claim 1, characterized in that: The chip further comprises a passivation layer, and the passivation layer covers the surface of the chip cutting path.

10. A method for manufacturing a reverse polarity LED chip according to any one of claims 1 to 9, characterized in that: The production method comprises: S1, providing a GaAs substrate as a reverse polarity epitaxial structure growth substrate; S2, sequentially growing an N-type stack, a light-emitting layer, a P-type stack and a window layer on a GaAs substrate, wherein the N-type stack includes a roughening layer, a current spreading layer and an N-type limiting layer, to prepare an epitaxial wafer; S3, taking the patterned silicon substrate for organic cleaning, and completing the evaporation of the reflector cover layer material by electron beam evaporation; S4, cleaning the surface of the reflector cover layer with an organic solution, and depositing a SiO2 dielectric film by PECVD; S5, grinding and polishing the SiO2 dielectric film by CMP method until Au metal is exposed, thereby completing the preparation of the silicon dioxide leveling layer; S6, cleaning the epitaxial wafer with an acid-base solution, and coating a transparent conductive adhesive layer on the surface of the epitaxial wafer by spin coating; S7, attaching the epitaxial wafer transparent conductive adhesive layer and the Si wafer after CMP together, and placing them in a pressing fixture to complete the bonding of the two; S8, removing the GaAs substrate from the bonded source sheets by chemical etching to expose the N-type stacked layer; S9, through negative photolithography, lift-off is used to complete the front electrode production and high-temperature fusion; S10, using positive resist to make cutting path patterns, and using dry etching to etch the cutting paths; S11, using positive resist to make a roughening protection pattern, and roughening the surface of the N-type stack by wet etching; S12, depositing a passivation layer material by PECVD, and completing the preparation of the passivation layer by photolithography and etching; S13, thinning the patterned silicon substrate, making the back electrode, laser cutting, and testing to complete the LED core production.

Images