Nitrogen plasma processing for bottom-up growth

Abstract

A method of forming a semiconductor device structure includes forming a nucleation layer within at least one feature. The method includes exposing the nucleation layer to a nitrogen plasma treatment. Nitrogen plasma processing preferentially processes the top field and sidewalls while leaving a substantially unprocessed bottom surface to facilitate bottom-up metal growth.

Description

Technical Field

[0001] The present disclosure relates to a method and apparatus for forming a thin film. More particularly, the present disclosure relates to a method and apparatus for metal gap filling in a semiconductor device. Background Art

[0002] The manufacture of microelectronic devices typically involves complex processing sequences that require hundreds of individual processes to be performed on semiconductor, dielectric, and conductive substrates. Examples of these processes include oxidation, diffusion, ion implantation, thin film deposition, cleaning, etching, lithography, and other operations. Each operation is time-consuming and expensive.

[0003] As the critical dimensions of microelectronic devices continue to decrease, the design and manufacture of these devices on substrates becomes increasingly complex. Control of critical dimensions and process uniformity becomes increasingly important. Complex multilayer stacks involve precise process monitoring of critical dimensions such as thickness, roughness, stress, density, and potential defects. Multiple incremental processes in the process recipe used to form the device ensure that the critical dimensions are maintained. However, each recipe process may utilize one or more process chambers, which adds additional time for forming the device in the processing system and also provides additional opportunities for defects to form. Therefore, each process increases the overall manufacturing cost of the completed microelectronic device.

[0004] In addition, as the critical dimensions of these devices shrink, past manufacturing techniques encounter new obstacles. For example, when preparing a liner and / or nucleation layer to grow a metal gap fill, the liner and / or nucleation layer may still exist on the sides of the gap, causing the metal fill material to close the gap before it is fully filled, resulting in seams in the metal gap fill material.

[0005] For at least the foregoing reasons, there continues to be a need for improved manufacturing methods to minimize costs while maintaining critical dimensions of microelectronic devices. Summary of the invention

[0006] The present disclosure relates to a method and apparatus for forming a thin film. More particularly, the present disclosure relates to a method and apparatus for tungsten gap filling in a semiconductor device.

[0007] In one aspect, a method for processing a semiconductor device structure in a processing chamber is provided. The method includes generating a plasma containing nitrogen-containing radicals in a remote plasma source. The plasma is formed by a processing gas containing nitrogen and an inert gas. The method further includes flowing the plasma containing nitrogen-containing radicals into a processing region of the processing chamber, wherein a semiconductor device structure is disposed in the processing region. The semiconductor device structure includes a feature formed thereon, the feature having a sidewall surface and a bottom surface extending between the sidewall surfaces and a tungsten nucleation layer formed above the sidewall surface and the bottom surface. The method further includes exposing an exposed portion of the tungsten nucleation layer along the sidewall surface of the tungsten nucleation layer to nitrogen-containing radicals to passivate the exposed portion of the tungsten nucleation layer, while the tungsten nucleation layer formed along the bottom surface remains substantially unpassivated. The method further includes filling the feature with a tungsten layer, including preferentially growing the tungsten layer from the tungsten nucleation layer remaining on the bottom surface of the feature.

[0008] Embodiments may include one or more of the following. The method further includes maintaining a pressure within a processing region such that a nitrogen partial pressure within the processing region is within a range of about 5 mTorr to about 20 mTorr. The pressure within the processing region is maintained within a range of about 1 Torr to about 10 Torr. Exposing an exposed portion of the tungsten nucleation layer along a sidewall surface of the tungsten nucleation layer to nitrogen-containing radicals for a period of time within a range of about 5 seconds to about 40 seconds. The method further includes filtering ions delivered to the processing region from a remote plasma source. The method further includes filtering ions output from the remote plasma source. Filling the feature with a tungsten layer is performed in the processing region. The processing gas includes about 5% to about 20% nitrogen and the remainder an inert gas, wherein the inert gas is argon.

[0009] On the other hand, a method for processing a semiconductor device structure in a processing chamber is provided. The method includes generating a plasma containing nitrogen-containing ions using an inductively coupled plasma (ICP) source. The plasma is formed by a processing gas containing nitrogen and an inert gas. The method further includes flowing the plasma containing nitrogen-containing ions into a processing region of the processing chamber where the semiconductor device structure is disposed. The semiconductor device structure has a feature formed thereon, the feature having a sidewall surface and a bottom surface extending between the sidewall surface and a tungsten nucleation layer formed above the sidewall surface and the bottom surface. The method further includes exposing an exposed portion of the tungsten nucleation layer along the sidewall surface of the tungsten nucleation layer to nitrogen-containing ions to passivate the exposed portion of the tungsten nucleation layer. The tungsten nucleation layer formed along the bottom surface remains substantially unpassivated. The method further includes filling the feature with a tungsten layer, including preferentially growing the tungsten layer from the tungsten nucleation layer retained on the bottom surface of the feature.

[0010] Embodiments may include one or more of the following. The method further includes maintaining a pressure within a processing region such that a nitrogen partial pressure in the processing region is within a range of about 0.01 mTorr to about 0.05 mTorr. The pressure within the processing region is maintained within a range of about 5 mTorr to about 20 mTorr. Exposing an exposed portion of the tungsten nucleation layer along a sidewall surface of the tungsten nucleation layer to nitrogen-containing ions for a time period within a range of about 3 seconds to about 20 seconds. The method further includes filtering free radicals transmitted from an ICP source to the processing region. The method further includes filtering free radicals output from the ICP source. Filling the feature with a tungsten layer is performed in the processing region. The processing gas comprises about 1% to about 10% nitrogen and the remainder an inert gas, wherein the inert gas is argon.

[0011] In yet another aspect, a method for processing a semiconductor device structure in a processing chamber is provided. The method includes exposing the semiconductor device structure to nitrogen-containing ions in a processing region of the processing chamber. The semiconductor device structure has a feature formed thereon, the feature having a sidewall surface and a bottom surface extending between the sidewall surfaces, one or more conformal / non-conformal layers formed above the sidewall surface and the bottom surface, and a boron-tungsten nucleation layer formed above the one or more conformal / non-conformal layers, wherein an exposed portion of the tungsten nucleation layer along the sidewall surface of the tungsten nucleation layer is passivated by the nitrogen-containing ions to inhibit subsequent tungsten growth, and the boron-tungsten nucleation layer formed along the bottom surface remains substantially unpassivated. The method further includes partially filling the feature with a tungsten layer, including preferentially growing a tungsten layer from the tungsten nucleation layer remaining on the bottom surface of the feature. The method further includes repeatedly exposing the semiconductor device structure to the nitrogen-containing ions in the processing region and partially filling the feature with a tungsten layer until the tungsten layer reaches a target thickness.

[0012] Embodiments may include one or more of the following. The method further includes maintaining a pressure within the processing region such that a nitrogen partial pressure within the processing region is in a range of about 0.01 mTorr to about 0.05 mTorr. The pressure within the processing region is maintained in a range of about 5 mTorr to about 20 mTorr. Exposing an exposed portion of the boron-tungsten nucleation layer along the sidewall surface to the nitrogen-containing ions for a time period in a range of about 3 seconds to about 20 seconds.

[0013] In another aspect, a non-transitory computer-readable medium has stored thereon instructions that, when executed by a processor, cause the processor to perform the operations of the apparatus and / or method described above. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] In order to be able to understand in detail the manner in which the above-mentioned features of the present disclosure are achieved, a more specific description of the various aspects briefly summarized above may be obtained by reference to the embodiments, some of which are illustrated in the accompanying drawings. However, it should be noted that the drawings illustrate only typical embodiments of the present disclosure and are therefore not to be considered limiting of the scope, as the present disclosure may admit of other equally effective embodiments.

[0015] Figure 1 A flow chart of a method for manufacturing a semiconductor device according to one or more embodiments of the present disclosure is shown.

[0016] Figures 2A-2H Views showing various stages of fabricating a semiconductor device according to one or more embodiments of the present disclosure.

[0017] Figure 3 A schematic top view of one example of a multi-chamber processing tool according to one or more embodiments of the present disclosure is shown.

[0018] To facilitate understanding, identical reference numerals have been used, where possible, to designate identical elements that are common to the figures. It is contemplated that elements and features of one embodiment may be beneficially incorporated in other embodiments without further recitation. DETAILED DESCRIPTION

[0019] In the above-mentioned "Summary of the Invention", the following "Detailed Description", "Claims" and "Drawings", reference is made to specific features (including method operations) of the present disclosure. It should be understood that the disclosure in this specification includes all possible combinations of these specific features. For example, where a specific feature is disclosed in the context of a specific aspect or embodiment of the present disclosure or a specific claim, the feature may also be used in combination with other features and / or in the context of other features to the extent possible in the specific aspects and embodiments of the present disclosure, as well as in the general case of the present disclosure.

[0020] As used herein, the term "comprising" and its grammatical equivalents mean that other components, ingredients, operations, etc. are optionally present. For example, an article "comprising" (or "which comprises") components A, B, and C may consist of (i.e., only comprise) components A, B, and C, or may comprise not only components A, B, and C but also one or more other components.

[0021] Where reference is made herein to a method comprising two or more defined operations (e.g., processes), the defined operations may be performed in any order or concurrently (unless the context excludes that possibility), and the method may include one or more other operations performed before any defined operation, between two defined operations, or after all defined operations (unless the context excludes that possibility).

[0022] It is challenging to deposit gap-filling metal films (e.g., tungsten, copper, cobalt, ruthenium, or molybdenum-containing films) in features with ultra-high aspect ratios. At early nodes, larger dimensions made it possible to achieve metal gap filling using nucleation and subsequent conformal chemical vapor deposition (CVD). However, as the critical dimensions of features continue to shrink, the tops of ultra-small features tend to overhang, so conformal processing in which the film grows uniformly over the field area or surface closes or pinches off the opening before the filling is completed, leaving voids in the metal gap filling. Even without voids, the center seam is a typical result of conformal deposition as the metal gap fill grows from the sidewalls. This incomplete filling may result in high resistance. Metal gap filling may also be adversely affected by the presence of impurities. Fluorine-terminated (F-terminated) impurities are present on the surface of the underlying layers (e.g., liner, barrier layer, and / or nucleation layer) present in the feature. Other impurities (e.g., boron, nitrogen, and oxides) may also have an adverse effect on metal gap filling. For example, in some conventional bottom-up metal fill processes that incorporate a nucleation layer with contaminants, it is not uncommon to have a 15-20% resistance loss compared to a metal gap fill without a nucleation layer.

[0023] Various embodiments provide improved metal gap filling in features with reduced critical dimensions. Various embodiments utilize nitrogen (e.g., N2, NO, NO2, and N2H4) plasmas including nitrogen-containing ions or nitrogen-containing radicals and appropriate processing conditions to achieve near-conformal processing inside features. Such conformal processing inside features can achieve bottom-up growth before losing the incubation delay at the top field and sidewalls. The inventors have found that treating the underlying film deposited along the top field and sidewalls with the nitrogen plasma treatment described herein provides conformal processing of the top field and sidewalls. This conformal treatment delays the incubation / growth of the metal filler along the top field and sidewalls, thereby achieving bottom-up growth of the metal filler. Bottom-up growth provides growth of large grains within features, rather than the growth of smaller grains typically formed using conventional bottom-up growth methods. The improved conformal processing described herein provides large grain growth, resulting in no resistance, reduced resistance loss, or in some cases resistance benefits. Some embodiments may provide improved Rs / Rc performance relative to conventional deposition alone and overcome the Rs penalty typically observed in conventional metal gapfill.

[0024] Figure 1 A flow chart of a method 100 for manufacturing a semiconductor device according to one or more embodiments of the present disclosure is shown. At operation 110, a substrate is provided. The substrate may be a device substrate or a semiconductor substrate as described herein. The substrate may include multiple layers. The substrate has one or more features formed therein. The one or more features may include a sidewall surface and a bottom surface. The sidewall surface may be defined by a dielectric material, and the bottom surface may be defined by a dielectric material or other material, such as a silicide layer, a metal silicide layer, a semiconductor layer, an etch stop layer (ESL), or a metal layer.

[0025] At operation 120, one or more conformal / non-conformal layers may be formed over the surface of one or more features. The one or more conformal / non-conformal layers may include one or more layers of a barrier layer, an adhesion layer, and / or a liner layer. The one or more conformal / non-conformal layers may include or may be a nitride, such as silicon nitride, carbon nitride, aluminum nitride, tantalum nitride, titanium nitride, tungsten nitride, the like, or a combination thereof, or a metal, such as tantalum, cobalt, titanium, tungsten, copper, ruthenium, the like, or a combination thereof, or a carbide, such as tungsten carbide, aluminum carbide, the like, or a combination thereof. The one or more conformal / non-conformal layers may be formed by any suitable deposition process, such as ALD, CVD, PVD, or a hybrid ALD / CVD process. The one or more conformal / non-conformal layers may produce an overhang in the field region that obstructs or blocks the top opening of the one or more features, thereby causing a seam to form in the metal gap fill.

[0026] At operation 130, a nucleation layer may be formed over the feature or one or more conformal / non-conformal layers (if present). The nucleation layer may be used to repair any damage or discontinuity in one or more conformal / non-conformal layers. The nucleation layer may be a tungsten-containing nucleation layer, such as a boron-tungsten (BW) nucleation layer, a boron-silicon-tungsten (BSW) nucleation layer, or a silicon-tungsten (SW) nucleation layer. The nucleation layer may be deposited using any suitable deposition process. The deposition process may be an atomic layer deposition (ALD) process, a cyclic chemical vapor deposition (CCVD) process, or a combination thereof (e.g., a hybrid ALD / CVD process). In one example, one cycle of the ALD process includes a boron pulse / boron purge / tungsten pulse / tungsten purge. The ALD process may be repeated for any number of cycles sufficient to deposit a nucleation layer of a target thickness. In one example, the ALD cycle is repeated for 3 to 5 cycles. The nucleation layer may also contribute to the thickness of the overhang (if present) formed by one or more conformal / non-conformal layers during operation 120.

[0027] At operation 140, the substrate is exposed to a nitrogen plasma treatment. In some embodiments, the nitrogen plasma treatment of operation 140 may include exposing a portion of the lower layer (e.g., one or more conformal / non-conformal layers and / or nucleation layers) to a nitrogen plasma treatment. In some embodiments, the nitrogen plasma treatment is an inductively coupled plasma treatment. In some embodiments, the nitrogen plasma treatment is a capacitively coupled plasma treatment. In some embodiments, the nitrogen plasma is formed in a remote plasma source (RPS). In some embodiments, the nitrogen plasma is generated in a processing region (e.g., a direct plasma). In some embodiments, the nitrogen plasma treatment includes exposing the nucleation layer to a plasma formed by a processing gas including a nitrogen-containing gas. The nitrogen-containing gas may be selected from N2, NO, NO2, N2H4, or a combination thereof. The processing gas may further include an inert gas, such as argon (Ar), helium (He), krypton (Kr), or a combination thereof. The processing gas may include argon (Ar), helium (He), hydrogen (H2), nitrogen (N2), or a H2 / N2 mixture. In some embodiments, the plasma processing treatment includes exposing the nucleation layer to an ICP formed by a process gas including a nitrogen-containing gas (e.g., N2) and an inert gas (e.g., Ar). In some embodiments, the plasma processing treatment may include exposing the underlying layer to a plasma formed in an RPS, the process gas including one or more of N2 and Ar. In some embodiments, the nitrogen plasma processing treatment may include exposing the nucleation layer to a plasma substantially containing radicals (nitrogen radicals) or substantially containing ions (nitrogen ions).

[0028] At operation 150, one or more features may be filled with a metal fill material, such as a tungsten, copper, cobalt, ruthenium or molybdenum metal filler. In one example, when the metal filler is tungsten, the tungsten layer may be a tungsten gap fill layer. The metal gap fill layer may be deposited using any suitable metal fill deposition process. The metal gap fill layer may be deposited via a CVD gap fill process, an ALD gap fill process or a hybrid ALD / CVD process. The metal gap fill layer may partially or completely fill one or more features. Due to the nitrogen plasma treatment of operation 140, the clean surface of the metal-containing layer (e.g., a conformal layer and / or a nucleation layer) below provides good gap filling through the metal gap fill layer and reduces Rs in the final device. In some embodiments, the feature may be partially filled with a metal filler at operation 160, followed by an additional nitrogen plasma treatment of the partial metal filler at operation 170. The nitrogen plasma treatment of operation 170 may be performed similarly to the nitrogen plasma treatment of operation 140. Operations 160 and 170 may be repeated until the metal fill material reaches a target thickness within the feature.

[0029] At operation 180, additional processing may be performed. In some embodiments, a planarization process (e.g., a CMP process or an etchback process) may be performed to remove excess or overburden of the metal fill material (if present). In some embodiments, an annealing process may be performed during operation 180.

[0030] Reference Figures 2A-2H , cross-sectional views of some embodiments of device structures of semiconductor devices at various stages of manufacture are provided to illustrate Figure 1 Although Figures 2A-2H The method 100 is described, but it should be understood that Figures 2A-2H The structure disclosed in is not limited to the method 100, but can exist independently as a structure independent of the method 100. Similarly, although it is a reference Figures 2A-2H To describe the method 100, it should be understood that the method 100 is not limited to Figures 2A-2H The structure disclosed in Figures 2A-2H The structure disclosed in .

[0031] Figures 2A-2H Views showing various stages of fabricating a semiconductor device according to one or more embodiments of the present disclosure.

[0032] Figure 2A 1. A cross-sectional view of a semiconductor device structure 200 is illustrated during an intermediate stage of fabrication corresponding to operation 110 according to some embodiments. The semiconductor device structure 200 includes a device substrate 210 having one or more layers formed thereon, such as Figure 2A The dielectric layer 220 is shown. The device substrate 210 can be or include a bulk semiconductor substrate, a semiconductor on insulator (SOI) substrate, or the like, which can be doped (e.g., with a p-type dopant or an n-type dopant) or undoped. In some embodiments, the semiconductor material of the device substrate 210 can include an elemental semiconductor, such as silicon (Si) or germanium (Ge); a compound semiconductor, such as silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; an alloy semiconductor including, for example, SiGe, GaAsP, AlInAs, GaInAs, GaInP, and / or GaInAsP; a combination thereof; or the like. The device substrate 210 can include additional materials, such as a silicide layer, a metal silicide layer, a metal layer, a dielectric layer, an etch stop layer, an interlayer dielectric, or a combination thereof.

[0033] The device substrate 210 may further include integrated circuit devices (not shown). One of ordinary skill in the art will recognize that a variety of integrated circuit devices such as transistors, diodes, capacitors, resistors, the like, or combinations thereof may be formed in and / or on the device substrate 210 to produce the structural and functional requirements of the design of the resulting semiconductor device structure 200.

[0034] The device substrate 210 has a front side 210f (also referred to as a front surface) and a rear side 210b (also referred to as a rear surface) opposite the front side 210f. A dielectric layer 220 is formed over the front side 210f of the device substrate 210. The dielectric layer 220 may include multiple layers. The dielectric layer 220 includes an upper surface 220u or a field region. In some embodiments, the dielectric layer 220 includes silicon oxide, silicon oxynitride, silicon nitride, a combination thereof, or multiple layers thereof. In some embodiments, the dielectric layer 220 is primarily composed of silicon oxide. It should be noted that the foregoing descriptors (e.g., silicon oxide) should not be interpreted as disclosing any particular stoichiometric ratio. Therefore, "silicon oxide" and the like will be understood by a person of ordinary skill in the art as a material consisting essentially of silicon and oxygen without disclosing any specific stoichiometric ratio.

[0035] The dielectric layer 220 is patterned to form one or more features 222. In some embodiments, the feature 222 may be selected from a groove, a via, a hole, or a combination thereof. In a specific embodiment, the feature 222 is a via. In some embodiments, the feature 222 extends from the upper surface 220u of the dielectric layer 220 to the front side 210f of the device substrate 210. The feature 222 includes a sidewall surface 222s and a bottom surface 222b extending between the sidewall surfaces 222s. In some embodiments, the sidewall surface 222s is tapered. The sidewall surface 222s may be defined by the dielectric layer 220 and the bottom surface may be defined by the device substrate 210. In some embodiments, the sidewall surface 222s may be defined by the dielectric layer 220, and the bottom surface may also be defined by the dielectric layer 220. The feature 222 has a first depth "D1" from the upper surface 220u to the bottom surface 222b and a width "W1" between the two sidewall surfaces 222s. In some embodiments, the depth D1 is in the range of 2nm to 200nm, 3nm to 200nm, 5nm to 100nm, 2nm to 100nm, or 50nm to 100nm. In some embodiments, the width W1 is in the range of 10nm to 100nm, 10nm to 20nm, 10nm to 50nm, or 50nm to 100nm. In some embodiments, the feature 222 has an aspect ratio (D / W) in the range of 1 to 20, 5 to 20, 10 to 20, or 15 to 20.

[0036] Figure 2B A cross-sectional view of a semiconductor device structure 200 during an intermediate stage of fabrication corresponding to operation 120 is illustrated in accordance with some embodiments. At operation 120, one or more conformal / non-conformal layers 230 may be formed over a surface of a feature 222. The one or more conformal / non-conformal layers 230 may include one or more barrier layers, adhesion layers, and / or liner layers. The one or more conformal / non-conformal layers 230 may include or may be a nitride, such as silicon nitride, carbon nitride, aluminum nitride, tantalum nitride, titanium nitride, tungsten nitride, the like, or a combination thereof, or a metal, such as tantalum, cobalt, titanium, tungsten, the like, or a combination thereof, or a carbide, such as tungsten carbide, aluminum carbide, the like, or a combination thereof. The one or more conformal / non-conformal layers 230 may be formed by a conformal / non-conformal layer deposition process 232. The one or more conformal / non-conformal layers 230 may be formed by any suitable conformal / non-conformal layer deposition process, such as ALD, CVD, PVD, or a hybrid ALD / CVD process.

[0037] One or more conformal / non-conformal layers 230 may be formed over the sidewall surfaces 222s and bottom surface 222b of feature 222 and over the upper surface 220u or field region of dielectric layer 220. In some embodiments, one or more conformal / non-conformal layers 230 include a barrier layer having a liner layer formed thereon, such as a titanium nitride barrier layer having a tungsten liner formed thereon. In some embodiments, one or more conformal / non-conformal layers 230 include a liner layer formed over the surface of feature 222. One or more conformal / non-conformal layers 230 may include or may be a liner layer. The liner layer may be a tungsten liner layer. The liner layer may have an initial thickness in the range of about 1 angstrom to about 100 angstroms, or in the range of about 20 angstroms to about 50 angstroms. In some embodiments, one or more conformal / non-conformal layers 230 may be discontinuous along, for example, sidewall surfaces 222s and / or bottom surface 222b. In a particular embodiment, the one or more conformal / non-conformal layers 230 include a tungsten liner layer formed via a PVD process. Figure 2B As shown, the liner layer can create an overhang 234 along the upper surface 220u or field region of the dielectric layer 220. The overhang 234 can partially block or obstruct the top opening of the feature 222. The overhang 234 can reduce the width of the top opening and thus Figure 2A W1 is reduced to Figure 2B W2 shown.

[0038] Figure 2C A cross-sectional view of a semiconductor device structure 200 during an intermediate stage of fabrication corresponding to operation 130 is illustrated in accordance with some embodiments. At operation 130, a nucleation layer (e.g., nucleation layer 240) is formed over a surface of a feature 222 (e.g., over a surface of one or more conformal / non-conformal layers 230). The nucleation layer 240 may serve as a seed layer for a subsequently deposited metal fill material. Additionally, in some embodiments where one or more previously deposited conformal / non-conformal layers 230 are discontinuous, such as along a sidewall surface 222s, the nucleation layer 240 may repair the discontinuous portion of the one or more conformal / non-conformal layers 230. The nucleation layer 240 may include or may be any suitable material for promoting the growth of a subsequently deposited metal fill material. The nucleation layer 240 may include or may be a metal, such as tantalum, cobalt, titanium, tungsten, ruthenium, the like, or a combination thereof, or a metal boride, such as tungsten boride or the like. The nucleation layer 240 may be formed by a nucleation layer deposition process 242. Any suitable nucleation layer deposition process may be used, such as ALD, CVD, PVD or a hybrid ALD / CVD process.

[0039] In some embodiments, the nucleation layer 240 may include or may be a tungsten-containing nucleation layer, such as a boron-tungsten (BW) nucleation layer, a boron-silicon-tungsten (BSW) nucleation layer, or a silicon-tungsten (SW) nucleation layer. The nucleation layer 240 may be a conformal layer. In some embodiments, the one or more conformal / non-conformal layers 230 include a barrier layer and / or a liner layer on which the nucleation layer 240 is formed, such as a tungsten liner layer on which the boron-tungsten nucleation layer is formed. In some embodiments, the one or more conformal / non-conformal layers 230 and the nucleation layer 240 may be individually or collectively referred to as a tungsten-containing layer or underlayer 246, such as Figure 2C shown.

[0040] In some embodiments where the nucleation layer 240 is a tungsten-containing nucleation layer, forming the nucleation layer 240 at operation 130 includes exposing the semiconductor device structure 200 to a tungsten-containing precursor gas at a first precursor gas flow rate, and then exposing the semiconductor device structure 200 to a reducing agent. The reducing agent may include boron and is introduced into the processing region at a reducing agent flow rate. The tungsten-containing precursor gas and the reducing agent may be cyclically alternating to form the nucleation layer 240 over the semiconductor device structure 200 within the feature 222 at the reducing agent flow rate. The reducing agent and the tungsten-containing precursor gas may be cyclically alternating, starting with the reducing agent or the tungsten-containing precursor gas and ending with the same starting gas or ending with a gas different from the starting gas. In some embodiments, the reducing agent or the tungsten-containing precursor gas is cyclically alternating starting with the tungsten-containing precursor gas and ending with the reducing agent.

[0041] In some embodiments, the nucleation layer 240 is deposited using an ALD process. The ALD process includes repeated cycles of alternatingly exposing the feature 222 to a tungsten-containing precursor and exposing the feature 222 to a reducing agent. In some embodiments, the processing area is purged between alternating exposures. In some embodiments, the processing area is continuously purged. Examples of suitable tungsten-containing precursors include tungsten halides, such as tungsten hexafluoride (WF6), tungsten hexachloride (WCl6), or combinations thereof. In some embodiments, the tungsten-containing precursor includes WF6, and the reducing agent includes a boron-containing agent, such as B2H6. In some embodiments, the tungsten-containing precursor includes an organometallic precursor and / or a fluorine-free precursor, such as MDNOW (methylcyclopentadienyl-dicarbonyInitrosyl-tungsten), EDNOW (ethylcyclopentadienyl-dicarbonyInitrosyl-tungsten), hexacarbonyl tungsten (W(CO)6), or a combination thereof.

[0042] In some embodiments, during the nucleation layer deposition process 242, the processing region is maintained at a pressure of less than about 120 Torr, such as in a range of about 900 mTorr to about 120 Torr, in a range of about 1 Torr to about 100 Torr, or such as in a range of about 1 Torr to about 50 Torr. Exposing the semiconductor device structure 200 to the tungsten-containing precursor includes flowing the tungsten-containing precursor into the processing region at a flow rate of about 100 sccm or less, such as in a range of about 10 sccm to about 60 sccm, or in a range of about 20 sccm to about 80 sccm. Exposing the semiconductor device structure 200 to the reducing agent includes flowing the reducing agent into the processing region at a flow rate in a range of about 200 sccm to about 1000 sccm, such as in a range of about 300 sccm to about 750 sccm. It should be noted that the flow rates of the various deposition and processing processes described herein are for a processing system configured to process a 300 mm diameter substrate. Appropriate scaling can be used for processing systems configured to process substrates of different sizes.

[0043] In some embodiments, the tungsten-containing precursor and the reducing agent are each flowed into the processing region for a duration in the range of about 0.1 seconds to about 10 seconds, such as in the range of about 0.5 seconds to about 5 seconds. The processing region may be purged between alternating exposures by flowing a purge gas, such as argon (Ar) or hydrogen, into the processing region for a duration in the range of about 0.1 seconds to about 10 seconds, such as in the range of from about 0.5 seconds to about 5 seconds. Typically, repeated cycles of the nucleation process continue until the thickness of the nucleation layer 240 is in the range of about 10 angstroms to about 200 angstroms, such as in the range of about 10 angstroms to about 150 angstroms, or in the range of about 20 angstroms to about 150 angstroms. In one example, the ALD cycle is repeated for 3 to 5 cycles. The nucleation layer 240 is disposed along the sidewall surface 222s and / or the bottom surface 222b of the feature 222, such as above one or more conformal / non-conformal layers 230. The nucleation layer 240 may also contribute to the thickness of the overhang 234 formed by the liner layer during operation 120.

[0044] Figure 2D A cross-sectional view of a semiconductor device structure 200 during an intermediate stage of fabrication corresponding to operation 140 is illustrated in accordance with some embodiments. At operation 140, the semiconductor device structure 200 is exposed to a nitrogen plasma processing treatment 252. The nitrogen plasma processing treatment 252 utilizes ions and / or radicals based on a nitrogen plasma to achieve a conformal treatment by forming a nitrogen passivation layer 254 within the feature 222 along the upper surface 220u or field region, the overhang 234, and along the sidewall surface 222s, while leaving the bottom surface 222b substantially uncoated. In some embodiments, as shown in FIG. Figure 2DAs shown, the nitrogen passivation layer 254 coats the nucleation layer 240. The nitrogen passivation layer 254 inhibits the growth of subsequently deposited metal fill material along the passivation region (e.g., the upper surface 220u, the overhang portion 234, and / or the sidewall surface 222s), while enabling bottom-up growth from the nucleation layer 240 formed above the bottom surface 222b. The nitrogen passivation layer 254 can be partially formed along the length "L1" of the sidewall surface 222s. For example, referring to Figure 2D As shown, the nitrogen passivation layer 254 can be formed along greater than or equal to 50% of "L1", or greater than or equal to 60% of "L1", or greater than or equal to 70% of "L1", or greater than or equal to 80% of "L1", or greater than or equal to 90% of "L1", or equal to 100% of "L1".

[0045] In some embodiments, the nitrogen plasma processing 252 includes a plasma formed by an inductively coupled plasma source. In some embodiments, the nitrogen plasma processing 252 includes a plasma formed by a capacitively coupled plasma source. In some embodiments, the nitrogen plasma processing 252 includes a plasma formed in a remote plasma source (RPS). In some embodiments, the plasma of the nitrogen plasma processing 252 includes a plasma generated in a processing region (e.g., a direct plasma). In some embodiments, the nitrogen plasma processing may include exposing the semiconductor device structure 200 or the lower layer 246 to a plasma formed by a processing gas including a nitrogen-containing gas and an optional inert or noble gas. The nitrogen-containing gas may be or include N2, NO, N2O, NO2, N2H4, or a combination thereof. The inert gas may be or include Ar, He, or Kr. In a specific embodiment, the nitrogen-containing gas may include or be N2, and the inert gas may include or be Ar. In some embodiments, the nitrogen plasma processing 252 may include exposing the lower layer 246 to an ICP formed by a processing gas including nitrogen and an optional inert gas. In some embodiments, the nitrogen plasma processing 252 may include exposing the lower layer 246 to a plasma formed from N 2 and one or more of Ar, He, or a combination thereof.

[0046] In some embodiments, the nitrogen plasma processing 252 may include exposing the semiconductor device structure 200 or the lower layer 246 to a plasma comprising substantially free radicals (nitrogen-containing free radicals) or substantially ions (nitrogen-containing ions). The nitrogen-containing free radicals may be or include N radicals, NO radicals, NH radicals, or NH2 radicals. In some embodiments, the plasma comprising substantially free radicals further includes free radicals from an inert gas.

[0047] In some embodiments, the semiconductor device structure 200 can be heated before or during the nitrogen plasma processing 252. For example, heating the semiconductor device structure 200 at a temperature of at least about 250 degrees Celsius or at least about 350 degrees Celsius can promote the effectiveness of the nitrogen plasma processing 252 of the underlying layer 246. In some embodiments, the substrate can be heated at a temperature of about 250 to about 550 degrees Celsius, or in some embodiments, at a temperature of about 350 to about 450 degrees Celsius. The actual maximum substrate temperature can vary depending on hardware limitations and / or the thermal budget of the substrate being processed.

[0048] In some embodiments, during the nitrogen plasma processing 252, the processing region is maintained at a pressure of less than or equal to about 20 Torr, or less than or equal to about 10 Torr, or less than or equal to about 5 Torr, or less than or equal to about 1 Torr, or less than or equal to about 20 mTorr, or less than or equal to about 10 mTorr, such as in the range of about 1 mTorr to about 20 mTorr, or in the range of about 5 mTorr to about 20 Torr, or in the range of about 1 mTorr to about 10 mTorr, or in the range of about 5 mTorr to about 10 mTorr, or in the range of about 1 Torr to about 20 Torr; or in the range of about 1 Torr to about 10 Torr, or in the range of about 1 Torr to about 5 Torr.

[0049] In some embodiments, the nitrogen plasma processing 252 may include exposing the lower layer 246 to a radio frequency (RF) plasma (e.g., ICP, CCP, or RPS) formed by a process gas including nitrogen and an optional inert gas. The process gas may include 1% to 20% N2, or 1% to 10% N2, or 5% to 20%, with the remainder being inert gas. In some embodiments, the process gas may be N2 or a mixture of N2 and an inert gas. The inert gas may be, for example, argon (Ar), helium (He), krypton (Kr), or the like. In some embodiments, the process gas includes nitrogen (N2) and argon (Ar). In some embodiments, the process gas consists only of nitrogen (N2) and the inert gas. In some embodiments, the process gas may consist primarily of nitrogen (N2) and the inert gas or may consist essentially of nitrogen (N2) and the inert gas.

[0050] In some embodiments, the process gas may be supplied at a total gas flow in a range of about 100 to about 1000 sccm or at about 400 sccm (although other flow rates may be used depending on the application and configuration of the process chamber). In some embodiments, the process gas may include about 10% to 100% N2 (e.g., a N2 gas flow in a range of about 100 sccm to about 1000 sccm). In some embodiments, the process gas may include about 0.5 to 99% N2 (e.g., a N2 gas flow in a range of about 5 to about 990 sccm), with the balance being substantially an inert gas, such as argon (Ar) (e.g., a percentage of inert gas in a range of about 1% to about 99.5%). In some embodiments, the process gas may be about 0.5 to 15% N2 (e.g., a N2 gas flow between about 5 and 150 sccm), with the balance being substantially an inert gas, such as argon (e.g., a percentage of inert gas in a range of about 85% to about 99.5%). In some embodiments, the process gas may be approximately 0.5-10% N2 (e.g., a N2 gas flow between approximately 5-100 sccm), with the balance being substantially an inert gas, such as argon (e.g., a percentage of approximately 90% to approximately 99.5% inert gas). In some embodiments, the process gas may be approximately 1-5% N2 (e.g., a N2 gas flow between approximately 10-50 sccm), with the balance being substantially an inert gas, such as argon (e.g., a percentage of approximately 95% to 99% inert gas). In some embodiments, the process gas may be approximately 2.5% N2 (e.g., a N2 gas flow of approximately 25 sccm when a total gas flow of 1000 sccm is provided), with the balance being substantially an inert gas, such as argon (e.g., a percentage of approximately 97.5% inert gas).

[0051] The process gas may be introduced into a process region of the RPS or process chamber (e.g., a plasma reactor) and used to form a plasma. The plasma may be formed by using an RF source power. In some embodiments, the RF source power is up to about 5000 watts, such as in the range of about 10 watts to about 500 watts. The RF source power may be provided at any suitable RF frequency. For example, in some embodiments, the RF source power may be provided at a frequency of about 2 to about 60 MHz (e.g., about 13.56 MHz).

[0052] The plasma may be pulsed or applied continuously at a power of up to about 5000 watts. For example, the plasma may be applied continuously at a power of up to about 5000 watts for a duration in the range of about 1 second to about 240 seconds, or in the range of about 3 seconds to about 20 seconds, or in the range of about 5 seconds to about 40 seconds. The duration may be adjusted (e.g., shortened) to limit damage to the semiconductor device structure 200. Alternatively, the plasma may be pulsed at a pulse frequency of about 4 kHz to about 15 kHz. The pulsed plasma may have a duty cycle of about 2% to about 70% at a peak power of up to 2000 watts, wherein the duty cycle and / or RF source power may be adjusted to limit damage to the semiconductor device structure 200. In some embodiments, the pulsed plasma may have a duty cycle of about 30% to about 70% at a peak power of up to 4000 watts, wherein the duty cycle and / or RF source power may be adjusted to limit damage to the semiconductor device structure 200.

[0053] In some embodiments, it is preferred that the plasma substantially contains nitrogen free radicals. In some embodiments, nitrogen free radicals may be preferred because ions have high chemical activity compared to free radicals, so ions cannot achieve the selectivity of free radicals. High free radical density relative to ion density can be achieved by using a high pressure plasma treatment of a pressure in the range of, for example, about 1 torr to about 20 torr (e.g., about 5 torr or less). High pressure prompts ions to recombine rapidly with electrons, leaving neutral free radical species and inactive species. In some embodiments, free radical gas is formed. In some embodiments, remote plasma can be used to selectively generate free radical species by various methods. In some embodiments, ions transmitted from a remote plasma source to a processing area are filtered out from the plasma before arriving at the processing area. In some embodiments, ions are filtered from the plasma at the output of a remote plasma source. A remote plasma generator (e.g., microwave, RF, or hot chamber) can be connected to a processing chamber by a delivery tube. The delivery tube can be a relatively long path positioned at an angle relative to the processing chamber to facilitate the recombination of ion species along the path before arriving at the processing area. The free radicals flowing through the delivery tube can flow into the chamber at a flow rate between about 1 slm and about 20 slm, such as between about 5 slm and about 20 slm, such as about 10 slm, through a showerhead or free radical distributor, or through an inlet in the chamber sidewall. It is believed that higher pressures and lower gas flows promote collisions. In one embodiment, nitrogen free radicals can be formed by exposing a nitrogen-containing gas (e.g., nitrogen) optionally with a carrier gas (e.g., argon) to a microwave power between about 1 and 3 kW at a pressure of about 5 torr or less.

[0054] In embodiments where the plasma substantially includes nitrogen radicals, the semiconductor device structure 200 is exposed to a plasma formed from a process gas including 5% to 20% nitrogen (N2) and a balance of argon at a nitrogen partial pressure in a range of about 5 mTorr to about 20 mTorr (e.g., 10 mTorr) for a time period in a range of about 5 seconds to about 40 seconds. Without being bound by theory, it is believed that performing the nitrogen plasma processing 252 at a nitrogen partial pressure of less than 5 mTorr does not provide enough nitrogen radicals to ensure adequate sidewall passivation by nitrogen radicals, and performing the nitrogen plasma processing 252 at a nitrogen partial pressure of greater than 20 mTorr may generate excessive nitrogen radicals, which may passivate the bottom surface of the feature, thereby preventing bottom-up growth.

[0055] In embodiments where the plasma substantially comprises nitrogen ions, the semiconductor device structure 200 is exposed to a plasma formed from a process gas comprising 1% to 10% nitrogen (N2) and the balance argon at a nitrogen partial pressure in a range of about 0.01 mTorr to about 0.05 mTorr, such as 0.025 mTorr, for a time period in a range of about 3 seconds to about 20 seconds.

[0056] Figure 2E 1 illustrates a cross-sectional view of a semiconductor device structure 200 during an intermediate stage of fabrication corresponding to operation 150, according to some embodiments. At operation 150, a metal gap fill material 264 is optionally at least partially deposited into the feature 222 via a bottom-up metal fill process 262. In some embodiments, the bottom-up metal fill process 262 may completely fill the feature 222, such as Figure 2G shown.

[0057] In other embodiments, the bottom-up metal filling process 262 can be performed by Figure 2F The nitrogen plasma treatment 272 performed at operation 170 is shown as Figure 2E The feature 222 is partially filled at operation 160 as shown. The nitrogen plasma treatment 272 at operation 170 can be performed similar to the nitrogen plasma treatment in operation 140. In some embodiments, the nitrogen passivation layer 254 formed during operation 140 can dissipate after a certain amount of time. The nitrogen plasma treatment 272 at operation 170 reforms the nitrogen passivation layer 254 on the sidewalls, overhang 234, and exposed surfaces above the upper surface 220u or field region, such as Figure 2E As shown. At operation 170, the nitrogen passivation layer 254 is re-formed to enable the bottom-up metal filling to continue using the metal gap filling material 264. Operations 160 and 170 may be repeated until the metal gap filler material 264 is filled. Figure 2G Feature 222 is shown filled to a target level.

[0058] In some embodiments, the metal gap fill material 264 is formed using a CVD process that includes flowing (co-flowing) a tungsten-containing precursor gas and a reducing agent simultaneously into a processing region and exposing the semiconductor device structure 200 thereto. The tungsten-containing precursor and reducing agent used for the tungsten gap fill CVD process may include any combination of the tungsten-containing precursors and reducing agents described herein. In some embodiments, the tungsten-containing precursor includes WF6, and the reducing agent includes hydrogen. In some embodiments, the metal gap fill material 264 partially fills the feature 222.

[0059] In some embodiments, the tungsten-containing precursor flows into the processing region at a flow rate in the range of about 10 sccm to about 1200 sccm, or greater than about 50 sccm, or less than about 1000 sccm, or in the range of about 100 sccm to about 900 sccm. The reducing agent flows into the processing region at a rate greater than about 500 sccm, such as greater than about 750 sccm, greater than about 1000 sccm, or in the range of about 500 sccm to about 10000 sccm, such as in the range of about 1000 sccm to about 9000 sccm, or in the range of about 1000 sccm to about 8000 sccm.

[0060] In some embodiments, the tungsten gapfill CVD process conditions are selected to provide a tungsten feature with relatively low residual film stress compared to conventional tungsten CVD processes. For example, in some embodiments, the tungsten gapfill CVD process includes heating the substrate at a temperature of about 250° C. or higher, such as about 300° C. or higher, or in a range of about 250° C. to about 500° C., or in a range of about 300° C. to about 500° C. During the CVD process, the process region can be maintained at a pressure of less than about 500 Torr, less than about 600 Torr, less than about 500 Torr, less than about 400 Torr, or in a range of about 1 Torr to about 500 Torr, such as in a range of about 1 Torr to about 450 Torr, or in a range of about 1 Torr to about 400 Torr, or such as in a range of about 1 Torr to about 300 Torr.

[0061] In another embodiment, an atomic layer deposition (ALD) process is used to deposit the metal gapfill material 264 at operation 160. The tungsten gapfill ALD process includes repeated cycles of alternatingly exposing the semiconductor device structure 200 to a tungsten-containing precursor gas and a reducing agent and purging the process region between alternating exposures.

[0062] The tungsten-containing precursor and the reducing agent are each flowed into the processing region for a duration between about 0.1 seconds to about 10 seconds, such as a duration between about 0.5 seconds to about 5 seconds. The processing region can be purged between alternating exposures by flowing an inert purge gas, such as argon (Ar) or hydrogen, into the processing region for a duration in the range of about 0.1 seconds to about 10 seconds, such as in the range of from about 0.5 seconds to about 5 seconds.

[0063] In other embodiments, the metal gap fill material 264 is deposited using a pulsed CVD process that includes repeated cycles of alternating exposure of the semiconductor device structure 200 to a tungsten-containing precursor gas and a reducing gas without purging the process region. The process conditions of the tungsten gap fill pulsed CVD process may be the same, substantially the same, or within the same range as the process conditions of the tungsten gap fill ALD process described above.

[0064] Figure 2H A cross-sectional view of the semiconductor device structure 200 during an intermediate stage of fabrication corresponding to operation 180 is illustrated in accordance with some embodiments. At operation 180, the semiconductor device structure 200 may be subjected to additional processing 282. In some embodiments, the additional processing 282 includes a planarization process, such as a chemical mechanical polishing (CMP) process or an etch-back process may be performed to remove excess portions or overburden of conductive material (if present) on the upper surface 220u of the dielectric layer 220. After the planarization process is completed, the top surface 284 of the metal gap fill material 264 may be coplanar or flush with the upper surface 220u of the dielectric layer and the top surface of the nucleation layer 240 and the one or more conformal / non-conformal layers 230, as shown. Figure 2H In some embodiments, an annealing process may be performed during operation 180 .

[0065] In some embodiments, Figure 2H As shown, the one or more conformal / non-conformal layers 230, the nucleation layer 240, and the metal gap fill material 264 are monolithic and have no interface therebetween. The metal gap fill material 264, the one or more conformal / non-conformal layers 230, and the nucleation layer 240 together form a metal gap fill layer or a tungsten-containing layer.

[0066] Examples of processing systems that may be suitably modified according to the teachings provided herein include integrated processing systems or other suitable processing systems commercially available from Applied Materials, Inc. located in Santa Clara, Calif. It is contemplated that other processing systems, including those from other manufacturers, may be adapted to benefit from the aspects described herein. Figure 3A schematic top view of an exemplary multi-chamber processing system 300 or cluster tool that can be used to perform gradient oxidation and etching of PVD metals followed by post-etch processing is shown in accordance with an embodiment of the present disclosure. Figure 3 As shown, a plurality of processing chambers 302 are coupled to a first transfer chamber 304. The first transfer chamber 304 is also coupled to a first pair of pass-through chambers 306. The first transfer chamber 304 has a centrally disposed transfer robot (not shown) for transferring substrates between the pass-through chamber 306 and the processing chambers 302. The pass-through chamber 306 is coupled to a second transfer chamber 310, which is coupled to a processing chamber 314 configured to perform a pre-clean process and a processing chamber 316 configured to perform an epitaxial process or (alternatively) a PVD deposition process. The second transfer chamber 310 has a centrally disposed transfer robot (not shown) for transferring substrates between a set of load lock chambers 312 and the processing chambers 314 or the processing chambers 316. The factory interface 320 is coupled to the second transfer chamber 310 through the load lock chamber 312. The factory interface 320 is coupled to one or more pods 330 on the opposite side of the load lock chamber 312. The pods 330 are typically front opening unified pods (FOUPs) accessible from the cleanroom.

[0067] Prior to various operations, the substrate may first be transferred to the processing chamber 314 where a pre-cleaning process is performed to remove contaminants, such as carbon or oxide contaminants, from exposed surfaces of source / drain regions of transistors of the substrate.

[0068] The substrate is then transferred to one or more processing chambers 302. In some embodiments, the processing chamber 302 can etch vias or trenches in the substrate. In some embodiments, the substrate is provided to an etching chamber to perform a trench formation process that is not part of a processing system that includes the processing chambers 314, 316 and one or more processing chambers 302. In other operations, the substrate has trenches formed therein. Once the trenches are formed in the dielectric material, the substrate is transferred to the processing chamber 314 for cleaning.

[0069] The substrate is then transferred to at least one of the processing chambers 316 and / or the processing chambers 302 where an operation is performed. For example, the substrate is transferred to one of the processing chambers 302 where a metal deposition operation is performed to form a seed layer. The metal may be deposited in any suitable chamber, such as PVD, atomic layer deposition (ALD), epitaxy (EPI), or other suitable chambers.

[0070] The substrate may be transferred to one of the processing chambers 302, where a gradient oxidation operation may be performed. The gradient oxidation may be performed in an inductively coupled plasma (ICP) reactor or other suitable plasma processing chamber. The gradient oxidation operation is configured to oxidize unwanted portions of a metal layer formed on the substrate.

[0071] The substrate is transferred to one of the processing chambers 302, where an etching operation is performed to selectively remove the oxidized portion of the deposited metal layer. For example, the etching operation can be performed in an etching chamber. Alternatively, the etching operation can be performed in an ICP reactor that performs gradient oxidation.

[0072] After the etching operation, the substrate can be transferred to one of the processing chambers 302, where a post-etch processing treatment is performed to reduce the tungsten oxide to tungsten and optionally remove contaminants from the tungsten surface. For example, the post-etch processing treatment can be performed in an ICP reactor where a gradient oxidation and etch back are performed. The post-etch processing treatment can be a CVT process, for example, a hydrogen and oxygen processing treatment as described herein.

[0073] After the post-etch processing, a portion of the deposited metal layer (e.g., seed material) will remain along the sidewall surfaces and bottom surface of the feature or trench. The substrate can then be transferred to one of the processing chambers 302 or 316, where a gap fill operation is performed. The gap fill operation can be performed in a CVD, ALD, or other suitable chamber. For example, the processing chamber 302 or 316 can deposit a metal such as tungsten or other suitable material for growth from the seed layer at the bottom of the trench or feature to form a portion of a microelectronic device.

[0074] The system controller 380 is coupled to the processing system 300 for controlling the processing system 300 or components thereof. For example, the system controller 380 can control the operation of the processing system 300 using direct control of the processing chambers 302, 304, 306, 310, 312, 314, 316, 320, 330 of the processing system 300 or by controlling controllers associated with the processing chambers 302, 304, 306, 310, 312, 314, 316, 320, 330, 360. In operation, the system controller 380 enables data and feedback to be collected from the various chambers to coordinate the execution of the processing system 300.

[0075] The system controller 380 generally includes a central processing unit (CPU) 382, ​​a memory 384, and support circuits 386. The CPU 382 can be one of any form of general purpose processor that can be used in an industrial environment. The memory 384, a non-transitory computer readable medium, or a machine readable storage device can be accessed by the CPU 382 and can be one or more memories, such as a random access memory (RAM), a read-only memory (ROM), a floppy disk, a hard disk, or any other form of local or remote digital storage. The support circuits 386 are coupled to the CPU 382 and can include caches, clock circuits, input / output subsystems, power supplies, and the like. The various embodiments disclosed in the present disclosure can generally be implemented by executing computer instruction codes stored in the memory 384 (or in the memory of a particular processing chamber) under the control of the CPU 382, ​​such as a computer program product or software program. That is, the computer program product is tangibly embodied on the memory 384 (or a non-transitory computer readable medium or a machine readable storage device). When the CPU 382 executes the computer instruction code, the CPU 382 controls the chamber to perform operations according to various embodiments.

[0076] System controller 380 is configured to execute a number of methods, such as method 100 stored in memory 384 .

[0077] In some embodiments, the first process chamber 302 includes a nitrogen-containing gas source 332 fluidly coupled to a process region 340 of the first process chamber 302, wherein the nitrogen-containing gas source 332 is configured to deliver the nitrogen-containing gas to the process region 340. The first process chamber 302 may also include a first gas flow control valve 333, which is configured to control the flow of the nitrogen-containing gas provided from the nitrogen-containing gas source 332 to the process region 340. In some embodiments, the first process chamber 302 also includes a non-reactive gas source 334 fluidly coupled to the process region 340 of the first process chamber 302, wherein the non-reactive gas source 334 is configured to deliver a noble gas or an inert gas to the process region 340. The first process chamber 302 may also include a second gas flow control valve 335, which is configured to control the flow of the non-reactive gas provided from the non-reactive gas source 334 to the process region 340. The first processing chamber 302 may further include an inductively coupled plasma source or a capacitively coupled plasma source 338 configured to generate a plasma in the processing region 340, wherein the plasma is formed from the nitrogen-containing gas and the non-reactive gas.

[0078] In other embodiments, the first processing chamber 302 includes a remote plasma source (RPS) 336 fluidly coupled to a processing region 340 of the first processing chamber 302, wherein the RPS 336 is configured to deliver a remote plasma to the processing region 340. The first processing chamber 302 may also include a third gas flow control valve 337 configured to control a flow of the remote plasma provided from the RPS 336 to the processing region 340. In some embodiments including the RPS, the non-reactive gas source 334 and the nitrogen-containing gas source 332 are fluidly coupled to the RPS (not shown).

[0079] In some embodiments, the system controller 380 is configured to control the first gas flow control valve 333 and the second gas flow control valve 335 so that a certain amount of nitrogen-containing gas and non-reactive gas are provided to the processing region 340 of the first processing chamber 302 to preferentially passivate one or more tungsten-containing layers disposed on the sidewalls of features formed in the field region and in the substrate by generating plasma in the processing region 340 of the first processing chamber 302.

[0080] In other embodiments, the system controller is configured to control the third gas flow control valve 337 so that at least a certain amount of remote plasma formed by the nitrogen-containing gas is provided to the processing region 340 of the first processing chamber 302 to preferentially passivate one or more tungsten-containing layers on the sidewalls of the features formed in the field region and the substrate.

[0081] The embodiments and all functional operations described in this specification can be implemented in digital electronic circuits, or in computer software, firmware or hardware, including the structural devices disclosed in this specification and their structural equivalents, or in a combination thereof. The embodiments described herein can be implemented as one or more non-transitory computer program products, that is, one or more computer programs tangibly embodied in a machine-readable storage device, which is used to be executed or control its operation by a data processing device (e.g., a programmable processor, a computer, or multiple processors or computers).

[0082] The processes and logic flows described in this specification can be performed by one or more programmable processors executing one or more computer programs to perform functions by operating on input data and generating output. The processes and logic flows can also be performed by special purpose logic circuits, and the devices can also be implemented as special purpose logic circuits, such as FPGAs (field programmable gate arrays) or ASICs (application specific integrated circuits).

[0083] The term "data processing apparatus" covers all devices, means and machines for processing data, including, for example, a programmable processor, a computer or a plurality of processors or computers. In addition to hardware, the apparatus may include code that creates an execution environment for the computer program in question, such as code constituting processor firmware, a protocol stack, a database management system, an operating system, or a combination of one or more of these. Processors suitable for the execution of a computer program include, by way of example, both general and special purpose microprocessors, and any one or more processors of any type of digital computer.

[0084] Computer readable media suitable for storing computer program instructions and data include all forms of non-volatile memory, media and storage devices, including, for example, semiconductor memory devices, such as EPROM, EEPROM and flash memory devices; magnetic disks, such as internal hard disks or removable disks; magneto-optical disks; and CD ROM and DVD-ROM disks. The processor and memory may be supplemented by, or incorporated in, special purpose logic circuits.

[0085] When introducing elements of the present disclosure or exemplary aspects or embodiments thereof, the articles "a," "an," "the," and "said" are intended to mean that there are one or more of the elements.

[0086] While the foregoing is directed to embodiments of the present disclosure, other and further embodiments of the disclosure may be devised without departing from the basic scope thereof, and the scope of the same is determined by the claims that follow.

Claims

1. A method for processing a semiconductor device structure in a processing chamber, comprising the steps of: generating a plasma comprising nitrogen-containing radicals in a remote plasma source, wherein the plasma is formed from a process gas comprising nitrogen and an inert gas; causing the plasma including nitrogen-containing radicals to flow into a processing region of the processing chamber where the semiconductor device structure is disposed, wherein the semiconductor device structure has: a feature formed on the semiconductor device structure, the feature having a plurality of sidewall surfaces and a bottom surface extending between the sidewall surfaces; and a tungsten nucleation layer formed over the sidewall surface and the bottom surface; exposing an exposed portion of the tungsten nucleation layer along the sidewall surface of the tungsten nucleation layer to the nitrogen-containing radicals to passivate the exposed portion of the tungsten nucleation layer, wherein the tungsten nucleation layer formed along the bottom surface remains substantially unpassivated; and Filling the feature with a tungsten layer includes the steps of preferentially growing the tungsten layer from the tungsten nucleation layer remaining on the bottom surface of the feature.

2. The method according to claim 1, further comprising the steps of: The pressure within the processing region is maintained such that a nitrogen partial pressure within the processing region is in a range of about 5 mTorr to about 20 mTorr.

3. The method of claim 2, wherein the pressure within the processing region is maintained in a range of about 1 Torr to about 10 Torr. 4 . The method of claim 1 , wherein the exposed portion of the tungsten nucleation layer along the sidewall surface of the tungsten nucleation layer is exposed to the nitrogen-containing radicals for a time period in a range from about 5 seconds to about 40 seconds.

5. The method according to claim 1, further comprising the steps of: Ions transmitted from the remote plasma source to the processing region are filtered.

6. The method according to claim 1, further comprising the steps of: Ions from the output of the remote plasma source are filtered.

7. The method of claim 1 wherein filling the feature with the tungsten layer is performed in the processing region.

8. The method of claim 1, wherein the process gas comprises about 5% to about 20% nitrogen and the remainder being the inert gas, wherein the inert gas is argon.

9. A method for processing a semiconductor device structure in a processing chamber, comprising the steps of: generating a plasma comprising nitrogen-containing ions using an inductively coupled plasma source, wherein the plasma is formed from a process gas comprising nitrogen and an inert gas; causing the plasma including the nitrogen-containing ions to flow into a processing region of the processing chamber where the semiconductor device structure is disposed, wherein the semiconductor device structure has: a feature formed on the semiconductor device structure, the feature having a plurality of sidewall surfaces and a bottom surface extending between the sidewall surfaces; and a tungsten nucleation layer formed over the sidewall surface and the bottom surface; exposing an exposed portion of the tungsten nucleation layer along the sidewall surface of the tungsten nucleation layer to the nitrogen-containing ions to passivate the exposed portion of the tungsten nucleation layer, wherein the tungsten nucleation layer formed along the bottom surface remains substantially unpassivated; and Filling the feature with a tungsten layer includes the steps of preferentially growing the tungsten layer from the tungsten nucleation layer remaining on the bottom surface of the feature.

10. The method according to claim 9, further comprising the steps of: The pressure within the processing region is maintained such that a nitrogen partial pressure within the processing region is in a range of about 0.01 mTorr to about 0.05 mTorr.

11. The method of claim 10, wherein the pressure within the processing region is maintained in a range of about 5 mTorr to about 20 mTorr.

12. The method of claim 9, wherein the exposed portion of the tungsten nucleation layer along the sidewall surface of the tungsten nucleation layer is exposed to the nitrogen-containing ions for a time period in a range from about 3 seconds to about 20 seconds.

13. The method according to claim 9, further comprising the steps of: Free radicals transmitted from the ICP source to the processing region are filtered.

14. The method according to claim 9, further comprising the steps of: Free radicals are filtered from the output of the ICP source.

15. The method of claim 9, wherein filling the feature with the tungsten layer is performed in the processing region.

16. The method of claim 9, wherein the process gas comprises about 1% to about 10% nitrogen and the remainder being the inert gas, wherein the inert gas is argon.

17. A method for processing a semiconductor device structure in a processing chamber, comprising the steps of: exposing a semiconductor device structure to nitrogen-containing ions in a processing region of the processing chamber, the semiconductor device structure having: a feature formed on the semiconductor device structure, the feature having a plurality of sidewall surfaces and a bottom surface extending between the sidewall surfaces; one or more conformal / non-conformal layers formed over the sidewall surfaces and the bottom surface; and a boron-tungsten nucleation layer formed over the one or more conformal / non-conformal layers, wherein exposed portions of the tungsten nucleation layer along the sidewall surfaces of the tungsten nucleation layer are passivated by the nitrogen-containing ions to inhibit subsequent tungsten growth, and the boron-tungsten nucleation layer formed along the bottom surface remains substantially unpassivated; and partially filling the feature with a tungsten layer, comprising the steps of: preferentially growing the tungsten layer from the tungsten nucleation layer remaining on the bottom surface of the feature; and Exposing the semiconductor device structure to nitrogen-containing ions in the processing region and partially filling the feature with the tungsten layer is repeated until the tungsten layer reaches a target thickness.

18. The method according to claim 17, further comprising the steps of: The pressure within the processing region is maintained such that a nitrogen partial pressure within the processing region is in a range of about 0.01 mTorr to about 0.05 mTorr.

19. The method of claim 18, wherein the pressure within the processing region is maintained in a range of about 5 mTorr to about 20 mTorr.

20. The method of claim 19, wherein the exposed portion of the boron-tungsten nucleation layer along the sidewall surface is exposed to the nitrogen-containing ions for a time period in a range from about 3 seconds to about 20 seconds.

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