Via alternating mesh spacing

Abstract

The invention relates to via alternating mesh spacing. A chip includes a first web and a second web, where the first web and the second web are formed of the same metal layer, and the second web is adjacent to the first web. The chip also includes a first via disposed on the first web and a second via disposed on the second web. The first spacing is greater than the second spacing, the first spacing is between a first first via hole in the first via holes and a second first via hole in the first via holes, and the first first via hole in the first via holes is adjacent to the second first via hole in the first via holes; and the second pitch is between a first one of the first vias and a second one of the second vias closest to the first one of the first vias.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and the benefit of non-provisional application serial number 17 / 886,805 filed with the U.S. Patent Office on August 12, 2022. Technical Field

[0003] Aspects of the present disclosure relate generally to chip layout, and more particularly to via layout on a chip. Background Art

[0004] A chip (i.e., die) includes integrated devices (e.g., transistors) and a stack of metal layers that provide wiring for the devices. A chip may also include vias that provide electrical coupling between metal layers. As chip manufacturing advances, the size of structures on a chip continues to shrink. As the size decreases, the parasitic resistance of the vias on the chip continues to increase, which has a negative impact on the performance of the chip. Summary of the invention

[0005] The following is a simplified overview of one or more implementations to provide a basic understanding of such implementations. This overview is not an extensive overview of all contemplated implementations and is neither intended to identify key or essential elements of all implementations nor to define the scope of any or all implementations. Its sole purpose is to present some concepts of one or more implementations in a simplified form as a prelude to a more detailed description that is presented later.

[0006] A first aspect relates to a chip. The chip includes a first mesh and a second mesh, wherein the first mesh and the second mesh are formed by the same metal layer, and the second mesh is adjacent to the first mesh. The chip also includes a first via disposed on the first mesh and a second via disposed on the second mesh. The first spacing is greater than the second spacing, the first spacing is between a first first via in the first vias and a second first via in the first vias, the first first via in the first vias is adjacent to the second first via in the first vias, and the second spacing is between a first first via in the first vias and a second via in the second vias that is closest to the first first via in the first vias.

[0007] A second aspect relates to a chip. The chip includes a first mesh and a second mesh, wherein the first mesh and the second mesh are formed by the same metal layer, and the second mesh is adjacent to the first mesh. The chip also includes a first via disposed on the first mesh and a second via disposed on the second mesh. The first spacing is between a first first via in the first vias and a second first via in the first vias, the first first via in the first vias is adjacent to the second first via in the first vias, the second spacing is between the first first via in the first vias and the second via in the second vias that is closest to the first first via in the first vias, and each of the first spacing and the second spacing is within a range of a minimum spacing specified by a design rule to 1.1 times the minimum spacing. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 shows a side view of an example of a chip including metal layers and vias according to certain aspects of the present disclosure;

[0009] Figure 2A illustrates a side view of an example of a fin field effect transistor (FinFET) according to certain aspects of the present disclosure;

[0010] Figure 2B shows a top view of a FinFET according to certain aspects of the present disclosure;

[0011] Figure 3 shows a top view of an example of a multi-gate transistor according to certain aspects of the present disclosure;

[0012] Figure 4 shows an example of wiring according to certain aspects of the present disclosure;

[0013] Figure 5 shows an example of a layout using minimum spacing between vias on the same net according to certain aspects of the present disclosure;

[0014] Figure 6 shows an example of a layout using non-minimum spacing between vias on the same net in accordance with certain aspects of the present disclosure; and

[0015] Figure 7 An example of a layout using minimum spacing between vias in two directions in accordance with certain aspects of the present disclosure is shown. DETAILED DESCRIPTION

[0016] The detailed description given below in conjunction with the accompanying drawings is intended to describe various configurations rather than merely represent configurations in which the concepts described herein may be practiced. The detailed description includes specific details for providing a thorough understanding of the various concepts. However, it is clear to those skilled in the art that these concepts may be practiced without these specific details. In some cases, well-known structures and components are shown in block diagram form to avoid confusing such concepts.

[0017] Figure 1 1 shows a side view of an example of a chip 100 (ie, a die) according to certain aspects. The chip 100 may include many devices (eg, transistors) integrated on the chip 100. In this regard, Figure 1 An example of a transistor 110 integrated on a chip 100 is shown. Figure 1 One transistor 110 is shown in FIG. 1 , but it should be understood that chip 100 may include many transistors.

[0018] exist Figure 1 In the example shown, the transistor 110 includes a gate 115, a first source / drain 120-1, and a second source / drain 120-2. As used herein, the term "source / drain" refers to a source or a drain. The gate 115 is formed over a channel between the first source / drain 120-1 and the second source / drain 120-2, wherein the gate 115 controls the conductance of the channel based on a potential (i.e., voltage) applied to the gate 115. The transistor 110 may also include a thin gate oxide (not shown) between the gate and the channel. The gate 115 may be a polysilicon gate, a metal gate, or another type of gate. Figure 1 In the example shown, transistor 110 is depicted as a planar transistor. However, it should be understood that transistor 110 may be implemented using a fin field effect transistor (FinFET), an example of which will be described below with reference to FIG. Figure 2A and Figure 2B Have a discussion.

[0019] The chip 100 may further include a first source / drain contact 130-1 formed on the first source / drain 120-1 and a second source / drain contact 130-2 formed on the second source / drain 120-2. The source / drain contacts 130-1 and 130-2 may be formed by a source / source contact layer ( Figure 1 Marked as "MD" in the Figure 1 In the example of FIG. 1 , the source / drain contact layer is labeled as “MD”, but it should be understood that the source / drain contact layer may also be labeled as “CA” or another label.

[0020] The chip 100 may further include a gate contact 135 formed on the gate 115. The gate contact 135 may be formed by forming a gate contact layer ( Figure 1 Marked as "MP" in the Figure 1 In the example shown in FIG. 1 , the gate contact layer is labeled as “MP”, but it should be understood that the gate contact layer may also be labeled with another label.

[0021] Chip 100 may also include a stack 150 of metal layers (also referred to as a metal layer stack). Metal layers 150 are patterned (e.g., using photolithography and etching) to provide metal wiring for transistor 110 and other devices (not shown) on chip 100. Metal wiring may be used, for example, to interconnect devices on chip 100, couple devices to a power source, couple devices to one or more input / output (I / O) pins, and so on. Figure 1 In the example of , the bottom metal layer may be designated as metal layer M0 (also referred to as metal 0), the metal layer directly above metal layer M0 may be designated as metal layer M1 (also referred to as metal 1), the alloy layer directly above metal layer M1 may be designated as metal layer M2 (also referred to as metal 2), and so on. Although for ease of explanation, in Figure 1 , but it should be understood that chip 100 may include additional metal layers (e.g., five or more metal layers, including metal layer M3, metal layer M4, etc.). It should be understood that the present disclosure is not limited to the nomenclature in which the bottom-most metal layer is designated as metal layer M0. For example, in another example, the bottom-most metal layer may be designated as metal layer M1 instead of metal layer M0.

[0022] Chip 100 also includes vias 160 that provide electrical coupling between metal layers 150 and between metal layer M0 and contacts 130-1, 130-2, and 135. In this example, via VD provides electrical coupling between source / drain contacts 130-1 and 130-2 and metal layer M0, and via VG provides electrical coupling between gate contact 135 and metal layer M0. Via V0 provides electrical coupling between metal layer M0 and metal layer M1, and via V1 provides electrical coupling between metal layer M1 and metal layer M2.

[0023] Figure 2A 1 shows a side view of an example in which transistor 110 is implemented with a FinFET, and Figure 2B 1 and 2. In this example, transistor 110 includes fins 210-1 to 210-4 extending vertically relative to gate 115 and source / drain contacts 130-1 and 130-2 (eg, Figure 2B Although Figure 2BIn the example of FIG. 1 , four fins 210 - 1 to 210 - 4 are shown, but it should be understood that the transistor 110 may include a different number of fins. In addition, although the fins 210 - 1 to 210 - 4 are shown as having a rectangular cross-section, it should be understood that the fins may have other cross-sectional shapes (e.g., a tapered cross-section). Note that the metal layer 150, the via 160, and the gate contact 135 are arranged in a substantially rectangular manner. Figure 2B Not explicitly shown.

[0024] In this example, gate 115 is formed over first portions 215 of fins 210-1 to 210-4. First portions 215 of fins 210-1 to 210-4 form a channel of transistor 110, wherein gate 115 controls the conductance of the channel based on a potential (i.e., voltage) applied to gate 115. Gate 115 may wrap around three or more sides of each fin (e.g., a top side and two opposing sidewalls of each fin). In this example, transistor 110 may also include a thin dielectric layer (not shown) between fins 210-1 to 210-4 and gate 115. Figure 2A As shown, a gate contact 135 may be formed on the gate 115 , and a via VG may electrically couple the gate contact 135 to the metal layer M0 .

[0025] A portion of the fins 210-1 to 210-4 extending from a first side 222-1 of the gate 115 forms a first source / drain 120-1, and a portion of the fins 210-1 to 210-4 extending from a second side 222-2 of the gate 115 forms a second source / drain 120-2, wherein the first side 222-1 and the second side 222-2 are opposite sides of the gate 115. In this example, a first source / drain contact 130-1 is formed over a second portion 220-1 of the fins 210-1 to 210-4 on the first side 222-1 of the gate 115, and a second source / drain contact 130-2 is formed over a third portion 220-2 of the fins 210-1 to 210-4 on the second side 222-2 of the gate 115. Each of the source / drain contacts 130-1 to 130-2 may be made of a conductive material (e.g., one or more metals). Figure 2A As shown, vias VD may electrically couple source / drain contacts 130 - 1 to 130 - 2 to metal layer M0 .

[0026] It should be understood that transistor 110 may include Figure 2A and Figure 2B For example, transistor 110 may include sidewall spacers on first side 222 - 1 and second side 222 - 2 of gate 115 .

[0027] In some aspects, transistor 110 may be implemented using a multi-gate transistor (also referred to as a multi-finger transistor) including multiple gates. In this regard, Figure 3 1 shows a top view in which transistor 110 includes multiple gates, including a first gate 115-1 and a second gate 115-2. The first gate 115-1 may correspond to gate 115 discussed above. The first gate 115-1 and the second gate 115-2 run (ie, extend) parallel to each other. Although in Figure 3 In the example of FIG. 1 , two gates are shown, but it should be understood that transistor 110 may include more than two gates. Gates 115 - 1 and 115 - 2 may be electrically coupled to each other through metal wiring (not shown) formed by one or more of metal layers 150 and two or more of vias 160 .

[0028] exist Figure 3 In the example shown, the transistor 110 includes fins 210-1 to 210-4 extending vertically relative to the gates 115-1 and 115-2. The first gate 115-1 and the second gate 115-2 are formed on the fins 210-1 to 210-4. Figure 3 As shown. In this example, transistor 110 includes a first source / drain contact 130-1 and a second source / drain contact 130-2 formed on fins 210-1 to 210-4. Transistor 110 also includes a third source / drain contact 130-3 formed on fins 210-1 to 210-4. Source / drain contacts 130-1 to 130-3 are parallel to each other and run (i.e., extend) parallel to gates 115-1 and 115-2. In this example, the first source / drain contact 130-1 and the second source / drain contact 130-2 are located on opposite sides of the first gate 115-1, and the second source / drain contact 130-2 and the third source / drain contact 130-3 are located on opposite sides of the second gate 115-2. Furthermore, in this example, a second source / drain contact 130 - 2 is located between the first gate 115 - 1 and the second gate 115 - 2 .

[0029] Figure 4A top view of an example of a wiring 410 according to certain aspects is shown. The wiring 410 can be used, for example, to provide wiring for the transistor 110. The wiring 410 includes a first net 420-1, a second net 420-2, a third net 420-3, and a fourth net 420-4. In this example, the first net 420-1, the second net 420-2, the third net 420-3, and the fourth net 420-4 are formed from the same metal layer (e.g., one of the metal layer M1, the metal layer M2, etc.). For example, the first net 420-1, the second net 420-2, the third net 420-3, and the fourth net 420-4 can be formed from the same metal layer using a photolithography process and an etching process that pattern the metal layer into individual nets 420-1, 420-2, 420-3, and 420-4. In this example, each of the webs 420 - 1 , 420 - 2 , 420 - 3 , and 420 - 4 extends in a lateral direction 450 . As used herein, the term “lateral” refers to a direction running parallel to the substrate of the chip 100 .

[0030] exist Figure 4 In the example in , each of the nets 420-1, 420-2, 420-3 and 420-4 is shown as a corresponding continuous metal line extending in the lateral direction 450, wherein the nets 420-1, 420-2, 420-3 and 420-4 run parallel to each other. However, it should be understood that the present disclosure is not limited to this example. Typically, each of the nets 420-1, 420-2, 420-3 and 420-4 can be a corresponding continuous metal path formed by a metal layer (e.g., one of the metal layers M1, M2, etc.). As used herein, a "net" refers to a continuous metal path formed by a metal layer. By patterning the metal layer into individual nets (e.g., using photolithography and etching), a net can be formed by the same metal layer.

[0031] Figure 4 An example is shown in which the wiring 410 is used for a transistor (eg, the transistor 110). However, it should be understood that the wiring 410 is not limited to this example. Figure 4In an example of, the first mesh 420-1 may provide wiring for the drain of a transistor (e.g., transistor 110). For example, the first mesh 420-1 may be electrically coupled to the first source / drain 120-1. In this example, the first mesh 420-1 may be electrically coupled to the first source and drain 120-1 through the first source / drain contact 130-1, vias, and one or more intermediate metal layers (i.e., one or more metal layers between the first source / drain 120-1 and the metal layer used to form the first mesh 420-1). For examples in which the first mesh 420-1 is formed by metal layer M1, the one or more intermediate metal layers may include metal layer M0. For examples in which the first mesh 420-1 is formed by metal layer M2, the one or more intermediate metal layers may include metal layer M0 and metal layer M1. For examples in which the first mesh 420-1 is formed by metal layer M0, there may be no intermediate metal layer. In this example, the first net 420 - 1 may be coupled to the first source / drain contact 130 - 1 through one or more vias VD.

[0032] exist Figure 4 In an example of, the second mesh 420-2 may provide wiring for a first gate of a transistor (e.g., transistor 110). For example, the second mesh 420-2 may be electrically coupled to the first gate 115-1. In this example, the second mesh 420-2 may be electrically coupled to the first gate 115-1 through a corresponding gate contact (e.g., gate contact 135), a via, and one or more intermediate metal layers (i.e., one or more metal layers between the first gate 115-1 and the metal layer used to form the second mesh 420-2). For an example in which the second mesh 420-2 is formed by a metal layer M1, the one or more intermediate metal layers may include a metal layer M0. For an example in which the second mesh 420-2 is formed by a metal layer M2, the one or more intermediate metal layers may include a metal layer M0 and a metal layer M1. For an example in which the second mesh 420-2 is formed by a metal layer M0, there may be no intermediate metal layer. In this example, the second mesh 420-2 may be coupled to the first gate 115-1 through one or more vias VG.

[0033] exist Figure 4In the example of , the third net 420-3 can provide wiring for the source of the transistor (e.g., transistor 110). For example, the third net 420-3 can be electrically coupled to the second source / drain 120-2. In this example, the third net 420-3 can be electrically coupled to the second source / drain 120-2 through the second source / drain contact 130-2, the via, and one or more intermediate metal layers (i.e., one or more metal layers between the second source / drain 120-2 and the metal layer used to form the third net 420-3). For the example in which the third net 420-3 is formed by the metal layer M1, the one or more intermediate metal layers may include the metal layer M0. For the example in which the third net 420-3 is formed by the metal layer M2, the one or more intermediate metal layers may include the metal layer M0 and the metal layer M1. For the example in which the third net 420-3 is formed by the metal layer M0, there may be no intermediate metal layer. In this example, the third net 420 - 3 may be coupled to the second source / drain contact 130 - 2 through one or more vias VD.

[0034] exist Figure 4 In the example of, the fourth net 420-4 can provide wiring for the second gate of the transistor (e.g., transistor 110). For example, the fourth net 420-4 can be electrically coupled to the second gate 115-2. In this example, the fourth net 420-4 can be electrically coupled to the second gate 115-2 through corresponding gate contacts, vias, and one or more intermediate metal layers (i.e., one or more metal layers between the second gate 115-2 and the metal layer used to form the fourth net 420-4). For the example in which the fourth net 420-4 is formed by the metal layer M1, the one or more intermediate metal layers may include the metal layer M0. For the example in which the fourth net 420-4 is formed by the metal layer M2, the one or more intermediate metal layers may include the metal layer M0 and the metal layer M1. For the example in which the fourth net 420-4 is formed by the metal layer M0, there may be no intermediate metal layer. In this example, the fourth net 420-4 can be coupled to the second gate 115-2 through one or more vias VG.

[0035] It should be understood that wiring 410 is not limited to Figure 4 The example shown, and the wiring 410 may include Figure 4 One or more additional nets other than the nets 420-1, 420-2, 420-3, and 420-4 shown. For example, wiring 410 may include Figure 3 A fifth network (not shown) of the third source / drain 130 - 3 is shown.

[0036] Vias may be placed on meshes 420-1, 420-2, 420-3, and 420-4 to electrically couple meshes 420-1, 420-2, 420-3, and 420-4 to a metal layer located above a metal layer used to form meshes 420-1, 420-2, 420-3, and 420-4. For example, when meshes 420-1, 420-2, 420-3, and 420-4 are formed by metal layer M1, vias may electrically couple meshes 420-1, 420-2, 420-3, and 420-4 to metal layer M2. However, it should be understood that the present disclosure is not limited to this example.

[0037] The placement of vias on nets 420-1, 420-2, 420-3, and 420-4 may be governed by design rules, which may be specified by a chip foundry or other entity. For example, a design rule may define a minimum spacing between vias. In this example, the design rule may allow the spacing between vias to be equal to or greater than the minimum spacing but not less than the minimum spacing. During chip layout, the placement of vias on nets 420-1, 420-2, 420-3, and 420-4 may be checked for compliance with the design rules in a process known as design rule checking (DRC). DRC helps ensure that the final layout of the vias on nets 420-1, 420-2, 420-3, and 420-4 complies with the design rules.

[0038] As chip manufacturing advances, the size of the vias becomes smaller, and the parasitic resistance of the vias on the chip 100 continues to increase, which has a negative impact on the performance of the chip 100. One way to reduce the parasitic resistance is to place multiple vias on the same net, where the spacing between the vias is equal to the minimum spacing between vias allowed by the design rules. Using a minimum spacing between vias allows more vias to be placed on the net, which increases the number of parallel vias between the net and the metal layer above the net (i.e., increases the parallelization of the vias). The increased parallelization of the vias reduces the parasitic resistance caused by the vias.

[0039] According to certain aspects, examples of the above method are as follows Figure 5 shown. Figure 5 An example of a via 510-1 disposed on the first mesh 420-1 is shown. The via 510-1 can electrically couple the first mesh 420-1 to another mesh (not shown) formed by a metal layer that is above the metal layer used to form the first mesh 420-1. For example, if the first mesh 420-1 is formed by the metal layer M1, the other mesh can be formed by the metal layer M2. However, it should be understood that the present disclosure is not limited to this example.

[0040] Figure 5An example of a via 510-2 disposed on the third net 420-3 is also shown. For example, the via 510-2 can electrically couple the third net 420-3 to another net (not shown) formed by a metal layer that is above the metal layer used to form the third net 420-3. For example, if the third net 420-3 is formed by the metal layer M1, the other net can be formed by the metal layer M2. However, it should be understood that the present disclosure is not limited to this example.

[0041] In this example, the spacing between the vias 510-1 on the first net 420-1 is equal to the minimum spacing between vias allowed by the design rules. Figure 5 , the minimum pitch is labeled “m.” In this example, placing vias 510 - 1 on first net 420 - 1 with the minimum pitch allows more vias to be placed on first net 420 - 1 to increase parallelism and reduce parasitic resistance.

[0042] Similarly, the spacing between vias 510-2 on the third net 420-3 is equal to the minimum spacing between vias. In this example, placing vias 510-2 on the third net 420-3 with the minimum spacing allows more vias to be placed on the third net 420-3 to increase parallelism and reduce parasitic resistance.

[0043] Thus, in this example, the minimum via spacing on the first net 420-1 and the third net 420-3 increases via parallelization and reduces the parasitic resistance of these nets 420-1 and 420-3. For an example in which the first net 420-1 provides drain wiring for the transistor 110 and the third net 420-3 provides source wiring for the transistor 110, the minimum via spacing can significantly reduce the drain resistance and the source resistance.

[0044] However, the minimum via spacing on the first net 420-1 and the third net 420-3 may result in forbidden zones 520-1 and 520-2 on adjacent nets (i.e., the second net 420-2 and the fourth net 420-4), where design rules do not allow other vias to be placed. The forbidden zones 520-1 and 520-2 (also referred to as blocking zones) may significantly limit the placement of vias on the second net 420-2 and the fourth net 420-4. For example, the forbidden zone 520-1 may limit the placement of vias on the second net 420-2 to the end of the second net 420-2 outside the forbidden zone 520-1. The same may apply to the fourth net 420-4. In other words, the electrical connections to the nets 420-2 and 420-4 may be pushed away from the nets 420-1 and 420-3.

[0045] Thus, the keep-outs 520-1 and 520-2 may prevent or significantly reduce the ability of the nets 420-2 to 420-4 to reduce parasitic resistance using via parallelization. For an example where the second net 420-2 and the fourth net 420-4 provide gate wiring for the transistor 110, the keep-outs 520-1 and 520-2 may result in high gate resistance. Therefore, a via layout that reduces overall parasitic resistance (e.g., over all terminals of the transistor 110) is desirable.

[0046] Aspects of the present disclosure provide via layouts that use non-minimum spacing for vias on the same net. This helps prevent keep-out zones (e.g., keep-out zones 520-1 and 520-2) on adjacent nets (e.g., nets 420-2 and 420-4), thereby allowing parallelization of vias on adjacent nets. Parallelization of vias on adjacent nets reduces the parasitic resistance of adjacent nets, which results in an overall reduction in parasitic resistance (e.g., between all terminals of a transistor such as transistor 110), as discussed further below.

[0047] As used herein, "non-minimum spacing" refers to a spacing that is greater than the minimum spacing between vias specified by the design rules. The design rules may be provided by a foundry (also referred to as a "fab") and may be defined for a manufacturing process for manufacturing chip 100. It should be understood that the design rules may vary from foundry to foundry and may be different for different manufacturing processes. As used herein, when there is no intervening net between two nets at the same metal layer (i.e., there is no intervening net formed by the same metal layer as the two nets), one net is an "adjacent net" of another net. Adjacent nets may also be referred to as adjacent nets or alternative nets. As used herein, the spacing between vias on the same net may refer to the spacing between adjacent vias on the same net. As used herein, the spacing between vias on two nets may refer to the spacing between one of the vias on one net and the closest one of the vias on the other net. As used herein, the "spacing" between two vias may be the closest spacing between the edge of one via and the edge of another via.

[0048] Figure 6 An example of a via layout using non-minimum spacing for vias on the same net according to certain aspects is shown. The vias in this example can be patterned from a via layer using a photolithography process and an etching process. In certain aspects, the photolithography process can use multiple masks to define the vias instead of using a single mask. Using multiple masks to define the vias may increase costs due to the addition of one or more additional masks. However, using multiple masks can provide finer via features, which can facilitate tighter spacing between vias in one or more lateral directions, as discussed further below.

[0049] exist Figure 6In the example of , webs 420 - 1 , 420 - 2 , 420 - 3 , and 420 - 4 extend in a transverse direction 450 , and are spaced apart from one another in a transverse direction 650 , wherein the transverse direction 650 is perpendicular to the transverse direction 450 .

[0050] exist Figure 6 In the example of , vias 610-1 to 610-4 are disposed on the first mesh 420-1. The vias 610-1 to 610-4 can electrically couple the first mesh 420-1 to another mesh (not shown) formed by a metal layer that is above the metal layer used to form the first mesh 420-1. For example, if the first mesh 420-1 is formed by the metal layer M1, the other mesh can be formed by the metal layer M2. However, it should be understood that the present disclosure is not limited to this example.

[0051] In this example, the spacing s1 between the vias 610-1 to 610-4 on the first net 420-1 is greater than the minimum spacing between vias specified by the design rules of the manufacturing process used to manufacture the chip 100. In one example, the spacing s1 between the vias 610-1 to 610-4 on the first net 420-1 is greater than 1.1 times the minimum spacing. In another example, the spacing s1 between the vias 610-1 to 610-4 on the first net 420-1 is greater than 1.3 times the minimum spacing. In yet another example, the spacing s1 between the vias 610-1 to 610-4 on the first net 420-1 is greater than 1.5 times the minimum spacing. Figure 6 In the example of , the spacing s1 is equal to the spacing between adjacent vias 610 - 1 to 610 - 4 on the first net 420 - 1 . Note that since the first net 420 - 1 extends in the lateral direction 450 , the spacing s1 is in the lateral direction 450 in this example.

[0052] Therefore, in this example, the spacing s1 between the vias 610-1 to 610-4 on the first net 420-1 is greater than the minimum spacing between vias specified by the design rule. In this example, the larger spacing s1 removes Figure 5 The exclusion zone 520-1 on the second net 420-2 is shown. The removal of the exclusion zone 520-1 allows vias to be placed on the second net 420-2 adjacent to the first net 420-1. In this regard, Figure 6 An example of vias 620-1 to 620-4 disposed on the second net 420-2 is shown. The vias 620-1 to 620-4 on the second net 420-2 provide parallelization of the vias on the second net 420-2, and Figure 5 This reduces the parasitic resistance of the second network 420-2 by comparison. Figure 6 The exemplary layout shown allows for parallelization of vias on the second net 420 - 2 (ie, an adjacent net to the first net 420 - 1 ).

[0053] In one example, the via spacing s2 between the second net 420-2 and the first net 420-1 may be equal to the minimum spacing between vias specified by the design rule (ie, s2=m). Figure 6 As shown, the via spacing s2 may refer to the spacing between one of the vias 620-1 to 610-4 on the second net 420-2 and the closest one of the vias 610-1 to 610-4 on the first net 420-1. For example, the via spacing s2 may refer to the spacing between the via 620-1 on the second net 420-1 and the via 610-1 of the first net 420-1, where the via 610-1 is the via closest to the via 620-1 on the first net 420-1. Figure 6 In the example in , the spacing s2 is in the transverse direction 650 .

[0054] Therefore, in this example, the minimum spacing between vias is used for the via spacing s2 between the first net 420-1 and the second net 420-2 (ie, adjacent nets), rather than the spacing s1 between the vias 610-1 to 610-4 on the first net 420-1 (ie, the same net). However, it should be understood that the present disclosure is not limited to this example, and the via spacing s2 may be greater than the minimum spacing. For example, the via spacing s2 may be in the range of the minimum spacing to 1.1 times the minimum spacing. Typically, the spacing s1 between the vias 610-1 to 610-4 on the first net 420-1 (ie, the same net) is greater than the via spacing s2 between the first net 420-1 and the second net 420-2 (ie, adjacent nets). In one example, the ratio of spacing s1 to spacing s2 is equal to or greater than 1.1. In another example, the ratio of spacing s1 to spacing s2 is equal to or greater than 1.3. In yet another example, the ratio of spacing s1 to spacing s2 is equal to or greater than 1.5.

[0055] and Figure 5 compared to, Figure 6 The larger spacing s1 between the vias 610-1 to 610-4 in the example slightly increases the parasitic resistance of the first net 420-1 due to the parallelization reduction of the vias on the first net 420-1. However, the slight increase in the parasitic resistance of the first net 420-1 is offset by the parallelization of the vias on the second net 420-2, which results in an overall reduction in parasitic resistance on the nets 420-1 and 420-2. In other words, the exemplary layout allows both the nets 420-1 and 420-2 to benefit from the parallelization of the vias, resulting in an overall reduction in parasitic resistance.

[0056] exist Figure 6In the example of , vias 610-1 to 610-4 and 620-1 to 620-4 can be patterned using a two-mask (i.e., dual-mask) process that allows a minimum spacing between vias in one of the lateral directions 450 and 650. In this example, the minimum spacing can be selected for the lateral direction 650. Since the nets 420-1 and 420-2 are spaced apart in the lateral direction 650, this allows the via spacing s2 between the first net 420-1 and the second net 420-2 (i.e., adjacent nets) to be equal to the minimum spacing in this example. It should be understood that the present disclosure is not limited to a two-mask process for patterning vias 610-1 to 610-4 and 620-1 to 620-4. For example, in other implementations, three or more masks can be used.

[0057] exist Figure 6 In the example shown, vias 610-1 to 610-4 on first net 420-1 are evenly spaced apart. However, it should be understood that the present disclosure is not limited to this example. In some aspects, spacing s1 may refer to the spacing between two adjacent vias on first net 420-1 (e.g., the spacing between vias 610-1 and 610-2). As used herein, two vias on the same net are adjacent to each other when there is no intervening via between the two vias on the same net.

[0058] exist Figure 6 In the example of FIG. 4 , the spacing s3 between the vias 620 - 1 to 620 - 4 on the second net 420 - 2 may be the same as the spacing s1 between the vias 610 - 1 to 610 - 4 on the first net 420 - 1 . However, it should be understood that the present disclosure is not limited to this example.

[0059] Figure 6 An example of vias 615-1 to 615-4 disposed on the third net 420-3 is also shown. For example, the vias 615-1 to 615-4 can electrically couple the third net 420-3 to another net (not shown) formed by a metal layer that is above the metal layer used to form the third net 420-3. For example, if the third net 420-3 is formed by the metal layer M1, the other net can be formed by the metal layer M2. However, it should be understood that the present disclosure is not limited to this example.

[0060] exist Figure 6In the example, the spacing s4 between the vias 615-1 to 615-4 on the third net 420-3 is greater than the minimum spacing between the above-mentioned vias. In some aspects, the spacing s4 can be equal to the spacing s1. In one example, the spacing s4 between the vias 615-1 to 615-4 on the third net 420-3 is greater than 1.1 times the minimum spacing. In another example, the spacing s4 between the vias 615-1 to 615-4 on the third net 420-3 is greater than 1.3 times the minimum spacing. In yet another example, the spacing s4 between the vias 615-1 to 615-4 on the third net 420-3 is greater than 1.5 times the minimum spacing. Figure 6 In the example of , the spacing s4 is equal to the spacing between adjacent vias 615 - 1 to 615 - 4 on the third net 420 - 3 . Note that since the third net 420 - 3 extends in the lateral direction 450 , the spacing s4 is in the lateral direction 450 in this example.

[0061] Therefore, in this example, the spacing s4 between the vias 615-1 to 615-4 on the third net 420-3 is greater than the minimum spacing between vias specified by the design rule. The larger spacing s4 removes Figure 5 The exclusion zone 520-2 on the fourth net 420-3 is shown. The removal of the exclusion zone 520-2 allows vias to be placed on the fourth net 420-4 adjacent to the third net 420-3. In this regard, Figure 6 An example of vias 625-1 to 625-4 disposed on the fourth net 420-3 is shown. The vias 625-1 to 625-4 on the fourth net 420-4 provide parallelization of the vias on the fourth net 420-4, and Figure 5 This reduces the parasitic resistance of the fourth network 420-4 by comparison. Figure 6 The exemplary layout shown allows for parallelization of vias on the fourth net 420 - 4 (ie, an adjacent net to the third net 420 - 3 ).

[0062] In one example, the via spacing s5 between the third net 420-3 and the fourth net 420-4 may be equal to the minimum spacing between vias specified by the design rule (i.e., s5=m). The via spacing s5 may refer to the spacing between one of the vias 615-1 to 615-4 on the third net 420-3 and the closest one of the vias 625-1 to 625-4 on the fourth net 420-4, such as Figure 6 For example, the via spacing s5 may refer to the spacing between the via 625-1 on the fourth net 420-4 and the via 615-1 on the third net 420-3, wherein the via 615-1 is the via closest to the via 625-1 on the third net 420-3. Figure 6 In the example in , the spacing s5 is in the transverse direction 650 .

[0063] In some aspects, the spacing s5 can be equal to the spacing s2. Therefore, in this example, the minimum spacing between the vias is used for the via spacing s5 between the third net 420-3 and the fourth net 420-4 (ie, adjacent nets), rather than the spacing s4 between the vias 615-1 to 615-4 on the third net 420-3 (ie, the same net). However, it should be understood that the present disclosure is not limited to this example, and the via spacing s5 can be greater than the minimum spacing. For example, the via spacing s5 can be in the range of 1.1 times the minimum spacing to the minimum spacing. Typically, the spacing s4 between the vias 615-1 to 615-4 on the third net 420-3 (ie, the same net) is greater than the via spacing s5 between the third net 420-3 and the fourth net 420-4 (ie, adjacent nets). In one example, the ratio of spacing s4 to spacing s5 is equal to or greater than 1.1. In another example, the ratio of spacing s4 to spacing s5 is equal to or greater than 1.3. In yet another example, a ratio of the spacing s4 to the spacing s5 is equal to or greater than 1.5.

[0064] and Figure 5 compared to, Figure 6 The larger spacing s4 between vias 615-2 to 625-4 in the example slightly increases the parasitic resistance of the third net 420-3 due to the parallelization reduction of the vias on the third net 420-3. However, the slight increase in the parasitic resistance of the third net 420-3 is offset by the parallelization of the vias on the fourth net 420-4, which results in an overall reduction in parasitic resistance on nets 420-3 and 420-4. In other words, the exemplary layout allows both nets 420-3 and 420-4 to benefit from the parallelization of the vias, resulting in an overall reduction in parasitic resistance.

[0065] exist Figure 6 In the example of , vias 615-1 to 615-4 and 625-1 to 625-4 can be patterned using a two-mask (i.e., dual-mask) process that allows a minimum spacing between vias in one of the lateral directions 450 and 650. In this example, the minimum spacing can be selected for the lateral direction 650. Since nets 420-3 and 420-4 are spaced apart in the lateral direction 650, this allows the via spacing s5 between the third net 420-3 and the fourth net 420-4 (i.e., adjacent nets) to be equal to the minimum spacing between the vias in this example. It should be understood that the present disclosure is not limited to a two-mask process for patterning vias 615-1 to 615-4 and 625-1 to 625-4. For example, in other implementations, three or more masks can be used.

[0066] exist Figure 6In the example shown, the vias 615-1 to 615-4 on the third net 420-3 are evenly spaced apart. However, it should be understood that the present disclosure is not limited to this example. In some aspects, the spacing s4 can refer to the spacing between two adjacent vias on the third net 420-3 (e.g., the spacing between vias 615-1 and 615-2).

[0067] exist Figure 6 In the example of FIG. 4 , the spacing s6 between the vias 625 - 1 to 625 - 4 on the fourth net 420 - 4 may be the same as the spacing s4 between the vias 615 - 1 to 615 - 4 on the third net 420 - 3 . However, it should be understood that the present disclosure is not limited to this example.

[0068] So, in the above example, with Figure 5 1 and 1 , using non-minimum spacing for vias on the same net slightly increases the parasitic resistance of the first net 420-1 and the third net 420-3 compared to the layout method shown. However, the parallelization of vias on adjacent nets (i.e., the second net 420-2 and the fourth net 420-4) results in an overall reduction in parasitic resistance (e.g., between all terminals of the transistor 110), which outweighs the slight increase in the parasitic resistance of the first net 420-2 and the third net 420-3. In other words, Figure 6 The exemplary layout approach shown allows all of the nets 420 - 1 , 420 - 2 , 420 - 3 , and 420 - 4 to benefit from the parallelization of vias, resulting in an overall reduction in parasitic resistance.

[0069] exist Figure 6 In the example shown, the nets 420-1, 420-2, 420-3, and 420-4 extend in a transverse direction 450 and are spaced apart from each other in a transverse direction 650, wherein the transverse direction 650 is perpendicular to the transverse direction 450. Furthermore, in this example, the spacings s1, s3, s4, and s6 between vias on the same net are in the transverse direction 450, and the spacings s2 and s5 between vias on adjacent nets are in the transverse direction 650. However, it should be understood that the present disclosure is not limited to this example.

[0070] exist Figure 6 In the example shown, the nets 420-1, 420-2, 420-3, and 420-4 are shown as having a generally rectangular shape. However, it should be understood that the nets 420-1, 420-2, 420-3, and 420-4 can have other shapes. In some aspects, each of the nets 420-1, 420-2, 420-3, and 420-4 is continuous, but can have any of a variety of different shapes.

[0071] Furthermore, it should be understood that nets 420-1, 420-2, 420-3, and 420-4 are not limited to drain, first gate, source, and second gate (ie, D, G, S, G), respectively. In general, nets 420-1, 420-2, 420-3, and 420-4 may be any nets that are different from one another.

[0072] exist Figure 6 In the example shown, the second net 420-2 and the third net 420-3 are also adjacent nets. Figure 6 The via spacing s7 shown may refer to the spacing between one of the vias 620-1 to 620-4 on the second net 420-2 and the closest one of the vias 615-1 to 615-4 on the third net 420-3. For example, the via spacing s7 may refer to the spacing between the via 620-1 on the second net 420-1 and the via 615-1 on the third net 420-3, where the via 615-1 is the via closest to the via 620-1 on the third net 420-3. In one example, the via spacing s7 between the second net 420-2 and the third net 420-3 may be equal to the minimum spacing between the vias specified by the design rule (i.e., s7=m). However, it should be understood that the present disclosure is not limited to this example, and the via spacing s7 may be greater than the minimum spacing. For example, the via spacing s7 may be in the range of the minimum spacing to 1.1 times the minimum spacing. Typically, the spacing s4 between the vias 615-1 to 615-4 on the third net 420-3 (i.e., the same net) is greater than the via spacing s7 between the second net 420-2 and the third net 420-3 (i.e., adjacent nets). In one example, the ratio of the spacing s4 to the spacing s7 is equal to or greater than 1.1. In another example, the ratio of the spacing s4 to the spacing s7 is equal to or greater than 1.3. In yet another example, the ratio of the spacing s4 to the spacing s7 is equal to or greater than 1.5.

[0073] In some aspects, vias 610-1 to 610-4, 615-1 to 615-4, 620-1 to 620-4, and 625-1 to 625-4 can be patterned using a multi-mask lithography process that allows for minimum pitch in both lateral direction 650 and lateral direction 450. For example, multi-mask lithography can use a combination of more than two masks, and / or extreme ultraviolet lithography (also known as EUV) and one or more masks. In this example, multiple masks and / or EUV allow for minimal pitch without Figure 5 The minimum spacing of vias on the same net in the case of the forbidden areas 520-1 and 520-2 is shown. Figure 7An example is shown where the spacing s1, s3, s4, and s6 between vias 610-1 to 610-6, 615-1 to 615-6, 620-1 to 620-6, and 625-1 to 625-6 on the same net is equal to the minimum spacing, and the via spacing s2, s5, and s7 is equal to the minimum spacing. Using the minimum spacing in both directions 450 and 650 increases via parallelization, thereby further reducing parasitic resistance.

[0074] It should be understood that the spacings s1 to s7 do not have to be exactly equal to the minimum spacing defined by the design rules. In some aspects, each of the spacings s1 to s7 or each of a subset of the spacings s1 to s7 can be in the range of the minimum spacing to 1.1 times the minimum spacing. For example, the spacing s1 can be in the range of the minimum spacing to 1.1 times the minimum spacing, where the spacing s1 can refer to the spacing between two adjacent vias on the first net 420-1 (e.g., the spacing between vias 610-1 and 610-2). In another example, the via spacing s2 between the second net 420-2 and the first net 420-1 can be in the range of the minimum spacing to 1.1 times the minimum spacing. As Figure 7 As shown, the via spacing s2 may refer to the spacing between one of the vias 620-1 to 620-4 on the second net 420-2 and the closest one of the vias 610-1 to 610-4 on the first net 420-1. For example, the via spacing s2 may refer to the spacing between the via 620-1 on the second net 420-1 and the via 610-1 of the first net 420-1, wherein the via 610-1 is the via closest to the via 620-1 on the first net 420-1.

[0075] As used herein, a pitch within the range of the minimum pitch to 1.1 times the minimum pitch includes a pitch equal to the minimum pitch, a pitch equal to 1.1 times the minimum pitch, or any one of a pitch between the minimum pitch and 1.1 times the minimum pitch.

[0076] Implementation examples are described in the following numbered clauses:

[0077] 1. A chip, comprising:

[0078] FirstNet;

[0079] a second mesh, wherein the first mesh and the second mesh are formed of a same metal layer and the second mesh is adjacent to the first mesh;

[0080] A first via hole is provided on the first net; and

[0081] A second via hole is provided on the second net;

[0082] Wherein the first spacing is greater than the second spacing, the first spacing is between a first one of the first vias and a second one of the first vias, the first one of the first vias is adjacent to the second one of the first vias, and the second spacing is between the first one of the first vias and a second one of the second vias that is closest to the first one of the first vias.

[0083] 2. The chip of clause 1, wherein the first pitch is greater than 1.1 times a minimum pitch specified by a design rule.

[0084] 3. The chip of clause 2, wherein the second pitch is in the range of the minimum pitch to 1.1 times the minimum pitch.

[0085] 4. The chip of clause 1, wherein the first pitch is greater than 1.3 times a minimum pitch specified by a design rule.

[0086] 5. The chip of clause 1, wherein the first pitch is greater than 1.5 times a minimum pitch specified by a design rule.

[0087] 6. A chip according to any one of clauses 1 to 5, wherein a ratio of the first pitch to the second pitch is greater than 1.1.

[0088] 7. A chip according to any one of clauses 1 to 5, wherein a ratio of the first pitch to the second pitch is greater than 1.3.

[0089] 8. A chip according to any one of clauses 1 to 5, wherein a ratio of the first pitch to the second pitch is greater than 1.5.

[0090] 9. A chip according to any of clauses 1 to 8, wherein the first net comprises a first continuous metal line and the second net comprises a second continuous metal line.

[0091] 10. A chip according to any one of clauses 1 to 9, wherein:

[0092] The first net is electrically coupled to a source or a drain of a transistor; and

[0093] The second net is electrically coupled to a gate of the transistor.

[0094] 11. A chip according to any one of clauses 1 to 10, further comprising:

[0095] a third mesh, wherein the third mesh is formed of the same metal layer as the first mesh and the second mesh, and the third mesh is adjacent to the second mesh; and

[0096] A third via hole is provided on the third net;

[0097] The third spacing is greater than the fourth spacing, the third spacing is between the first third via among the third vias and the second third via among the third vias, the first third via among the third vias is adjacent to the second third via among the third vias, and the fourth spacing is between the first third via among the third vias and the second via among the second vias that is closest to the first third via among the third vias.

[0098] 12. A chip according to clause 11, wherein:

[0099] The first network is electrically coupled to a drain of the transistor;

[0100] The second mesh is electrically coupled to a gate of the transistor; and

[0101] The third net is electrically coupled to the source of the transistor.

[0102] 13. The chip of clause 11 or 12, wherein the first pitch and the third pitch are each greater than 1.1 times a minimum pitch specified by a design rule.

[0103] 14. The chip of clause 11 or 12, wherein the first pitch and the third pitch are each greater than 1.3 times a minimum pitch specified by a design rule.

[0104] 15. The chip of clause 11 or 12, wherein the first pitch and the third pitch are each greater than 1.5 times a minimum pitch specified by a design rule.

[0105] 16. A chip, comprising:

[0106] FirstNet;

[0107] a second mesh, wherein the first mesh and the second mesh are formed of a same metal layer and the second mesh is adjacent to the first mesh;

[0108] A first via hole is provided on the first net; and

[0109] A second via hole is provided on the second net;

[0110] wherein a first spacing is between a first one of the first vias and a second one of the first vias, the first one of the first vias is adjacent to the second one of the first vias, a second spacing is between the first one of the first vias and a second one of the second vias that is closest to the first one of the first vias, and each of the first spacing and the second spacing is within a range from a minimum spacing specified by a design rule to 1.1 times the minimum spacing.

[0111] 17. The chip of clause 16, wherein the first net comprises a first continuous metal line and the second net comprises a second continuous metal line.

[0112] 18. A chip according to clause 16 or 17, wherein:

[0113] The first net is electrically coupled to a source or a drain of a transistor; and

[0114] The second net is electrically coupled to a gate of the transistor.

[0115] In this disclosure, the word "exemplary" is used to mean "serving as an example, instance, or illustration." Any implementation or aspect described herein as "exemplary" is not necessarily to be construed as advantageous over other aspects of the disclosure. Likewise, the term "aspect" does not require that all aspects of the disclosure include the discussed feature, advantage, or mode of operation. The term "coupled" is used herein to refer to a direct or indirect electrical coupling between two structures.

[0116] Any reference to an element using names such as "first", "second" etc. herein does not generally limit the quantity or order of these elements. On the contrary, these names are used as a convenient way to distinguish two or more elements or element instances in this article. Therefore, the reference to the first element and the second element does not mean that only two elements can be used, or that the first element must be before the second element.

[0117] The previous description of the disclosure is provided to enable any person skilled in the art to make or use the disclosure. Various modifications to the disclosure will be clear to those skilled in the art, and the general principles defined herein may be applied to other variations without departing from the spirit or scope of the disclosure. Therefore, the disclosure is not intended to be limited to the examples described herein, but should conform to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A chip, comprising: FirstNet; a second mesh, wherein the first mesh and the second mesh are formed of a same metal layer and the second mesh is adjacent to the first mesh; A first via hole is provided on the first net; as well as A second via hole is provided on the second net; Wherein the first spacing is greater than the second spacing, the first spacing is between a first one of the first vias and a second one of the first vias, the first one of the first vias is adjacent to the second one of the first vias, and the second spacing is between the first one of the first vias and a second one of the second vias that is closest to the first one of the first vias. 2 . The chip according to claim 1 , wherein the first pitch is greater than 1.1 times a minimum pitch specified by a design rule. 3 . The chip according to claim 2 , wherein the second pitch is in a range from the minimum pitch to 1.1 times the minimum pitch. The chip according to claim 1 , wherein the first pitch is greater than 1.3 times a minimum pitch specified by a design rule. The chip of claim 1 , wherein the first pitch is greater than 1.5 times a minimum pitch specified by a design rule. The chip according to claim 1 , wherein a ratio of the first pitch to the second pitch is greater than 1.

1. The chip according to claim 1 , wherein a ratio of the first pitch to the second pitch is greater than 1.

3. The chip according to claim 1 , wherein a ratio of the first pitch to the second pitch is greater than 1.

5. 9 . The chip of claim 1 , wherein the first net comprises a first continuous metal line and the second net comprises a second continuous metal line.

10. The chip according to claim 1, wherein: The first net is electrically coupled to a source or a drain of a transistor; and The second net is electrically coupled to a gate of the transistor.

11. The chip according to claim 1, further comprising: a third mesh, wherein the third mesh is formed of the same metal layer as the first mesh and the second mesh, and the third mesh is adjacent to the second mesh; as well as A third via hole is provided on the third net; The third spacing is greater than the fourth spacing, the third spacing is between the first third via among the third vias and the second third via among the third vias, the first third via among the third vias is adjacent to the second third via among the third vias, and the fourth spacing is between the first third via among the third vias and the second via among the second vias that is closest to the first third via among the third vias.

12. The chip according to claim 11, wherein: The first network is electrically coupled to a drain of the transistor; The second mesh is electrically coupled to a gate of the transistor; as well as The third net is electrically coupled to the source of the transistor. 13 . The chip of claim 11 , wherein the first pitch and the third pitch are each greater than 1.1 times a minimum pitch specified by a design rule. 14 . The chip of claim 11 , wherein the first pitch and the third pitch are each greater than 1.3 times a minimum pitch specified by a design rule. 15 . The chip of claim 11 , wherein the first pitch and the third pitch are each greater than 1.5 times a minimum pitch specified by a design rule.

16. A chip, comprising: FirstNet; a second mesh, wherein the first mesh and the second mesh are formed of a same metal layer and the second mesh is adjacent to the first mesh; A first via hole is provided on the first net; as well as A second via hole is provided on the second net; wherein a first spacing is between a first one of the first vias and a second one of the first vias, the first one of the first vias is adjacent to the second one of the first vias, a second spacing is between the first one of the first vias and a second one of the second vias that is closest to the first one of the first vias, and each of the first spacing and the second spacing is within a range from a minimum spacing specified by a design rule to 1.1 times the minimum spacing. 17 . The chip of claim 16 , wherein the first net comprises a first continuous metal line and the second net comprises a second continuous metal line.

18. The chip according to claim 16, wherein: The first net is electrically coupled to a source or a drain of a transistor; and The second net is electrically coupled to a gate of the transistor.

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