Semiconductor structure and preparation method thereof
By flip-bonding the second piezoelectric layer to the side of the first piezoelectric layer away from the substrate, the damage problem caused by excessive stress during the preparation of the heterogeneous substrate is solved, and the internal stress and longitudinal strain are reduced, thereby improving the performance of the MEMS device.
Patent Information
- Application Number
- CN202311278743.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-09-28
- Publication Date
- 2025-03-28
AI Technical Summary
Existing piezoelectric materials are susceptible to stress during the preparation of heterogeneous substrates, resulting in poor performance of MEMS devices.
By flip-bonding the second piezoelectric layer to the side of the first piezoelectric layer away from the substrate in the semiconductor structure, the internal stress and longitudinal strain of the first piezoelectric layer and the second piezoelectric layer are symmetrical, thereby reducing the overall internal stress and longitudinal strain.
The average stress of each thin film in the semiconductor structure is reduced, warping is reduced, and the performance and reliability of the device are improved.
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Abstract
Description
Technical Field
[0001] The present invention relates to the field of semiconductor technology, and in particular to semiconductor structures and methods for making the same. Background Art
[0002] MEMS (Micro-Electro-Mechanical System) is the abbreviation of micro-electromechanical system. MEMS devices can convert one form of energy into another form of energy, such as converting electrical energy into mechanical energy or mechanical energy into electrical energy. Generally speaking, MEMS devices require piezoelectric materials to achieve different forms of energy conversion. However, existing piezoelectric materials are easily damaged due to stress problems caused by the preparation of heterogeneous substrates, and the performance of MEMS devices is not good enough. Summary of the invention
[0003] To overcome the problems existing in the related art, this specification provides a semiconductor structure and a method for preparing the same.
[0004] According to a first aspect of an embodiment of this specification, a semiconductor structure is disclosed, comprising: a substrate and a first electrode layer, a first piezoelectric layer, a second piezoelectric layer, and a second electrode layer stacked in sequence on one side of the substrate;
[0005] The second piezoelectric layer is flip-chip bonded to the side of the first piezoelectric layer away from the substrate, and the internal stress and longitudinal strain of the first piezoelectric layer and the second piezoelectric layer are symmetrical, so that the overall internal stress and longitudinal strain formed by the bonding of the first piezoelectric layer and the second piezoelectric layer are reduced.
[0006] Optionally, the first piezoelectric layer is a polycrystalline structure, and the second piezoelectric layer is a single crystal structure;
[0007] Alternatively, the first piezoelectric layer is a polycrystalline structure, and the second piezoelectric layer is a polycrystalline structure;
[0008] Alternatively, the first piezoelectric layer is a single crystal structure, and the second piezoelectric layer is a single crystal structure;
[0009] Alternatively, the first piezoelectric layer is a single crystal structure, and the second piezoelectric layer is a polycrystalline structure.
[0010] Optionally, the second piezoelectric layer is a Group III nitride material, and a surface of the second piezoelectric layer away from the substrate is an N-face.
[0011] Optionally, the first piezoelectric layer is a group III nitride material, and a surface of the first piezoelectric layer close to the substrate is an N-face.
[0012] Optionally, the semiconductor structure further includes:
[0013] The first protective layer is located between the first piezoelectric layer and the second piezoelectric layer.
[0014] Optionally, the material of the protective layer is any one of AlGaN and AlScN.
[0015] Optionally, a stress direction applied by the first protective layer to one side of the first piezoelectric layer is the same as a stress direction applied by the substrate to the other side of the first piezoelectric layer, and a bending momentum direction applied by the first protective layer to one side of the first piezoelectric layer is opposite to a bending momentum direction applied by the substrate to the other side of the first piezoelectric layer;
[0016] The stress direction applied by the first protective layer to the second piezoelectric layer is the same as the stress direction applied by the first protective layer to the first piezoelectric layer, and the bending momentum direction applied by the first protective layer to the second piezoelectric layer is opposite to the bending momentum direction applied by the first protective layer to the first piezoelectric layer.
[0017] Optionally, the semiconductor structure further includes:
[0018] The third electrode layer is located between the first piezoelectric layer and the second piezoelectric layer.
[0019] Optionally, the semiconductor structure further includes:
[0020] a fourth electrode layer, located between the first piezoelectric layer and the second piezoelectric layer;
[0021] a second protective layer, located between the first piezoelectric layer and the fourth electrode layer; and
[0022] The third protection layer is located between the second piezoelectric layer and the fourth electrode layer.
[0023] Optionally, a cavity structure is provided, wherein the cavity structure is located between the first electrode layer and the substrate, and the cavity structure at least partially penetrates the substrate in a thickness direction of the substrate.
[0024] Optionally, the semiconductor structure further includes a through hole, wherein the through hole penetrates the first electrode layer, the first piezoelectric layer, the second piezoelectric layer and the second electrode layer, and the through hole is in communication with the cavity structure.
[0025] According to another aspect of the present disclosure, a method for preparing a semiconductor structure is also disclosed, comprising:
[0026] providing a substrate;
[0027] forming a first electrode layer and a first piezoelectric layer in sequence on one side of the substrate;
[0028] Provide a carrier;
[0029] preparing a second piezoelectric layer on the carrier;
[0030] Flip-chip bonding the second piezoelectric layer to a side of the first piezoelectric layer away from the substrate;
[0031] removing the carrier; and
[0032] forming a second electrode layer on a side of the second piezoelectric layer away from the substrate;
[0033] The internal stress and longitudinal strain of the first piezoelectric layer and the second piezoelectric layer are symmetrical, so that the overall internal stress and longitudinal strain formed by bonding the first piezoelectric layer and the second piezoelectric layer are reduced.
[0034] Optionally, the first piezoelectric layer is a polycrystalline structure, and the second piezoelectric layer is a single crystal structure;
[0035] Alternatively, the first piezoelectric layer is a polycrystalline structure, and the second piezoelectric layer is a polycrystalline structure;
[0036] Alternatively, the first piezoelectric layer is a single crystal structure, and the second piezoelectric layer is a single crystal structure;
[0037] Alternatively, the first piezoelectric layer is a single crystal structure, and the second piezoelectric layer is a polycrystalline structure.
[0038] Optionally, before bonding the second piezoelectric layer to a side of the first piezoelectric layer away from the substrate, the method further comprises:
[0039] forming a first protective layer on the first piezoelectric layer and / or the second piezoelectric layer;
[0040] Bonding the second piezoelectric layer to a side of the first piezoelectric layer away from the substrate includes bonding the second piezoelectric layer to a side of the first piezoelectric layer away from the substrate through the first protective layer.
[0041] Optionally, a stress direction applied by the first protective layer to one side of the first piezoelectric layer is the same as a stress direction applied by the substrate to the other side of the first piezoelectric layer, and a bending momentum direction applied by the first protective layer to one side of the first piezoelectric layer is opposite to a bending momentum direction applied by the substrate to the other side of the first piezoelectric layer;
[0042] The stress direction applied by the first protective layer to the second piezoelectric layer is the same as the stress direction applied by the first protective layer to the first piezoelectric layer, and the bending momentum direction applied by the first protective layer to the second piezoelectric layer is opposite to the bending momentum direction applied by the first protective layer to the first piezoelectric layer.
[0043] Optionally, before bonding the second piezoelectric layer to a side of the first piezoelectric layer away from the substrate, the method further comprises:
[0044] forming a third electrode layer on the first piezoelectric layer and / or the second piezoelectric layer;
[0045] The flip-chip bonding of the second piezoelectric layer to the side of the first piezoelectric layer away from the substrate includes bonding the second piezoelectric layer to the side of the first piezoelectric layer away from the substrate through the third electrode layer.
[0046] Optionally, before bonding the second piezoelectric layer to a side of the first piezoelectric layer away from the substrate, the method further comprises:
[0047] forming a second protective layer on the first piezoelectric layer, and forming a third protective layer on the second piezoelectric layer;
[0048] forming a fourth electrode layer on the second protective layer and / or the third protective layer;
[0049] The flip-chip bonding of the second piezoelectric layer to the side of the first piezoelectric layer away from the substrate includes bonding the second piezoelectric layer to the side of the first piezoelectric layer away from the substrate through the fourth electrode layer.
[0050] Optionally, it also includes:
[0051] providing a first electrode, and electrically connecting the first electrode to the first electrode layer; and
[0052] A second electrode is provided, and the second electrode is electrically connected to the second electrode layer.
[0053] Optionally, the method of sequentially forming a first electrode layer and a first piezoelectric layer on one side of the substrate further includes:
[0054] A sacrificial layer is prepared on the substrate, and the first electrode layer and the first piezoelectric layer are sequentially formed on the sacrificial layer;
[0055] The sacrificial layer is removed to form a cavity structure between the first electrode layer and the substrate, wherein the cavity structure at least partially penetrates the substrate in a thickness direction of the substrate.
[0056] Optionally, after forming the second electrode layer on the side of the second piezoelectric layer away from the substrate, the method further includes:
[0057] The second electrode layer, the second piezoelectric layer, the first piezoelectric layer, and the first electrode layer are etched to form a through hole, wherein the through hole is communicated with the cavity structure.
[0058] In the embodiment of the present specification, the second piezoelectric layer in the semiconductor structure is flip-chip bonded to the side of the first piezoelectric layer away from the substrate, and the internal stress directions and longitudinal deformations of the first piezoelectric layer and the second piezoelectric layer are symmetrical, so that the overall internal stress and longitudinal strain formed by the bonding of the first piezoelectric layer and the second piezoelectric layer are reduced.
[0059] The stresses on the first piezoelectric layer and the second piezoelectric layer are both tensile stresses, and the second piezoelectric layer is flip-chip bonded to the side of the first piezoelectric layer away from the substrate, so that the first piezoelectric layer and the second piezoelectric layer have opposite warping tendencies, that is, the longitudinal strains of the first piezoelectric layer and the second piezoelectric layer are symmetrical. The first piezoelectric layer and the second piezoelectric layer both have a tendency to be concave in the center and warp at the edges; wherein, the substrate applies tensile stress to the side of the first piezoelectric layer close to the substrate, causing the center of the first piezoelectric layer to have a tendency to be concave close to the substrate side; and since the second piezoelectric layer is flip-chip bonded to the side of the first piezoelectric layer away from the substrate, the side of the second piezoelectric layer away from the substrate is subjected to tensile stress, and the center of the second piezoelectric layer has a tendency to be concave away from the substrate side.
[0060] Therefore, after the first piezoelectric layer and the second piezoelectric layer are bonded, the first piezoelectric layer and the second piezoelectric layer have opposite bending momenta, the internal stress effects of the first piezoelectric layer and the second piezoelectric layer can offset each other, and the bending momenta of the first piezoelectric layer and the second piezoelectric layer also offset each other, thereby reducing the overall internal stress and longitudinal strain of the semiconductor structure formed after the first piezoelectric layer and the second piezoelectric layer are bonded, and the semiconductor structure formed after the first piezoelectric layer and the second piezoelectric layer are bonded has a relatively flat surface, reducing the average stress of each thin film in the semiconductor structure, and reducing the warping of the semiconductor structure formed after the first piezoelectric layer and the second piezoelectric layer are bonded, thereby improving device performance.
[0061] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present specification. BRIEF DESCRIPTION OF THE DRAWINGS
[0062] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the specification and, together with the description, serve to explain the principles of the specification.
[0063] Figure 1 It is a cross-sectional schematic diagram of the semiconductor structure shown in the first embodiment of this specification.
[0064] Figure 2-Figure 6 It is a schematic diagram of the preparation process of the semiconductor structure shown in the first embodiment of this specification.
[0065] Figure 7-Figure 10 It is a schematic diagram of the semiconductor structure preparation process shown in Example 2 of this specification.
[0066] Fig.11It is a structural schematic diagram of the semiconductor structure shown in the third embodiment of this specification.
[0067] Fig.12 It is a structural schematic diagram of the semiconductor structure shown in the fourth embodiment of this specification.
[0068] Figure 13-Figure 14 It is a structural schematic diagram of the semiconductor structure shown in Example 5 of this specification.
[0069] Fig.15 It is a structural schematic diagram of the semiconductor structure shown in Example 6 of this specification.
[0070] Fig.16 It is a structural schematic diagram of the semiconductor structure shown in Example 7 of this specification.
[0071] Description of reference numerals:
[0072] 110-substrate; 110a-carrier; 120-first electrode layer; 130-first piezoelectric layer; 140-second piezoelectric layer; 150-second electrode layer; 160-cavity structure; 170-first protective layer; 171 third electrode layer; 172-second protective layer; 173-third protective layer; 174 fourth electrode layer; 181-first electrode; 182-second electrode; 183-third electrode; 190-through hole. DETAILED DESCRIPTION
[0073] Exemplary embodiments will be described in detail herein, examples of which are shown in the accompanying drawings. When the following description refers to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The implementations described in the following exemplary embodiments do not represent all implementations consistent with this specification. Instead, they are merely examples of devices and methods consistent with some aspects of this specification as detailed in the appended claims.
[0074] The terms used in this specification are for the purpose of describing specific embodiments only and are not intended to limit this specification. The singular forms "a", "the" and "the" used in this specification and the appended claims are also intended to include plural forms unless the context clearly indicates otherwise. It should also be understood that the term "and / or" used herein refers to and includes any or all possible combinations of one or more associated listed items.
[0075] It should be understood that although the terms first, second, third, etc. may be used in this specification to describe various information, this information should not be limited to these terms. These terms are only used to distinguish the same type of information from each other. For example, without departing from the scope of this specification, the first information may also be referred to as the second information, and similarly, the second information may also be referred to as the first information. Depending on the context, the word "if" as used herein may be interpreted as "at the time of" or "when" or "in response to determining".
[0076] MEMS (Micro-Electro-Mechanical System) is the abbreviation of micro-electromechanical system. The internal structure size of MEMS devices is generally at the micron or nanometer level, and MEMS is an independent intelligent system. MEMS devices can convert one form of energy into another form of energy, such as converting electrical energy into mechanical energy or mechanical energy into electrical energy. Generally speaking, MEMS devices require piezoelectric materials to achieve different forms of energy conversion. Take the transducer that can convert the mechanical energy and electrical energy of sound waves as an example. When an alternating electric field is applied to the piezoelectric material, the piezoelectric material will vibrate at the frequency of the applied alternating electric field. If the frequency of the applied alternating electric field happens to be the resonant frequency of the MEMS device, the amplitude value will be greatly increased, and it has a higher energy conversion efficiency at this frequency. When the MEMS device is used as a transducer, it has a greater transmission sensitivity. On the other hand, when sound waves are transmitted to piezoelectric materials, they will cause vibration and deformation of the piezoelectric materials. This vibration will cause alternating charge distribution on the electrodes at both ends of the piezoelectric material. When the sound wave frequency is at the resonant frequency point of the MEMS device, it has a higher energy conversion efficiency at this frequency, and when the MEMS device is used as a transducer, it has a greater receiving sensitivity.
[0077] However, due to the lattice mismatch and thermal mismatch between the piezoelectric film layer and the adjacent film layer of the MEMS device, the stress in the piezoelectric film layer will increase with the increase of the thickness of the piezoelectric film layer, and the defect density in the atomic layer of the piezoelectric film layer will also increase layer by layer with the increase of thickness. The piezoelectric material is subjected to a large stress, which makes the piezoelectric material prone to problems such as warping and cracking. These problems lead to poor reliability of MEMS devices. If the problem of warping or cracking is alleviated by reducing the thickness of the piezoelectric material, the sensitivity of the MEMS device will be reduced. Therefore, there is an urgent need for a method to improve the problem of excessive stress on the piezoelectric material, which makes the piezoelectric material prone to warping, cracking and other problems.
[0078] To overcome the problems existing in the related art, this specification provides at least one exemplary embodiment of a semiconductor structure.
[0079] Embodiment 1
[0080] Figure 1Schematic diagram of the semiconductor structure shown in the first embodiment of this specification. Figure 1 As shown, the semiconductor structure 100 includes a substrate 110 and a first electrode layer 120, a first piezoelectric layer 130, a second piezoelectric layer 140 and a second electrode layer 150 stacked in sequence on one side of the substrate 110. The second piezoelectric layer 140 is flip-chip bonded to a side of the first piezoelectric layer 130 away from the substrate 110, and the internal stress and longitudinal strain of the first piezoelectric layer 130 and the second piezoelectric layer 140 are symmetrical, so that the overall internal stress and longitudinal strain formed after the first piezoelectric layer 130 and the second piezoelectric layer 140 are bonded are reduced.
[0081] Optionally, the stress directions experienced by the first piezoelectric layer 130 and the second piezoelectric layer 140 are symmetrical, and the stress experienced by the first piezoelectric layer 130 and the second piezoelectric layer 140 are both tensile stresses. The second piezoelectric layer 140 is flip-chip bonded to the side of the first piezoelectric layer 130 away from the substrate 1, so that the first piezoelectric layer 130 and the second piezoelectric layer 140 have opposite warping tendencies, that is, the longitudinal strains of the first piezoelectric layer 130 and the second piezoelectric layer 140 are symmetrical. When the stresses exerted on the first piezoelectric layer 130 and the second piezoelectric layer 140 are both tensile stresses, the first piezoelectric layer 130 and the second piezoelectric layer 140 both have a tendency to be concave in the center and to have raised edges; wherein, the substrate 110 applies tensile stress to the side of the first piezoelectric layer 130 close to the substrate 110, so that the center of the first piezoelectric layer 130 has a tendency to be concave close to the side of the substrate 110; and since the second piezoelectric layer 140 is flip-chip bonded to the side of the first piezoelectric layer 130 away from the substrate 1, the side of the second piezoelectric layer 140 away from the substrate 110 is subjected to tensile stress, and the center of the second piezoelectric layer 140 has a tendency to be concave away from the side of the substrate 110. Therefore, the first piezoelectric layer 130 and the second piezoelectric layer 140 have opposite bending momenta. After the first piezoelectric layer 130 and the second piezoelectric layer 140 are bonded, the internal stress effects of the first piezoelectric layer 130 and the second piezoelectric layer 140 can offset each other, and the bending momenta of the first piezoelectric layer 130 and the second piezoelectric layer 140 also offset each other, thereby reducing the overall internal stress and longitudinal strain of the semiconductor structure formed after the first piezoelectric layer 130 and the second piezoelectric layer 140 are bonded. The semiconductor structure formed after the first piezoelectric layer 130 and the second piezoelectric layer 140 are bonded has a relatively flat surface, which reduces the average stress of each thin film in the semiconductor structure, reduces the warping of the semiconductor structure formed after the first piezoelectric layer 130 and the second piezoelectric layer 140 are bonded, and improves the device performance.
[0082] Optionally, the materials of the first piezoelectric layer 130 and the second piezoelectric layer 140 are group III nitride materials, the surface of the first piezoelectric layer 130 close to the substrate 110 is a nitrogen (N) surface, and the surface of the second piezoelectric layer 140 away from the substrate 110 is a nitrogen (N) surface. The surface of the second piezoelectric layer 140 away from the substrate 110 is a nitrogen (N) surface, which can make the semiconductor structure have a smoother surface, and the semiconductor structure with a nitrogen (N) surface is easier to process, reducing the difficulty of preparing the subsequent device structure.
[0083] The semiconductor structure of this exemplary embodiment can reduce the total internal stress of the first piezoelectric layer 130 and the second piezoelectric layer 140 and improve the problem of easy damage of the piezoelectric material, thereby improving the problem of the piezoelectric material being subjected to large stress, which may cause the piezoelectric material to be prone to warping, cracking, and other problems.
[0084] refer to Figure 1 The semiconductor structure provided in this embodiment further includes a first electrode 181 and a second electrode 182 . The first electrode 181 is electrically connected to the first electrode layer 120 ; the second electrode 182 is electrically connected to the second electrode layer 150 .
[0085] It should be noted that the semiconductor structure in the exemplary embodiments of this specification can be used in a piezoelectric MEMS device.
[0086] Corresponding to the above-mentioned structural embodiments, this embodiment also provides an exemplary embodiment of a method for preparing a semiconductor structure.
[0087] Figure 2-Figure 6 FIG. 1 is a flow chart of a semiconductor structure fabrication process according to an exemplary embodiment of the present specification. Figure 2-Figure 6 As shown, the method for preparing the semiconductor structure 100 includes the following steps.
[0088] A substrate 110 is provided, and a first electrode layer 120 and a first piezoelectric layer 130 are sequentially formed on one side of the substrate 110 .
[0089] Specifically, Figure 2 As shown, the material of the substrate 110 can be any substrate material such as silicon (Si), single crystal lithium niobate (LiNbO3), silicon carbide (SiC), sapphire (Al2O3), quartz, etc.
[0090] That is, the first electrode layer 120 is located between the substrate 110 and the first piezoelectric layer 130 .
[0091] The material of the first electrode layer 120 may be a conductive material, such as a metal, specifically molybdenum, ruthenium, gold, aluminum, magnesium, tungsten, copper, titanium, iridium, osmium, chromium or a composite of the above metals or an alloy thereof. The first piezoelectric layer 130 may be at least one of lithium niobate (LiNbO3), lithium tantalate (LiTaO3), aluminum nitride (AlN), quartz (Quartz), lead zirconate titanate (PZT), lead magnesium niobate-lead titanate (PMN-PT) or aluminum scandium nitride (AlScN), and the first piezoelectric layer 130 may be a single crystal or polycrystalline material. Exemplarily, the first electrode layer 120 is molybdenum, and the first piezoelectric layer 130 is aluminum nitride.
[0092] Furthermore, the first electrode layer 120 may be formed by using a process such as physical vapor deposition (PVD) or chemical vapor deposition (CVD).
[0093] Furthermore, the first piezoelectric layer 130 may be formed by physical vapor deposition, chemical vapor deposition or epitaxial growth process.
[0094] Furthermore, the first piezoelectric layer 130 is a polycrystalline structure or a single crystal structure.
[0095] For example, an epitaxial growth process may be used to form a single crystal first piezoelectric layer 130. For example, the first piezoelectric layer 130 may be single crystal aluminum nitride. The first piezoelectric layer 130 may be formed using an epitaxial growth process to reduce defect density, improve piezoelectric properties, and thereby improve the performance of the MEMS device including the semiconductor structure (e.g., coupling coefficient and sensitivity, etc.).
[0096] Exemplarily, physical vapor deposition can also be used to form the polycrystalline first piezoelectric layer 130. For example, the first piezoelectric layer 130 is polycrystalline aluminum nitride. Physical vapor deposition can improve the production efficiency of semiconductor structures and reduce production costs.
[0097] The substrate 110 applies a tensile stress to the first piezoelectric layer 130 on the side close to the substrate 110 , so that the center of the first piezoelectric layer 130 tends to be concave close to the side of the substrate 110 .
[0098] like Figure 3 As shown, a carrier 110 a is provided, and a second piezoelectric layer 140 is prepared on the carrier 110 a.
[0099] Specifically, the material of the carrier 110a can be any substrate material such as silicon (Si), single crystal lithium niobate (LiNbO3), silicon carbide (SiC), sapphire (Al2O3), quartz (Quartz), etc. Optionally, the material of the carrier 110a is the same as or different from the material of the substrate 110. Further, in order to improve the performance of the second piezoelectric layer 140 formed on the carrier 110a, the surface of the carrier 110a is flat and has a small roughness to avoid excessive defects in the second piezoelectric layer 140.
[0100] In step 204 , the carrier 110 a applies a tensile stress to the second piezoelectric layer 140 on the side close to the carrier 110 a , so that the center of the second piezoelectric layer 140 tends to be concave close to the side of the carrier 110 a .
[0101] In an exemplary embodiment, the first piezoelectric layer 130 is a polycrystalline structure, and the second piezoelectric layer 140 is a single crystal structure; or, the first piezoelectric layer 130 is a polycrystalline structure, and the second piezoelectric layer 140 is a polycrystalline structure; the first piezoelectric layer 130 is a single crystal structure, and the second piezoelectric layer 140 is a polycrystalline structure; or, the first piezoelectric layer 130 is a single crystal structure, and the second piezoelectric layer 140 is a polycrystalline structure.
[0102] For example, the first piezoelectric layer 130 may be a polycrystalline structure formed by physical vapor deposition, which can improve the production efficiency of the semiconductor structure and reduce the production cost of the semiconductor structure. The second piezoelectric layer 140 may be a single crystal structure formed by epitaxial growth, which can improve the sensitivity and precision of the piezoelectric device including the semiconductor structure. This example can take into account both efficiency and sensitivity.
[0103] It should be noted that the present embodiment is not intended to limit the material and preparation process of the first piezoelectric layer 130 , and the material and preparation process of the first piezoelectric layer 130 and the second piezoelectric layer 140 may be adaptively adjusted according to actual needs.
[0104] Optionally, the material of the second piezoelectric layer 140 may be at least one of lithium niobate (LiNbO3), lithium tantalate (LiTaO3), aluminum nitride (AlN), quartz, lead zirconate titanate (PZT), lead magnesium niobate-lead titanate (PMN-PT) or aluminum scandium nitride (AlScN). Optionally, the material of the second piezoelectric layer 140 may be the same as or different from the material of the first piezoelectric layer 130. Exemplarily, the materials of the first piezoelectric layer 130 and the second piezoelectric layer 140 are both single crystal III group nitride materials (e.g., single crystal aluminum nitride) formed by an epitaxial growth process. Further, the process parameters for the epitaxial growth of the first piezoelectric layer 130 and the second piezoelectric layer 140 may be the same. Further, the thicknesses of the first piezoelectric layer 130 and the second piezoelectric layer 140 may be the same or different. The materials of the substrate 110 and the carrier 110a are the same or different.
[0105] refer to Figure 4 , the second piezoelectric layer 140 is flip-chip bonded to the side of the first piezoelectric layer 130 away from the substrate 110 .
[0106] Optionally, the second piezoelectric layer 140 is flip-chip bonded to the side of the first piezoelectric layer 130 away from the substrate 110. Specifically, the first piezoelectric layer 130 and the second piezoelectric layer 140 may be subjected to a bonding process (exemplary process conditions: 425° C., 1500 N, and holding pressure for 30 minutes).
[0107] Among them, since the second piezoelectric layer 140 is flip-chip bonded to the side of the first piezoelectric layer 130 away from the substrate 1, the side of the second piezoelectric layer 140 away from the substrate 110 is subjected to tensile stress, and the center of the second piezoelectric layer 140 has a tendency to be concave away from the side of the substrate 110. Therefore, the first piezoelectric layer 130 and the second piezoelectric layer 140 have opposite bending momenta, and after the first piezoelectric layer 130 and the second piezoelectric layer 140 are bonded, the internal stress effects of the first piezoelectric layer 130 and the second piezoelectric layer 140 can offset each other, and the bending momenta of the first piezoelectric layer 130 and the second piezoelectric layer 140 also offset each other, and then the semiconductor structure formed after the first piezoelectric layer 130 and the second piezoelectric layer 140 are bonded has a relatively flat surface, reducing the average stress of each thin film in the semiconductor structure, and can reduce the warping of the semiconductor structure formed after the first piezoelectric layer 130 and the second piezoelectric layer 140 are bonded, thereby improving the device performance.
[0108] refer to Figure 5 , remove the carrier 110a.
[0109] Optionally, a lift-off process is used to remove the carrier 110 a .
[0110] refer to Figure 6 A second electrode layer 150 is formed on a side of the second piezoelectric layer 140 away from the substrate 110 .
[0111] The material of the second electrode layer 150 may be a conductive material, such as a metal, specifically molybdenum, ruthenium, gold, aluminum, magnesium, tungsten, copper, titanium, iridium, osmium, chromium or a composite of the above metals or an alloy thereof. The second electrode layer 150 may be formed by a process such as physical vapor deposition or chemical vapor deposition. Optionally, the material of the second electrode layer 150 is the same as or different from that of the first electrode layer 120.
[0112] Optionally, in this embodiment, reference Figure 1, a first electrode 181 is also provided, and the first electrode 181 is electrically connected to the first electrode layer 120; a second electrode 182 is provided, and the second electrode 182 is electrically connected to the second electrode layer 150. Specifically, a portion of the second electrode layer 150, the second piezoelectric layer 140, and the first piezoelectric layer 130 can be etched to expose a portion of the surface of the first electrode layer 120, and the first electrode 181 is formed on the exposed portion of the surface of the first piezoelectric layer 120.
[0113] Embodiment 2
[0114] The content of the second embodiment is substantially the same as that of the first embodiment, and the difference is that before the first electrode layer 120 and the first piezoelectric layer 130 are sequentially formed on one side of the substrate 110, a sacrificial layer 160a is first formed on the substrate. Figures 7 to 10 As shown, Figure 7-Figure 10 is a schematic flow chart of a method for preparing a semiconductor structure shown in Embodiment 2 of this specification, Fig.10 It is a schematic diagram of the semiconductor structure shown in the second embodiment of this specification.
[0115] The method for preparing the semiconductor structure 200 provided in this embodiment includes the following steps.
[0116] A substrate 110 is provided, and a sacrificial layer 160 a is formed on the substrate 110 .
[0117] like Fig.10 As shown, the material of the sacrificial layer 160a may be porous silicon, silicon oxide, polysilicon, photoresist, etc. The sacrificial layer 160a may be etched away by a chemical etchant without damaging other film layers. Specifically, a patterned groove may be formed on one side of the substrate 110 by an etching process, and the sacrificial layer 160a may be formed in the groove; or a partial area of the substrate 110 may be etched to form the sacrificial layer 160a.
[0118] refer to Figure 8 , a first electrode layer 120 and a first piezoelectric layer 130 are sequentially formed on a side of the sacrificial layer 160a away from the substrate 110, and the first electrode layer 120 and the first piezoelectric layer 130 are sequentially formed on the substrate 110 and the sacrificial layer 160a.
[0119] refer to Fig. 9 , remove the sacrificial layer 160a. Specifically, the sacrificial layer 160a is removed to form a cavity structure 160 located between the first electrode layer 120 and the substrate. The cavity structure 160 is located between the first electrode layer 120 and the substrate. The cavity structure 160 is used to provide a certain space so that the piezoelectric material can deform and vibrate at the cavity structure 160.
[0120] In this embodiment, the sacrificial layer 160 a partially penetrates the substrate 110 or completely penetrates the substrate 110 , that is, the cavity structure 160 partially penetrates the substrate 110 or completely penetrates the substrate 110 .
[0121] Embodiment 3
[0122] The content of the third embodiment is substantially the same as that of the first embodiment or the second embodiment, except that it further includes forming a cavity structure 160 on the surface of the substrate 110 away from the first electrode layer 120. Fig.11 , Fig.11 The structure diagram of the semiconductor structure provided in the third embodiment of the present specification is shown. The cavity structure 160 completely penetrates the substrate 110 . The cavity structure 160 can be formed by etching the substrate 110 from the side away from the first electrode layer 120 .
[0123] Embodiment 4
[0124] The content of Example 4 is substantially the same as any one of Examples 1 to 3, with the only difference being that, before the second piezoelectric layer 140 is flip-chip bonded to the side of the first piezoelectric layer 130 away from the substrate 110, it also includes forming a first protective layer 170 on the side of the first piezoelectric layer 130 away from the substrate 110, and / or forming a first protective layer 170 on the side of the second piezoelectric layer 140 away from the carrier 110a.
[0125] Specifically, refer to Fig.12 , Fig.12 As shown is a structural schematic diagram of the semiconductor structure provided in Example 4 of the present specification, before the second piezoelectric layer 140 is bonded to the side of the first piezoelectric layer 130 away from the substrate 110, after the first piezoelectric layer 130 and / or the second piezoelectric layer 140 are formed, the preparation method also includes forming a first protective layer 170 on the first piezoelectric layer 130 and / or the second piezoelectric layer 140; that is, the first protective layer 170 can be formed only on the side of the first piezoelectric layer 130 away from the substrate 110, or the first protective layer 130 is formed only on the side of the second piezoelectric layer 140 away from the carrier 110a, or the protective layer 170 is formed on both the side of the first piezoelectric layer 130 away from the substrate 110 and the side of the second piezoelectric layer 140 away from the carrier 110a.
[0126] For example, the material of the first protective layer 170 may be aluminum gallium nitride (AlGaN) or aluminum scandium nitride (AlScN). The first protective layer 170 may be formed by physical vapor deposition or chemical vapor deposition.
[0127] In this embodiment, the second piezoelectric layer 140 is bonded to the first piezoelectric layer 130 on a side away from the substrate 110 through the first protective layer 170 . The first protective layer 170 is located between the first piezoelectric layer 130 and the second piezoelectric layer 140 . The stress direction applied by the first protective layer 170 to one side of the first piezoelectric layer 130 is the same as the stress direction applied by the substrate 110 and / or the first electrode layer 120 to the other side of the first piezoelectric layer 130. Optionally, the substrate 110 applies tensile stress to the side of the first piezoelectric layer 130 close to the substrate 110, so that the center of the first piezoelectric layer 130 has a tendency to be concave toward the side of the substrate 110, and the first protective layer 170 simultaneously applies tensile stress to the side of the first piezoelectric layer away from the substrate 110, so that the center of the first piezoelectric layer 130 has a tendency to be concave toward the side away from the substrate 110. Therefore, the bending momentum direction applied by the first protective layer 170 to one side of the first piezoelectric layer 130 is opposite to the bending momentum direction applied by the substrate 110 to the other side of the first piezoelectric layer 130. Under the interaction, the first piezoelectric layer 130 can tend to a relatively flat surface, thereby improving problems such as cracks, warping and peeling caused by stress differences and lattice mismatch and thermal mismatch, so as to improve the sensitivity and performance of the device. It can be understood that the stress direction applied by the first protective layer 170 to the second piezoelectric layer 140 is the same as the stress direction applied by the first protective layer 170 to the first protective layer 130, that is, the stress direction applied by the first protective layer 170 to the second piezoelectric layer 140 is the same as the stress direction applied by the carrier 110a to the second piezoelectric layer 140, and the bending momentum applied by the first protective layer 170 to the second piezoelectric layer 140 is opposite to the bending momentum applied by the first protective layer 170 to the second piezoelectric layer 140, that is, the bending momentum applied by the first protective layer 170 to the second piezoelectric layer 140 is opposite to the bending momentum applied by the carrier 110a to the second piezoelectric layer 140; so that the second piezoelectric layer 140 also tends to a relatively flat surface, improving problems such as cracks, warping and peeling caused by stress differences and lattice mismatch and thermal mismatch, so as to improve the sensitivity and performance of the device.
[0128] In addition, bonding the first piezoelectric layer 130 and the second piezoelectric layer 140 to each other through the first protective layer 170 can improve the bonding strength between the first piezoelectric layer 130 and the second piezoelectric layer 140 and achieve a better bonding effect.
[0129] In this embodiment, a first electrode 181 may be provided and electrically connected to the first electrode layer 120 ; a second electrode 182 may be provided and electrically connected to the second electrode layer 150 . The first electrode 181 is electrically connected to the first electrode layer 120 . The second electrode 182 is electrically connected to the second electrode layer 150 .
[0130] Embodiment 5
[0131] The content of the fifth embodiment is substantially the same as that of any one of the first to fourth embodiments, except that: Fig.13 and Fig.14 As shown, Fig.13 and Fig.14 Schematic diagram of the semiconductor structure shown in the fifth embodiment of this specification. Fig.13 As shown, in order to further improve the problem that the piezoelectric film layer is prone to cracking or peeling, the semiconductor structure provided by this exemplary embodiment is Fig.12 The semiconductor structures shown differ only in that Fig.12 The first protective layer 170 of the semiconductor structure shown is replaced by the third electrode layer 171. The third electrode layer 171 may be formed by forming the third electrode layer 171 on the first piezoelectric layer 130 and / or the second piezoelectric layer 140. Bonding the second piezoelectric layer 140 to the side of the first piezoelectric layer 130 away from the substrate 110 includes bonding the second piezoelectric layer 140 to the side of the first piezoelectric layer 130 away from the substrate 110 through the third electrode layer 171.
[0132] The material of the third electrode layer 171 can refer to the material of the first electrode layer 120 and the second electrode layer 150. For example, the material of the third electrode layer 171 is the same as the material of the first electrode layer 120. In addition, the sandwich structure of the first piezoelectric layer 130, the third electrode layer 171 and the second piezoelectric layer 140 can improve the coupling ability of the piezoelectric film layer and improve the sensitivity of the piezoelectric device including the semiconductor structure.
[0133] Alternatively, if Fig.14 As shown, the semiconductor structure may further include forming a third electrode 183, and the third electrode 183 is electrically connected to the third electrode layer 171. The material and process of the third electrode 183 may refer to the first electrode 181 or the second electrode 182 in the above embodiment, and will not be repeated here.
[0134] Embodiment 6
[0135] The content of the sixth embodiment is substantially the same as the content of any one of the first to fifth embodiments, and the difference is that after the first electrode layer 120 and the first piezoelectric layer 130 are sequentially formed on the substrate 110, a second protective layer 172 is formed on the side of the first piezoelectric layer 130 away from the substrate 110; after the second piezoelectric layer 140 is formed on the carrier 110a, a third protective layer 174 is formed on the side of the second piezoelectric layer 140 away from the carrier 110a; and a fourth electrode layer 174 is formed on the side of the second protective layer 172 away from the first piezoelectric layer 130 and / or the side of the third protective layer 173 away from the second piezoelectric layer 140. Reference Fig.15 , Fig.15 Schematic diagram of a semiconductor structure shown in Example 6 of this specification. The method for preparing a semiconductor structure provided in this exemplary embodiment includes the following steps.
[0136] A substrate 110 is provided, and a first electrode layer 120 and a first piezoelectric layer 130 are sequentially formed on one side of the substrate 110 .
[0137] A carrier 110 a is provided, and a second piezoelectric layer 140 is formed on the carrier 110 a.
[0138] A second protective layer 172, a third protective layer 173 and a fourth electrode layer 174 are formed. Fig.15 , including forming a second protective layer 172 on the first piezoelectric layer 130 , forming a third protective layer 173 on the second piezoelectric layer 140 , and forming a fourth electrode layer 174 on the second protective layer 172 and / or the third protective layer 173 .
[0139] For example, the materials and formation process of the second protective layer 172 and the third protective layer 173 can refer to the materials and formation process of the first protective layer 170, which will not be repeated here. The materials and formation process of the fourth electrode layer 174 can refer to the materials and formation process of the third electrode layer 171, which will not be repeated here.
[0140] The technical effects of the second protective layer 172 and the third protective layer 173 may refer to the first protective layer 170 ; the technical effects of the fourth electrode layer 174 may refer to the third electrode layer 171 , which will not be described in detail herein.
[0141] The second piezoelectric layer 140 is flip-chip bonded to a side of the first piezoelectric layer 130 away from the substrate 110 .
[0142] Bonding the second piezoelectric layer 140 to the side of the first piezoelectric layer 130 away from the substrate 110 includes bonding the second piezoelectric layer 140 to the side of the first piezoelectric layer 130 away from the substrate 110 through the fourth electrode layer 174 .
[0143] Specifically, the fourth electrode layer 174 is located between the first piezoelectric layer 130 and the second piezoelectric layer 140. The second protective layer 172 is located between the first piezoelectric layer 130 and the fourth electrode layer 174. The third protective layer 173 is located between the second piezoelectric layer 140 and the fourth electrode layer 174. The second protective layer 172 and the third protective layer 173 protect the piezoelectric layer, and improve the stress accumulation caused by the increase in the overall thickness of the piezoelectric film layer after the first piezoelectric layer 130 and the second piezoelectric layer 140 are bonded, thereby improving the problems of cracks and fragments in the piezoelectric film layer.
[0144] Embodiment 7
[0145] The content of Example 7 is substantially the same as the content of any one of Examples 1 to 6, with the only difference being that after the second electrode layer 150 is formed on the side of the second piezoelectric layer 140 away from the substrate 110a, the stacked structure including the second electrode layer 150, the second piezoelectric layer 140, the first piezoelectric layer 130 and the first electrode layer 120 is etched to form a through hole 190, and the through hole 190 is connected to the cavity structure 160.
[0146] Specifically, see Fig.16 , Fig.16 The schematic diagram of the structure of the semiconductor structure provided in Embodiment 7 is shown in FIG. 1 . Exemplarily, the second electrode layer 150, the second piezoelectric layer 140, the first piezoelectric layer 130, and the first electrode layer 120 are etched to form a through hole 190, and the through hole 190 is connected to the cavity structure 160. Specifically, the through hole 190 passes through the first electrode layer 120, the first piezoelectric layer 130, the second piezoelectric layer 140, and the second electrode layer 150, and the through hole 190 is connected to the cavity structure 160. The through hole 190 is a small gap.
[0147] When the piezoelectric material is deformed, the through hole 190 is used to discharge the air in the cavity structure 160 of the piezoelectric material to reduce the pressure on the piezoelectric material. The through hole 190 is connected to the cavity structure 160 to improve the sensitivity of the semiconductor structure. The number and size of the through hole 190 can be set according to actual conditions, and no specific restrictions are made here.
[0148] The steps not described in detail in this exemplary embodiment can refer to the above exemplary embodiments and will not be described in detail here.
[0149] Accordingly, the present specification also provides a piezoelectric device, which includes the semiconductor structure provided by any of the above exemplary embodiments. Specifically, the piezoelectric device can be a device that is applicable to a variety of piezoelectric MEMS devices. For example, the piezoelectric device can be a MEMS ultrasonic transducer, a MEMS microphone, a MEMS speaker, a MEMS hydrophone, a coupled resonator filter, etc.
[0150] The piezoelectric device includes the semiconductor structure provided by any of the above exemplary embodiments and has corresponding beneficial effects, which will not be described in detail herein.
[0151] The above is a description of a specific embodiment of the specification. Other embodiments are within the scope of the appended claims. In some cases, the actions or steps recorded in the claims can be performed in an order different from that in the embodiments and still achieve the desired results. In addition, the processes depicted in the drawings do not necessarily require the specific order or continuous order shown to achieve the desired results. In some embodiments, multitasking and parallel processing are also possible or may be advantageous.
[0152] Those skilled in the art will readily appreciate other embodiments of the specification after considering the specification and practicing the invention claimed herein. The specification is intended to cover any variations, uses or adaptations of the specification that follow the general principles of the specification and include common knowledge or customary techniques in the art that are not claimed in the specification. The specification and examples are to be considered exemplary only, and the true scope and spirit of the specification are indicated by the following claims.
[0153] It should be understood that the present description is not limited to the precise structures that have been described above and shown in the drawings, and that various modifications and changes may be made without departing from the scope thereof. The scope of the present description is limited only by the appended claims.
[0154] The above description is only a preferred embodiment of this specification and is not intended to limit this specification. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of this specification should be included in the scope of protection of this specification.
Claims
1. A semiconductor structure, characterized in that: include: A substrate (110) and a first electrode layer (120), a first piezoelectric layer (130), a second piezoelectric layer (140) and a second electrode layer (150) stacked in sequence on one side of the substrate (110); The second piezoelectric layer (140) is flip-chip bonded to the side of the first piezoelectric layer (130) away from the substrate (110), and the internal stress and longitudinal strain of the first piezoelectric layer (130) and the second piezoelectric layer (140) are symmetrical, so that the overall internal stress and longitudinal strain formed by the bonding of the first piezoelectric layer (130) and the second piezoelectric layer (140) are reduced.
2. The semiconductor structure according to claim 1, characterized in that: The first piezoelectric layer (130) is a polycrystalline structure, and the second piezoelectric layer (140) is a single crystal structure; Alternatively, the first piezoelectric layer (130) is a polycrystalline structure, and the second piezoelectric layer (140) is a polycrystalline structure; Alternatively, the first piezoelectric layer (130) is a single crystal structure, and the second piezoelectric layer (140) is a single crystal structure; Alternatively, the first piezoelectric layer (130) is a single crystal structure, and the second piezoelectric layer (140) is a polycrystalline structure.
3. The semiconductor structure according to claim 1, characterized in that: The second piezoelectric layer (140) is made of a group III nitride material, and a surface of the second piezoelectric layer (140) that is away from the substrate (110) is an N-face.
4. The semiconductor structure according to claim 1, characterized in that: The first piezoelectric layer (130) is made of a group III nitride material, and a surface of the first piezoelectric layer (130) close to the substrate (110) is an N-face.
5. The semiconductor structure according to claim 1, characterized in that: The semiconductor structure further comprises: A first protective layer (170) is located between the first piezoelectric layer (130) and the second piezoelectric layer (140).
6. The semiconductor structure according to claim 5, characterized in that: The material of the protective layer (170) is any one of AlGaN and AlScN.
7. The semiconductor structure according to claim 5, characterized in that: The stress direction applied by the first protective layer (170) to one side of the first piezoelectric layer (130) is the same as the stress direction applied by the substrate (110) to the other side of the first piezoelectric layer (130), and the bending momentum direction applied by the first protective layer (170) to one side of the first piezoelectric layer (130) is opposite to the bending momentum direction applied by the substrate (110) to the other side of the first piezoelectric layer (130); The stress direction applied by the first protective layer (170) to the second piezoelectric layer (140) is the same as the stress direction applied by the first protective layer (170) to the first piezoelectric layer (130), and the bending momentum direction applied by the first protective layer (170) to the second piezoelectric layer (140) is opposite to the bending momentum direction applied by the first protective layer (170) to the first piezoelectric layer (130).
8. The semiconductor structure according to claim 1, characterized in that: The semiconductor structure further comprises: The third electrode layer (171) is located between the first piezoelectric layer (130) and the second piezoelectric layer (140).
9. The semiconductor structure according to claim 1, characterized in that: The semiconductor structure further comprises: A fourth electrode layer (174) located between the first piezoelectric layer (130) and the second piezoelectric layer (140); a second protective layer (172) located between the first piezoelectric layer (130) and the fourth electrode layer (174); and The third protective layer (173) is located between the second piezoelectric layer (140) and the fourth electrode layer (174).
10. The semiconductor structure according to claim 1, wherein: Also includes: A cavity structure (160), wherein the cavity structure (160) is located between the first electrode layer (120) and the substrate (110), and the cavity structure (160) at least partially penetrates the substrate (110) in the thickness direction of the substrate (110).
11. The semiconductor structure according to claim 10, characterized in that: The semiconductor structure also includes a through hole (190), wherein the through hole (190) penetrates the first electrode layer (120), the first piezoelectric layer (130), the second piezoelectric layer (140) and the second electrode layer (150), and the through hole (190) is in communication with the cavity structure (160).
12. A method for preparing a semiconductor structure, characterized in that: include: Providing a substrate (110); A first electrode layer (120) and a first piezoelectric layer (130) are sequentially formed on one side of the substrate (110); Providing a carrier (110a); Preparing a second piezoelectric layer (140) on the carrier (110a); Flip-chip bonding the second piezoelectric layer (140) to a side of the first piezoelectric layer (130) away from the substrate (110); removing the carrier (110a); and forming a second electrode layer (150) on a side of the second piezoelectric layer (140) away from the substrate (110); The internal stress and longitudinal strain of the first piezoelectric layer (130) and the second piezoelectric layer (140) are symmetrical, so that the overall internal stress and longitudinal strain formed by bonding the first piezoelectric layer (130) and the second piezoelectric layer (140) are reduced.
13. The method for preparing a semiconductor structure according to claim 12, characterized in that: The first piezoelectric layer (130) is a polycrystalline structure, and the second piezoelectric layer (140) is a single crystal structure; Alternatively, the first piezoelectric layer (130) is a polycrystalline structure, and the second piezoelectric layer (140) is a polycrystalline structure; Alternatively, the first piezoelectric layer (130) is a single crystal structure, and the second piezoelectric layer (140) is a single crystal structure; Alternatively, the first piezoelectric layer (130) is a single crystal structure, and the second piezoelectric layer (140) is a polycrystalline structure.
14. The method for preparing a semiconductor structure according to claim 12, characterized in that: Before bonding the second piezoelectric layer (140) to the side of the first piezoelectric layer (130) away from the substrate (110), the method further comprises: forming a first protective layer (170) on the first piezoelectric layer (130) and / or the second piezoelectric layer (140); The step of bonding the second piezoelectric layer (140) to the side of the first piezoelectric layer (130) away from the substrate (110) includes bonding the second piezoelectric layer (140) to the side of the first piezoelectric layer (130) away from the substrate (110) through the first protective layer (170).
15. The method for preparing a semiconductor structure according to claim 14, characterized in that: The stress direction applied by the first protective layer (170) to one side of the first piezoelectric layer (130) is the same as the stress direction applied by the substrate (110) to the other side of the first piezoelectric layer (130), and the bending momentum direction applied by the first protective layer (170) to one side of the first piezoelectric layer (130) is opposite to the bending momentum direction applied by the substrate (110) to the other side of the first piezoelectric layer (130); The stress direction applied by the first protective layer (170) to the second piezoelectric layer (140) is the same as the stress direction applied by the first protective layer (170) to the first piezoelectric layer (130), and the bending momentum direction applied by the first protective layer (170) to the second piezoelectric layer (140) is opposite to the bending momentum direction applied by the first protective layer (170) to the first piezoelectric layer (130).
16. The method for preparing a semiconductor structure according to claim 12, characterized in that: Before bonding the second piezoelectric layer (140) to the side of the first piezoelectric layer (130) away from the substrate (110), the method further comprises: forming a third electrode layer (171) on the first piezoelectric layer (130) and / or the second piezoelectric layer (140); The flip-chip bonding of the second piezoelectric layer (140) to the side of the first piezoelectric layer (130) away from the substrate (110) includes bonding the second piezoelectric layer (140) to the side of the first piezoelectric layer (130) away from the substrate (110) through the third electrode layer (171).
17. The method for preparing a semiconductor structure according to claim 12, characterized in that: Before bonding the second piezoelectric layer (140) to the side of the first piezoelectric layer (130) away from the substrate (110), the method further comprises: forming a second protective layer (172) on the first piezoelectric layer (130), and forming a third protective layer (173) on the second piezoelectric layer (140); forming a fourth electrode layer (174) on the second protective layer (172) and / or the third protective layer (173); The flip-chip bonding of the second piezoelectric layer (140) to the side of the first piezoelectric layer (130) away from the substrate (110) includes bonding the second piezoelectric layer (140) to the side of the first piezoelectric layer away from the substrate (110) through the fourth electrode layer (174).
18. The method for preparing a semiconductor structure according to claim 12, characterized in that: Also includes: Providing a first electrode (181), and electrically connecting the first electrode (181) to the first electrode layer (120); as well as A second electrode (182) is provided, and the second electrode (182) is electrically connected to the second electrode layer (150).
19. The method for preparing a semiconductor structure according to claim 13, characterized in that: The first electrode layer (120) and the first piezoelectric layer (130) are sequentially formed on one side of the substrate (110), and further comprises: A sacrificial layer (110a) is prepared on the substrate (110), and the first electrode layer (120) and the first piezoelectric layer (130) are sequentially formed on the sacrificial layer (110a); The sacrificial layer is removed to form a cavity structure (160) located between the first electrode layer (120) and the substrate (110), wherein the cavity structure (160) at least partially penetrates the substrate (110) in a thickness direction of the substrate (110).
20. The method for preparing a semiconductor structure according to claim 19, characterized in that: After forming the second electrode layer on the side of the second piezoelectric layer away from the substrate, the method further includes: The second electrode layer (150), the second piezoelectric layer (140), the first piezoelectric layer (130) and the first electrode layer (120) are etched to form a through hole (190), wherein the through hole (190) is in communication with the cavity structure (160).