Selective transfer of optical and optoelectronic components

Abstract

Methods of selectively transferring integrated circuit (IC) components between substrates, as well as devices and systems formed using the methods, are disclosed herein. In one embodiment, a first substrate having a release layer and an IC component layer over the release layer is received, and a second substrate having one or more bonding regions is received. The IC component layer may include one or more waveguides, ring resonators, drivers, photodetectors, transimpedance amplifiers, and / or electronic integrated circuits. The first substrate is partially bonded to the second substrate such that a subset of the IC components on the first substrate are bonded to the bonding region on the second substrate. The first substrate is then separated from the second substrate, and a subset of the IC components bonded to the second substrate is separated from the first substrate and remains on the second substrate.

Description

Background Art

[0001] In semiconductor manufacturing, layer transfer techniques are commonly used at the wafer level to transfer layers from one substrate to another. These techniques require that the entire layer be transferred as a whole, regardless of whether the entire layer is needed. As a result, any unwanted portions of the transferred layer must be etched away after the transfer, which increases cost and process complexity. BRIEF DESCRIPTION OF THE DRAWINGS

[0002] Figures 1A-1I An example process flow for selective layer transfer using selective release technology is shown.

[0003] Figure 2A-2I An example process flow for selective layer transfer using blanket laser irradiation is shown.

[0004] Figures 3A-3I An example process flow for selective layer transfer from a singulated donor substrate is shown.

[0005] Figures 4A-4C An example process flow for selective layer transfer from multiple donor substrates is shown.

[0006] Figures 5A-5F An example process flow for forming an integrated circuit package using selective transfer of a passive interposer is shown.

[0007] Figure 6A-6B An example of selective layer transfer between wafers is shown.

[0008] Figure 7 A flow chart for performing a selective layer transfer is shown.

[0009] Figure 8 An example embodiment of an optical transceiver is shown.

[0010] Figures 9A-9F An example process flow for forming an optical transceiver using a selective transfer technique is shown.

[0011] Figures 10A-10E Various configurations of electrical and optical components integrated using selective transfer techniques are shown.

[0012] Figures 11A-11B Single and multi-layer arrangements of selectively transferred optical components are shown.

[0013] Figures 12A-12B A computing platform with an optical interconnect is shown in accordance with certain embodiments.

[0014] Figures 13A-13B Example embodiments of optical packages in accordance with certain embodiments are shown.

[0015] Fig.14 Shown are top views of wafers and dies that may be included in a microelectronic assembly.

[0016] Fig.15 A cross-sectional side view of an integrated circuit device that may be included in a microelectronic assembly is shown.

[0017] Fig.16 A cross-sectional side view of an integrated circuit device assembly that may include a microelectronic assembly is shown.

[0018] Fig.17 A block diagram of an example electrical device that may include a microelectronic assembly is shown. DETAILED DESCRIPTION

[0019] Selective layer transfer

[0020] In semiconductor manufacturing, layer transfer techniques are typically used to transfer layers from one substrate to another on a wafer-level scale. Layer transfer can be used for a variety of applications in semiconductor manufacturing, including two-dimensional (2D) material manufacturing, III-V semiconductors on complementary metal oxide semiconductors (CMOS), and traditional CMOS applications, such as metal-insulator-metal (MIM) devices and thin devices and / or interconnect layer transfer. However, current layer transfer techniques are limited to whole-layer transfer, which may affect cost and performance when the whole layer is not required. For example, blanket layer transfer techniques (such as ion cutting and laser lift-off layer transfer) require the transfer of the whole layer as a whole. As a result, any unwanted areas of the transferred layer must be etched away after the transfer, which leads to increased cost and process complexity.

[0021] Alternatively, pick and place techniques can be used to transfer specific dies or chiplets. For example, a chiplet generally refers to an integrated circuit (IC) that contains a well-defined subset of functions and is designed to be combined with other chiplets to form a single IC package. In order to transfer chiplets (e.g., for MIM chiplet integration in a system on a chip (SoC)), a chiplet device is manufactured on a donor substrate (e.g., a wafer or panel), the donor substrate is singulated into chiplets, and then the chiplets are individually attached to a receiver substrate (e.g., a SoC wafer or package) using a pick and place machine. This adds significant cost due to the additional processing required to singulate the wafer and individually attach the corresponding chiplet dies. For example, chiplets are typically manufactured on relatively thick substrates so that they can be handled without being damaged during the singulation and attachment steps, and after the attachment step, additional processing is performed to thin the chiplets and / or remove the carrier substrate, which further increases cost and process complexity. In particular, chiplets are typically fabricated on substrates that are over 700 micrometers (μm or microns) thick to provide structural and mechanical stability during manufacturing, and after the singulation / attachment steps, they can be thinned to about 20-100 μm by grinding the backside. However, grinding often results in chiplet cracking along the edges of the chiplet die. Furthermore, thinning chiplets beyond 20 μm without creating defects can be challenging. Similarly, chiplets are typically singulated with die areas on a millimeter scale, as pick and place assembly is difficult for devices smaller than 1 mm. 2 (mm 2 ) chiplets become very challenging.

[0022] Integrated circuits can also be manufactured monolithically, where all IC components and interconnects are fabricated sequentially on the same underlying substrate or wafer. However, monolithic ICs have various limitations, including design restrictions due to incompatible processes, lack of flexibility, and low yields.

[0023] Therefore, the present disclosure proposes a selective layer transfer technique for selectively transferring portions of a layer between substrates, and devices and systems formed using the selective layer transfer technique. For example, the described technique enables a selected area of ​​a donor substrate to be transferred to a receptor substrate, which enables the donor substrate to be reused multiple times while also addressing the limitations described above for blanket layer transfer and pick-and-place techniques. In particular, the described solution uses a selective release technique on a donor substrate (e.g., a wafer, panel, or die) in conjunction with a patterned bonding template on a receptor substrate (e.g., a wafer, panel, or die) to allow a selected area of ​​a layer on the donor substrate to be transferred to the receptor substrate. For the purposes of the present disclosure, a layer may refer to one or more layers formed above a substrate, such as a single material layer, or a stack of layers that together form an IC component (e.g., a die, interconnect, bridge, capacitor, and / or other semiconductor device) layer. A layer may also include stacked wafers, such as wafer-to-wafer bonded and stacked logic and / or memory wafers. As an example, a donor wafer may include a layer of IC components (eg, IC dies), and selective layer transfer may be used to selectively transfer specific subsets of those IC components to a recipient wafer simultaneously.

[0024] The described solution provides various advantages. For example, the described solution enables transfer of selected areas of a donor wafer, rather than an entire layer, which enables the donor wafer to be reused for multiple products, thereby amortizing the cost of expensive devices (e.g., high-density MIM capacitors or high-density passive interposers) across multiple wafers. The solution also eliminates the need to etch away excess areas as required for full-layer transfer (and thus, unlike etched areas after full-layer transfer, selectively transferred areas may not have tapered edges from etching, or may have reverse tapering due to etching as a single cut prior to transfer).

[0025] Furthermore, layers of IC components may be selectively transferred at any level of granularity, including complete IC dies and packages, interconnects, transistors, resistors, capacitors, partial layers, or layer stacks, etc.

[0026] The solution also enables selective transfer of areas of ultra-thin layers without the additional processing and yield loss caused by the processing challenges of chiplet pick and place methods (e.g., singulation, attaching each chiplet individually, post-attachment thinning of the chiplets). This helps to reduce the Z height of the product (e.g., for form factor, thermal and / or power delivery reasons) as well as the overall process complexity. For example, very thin IC dies or chiplets can be formed on any substrate and selectively transferred directly from the substrate. Therefore, selectively transferring the die not only eliminates the need for post-attachment thinning, but also enables the die to be much thinner than a die that is singulated, picked and placed, attached, and subsequently thinned. In some cases, for example, the described solution can enable the transfer of dies having thicknesses ranging from 100 nanometers (nm) to 5μm or more. In addition, since post-attachment thinning is not required, the selectively transferred die can have no or minimal chipping on the die edge because grinding is not performed, which is different from chiplets that are thinned after attachment.

[0027] Similarly, the solution supports the selective transfer of very small areas on the donor substrate (such as very small dies or chiplets), which is extremely challenging using pick and place techniques. In some cases, for example, the described solution can achieve a small area with less than 1mm 2 area (such as 100 μm 2 (10×10μm), 10000μm 2 (100×100μm), 810000μm 2 Transfer of dies (or other IC components) of size (900 x 900 μm, etc.) (there is no limit to the maximum size of the area that can be selectively transferred).

[0028] The solution also supports the selective transfer of dies with non-standard shapes and designs that are difficult to handle using pick and place machines, such as dies with atypical, arbitrary, irregular, or non-convex shapes (e.g., L-shape, U-shape, shapes with sharp angles), dies with high aspect ratios (e.g., 8:1 aspect ratio or higher), dies with holes, etc.

[0029] Furthermore, the solution has very low topography and supports high surface cleanliness and planarization (eg, using a chemical mechanical polishing (CMP) process), which makes it compatible with hybrid bonding and fusion bonding processes. Additional advantages are described throughout this disclosure and will be apparent from the description below.

[0030] Thus, the solution enables the manufacture of complex IC packages and products by selectively transferring certain components (e.g., active circuit systems such as IC dies, passive circuit systems), rather than combining them using traditional processes (e.g., (i) full-layer transfer with excess areas etched away; (ii) pick-and-place assembly of individual IC components; and / or (iii) monolithic IC manufacturing).

[0031] Figure 1A -I shows an example process flow for selective layer transfer using a selective release technique. In the example shown, an integrated circuit (IC) component layer is selectively transferred from a donor substrate 100 to an acceptor substrate 110, as further described below.

[0032] exist Figure 1A , a release layer 102 is formed over a carrier substrate, referred to as a donor substrate 100. The release layer 102 is a temporary bonding and peeling layer for the layer 104 to be selectively transferred. In some embodiments, the release layer 102 may include one or more layers and / or materials capable of providing adhesion to the donor substrate 100 and / or absorbing energy from a laser (e.g., a laser beam), such as (one or more) lossy dielectric and / or thin metal layers that provide adhesion and absorb / reflect infrared (IR) light, (one or more) organic polymer layers (e.g., polyimide) that provide adhesion and absorb visible or ultraviolet (UV) light, and / or (one or more) patterned dielectric layers with anchors to provide residual adhesion (e.g., after ablation of a metal layer by an IR laser).

[0033] The layer 104 to be selectively transferred is formed over the release layer 102 of the donor substrate 100, such as by direct fabrication of the layer 104 or blanket transfer of the layer 104. The selective transfer layer 104 may include one or more material layers, such as a single layer of material, or a stack of layers that together form layers of an IC component (e.g., a complete IC die, a chiplet, an interconnect, a bridge, a capacitor, a transistor, and / or other semiconductor device). In some embodiments, for example, the selective transfer layer 104 may be a prefabricated semiconductor wafer containing unsingulated integrated circuit (IC) dies that is blanket transferred to the release layer 102 on the donor wafer 100.

[0034] exist Figure 1B In the process, the selective transfer layer 104 is cut over the donor substrate 100—without cutting through the donor substrate 100—to partially singulate the IC components 106 in the layer 104 using a technique such as etching, reactive ion etching (RIE), plasma cutting, mechanical sawing, etc. In some embodiments, the release layer 102 may also be singulated (e.g., cut or etched) together with the transfer layer 104.

[0035] exist Figure 1C In the embodiment of the present invention, a release layer 112 is optionally formed over another carrier substrate, which is referred to as an acceptor substrate 110. For example, if the selectively transferred IC component 106 will be subsequently peeled from the acceptor substrate 110 after transfer, the release layer 112 can be formed over the acceptor substrate 110. Otherwise, if the selectively transferred IC component 106 will remain on the acceptor substrate 110 after transfer, the release layer 112 on the acceptor 110 can be omitted.

[0036] Next, a bonding template 114 is formed on a surface of the acceptor substrate 110 (e.g., over the release layer 112, if included). The bonding template 114 includes a pattern of bonding features or adhesion areas 114 that enable specific areas of the donor substrate 100 to be selectively transferred to the acceptor substrate 110. For example, the locations of the bonding features 114 on the acceptor substrate 110 correspond to the areas or IC components 106 on the donor substrate 100 that are to be transferred to the acceptor substrate 110.

[0037] In some embodiments, for example, the bonding features 114 may include "island" or "mesa" structures that are similar in size to the target area to be transferred from the donor substrate 100. For example, each island or mesa structure 114 may be a raised structure on the surface of the acceptor substrate 110 that has a similar footprint (e.g., shape / surface area) as the corresponding IC component 106 on the donor substrate 100. In other embodiments, the mesas 114 may be replaced by a photolithographic or additively manufactured surface treatment that enhances adhesion in the target area of ​​the acceptor substrate 110 (e.g., the area showing the mesas 114) and prevents adhesion in other areas, including but not limited to surface topography changes, use of materials with high and / or low adhesion, use of hydrophobic materials and / or self-assembled monolayer (SAM) treatments, and / or surface activation techniques, among other examples.

[0038] In various embodiments, these bonding features 114 may be made of a dielectric material, a conductive material (e.g., metal), or both, depending on whether an electrical connection is required between the bonded IC component 106 and the receptor substrate 110. For example, the bonding features 114 may be blanket dielectric structures with no electrical contacts, or they may be dielectric structures with electrical contacts through them (e.g., hybrid bond pads) if electrical connection through the bonding interface is required.

[0039] exist Figure 1D In the embodiment, a donor substrate 100 and an acceptor substrate 110 are contacted with each other with their top surfaces aligned face-to-face so that a target IC component 106 on the donor 100 is aligned with a corresponding bonding feature 114 on the acceptor 110 .

[0040] exist Figure 1E, donor substrate 100 and acceptor substrate 110 are partially bonded together. For example, an area of ​​acceptor substrate 110 having a protruding surface feature or "mesa" 114 is bonded to a corresponding area of ​​donor substrate 110 having a target IC component 106, while other areas of donor substrate 100 and acceptor substrate 110 remain unbonded. In some embodiments, this is controlled, for example, by the height of the bonding protrusions 114 to prevent undesired contact between areas that are not to be transferred. As previously described, this can also be controlled by surface treatment of different areas to achieve good adhesion in the target area (e.g., the location of the mesa 114 is shown) and prevent or reduce adhesion in other areas.

[0041] exist Figure 1F In the present invention, IC components 106 bonded to receptor 110 are selectively peeled from donor 100 using a selective release technique such as IR peeling, selective visible or ultraviolet (UV) laser irradiation, etc. For example, regions 103 of release layer 102 where those IC components 106 are bonded to donor 100 can be selectively removed or ablated using a laser such as an IR or UV laser, which forms gaps or voids 103 in release layer 102 and releases those IC components 106 from donor 100.

[0042] exist Figure 1G , the donor substrate 100 and the acceptor substrate 110 are mechanically separated from each other. At this point, the IC components 106 that were selectively bonded to the acceptor 110 (e.g., via the bonding structures 114) and peeled from the donor 100 remain on the acceptor 110 and are separated from the donor 100. All other IC components 106 that were not bonded to the acceptor 110 remain on the donor 100.

[0043] exist Figure 1H , the receptor substrate 110 is now ready for continued processing, such as dielectric fill 116 around the transferred IC components 106, planarization, selective transfer or pick and place attachment of additional IC dies or other IC components, via formation, formation of interconnect / metallization layers, attaching a structural substrate, stripping the receptor substrate (e.g., via an optional receptor release layer 112), and / or any other processing required for a finished product (e.g., an IC package).

[0044] exist Fig. 1I The donor substrate 100 is then reused to transfer the remaining IC components 106 (e.g., the remaining areas of the selectively transferred layer 104) to a new acceptor substrate 110'. The donor substrate 100 can continue to be reused in this manner until all IC components 106 or the entire layer 104 have been selectively transferred to any number of acceptor substrates 110.

[0045] It should be understood that the process flow shown for selective layer transfer is presented only as an example, and many other process variations are possible. For example, the donor substrate 100 and the acceptor substrate 110 can be wafers, panels, IC packages, chiplets, dies, or any combination thereof (e.g., for transfer from wafer to panel, from chiplet to wafer, etc.). In addition, each substrate 100, 110 can be made of various materials, including but not limited to inorganic materials (such as silicon, silicon on insulator (SOI), quartz, glass, and / or III-V materials), organic materials (such as IR or UV transparent epoxy resins), etc.

[0046] The materials used in the release layers 102, 112 may vary depending on the type of release or stripping technology used. For example, for infrared (IR) laser stripping, the release layers 102, 112 may include one or more materials that can absorb and / or reflect infrared (IR) light, such as a thin metal layer or multiple metal layers (e.g., aluminum (Al), tungsten (W), copper (Cu), titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN)). For ultraviolet (UV) laser stripping, the release layers 102, 112 may include one or more materials that can absorb UV light (e.g., a wide range of organic polymers, including but not limited to polyimide). In some embodiments, the release layers 102, 112 may additionally or alternatively include one or more layers of dielectric material (e.g., silicon dioxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiON), silicon carbide (SiC), silicon carbonitride (SiCN), silicon carbon oxynitride (SiOCN), aluminum oxide (Al2O3), low-k dielectrics (such as carbon-doped oxide (CDO) or porous silicon dioxide (SiO2), titanium dioxide (TiO2), tantalum oxide (Ta2O5)), which can be used to buffer laser ablation and thermal energy, control film interference or adhesion, and / or provide residual adhesion after other materials and / or layers in the release layers 102, 112 are weakened, removed and / or ablated by the laser.

[0047] The number of layers 104 on the donor substrate 100, the arrangement / structure of the layers 104, the materials in each layer 104, and the types of IC components 106 formed in those layers 104 may vary.

[0048] The bonding areas or bonding features 114 on the acceptor substrate 110 may be formed using any suitable surface treatment or other technique to control the level of bonding in different areas, including but not limited to surface topography variations (e.g., terraces, recesses), use of materials with high and / or low adhesion, use of hydrophobic materials and / or self-assembled monolayer (SAM) treatments, and / or surface activation techniques, among other examples. In addition, the bonding features or bonding areas 114 on the acceptor substrate 110 may vary in size, shape, height, topography, pattern, and material. For example, the bonding features 114 may be formed using inorganic dielectrics such as silicon dioxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiON), and / or silicon carbonitride (SiCN), organic dielectrics such as photoresists and adhesives, conductive materials such as metals, and combinations thereof.

[0049] Any suitable bonding technique, including but not limited to hybrid bonding, fusion bonding, and adhesive bonding, may be used to (partially) bond the donor substrate 100 and the acceptor substrate 110. Any suitable stripping technique, including but not limited to IR and UV laser stripping, may be used to strip or release the donor substrate 100 and the acceptor substrate 110. Furthermore, before or after each selective layer is transferred to the acceptor substrate 110, there may be an additional cleaning step to reuse the donor substrate 100.

[0050] In addition, in some embodiments, additional bonding and / or alignment features can be included at the wafer level and / or die level (e.g., on the donor die, donor wafer, acceptor wafer, and / or final product). For example, the donor and / or acceptor wafers can include ridges or cross structures to facilitate bonding, such as a single ridge (e.g., a line or strip of dielectric material) extending across and / or through the center of the wafer, or multiple orthogonal ridges forming a cross-like pattern. Alignment features for wafers, small dies, and / or arrays of dies can also be included to facilitate bonding with proper alignment. In addition, multiple dies can be connected by small (e.g., dielectric) bridges to help them bond and transfer together. For example, if some of the dies connected by the bridge are successfully bonded to the acceptor, the bridges can also help other dies bond. Therefore, these inter-die bridges can exist on the donor before the transfer and on the acceptor and final product after the transfer.

[0051] Furthermore, in some cases the stripping process may cause some unique damage or delamination near the edge and / or on the backside of the die, which does not affect process performance but may indicate that this solution is being used.

[0052] Figure 2A-2IAn example process flow for selective layer transfer using blanket laser irradiation is shown. In the example shown, a layer 204 of an integrated circuit (IC) component 206 is selectively transferred from a donor substrate 200 to a receptor substrate 210. However, prior to the transfer, the entire release layer 202 on the donor 200 is mechanically weakened (e.g., using IR lasers, visible light lasers, UV lasers, chemical etching, and / or thermal techniques), which may also be referred to as a partial release. In this manner, after the target IC components 206 on the donor 200 are bonded to the receptor 210, they can be completely released from the donor 200 by mechanically separating the donor 200 from the receptor 210. In some cases, the release layer 202 may be mechanically weakened (e.g., using IR lasers, visible light lasers, UV lasers, chemical etching, and / or thermal techniques) to form a partially released layer. Figures 1A-1I This can result in a simplified and faster bonding / stripping process compared to a conventional bonding / selective release / stripping process. Alternatively, rather than using blanket laser irradiation, the respective materials used in donor release layer 202 and receptor bonding template 214 can be selected so that the bond to donor 200 is weaker than the subsequently formed bond to receptor 210.

[0053] exist Figure 2A In the present invention, a release layer 202 is formed over a donor substrate 200. A layer 204 to be selectively transferred is formed over the release layer 202, such as by directly fabricating the layer 204 or blanket transferring the layer 204. In some embodiments, the selectively transferred layer 204 may be an IC component (e.g., an IC die, chiplet, interconnect, bridge, capacitor, transistor, and / or other semiconductor device) layer.

[0054] exist Figure 2B In the embodiment of the present invention, the selective transfer layer 204 is cut over the donor substrate 200—without cutting through the donor substrate 200—to partially singulate the IC components 206 in the layer 204.

[0055] exist Figure 2C In the embodiment of the present invention, blanket laser irradiation is performed on the donor release layer 202 to weaken the entire release layer 202 before transfer. In some embodiments, for example, laser (e.g., IR or UV laser irradiation), chemical and / or thermal techniques can be used to perform blanket laser irradiation. In this way, the weakened release layer 202 has a lower bonding energy, which results in partial release of the IC component 206 bonded to the layer 202.

[0056] exist Figure 2D In the embodiment of the present invention, release layer 212 is optionally formed over acceptor substrate 210. For example, if selectively transferred IC component 206 will be subsequently peeled from acceptor substrate 210 after transfer, release layer 212 may be formed over acceptor 210; otherwise, release layer 212 on acceptor 210 may be omitted.

[0057] Next, a bonding template 214 is formed on the surface of the acceptor substrate 210 (e.g., over the release layer 212, if included). The bonding template 214 includes a pattern of bonding features or bonding areas 214 (such as mesas) that enable specific areas of the donor substrate 200 to be selectively transferred to the acceptor substrate 210. However, in various embodiments, any suitable surface treatment or other technique may be used to control the level of adhesion on different areas of the acceptor substrate 210 (e.g., to form bonding and non-bonding areas for selective transfer), including but not limited to surface topography changes (e.g., mesas, recesses), use of materials with high and / or low adhesion, use of hydrophobic materials and / or self-assembled monolayer (SAM) treatments, and / or surface activation techniques, among other examples.

[0058] exist Figure 2E In the embodiment, the donor substrate 200 and the acceptor substrate 210 are brought into contact with each other with their top surfaces aligned face-to-face so that the target IC components 206 on the donor 200 are aligned with the corresponding bonding features 214 on the acceptor substrate 210 .

[0059] exist Figure 2F In FIG. 1 , a donor substrate 200 and an acceptor substrate 210 are partially bonded together, wherein a region of the donor 200 having a target IC component 206 is bonded to a region of the acceptor 210 having a bonding mesa 214 .

[0060] exist Figure 2G 2, donor substrate 200 and acceptor substrate 210 are mechanically separated from each other. At this point, IC components 206 that are selectively bonded to acceptor 210 (e.g., via bonding mesas 214) remain on acceptor 210 and are peeled / separated from donor 200 due to blanket weakening of donor release layer 202. All other IC components 206 that are not bonded to acceptor 210 remain on donor 200.

[0061] Alternatively, in some embodiments, instead of (or in addition to) executing Figure 2C By blanket laser irradiation in the embodiment of the present invention, the corresponding materials used in the donor release layer 202 and the receptor bonding template 214 can be selected so that the target IC component 206 will have a stronger bond to the receptor 210 than the donor 200. In this way, when the donor 200 and the receptor 210 are mechanically separated, the target IC component 206 will be peeled from the donor 200 and remain on the receptor 210 due to the difference in bonding strength.

[0062] exist Figure 2H, the receptor substrate 210 is ready for continued processing, such as dielectric fill 216 around the transferred IC components 206, planarization, selective transfer or pick and place attachment of additional IC dies or other IC components, via formation, formation of interconnect / metallization layers, attaching a structural substrate, stripping the receptor substrate (e.g., via an optional receptor release layer 212), and / or any other processing required for a finished product (e.g., an IC package).

[0063] exist Fig.2I The donor substrate 200 is then reused to transfer the remaining IC components 206 (e.g., the remaining areas of the selectively transferred layer 204) to a new acceptor substrate 210'. The donor substrate 200 may continue to be reused in this manner until all IC components 206 or the entire layer 204 have been selectively transferred to any number of acceptor substrates 210.

[0064] Figure 2A-2I The elements marked with reference numerals in FIG. 1 may be similar to those in FIG. Figures 1A-1I Furthermore, it should be understood that the process flow shown for selective layer transfer is presented as an example only, and many other process variations are possible, including but not limited to the process variations described throughout the present disclosure.

[0065] Figures 3A-3I An example process flow for selective layer transfer from a singulated donor substrate 300 is shown. In some cases, for example, if for each selective layer transfer, the percentage of integrated circuit (IC) components 306 that are transferred is relatively small, it may be easier and more cost-effective to cut the donor substrate 300 and perform the transfer from a singulated donor die 301 that contains a smaller subset of the IC components 306 from the original donor substrate 300. Thus, in the example shown, the donor substrate 300 having the layer 304 of IC components 306 is cut, and the resulting layer of IC components 306 on the singulated donor die 301 is selectively transferred to an acceptor substrate 310. In this way, the transfer is performed at the donor die level rather than at the wafer or panel level.

[0066] exist Figure 3A In the embodiment of the present invention, a release layer 302 is formed over a donor substrate 300. A layer 304 to be selectively transferred is formed over the release layer 302, such as by directly fabricating the layer 304 or blanket transferring the layer 304. In some embodiments, the selectively transferred layer 304 may be an IC component (e.g., an IC die, chiplet, interconnect, bridge, capacitor, transistor, and / or other semiconductor device) layer.

[0067] exist Figure 3BIn the embodiment, the selective transfer layer 304 is cut over the donor substrate 300—without cutting through the donor substrate 300—to partially singulate the IC components 306 in the layer 304. In some embodiments, the release layer 302 may also be singulated (eg, cut or etched) along with the transfer layer 306.

[0068] exist Figure 3C , donor substrate 300 is cut into singulated donor dies 301, each singulated donor die 301 containing a subset of IC components 306 from the original donor substrate 300. For example, each donor die 301 may include one or more IC components 306 from layer 304 on the original donor substrate 300.

[0069] exist Figure 3D In the process, blanket laser irradiation (as shown) or selective laser release is performed on the donor release layer 302 to weaken the entire release layer 302 (e.g., using IR / UV laser irradiation or thermal techniques) before transfer, thereby partially releasing the IC component 306 from the donor die 301.

[0070] exist Figure 3E , a release layer 312 is optionally formed over the acceptor substrate 310 (e.g., in the case where the selectively transferred IC component 306 will subsequently be peeled from the acceptor substrate 310 after transfer). Next, a bonding template 314 is formed on the surface of the acceptor substrate 310 (e.g., over the release layer 312, if included). The bonding template 314 includes a pattern of bonding features or bonding areas 314 (such as mesas) that enable specific areas of the donor die 301 to be selectively transferred to the acceptor substrate 310. However, in various embodiments, any suitable surface treatment or other technique may be used to control the level of adhesion on different areas of the acceptor substrate 310 (e.g., to form bonding and non-bonding areas for selective transfer), including but not limited to surface topography changes (e.g., mesas, recesses), use of materials with high and / or low adhesion, use of hydrophobic materials and / or self-assembled monolayer (SAM) treatments, and / or surface activation techniques, among other examples.

[0071] exist Figure 3F In the embodiment, a bond head 320 is used to pick up one of the donor dies 301 and place it face down on an acceptor substrate 310 so that a target IC component 306 on the donor die 301 is aligned with a corresponding bond mesa 314 on the acceptor substrate 310. The donor die 301 and the acceptor substrate 310 are then partially bonded together (e.g., die-to-wafer bonding), with the target IC component 306 bonded to the acceptor bond mesa 314.

[0072] exist Figure 3G3, the bond head 320 lifts and mechanically separates the donor die 301 from the acceptor substrate 310. At this point, due to the blanket weakening of the donor release layer 302, the IC components 306 that are selectively bonded to the acceptor 310 (e.g., via the bonding mesas 314) remain on the acceptor 310 and are peeled / separated (e.g., die-to-wafer peel) from the donor die 301. All other IC components 306 that are not bonded to the acceptor substrate 310 remain on the donor die 301.

[0073] Alternatively, in some embodiments, instead of (or in addition to) executing Figure 3D The blanket laser irradiation in the embodiment can also selectively release the target IC component 306 (e.g., as described in relation to Figure 1F ), or donor release layer 302 and acceptor bonding template 314 may be formed of materials having different bonding strengths so that target IC component 306 will have a stronger bond to acceptor substrate 310 than donor die 301.

[0074] exist Figure 3H and Fig. 3I In the embodiment, the bonding head 320 steps and repeats. For example, the bonding head 320 moves to a new position and repeats respectively Figure 3F and Figure 3G The process is performed to selectively transfer another set of IC components 306 from the donor die 301 to other areas of the acceptor substrate 310.

[0075] The process may be repeated in this manner until all IC components 306 on the donor die 301 have been transferred. At this point, the bond head 320 may pick up another donor die 301 and continue transferring IC components 306 from the new donor die 301 to the same or a different receptor substrate 310.

[0076] After all transfers to receptor substrate 310 are completed, receptor 310 can be ready for continued processing, such as dielectric fill around transferred IC components 306, planarization, selective transfer or pick and place attachment of additional IC dies or other IC components, via formation, formation of interconnect / metallization layers, attaching a structural substrate, stripping of the receptor substrate (e.g., via optional receptor release layer 312), and / or any other processing required for a finished product (e.g., an IC package).

[0077] Figures 3A-3I The elements marked with reference numerals in FIG. 1 may be similar to those in FIG. Figures 1A-1I Furthermore, it should be understood that the process flow shown for selective layer transfer is presented as an example only, and many other process variations are possible, including but not limited to the process variations described throughout the present disclosure.

[0078] Figures 4A-4C An example process flow for selective layer transfer from multiple donor substrates is shown. In the example shown, integrated circuit (IC) components 414, 434 from multiple donor substrates 410, 430 are selectively transferred to an acceptor substrate 450 using intermediate carrier substrates 420, 440. In some embodiments, the respective donors 410, 430 may have different types of IC components 414, 434, such as different types of IC dies or chiplets. In this way, selective layer transfer can be used to transfer multiple types of IC components (such as different types of dies or chiplets) to the same acceptor substrate 450. Although the example shown shows selective transfer from two types of donor substrates 410, 430 (e.g., having two types of IC components 414, 434), any number of donor substrates having any type of IC die or other components is possible (including different die sizes).

[0079] exist Figure 4A 4. In the process of selectively transferring a layer of an IC component 414 from a first donor substrate 410 to an intermediate carrier substrate 420 (e.g., using any of the selective transfer processes described throughout the present disclosure). For example, a release layer 412 is formed over the donor substrate 410. The layer 414 to be selectively transferred is then formed over the release layer 412 (e.g., by directly fabricating the layer 414 or blanket transferring the layer 414 from a wafer to the donor carrier 410) and cut into partially singulated IC components 414. Separately, a release layer 422 is formed over the intermediate carrier / receiver substrate 420, and a bonding template 424 is formed on a surface of the intermediate carrier 420 (e.g., over the release layer 422). The donor 410 and the intermediate carrier 420 are then partially bonded together (e.g., the target IC component 414 on the donor 410 is bonded to a bonding feature or bonding area 424 on the intermediate carrier 420). Donor 410 and intermediate carrier 420 are then peeled and separated from one another using any of the techniques described throughout this disclosure (eg, selective release, blanket laser irradiation, etc.). As a result, target IC component 414 is peeled / separated from donor 410 and remains on intermediate carrier 420 .

[0080] exist Figure 4B, another layer of IC components 434 is selectively transferred from a second donor substrate 430 to another intermediate carrier substrate 440 (e.g., using any of the selective transfer processes described throughout the present disclosure). For example, a release layer 432 is formed over the donor substrate 430. The layer 434 to be selectively transferred is then formed over the release layer 432 (e.g., by directly fabricating the layer 434 or blanket transferring the layer 434 from a wafer to the donor carrier 430) and cut into partially singulated IC components 434. Separately, a release layer 442 is formed over the intermediate carrier / receiver substrate 440, and a bonding template 444 is formed on a surface of the intermediate carrier 440 (e.g., over the release layer 442). The donor 430 and the intermediate carrier 440 are then partially bonded together (e.g., the target IC component 434 on the donor 430 is bonded to a bonding feature or bonding area 444 on the intermediate carrier 440). Donor 430 and intermediate carrier 440 are then peeled and separated from one another using any of the techniques described throughout this disclosure (eg, selective release, blanket laser irradiation, etc.). As a result, target IC component 434 is peeled / separated from donor 430 and remains on intermediate carrier 440 .

[0081] exist Figure 4C , the IC components 414, 434 on both intermediate carriers 420, 440 are selectively transferred to an acceptor substrate 450 (e.g., using any of the selective transfer processes described throughout the present disclosure). For example, a release layer 452 is optionally formed over the acceptor substrate 450 (e.g., in the case where the selectively transferred IC components 414, 434 will be subsequently peeled off from the acceptor substrate 450 after transfer). A bonding layer 454 (e.g., having bonding areas / bonding features) is then formed on the surface of the acceptor 450 (e.g., over the release layer 452, if included). Next, the IC component 414 on the first intermediate carrier 420 is selectively transferred to the acceptor substrate 450 (e.g., using any of the selective transfer processes described throughout the present disclosure). Finally, the IC component 434 on the second intermediate carrier 440 is selectively transferred to the acceptor substrate 450 (e.g., using any of the selective transfer processes described throughout the present disclosure).

[0082] Additional processing may then be performed on the receptor substrate 450, such as cleaning steps (e.g., removing remaining bonding structures 424, 444 from the transferred IC components 414, 434), dielectric fill around the transferred IC components 414, 434, planarization, selective transfer or pick and place attachment of additional IC dies or other IC components, via formation, formation of interconnect / metallization layers, attaching structural substrates, stripping of the receptor substrate (e.g., via an optional receptor release layer 452), and / or any other processing required for a finished product (e.g., an IC package).

[0083] It should be understood that the illustrated process flow for selective layer transfer is presented by way of example only, and that numerous other process variations are possible, including but not limited to those described throughout this disclosure.

[0084] Figures 5A-5F An example process flow for forming an integrated circuit (IC) package 500 utilizing selective transfer of a passive interposer 506 is shown. Selective transfer can be used for a variety of applications, including transfer of active components (e.g., IC die, transistors, diodes) and passive components (e.g., interconnects, metal-insulator-metal (MIM) chiplets, resistors, capacitors, inductors, transformers). In the example shown, the process flow is used to form an IC package 500 utilizing a selectively transferred, low-cost passive interposer 506. For example, an interposer 506 having high-density die-to-die (D2D) links 508 is produced on a donor wafer 502 and then selectively transferred to a recipient wafer 512, which enables the same donor wafer 502 to be reused multiple times and the cost of interconnect devices across multiple recipient wafers 512 to be amortized. In some embodiments, other components of the IC package 500, such as IC die 518a-b, may also be selectively transferred. Selective transfer can also be used for other applications, including but not limited to the transfer of photonic / optical components, and localized transfer of III-V semiconductors for radio frequency (RF) and high power devices.

[0085] exist Figure 5A In the embodiment of the present invention, a repeating D2D interconnect pattern 506 is produced on a release layer 504 of a donor substrate 502, and the resulting D2D interconnect is partially singulated (eg, the donor substrate 502 is cut but not cut through the donor substrate 502). The D2D interconnect 506 includes high-density interconnect links 508 separated by dielectric layers 510.

[0086] exist Figure 5B , a transfer template 516 for selective transfer is created on a release layer 514 of an acceptor / carrier substrate 512. The transfer template 516 includes dielectric bonding protrusions 516, referred to as mesas, on the surface of the acceptor substrate 512. However, in various embodiments, any suitable surface treatment or other technique may be used to control the level of adhesion on different areas of the acceptor substrate 512 (e.g., to form bonding and non-bonding areas for selective transfer), including but not limited to examples such as surface topography changes (e.g., mesas, recesses), use of materials with high and / or low adhesion, use of hydrophobic materials and / or self-assembled monolayers (SAMs), and / or surface activation techniques. In addition, in various embodiments, any number of buildup layers may be formed on the acceptor substrate 512 prior to forming the templated connection base or mesas 516 for selective transfer.

[0087] The bonding mesas 516 are used to selectively transfer the D2D interconnects 506 from the donor 502 to the receptor 512 (e.g., using any of the selective transfer processes described throughout the present disclosure). For example, the donor 502 and the receptor 512 are aligned face to face, stacked, and then partially bonded together so that one of the D2D interconnects 506 on the donor 502 is bonded to the bonding mesas 516 on the receptor 512.

[0088] exist Figure 5C In the embodiment, the D2D interconnect 506 bonded to the acceptor mesa 516 is peeled and / or released from the donor release layer 504 using any of the techniques described herein (e.g., selective release, blanket laser irradiation, forming a bond with a strength difference), and the donor 502 is mechanically separated from the acceptor 512. As a result, the transferred D2D interconnect 506 is separated from the donor 502 and remains on the acceptor 512.

[0089] exist Figure 5D In the process, additional processing is performed to form the remaining interconnects, including dielectric (e.g., oxide) fill 510 and planarization, interconnect 508 patterning / metallization (e.g., forming through dielectric vias (TDVs) 508, top metal contacts 508 (such as hybrid bonding pads), dielectric layers 510), etc.

[0090] It is worth noting that, since the D2D interposer 506 is selectively transferred while the surrounding dielectric layer 510 is directly fabricated on the receptor 512, there is a seam 511 between the transferred D2D interposer 506 and the surrounding layer 510, as shown in FIG. Figure 5D In general, this type of seam or transition can exist around any type of selectively transferred part because they are not formed simultaneously with the surrounding layers.

[0091] exist Figure 5E In the embodiment, multiple IC dies 518a-b are attached to the top metal pad 508 (e.g., via hybrid bonding), the area around the dies 518a-b is filled with a dielectric material 510 (e.g., oxide) and planarized, and a structural substrate 520 (e.g., a structural silicon wafer) is attached.

[0092] Dies 518a-b may be attached using standard assembly techniques (such as pick and place) or using the selective transfer techniques described herein (eg, similar to the transferred D2D interconnect 506).

[0093] If the dies 518a-b are attached using pick and place assembly, they are typically formed on a thick substrate for handling purposes and then thinned after attachment.

[0094] However, if the die 518a-b are selectively transferred, they can be formed on and transferred directly from a very thin substrate. Therefore, selectively transferring the die 518a-b not only eliminates the need for post-attachment thinning, but also enables the die 518a-b to be much thinner than a die that is picked and placed for attachment and then thinned. In addition, if the die 518a-b are selectively transferred, there may be a seam 511 between the die 518a-b and the portion of the layer 510 surrounding the die 518a-b, similar to the seam 511 shown around the transferred D2D interconnect 506 as described above. In addition, because the die 518a-b are selectively transferred, they can be different types of dies, formed on separate pieces of substrate material (e.g., separate wafers or panels) using separate processes, and then selectively transferred to the same layer of the IC device 500.

[0095] exist Fig. 5F In the process, receptor 512 is peeled off and released from release layer 514 (eg, using any of the techniques described herein, such as IR or UV laser ablation).

[0096] At this point, IC package 500 may be complete, or alternatively, additional processing may be performed. For example, if processing is performed at the wafer or panel level, the resulting IC package 500 on structural substrate 520 may be singulated.

[0097] Figure 6A-6B An example of selective layer transfer between a donor wafer 600 and a receptor wafer 610 is shown. In particular, Fig. 6A 6 shows wafers 600, 610 before transfer, and Figure 6B Wafers 600, 610 are shown after transfer. In the example shown, non-contiguous regions of the donor wafer 600 are selectively transferred to non-contiguous locations on the receptor wafer 610. However, in other embodiments, the target region on the donor 600 and the destination region on the receptor 610 may be partially contiguous or completely contiguous.

[0098] like Fig. 6AAs shown, prior to transfer, a donor wafer 600 includes a layer of integrated circuit (IC) components 602 (e.g., dies, chiplets, interconnects, capacitors, transistors, etc.), which may be partially singulated (e.g., cut down but not through the underlying wafer 600). A receptor wafer 610 includes bonding areas 612 patterned in non-contiguous locations on a surface (also referred to as a bonding template), which are locations where target IC components 602 from the donor 600 will be transferred. In some embodiments, for example, the bonding areas 612 may be raised structures or protrusions (referred to as "mesas") patterned on the surface of the receptor 612. Furthermore, in some embodiments, the bonding areas 612 on the receptor 610 may have a similar footprint as the target IC components 602 on the donor 600. However, in various embodiments, any suitable surface treatment or other technique may be used to control the level of adhesion on different areas of the receptor substrate 610 (e.g., to form adhered and non-adhesive areas for selective transfer), including but not limited to examples such as variations in surface topography (e.g., mesas, recesses), use of materials with high and / or low adhesion, treatment with hydrophobic materials and / or self-assembled monolayers (SAMs), and / or surface activation techniques.

[0099] like Figure 6B As shown, after transfer, the target IC components 602 have been transferred from the donor wafer 600 to the acceptor wafer 610. As a result, the donor wafer 600 includes empty areas 603 where the transferred IC components 602 are located, while the acceptor wafer 610 includes the transferred IC components 602 in the locations of the patterned bonding areas 612. In particular, the individual IC components 602 from the donor wafer 600 are now bonded to the individual bonding areas 612 on the acceptor wafer 610.

[0100] Although the illustrated example shows selective transfer between two wafers, selective transfer may be performed between panels or other substrates of any shape or size, including substrates with non-matching shapes and sizes.

[0101] Figure 7A flow chart 700 for performing a selective layer transfer is shown. It will be understood from the present disclosure that the process flow shown is only an example method for performing a selective layer transfer. In addition, any suitable semiconductor manufacturing technology can be used to perform the steps of the process flow shown. For example, any suitable deposition technology (including, for example, chemical vapor deposition (CVD), metal organic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE), atomic layer deposition (ALD) and / or physical vapor deposition (PVD)) can be used to perform film deposition-such as depositing a layer, filling a portion of a layer (e.g., a portion that is removed) and filling a via opening. In addition, any suitable technology (such as lithography-based patterning / masking and / or etching) can be used to perform patterning and removal-such as interconnect patterning, forming via openings and shaping.

[0102] The flow chart begins at block 702 by receiving a first substrate (which may be referred to as a donor substrate) having a layer of integrated circuit (IC) components. In some embodiments, the donor substrate may include a base substrate, a release layer over the base substrate, and a (partially singulated) layer of IC components over the release layer.

[0103] In some embodiments, a donor substrate can be formed by receiving a base substrate, forming a release layer over the base substrate, forming an IC component layer over the release layer (e.g., by fabricating or transferring the IC component layer over the release layer), and partially singulating the IC component layer (e.g., by cutting through the IC component layer without cutting through the base substrate).

[0104] In various embodiments, the IC component layer may include one or more IC dies, interconnects, transistors, diodes, resistors, capacitors, inductors, transformers, optical / optoelectronic components (e.g., optical waveguides, ring resonators, drivers, photodetectors, transimpedance amplifiers, electronic integrated circuits, optical transceivers, optical interfaces), and / or any other active or passive circuit systems or components.

[0105] The base substrate can be made of one or more materials, including elements such as silicon (Si), oxygen (O), carbon (C), hydrogen (H) and / or III-V group elements (e.g., aluminum (Al), gallium (Ga), indium (In), nitrogen (N), phosphorus (P), arsenic (As), antimony (Sb)), including but not limited to silicon (Si), silicon dioxide (silica or SiO2), silicon on insulator (SOI), quartz, glass, III-V group materials (e.g., gallium nitride (GaN), aluminum gallium nitride (AlGaN), gallium arsenide (GaAs), indium gallium arsenide (InGaAs), indium phosphide (InP)), and epoxy resin / resin (e.g., IR or UV transparent epoxy resin).

[0106] Depending on the type of release or stripping technology used, the release layer can include one or more layers of different materials. For example, for IR laser stripping, the release layer can include one or more layers of (one or more) materials that can absorb and / or reflect infrared (IR) electromagnetic radiation, such as a thin metal layer or multiple metal layers (e.g., aluminum (Al), tungsten (W), copper (Cu), titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN)). For UV laser stripping, the release layer can include one or more layers of (one or more) materials that can absorb ultraviolet (UV) electromagnetic radiation (e.g., organic polymers such as polyimide). In some embodiments, the release layer may additionally or alternatively include one or more layers of dielectric material to buffer laser ablation and thermal energy, control film interference or adhesion, and / or provide residual adhesion after other materials and / or layers in the release layer are laser weakened, removed and / or ablated (e.g., silicon dioxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiON), silicon carbide (SiC), silicon carbonitride (SiCN), silicon carbon oxynitride (SiOCN), aluminum oxide (Al2O3), low-k dielectrics (e.g., carbon-doped oxide (CDO) or porous silicon dioxide (SiO2), titanium dioxide (TiO2), tantalum oxide (Ta2O5)). Therefore, in some embodiments, the (one or more) release layers may be made of one or more materials including elements such as aluminum (Al), tungsten (W), copper (Cu), titanium (Ti), tantalum (Ta), silicon (Si), oxygen (O), nitrogen (N), hydrogen (H) and carbon (C), including but not limited to any of the above materials.

[0107] The flow chart then proceeds to block 704 to receive a second substrate having one or more bonding areas, which may be referred to as an acceptor substrate. In some embodiments, the acceptor substrate may include a base substrate having one or more bonding areas patterned on a surface, such as a layer of raised bonding structures or "mesas" above the base substrate. The acceptor substrate may also optionally include a release layer above the base substrate (e.g., to enable the base substrate to be subsequently peeled off after transfer) and / or one or more additional buildup layers and / or IC components.

[0108] In some embodiments, the acceptor substrate can be formed by receiving a base substrate, optionally forming a release layer over the base substrate, optionally forming additional buildup layers and / or IC components over the base substrate (e.g., over the optional release layer, if included), and forming bonding areas (e.g., bonding structures) on the surface of the acceptor substrate (e.g., over the previously referenced layers, if included). In some embodiments, the acceptor's base substrate and optional release layer can be made of any of the materials mentioned above for the donor's base substrate and release layer, respectively.

[0109] In some embodiments, the bonding area can include a mesa structure having a similar footprint as the corresponding IC component to be transferred from the donor (although in some cases, the mesa can be slightly larger or smaller than the IC component to accommodate alignment and manufacturing tolerances). The mesa structure can be made of different materials, depending on the type of bonding and / or whether electrical connection is required through the bonding interface of the subsequently bonded IC component (e.g., dielectric material, metal, or both). For example, the mesa structure can include a blanket dielectric structure without conductive contacts (e.g., for dielectric-to-dielectric bonding), a dielectric structure with conductive contacts (e.g., for mixed dielectric and metal bonding), and / or the conductive contacts themselves (e.g., for metal-to-metal bonding). Therefore, in some embodiments, the mesa structure can be made of one or more materials, including elements such as silicon (Si), oxygen (O), hydrogen (H), nitrogen (N), carbon (C), aluminum (Al), tungsten (W), copper (Cu), titanium (Ti), tantalum (Ta), including but not limited to inorganic dielectrics (such as silicon dioxide (SiO2), silicon nitride (Si3N4) and / or silicon carbonitride (SiCN)), organic dielectrics (such as photoresists and adhesives), and / or conductive materials (such as metals and alloys (for example, any of the aforementioned metal elements and / or their compounds / alloys)).

[0110] However, in various embodiments, any suitable technique(s) may be used to control adhesion levels on different regions of the acceptor substrate. For example, various surface treatments (e.g., photolithography or additive manufacturing) may be used to enhance and / or reduce adhesion in selected regions of the acceptor substrate, including but not limited to modifying the surface topography (e.g., raised and recessed regions, smooth and rough regions), using materials with high and / or low adhesion (e.g., forming a layer with adhesive and non-adhesive materials in selected regions), using hydrophobic materials and / or self-assembled monolayers (SAM) treatments, and / or surface activation techniques (e.g., plasma or wet activation), among other examples.

[0111] For example, the surface topography of the receptor substrate can be modified (e.g., using techniques such as deposition, lithography, etching, roughening) to form regions with different adhesion levels, such as raised (e.g., bonding) and recessed (e.g., non-bonding) regions, smooth (e.g., bonding) and rough (e.g., non-bonding) regions, etc.

[0112] As another example, the surface of the acceptor substrate can be patterned with a material having high and / or low adhesion in selected areas. For example, a layer patterned with different areas of adhesive material and non-adhesive material can be formed on the acceptor substrate. In some embodiments, the adhesive material can include silicon dioxide (SiO2) or silicon carbonitride (SiCN) to promote strong oxide melt bonding, can include silicon carbide (SiC) to provide lower thermal contact resistance compared to SiO2 or SiCN, and / or can include metal to form an electrical connection. In addition, in some embodiments, the non-adhesive material can include silicon nitride (Si3N4) to form a weak bond or no bond.

[0113] As another example, treatment with a hydrophobic material and / or a self-assembled monolayer (SAM) can be used to enhance and / or reduce adhesion in selected areas of a receptor substrate (e.g., using a SAM treatment to produce a monolayer with high and / or low adhesion in selected areas). In some embodiments, the hydrophobic material can include a SAM material, such as an alkyl or fluoroalkyl silane (e.g., ODS, FDTS), a thiol (e.g., hexadecanethiol), a phosphonic acid (e.g., octadecyl or perfluorooctanephosphonic acid), or an alkanoic acid (e.g., heptadecanoic acid). However, non-SAM-based materials or membranes can also be used. In some embodiments, the hydrophobic material can include a thin polymer film, such as a siloxane (e.g., PDMS and derivatives, HMDSO), a silazane (HMDS), a polyolefin (e.g., PP), or a fluorinated polymer (e.g., PTFE, PFPE, PFDA, C4F8 plasma polymerized membrane, etc.). Other hydrophobic materials can be used in other embodiments.

[0114] As another example, surface activation techniques may be used to enhance and / or reduce adhesion in selected areas of the receptor substrate, including, but not limited to, plasma or wet activation.

[0115] The flow chart then proceeds to block 706 to partially bond the donor substrate to the acceptor substrate (e.g., face-to-face) such that one or more target IC components on the donor substrate are selectively bonded to one or more bonding regions on the acceptor substrate. The donor substrate and the acceptor substrate may be partially bonded using any suitable bonding technique, including, but not limited to, hybrid bonding, fusion bonding, and / or adhesive bonding.

[0116] The flow chart then proceeds to block 708 to release the target IC component from the donor substrate and separate the donor substrate from the acceptor substrate. In this manner, when the donor substrate is separated from the acceptor substrate, the target IC component is separated from the donor substrate and remains on the acceptor substrate.

[0117] In some embodiments, the donor substrate and the acceptor substrate can be peeled / separated from each other by at least partially releasing the target IC component from the release layer of the donor substrate and then mechanically separating the donor substrate and the acceptor substrate. For example, in some embodiments, the target IC component can be completely released from the donor substrate by selectively peeling the target IC component from the donor release layer using a laser (e.g., an IR or UV laser), or alternatively, the target IC component can be partially released from the donor substrate by weakening the donor release layer using a laser (e.g., an IR or UV laser). After the target IC component is completely or partially released from the donor, the donor substrate and the acceptor substrate are mechanically separated, and after separation, the target IC component remains bonded to the acceptor and is no longer on the donor.

[0118] Alternatively or additionally, the donor release layer and receptor bonding structure can be formed of corresponding materials having different bonding strengths - so that the target IC component bonds more strongly to the receptor than to the donor - thereby causing the target IC component to peel away from the donor and remain on the receptor when the donor and receptor are mechanically separated.

[0119] The flowchart then proceeds to box 710 to perform any remaining processing, such as dielectric fill and planarization, attaching additional IC dies or components (e.g., via selective transfer or pick and place assembly), forming interconnects (e.g., vias, traces), attaching a structural substrate, stripping off a receptor base substrate (e.g., via an optional receptor release layer), and / or any other processing required for a finished product (e.g., an IC package, device, system, etc.).

[0120] The finished product may include various components and circuit systems (some of which may have been selectively transferred), including electrical components (e.g., electronic integrated circuits (EICs), processors, XPUs, controllers, memory), optical components (e.g., optical interfaces, photonic integrated circuits (PICs), optical connectors, optical fibers), and / or radio frequency (RF) or high voltage components (e.g., high voltage electrostatic discharge (ESD) devices, power amplifiers (PAs), low noise amplifiers (LNAs), voltage controlled oscillators (VCOs), surface acoustic wave (SAW) / bulk acoustic wave (BAW) devices or filters, bandpass filters (BPFs), intermediate frequency (IF) amplifiers, frequency synthesizers, mixers, RF digital-to-analog converters (DACs), RF analog-to-digital converters (ADCs), thick gate oxide devices, III-V devices / chiplets, passive RF devices (such as interconnects, antennas, and inductors)).

[0121] Furthermore, in some embodiments, the resulting IC package or product may be electrically coupled to a circuit board and / or incorporated into an electronic device or system (eg, with other electronic components).

[0122] At this point, the flow chart can be completed. However, in some embodiments, the flow chart can restart and / or can repeat certain frames. For example, in some embodiments, the flow chart can restart at frame 702 to continue to perform selective transfer.

[0123] Selective transfer of optical and optoelectronic components

[0124] A typical silicon photonics architecture may have some components fabricated in situ (e.g., waveguides, ring resonators), other components assembled by hybrid assembly techniques (e.g., by transferring a blank semiconductor component and then processing it in situ, such as for certain laser fabrication techniques), and the remainder assembled by standard assembly techniques (e.g., pick-and-place assembly for electronic integrated circuit (EIC) components such as drivers and transimpedance amplifiers (TIAs)). While this combination attempts to leverage the capabilities of each individual technology to achieve performance and cost targets, there are various drawbacks. Other embodiments are also possible, for example, where all components can be fabricated monolithically on the same substrate (e.g., using combined CMOS and optical / optoelectronic fabrication processes).

[0125] For example, in-situ fabrication techniques typically involve the complete transfer or growth of an active layer (e.g., gallium nitride (GaN) or indium phosphide (InP)) followed by etching away the unwanted portions. This approach is low cost because most of the transferred or grown material is effectively etched away.

[0126] Hybrid manufacturing techniques typically involve transferring blocks of the active layer (e.g., GaN or InP material) and then processing them in situ. While this approach is more cost-effective than in situ techniques with full-layer transfer, manufacturing cannot be parallelized well because much of the wafer is effectively masked while the transferred parts are being made.

[0127] Pick-and-place assembly techniques typically involve mechanically transferring a fabricated device (e.g., an array of optoelectronic components) to a photonic substrate. In this way, all components can be fabricated in parallel on their respective ideal substrates (e.g., logic / Si, GaN, InP, etc.), and the completed components can then be attached to the final photonic substrate. However, standard assembly techniques have limitations on the size and thickness of the respective components, which limits the applicability of this method to relatively large components or to transferring larger components and then etching them to reduce their size, which limits efficiency and increases cost. In addition, die handling can result in edge dislocations, which can make the substrate material (e.g., InP) inefficient and susceptible to defects.

[0128] Therefore, the present disclosure provides a technique for transferring optical and optoelectronic components in parallel using a selective transfer technique, as well as devices and systems formed using the technique. In particular, the selective transfer technique (e.g., as described above in conjunction with FIGS. 1-7 ) is used to transfer various optical and optoelectronic components from their original substrates to a photonic substrate.

[0129] The described solution provides various advantages. For example, the solution enables parallel manufacturing and transfer of respective components of an optical device, which increases manufacturing speed and reduces costs compared to in-situ manufacturing techniques and standard pick-and-place assembly. The solution also enables manufacturing of all components on their respective substrates with significantly less wasted processing area compared to hybrid manufacturing techniques. Furthermore, the solution enables direct assembly of all components, which simplifies the manufacturing process, reduces costs, and improves performance.

[0130] This solution also enables granular integration of different optical and optoelectronic components with high placement accuracy and very few restrictions on the area of ​​the transferred components. As a result, optical and electronic components can be placed very close together, which leads to much lower parasitic effects and higher energy efficiency.

[0131] The solution also enables the integration of components from incompatible process technologies. For example, a photonic integrated circuit (PIC) includes various components manufactured using different process technologies, some of which may be incompatible with each other. In particular, silicon / silicon dioxide (Si / SiO2) waveguides, germanium (Ge) photodiodes, and gallium nitride (GaN) transistor technologies incorporate high temperature manufacturing steps, which may be incompatible with the process technologies of ring modulators and lasers. The solution enables all of these components to be manufactured using separate and different process technologies in different manufacturing plants and ultimately assembled using selective transfer.

[0132] The solution also enables novel base substrates to be used for optical devices. In particular, since typical in-situ manufacturing steps can be completely replaced with selective transfer, the solution provides the flexibility of using base substrates made of materials other than silicon (such as glass substrates, silicon on insulator (SOI) substrates, or silicon carbide (SiC) substrates, etc.). In some cases, for example, glass substrates can be used to reduce losses, improve electrical losses, and / or operate at different frequencies. Substrates in the form of panels can be used to implement wafer-level systems. In addition, in some cases, substrates and / or components can be selectively transferred directly to the top of a silicon substrate within a CMOS manufacturing process flow.

[0133] Figure 8An example embodiment of an optical transceiver 800 is shown. In various embodiments, some or all of the components of the optical transceiver 800 may be assembled using the selective transfer techniques described throughout this disclosure (eg, in conjunction with FIGS. 1-7 and 9-12 ).

[0134] In the illustrated embodiment, the optical transceiver 800 includes an electronic integrated circuit (EIC) 802 , a transmitter 810 , and a receiver 820 .

[0135] The EIC 802 includes various high-speed electronics and / or control electronics (e.g., in-plane or stacked), such as carrier phase recovery (CPR), clock and data recovery (CDR), error correction, serializer / deserializer (serdes), equalizer, sampler, mixer, amplifier, temperature control (e.g., heater), analog-to-digital converter (ADC) and digital-to-analog converter (DAC), control and switching, controller / computation engine, power delivery and / or power conversion. The EIC 802 also typically includes a driver 811 and a transimpedance amplifier (TIA) 821, but in the illustrated embodiment, the driver 811 and the TIA 821 are separated from the EIC 802 (e.g., implemented on separate IC dies) and placed near the modulator 812a-b and the photodetector (PD) 823, respectively, to improve performance, as described below.

[0136] The transmitter 810 includes a laser source 818, a waveguide 816 for guiding light from the laser source 818, an optical coupler 817 for coupling the waveguide 816 to another optical component such as an optical fiber (not shown), a plurality of modulators 812a-b for modulating light of different wavelengths (λ1, λ2) on the transmitter waveguide 816, and a plurality of drivers 811 for controlling the corresponding modulators 812a-b. In the illustrated embodiment, ring resonator modulators 812a-b are used. Each modulator 812a-b includes an electrode 813, a ring resonator 814, and a waveguide 815. When the corresponding driver 811 applies a voltage to the ring resonator 814 via the electrode 813, light of a specific wavelength (e.g., λ1 or λ2) on the transmitter waveguide 816 is absorbed by the ring resonator 814 and output to the modulator waveguide 815, thereby effectively filtering the light of the specific wavelength from the transmitter waveguide 816. In this way, multiple wavelengths of light can be multiplexed on the transmitter waveguide 816 using corresponding drivers 811 and modulators 812a-b, which is known as wavelength division multiplexing (WDM). Other types of modulators are also possible, such as Mach-Zehnder modulators and variations thereof.

[0137] The receiver 820 includes a waveguide 826 for guiding light received from another component (not shown) via an optical coupler 827, a plurality of detectors 822a-b for detecting light of different wavelengths (λ1, λ2) on the receiver waveguide 826, and a plurality of photodetectors (PD) 823 and transimpedance amplifiers (TIA) 821 for converting the detected light waves into electrical signals and amplifying them. Each detector 822a-b includes a ring resonator 824 and a waveguide 825. When light of a specific wavelength (e.g., λ1 or λ2) is received on the receiver waveguide 826, the light waves are transmitted by the corresponding ring resonator 824 to the detector waveguide 825, and then delivered as input to the PD 823. The PD 823 converts the light waves (e.g., optical signals) into currents, and the TIA 821 converts the currents into corresponding voltages (e.g., current-to-voltage conversion), which are then delivered to the EIC 802 to generate / output electrical (e.g., digital) signals based on the voltages. In this manner, multiple wavelengths of light may be received on the receiver waveguide 826, demultiplexed, and then converted to corresponding electrical signals (e.g., using corresponding TIA 821, PD 823, and detectors 822a-b). For simplicity, not all components of the optical transceiver 800 are shown in the illustrated example (e.g., a heater and corresponding control circuitry may be present to control the temperature of the various optical / optoelectronic components, among other components).

[0138] In the illustrated embodiment, certain components that are typically integrated within the EIC 802 are separated or decomposed from the EIC 802 to improve performance. For example, the TIA 821 is separated from the EIC 802 and placed closer to the PD 823 to reduce parasitic effects, maximize receiver sensitivity, and provide higher energy efficiency. Similarly, the driver 811 is separated from the EIC 802 - so that they can be implemented using different (e.g., optimized) semiconductor processes - and is placed closer to the corresponding modulators 812a-b. In some embodiments, these separated components can be assembled in the optical transceiver 800 using selective transfer technology, which enables the components to be manufactured in parallel on the best substrate material using the best process technology and then selectively transferred to the best location in the optical transceiver circuit 800 without the disadvantages of other technologies (e.g., the constraints on the size, area, and thickness of components assembled using pick and place technology).

[0139] In some embodiments, other components of the optical transceiver 800, including examples such as EIC 802, waveguides 815, 816, 825, 826, ring resonators 814, 824, electrodes 813, PD 823, and laser source 818, may be similarly assembled using selective transfer techniques.

[0140] It should be understood that the illustrated embodiment of the optical transceiver 800 is presented only as an example, and many other variations are possible. For example, the optical transceiver 800 may include any number of EICs 802, transmitter units 810, receiver units 820, waveguides 816, 826, modulators 812, detectors 822, drivers 811, TIAs 821, PDs 823, etc. The optical transceiver 800 may include other components not shown, and / or certain components may be omitted, combined, separated, and / or rearranged.

[0141] Figures 9A-9F An example process flow is shown for forming an optical transceiver 900 using a selective transfer technique. In the example shown, a transimpedance amplifier (TIA) 905 is laterally integrated into the optical transceiver 900 using the selective transfer technique. However, the same approach can also be used to integrate other electrical and / or optical components into the optical transceiver 900 (e.g., laterally / in-plane or stacked).

[0142] Selective transfer techniques combined with quasi-monolithic chip (QMC) building blocks can be used to transfer electrical components very close to optical components to improve overall system performance. In particular, certain components that are typically integrated within an electronic integrated circuit (EIC) 906 can be separated or decomposed from the EIC 906 (e.g., such that the EIC and the separated components are implemented on separate IC dies) to enable them to be placed closer to the corresponding optical components. As an example, a TIA circuit 905 can be separated from the EIC 906 and fabricated as an independent chiplet, and the TIA chiplet 905 can be selectively transferred near a photodetector (PD) 904 on a photonic substrate 902, which enables a very close connection between the TIA 905 and the PD 904 to maximize receiver sensitivity. Similarly, a driver circuit can be separated from the EIC 906 and selectively transferred near an optical modulator.

[0143] In this way, electrical components can be fabricated in parallel on optimal substrate materials using optimal process technologies, and then selectively transferred to optimal locations in the photonic substrate 902 without the drawbacks of other technologies (e.g., incompatible process technologies, dimensional constraints of pick and place assembly). In some embodiments, for example, certain high-speed electronic devices can be implemented using III-V semiconductor devices (such as GaN transistors), which are well suited for high-voltage and high-frequency driver electronics and low-noise amplifiers due to their wide bandgap and high-mobility channels.

[0144] Figures 9A-9F An example processing flow is shown in FIG. Fig. 9A, three substrates are fabricated in parallel: a photonic substrate 902, a donor substrate 910, and a stamp substrate 920. The photonic substrate 902 can be fabricated using any suitable technique, including selective transfer techniques, monolithic fabrication, and / or pick-and-place assembly. In the illustrated embodiment, the photonic substrate 902 includes through-silicon vias (TSVs) 908a, optical waveguides 903, and photodetectors 904 (with pads 908b). In parallel, sensitive electrical components (e.g., TIA 905 for PD 904) are fabricated on a separate substrate, thinned, then transferred to the donor substrate 910 and singulated over a release layer 912. The stamp substrate 920 is fabricated with raised mesas 924 over a release layer 922 to enable the TIA die 905 to be placed in a target area on the photonic substrate 902. In some embodiments, the raised mesas 924 may be raised dielectric and / or metal structures having a similar footprint as corresponding components to be selectively transferred (eg, TIA 905, PD 904, optical waveguides, ring resonators, drivers, EICs, etc.).

[0145] exist Fig. 9B In the process, some TIAs 905 on the donor substrate 910 are selectively transferred to the stamp substrate 920.

[0146] exist Fig. 9C In the embodiment, the TIA 905 on the stamp substrate 920 is selectively transferred to the photonic substrate 902 near the corresponding PD 904 (only one of the transferred TIA 905 and the corresponding PD 904 is shown on the photonic substrate 902). In addition, the mesa 924 on the stamp 920 is transferred with the TIA 905 and remains above the TIA 905 after the transfer. As a result, the mesa 924 is subsequently removed from the TIA 905 (e.g., via etching) to expose the pad 908c on the TIA 905 before further processing (e.g., Fig.9D shown).

[0147] exist Fig.9D , interconnect 908d is formed over PD 904 and TIA 905 within dielectric layer 907. Interconnect 908d includes short lateral wiring between PD 904 and TIA 905 to achieve low parasitics, as well as vertical connections to hybrid bond pads (eg, for attaching EIC 906).

[0148] Other interconnects may also be formed on substrate 902 to enable additional electrical connections. In some embodiments, for example, the photonic IC may also function as an electrical interposer to enable electrical connections between multiple top chiplets, and thus interconnects may be formed for interposer capabilities. Furthermore, the interconnects may be fabricated monolithically as shown, or other chiplets capable of providing electrical connection functionality may be fabricated and then assembled and / or selectively transferred.

[0149] exist Fig.9E In the embodiment of the present invention, the interlayer dielectric 907 above the waveguide 903 is etched away to expose the waveguide 903. For example, depending on the specific architecture, some components may be sensitive to the surrounding dielectric 907 (e.g., low loss waveguide 903), or may need to be exposed for other reasons (e.g., attaching a coupler to an optical fiber). In those cases, a deep etch can be performed to etch away the ILD dielectric 907 and expose those areas. In some embodiments, the optical components can be exposed by coating a thin etch stop layer or sacrificial layer (e.g., aluminum oxide (AlO)) on the optical components. x )) to include this etching process in the manufacturing flow, this layer acts as an etch stop layer during the oxide etch and can be removed later with a different etching process.

[0150] Furthermore, if the density and added parasitics are acceptable, the EIC 906 can be attached to the top surface using standard assembly techniques, such as pick-and-place assembly using hybrid bonding (e.g., via respective hybrid bonding pads 908d, 908e and dielectric layer 907) or solder assembly. Alternatively, in some embodiments, highly separated EIC chiplets can be attached using selective transfer techniques with on-chip wiring to achieve electrical connections.

[0151] exist Fig.9F , the bottom side of the photonic substrate 902 is thinned to expose the TSV 908a, and solder bumps 901 are formed on pads 908f on the bottom side to enable flip chip assembly with the TSV 908a. In other embodiments, any suitable interconnect or packaging technology may be used, such as wire bonding with solder connections on the top side or TSV-free attachment. The completed optical transceiver 900 may then be attached to an IC package, a printed circuit board (PCB), or other device / substrate as desired.

[0152] It should be understood that the illustrated process flow for forming the optical transceiver 900 using the selective transfer technique is presented only as an example, and that many other process variations and architectures are possible, including those described in conjunction with other figures. In addition, other electrical and / or optical components can be selectively transferred to the photonic substrate 902 in a similar manner, including EICs, drivers, photodetectors 904, optical waveguides, mirrors, ring resonators, modulators, detectors, diffraction gratings, isolation and / or anti-reflection structures, heater elements, etc.

[0153] Furthermore, the selective transfer may be performed using any of the selective transfer techniques described throughout this disclosure (e.g., in conjunction with FIGS. 1-7 ). Figures 1A-1I Alternatively or additionally, a process flow such as that shown in FIG. 1 may be used to perform selective transfer of dies of the same type. Figures 4A-4C The intermediate donor / acceptor substrate described is used to perform selective transfer of different types of dies / components. For example, multiple types of electronic and / or optical components (eg, TIA, PD, driver, etc.) can be transferred from different donor substrates 910 to the stamp substrate 920.

[0154] In some embodiments, for example, the donor wafer 910 may include various IC components, such as a TIA IC, a driver IC, a telemetry IC, etc. In addition, during the die 920 bond / peel transfer step, the stamp 920 may first pick up the TIA IC and selectively transfer the TIA IC to the photonics wafer 902, followed by the driver IC, then the telemetry IC, etc. Alternatively or additionally, there may be multiple donor wafers 910, each containing separate intellectual property (IP) blocks, such as a donor 910 with a TIA IC, a donor 910 with a driver IC, etc. During the die 920 bond / peel selective transfer step, the stamp 920 may first pick up the TIA and transfer the TIA from the TIA donor wafer 910 to the photonics wafer 902, then transfer the driver IC from the driver donor wafer 910, etc. In the case of the stamp 920 selective transfer, there may not be a corresponding lower mesa on the transferred component, but there may be a corresponding mesa if other selective transfer techniques are used.

[0155] Figures 10A-10E Example configurations of electrical and optical components integrated using selective transfer techniques are shown. In particular, an electronic integrated circuit (EIC) 1004, a transimpedance amplifier (TIA) 1006, and a photodetector (PD) 1008 are integrated in various configurations using selective transfer techniques.

[0156] exist Fig. 10A1 , the TIA circuit 1006 is separated from the EIC 1004 and associated logic, which enables low parasitic wiring 1010a between the TIA 1006 and the PD 1008, and optimized process technology for manufacturing the TIA 1007. For example, the PD 1008 and the TIA 1006 are selectively transferred to the substrate 1002 adjacent to each other on the raised dielectric mesa 1003 (e.g., in the same layer). In addition, interconnects 1010 are formed in an interlayer dielectric (ILD) material 1012 above the PD 1008 and the TIA 1006, wherein lateral wiring 1010a is between the PD 1008 and the TIA 1006, and vertical wiring 1010b is between the TIA 1006 and the EIC 1004 (where the EIC 1004 is above the TIA 1006). In the illustrated embodiment, the EIC 1004 is hybrid-bonded over the TIA 1006 , but in other embodiments, the EIC 1004 may be selectively transferred over the TIA 1006 .

[0157] exist Fig. 10B In the embodiment, the TIA circuit 1006 is separated from the EIC 1004 and placed above the PD 1008 and lateral to the EIC 1004, with vertical wiring 1010c between the TIA 1006 and the PD 1008, lateral wiring 1010d between the TIA 1006 and the EIC 1004, and vertical wiring 1010e, 1010f between the bottom of the substrate 1002 and the EIC 1004 (e.g., through-dielectric vias 1010e in the ILD 1012 and through-silicon vias (TSVs) 1010f in the substrate 1002). The PD 1008 is selectively transferred to the substrate 1002 on the raised dielectric mesa 1003, the TIA 1006 is hybrid-bonded above the PD 1008, and the EIC 1004 is hybrid-bonded next to the TIA 1006.

[0158] exist Fig. 10C In the embodiment, the TIA circuit system 1006 is integrated as a part of the EIC chip 1004, wherein fast vias or super vias 1010g are used to vertically route between the TIA circuit system 1006 and the PD 1008 to minimize routing parasitics, and TDVs 1010e and TSVs 1010f are used to vertically route to the bottom of the substrate 1002. The PD 1008 is selectively transferred to the substrate 1002 on the raised dielectric mesa 1003, and the EIC 1004 (with the integrated TIA circuit system 1006) is hybrid-bonded over the PD 1008.

[0159] exist Fig. 10D, a separate TIA circuit 1006 is integrated with a PD 1008 before selective transfer. The integrated TIA / PD 1007 is then selectively transferred to the substrate 1002 on the raised dielectric mesa 1003. This enables lowest parasitic integration and minimizes the wiring required on the PD circuit 1008. The EIC 1004 is hybrid-bonded over the integrated TIA / PD 1007 with vertical wiring 1010e, 1010f between the bottom of the substrate 1002 and the EIC 1004 (e.g., with through-dielectric vias 1010e in the ILD 1012 and through-silicon vias (TSVs) 1010f in the substrate 1002).

[0160] exist Fig. 10E , a plan view of an EIC chip 1004 is shown with routing 1010 to a separate TIA 1006 and associated PD 1008. In some embodiments, the EIC 1004 itself may be broken down to enable optical routing and / or placement of higher components within the EIC controller.

[0161] Figures 11A-11B Various arrangements of selectively transferred optical components are shown. In particular, Fig.11A and Fig. 11B Single-layer and multi-layer arrangements of selective transfer features in the receiver 820 of the optical transceiver 800 are shown, respectively.

[0162] For example, the selective transfer technique can be used to transfer optical components such as photodetectors, optical waveguides, mirrors, ring resonators, modulators, detectors, diffraction gratings, isolation and / or anti-reflection structures, and heater elements, among others. Individual components can be selectively transferred in a plane (e.g., within a single layer) to maintain the same architectural capabilities, or they can be stacked across multiple layers to further reduce system size and / or reduce losses.

[0163] exist Fig.11A and Fig. 11B Examples of micro-ring resonator devices transferred into a single layer and across multiple layers are shown in . In these examples, the micro-ring resonator device includes a ring resonator 824 and waveguides 825, 826 from a receiver 820 of an optical transceiver 800.

[0164] exist Fig.11A805, the waveguides 825, 826 and the ring resonator 824 are shifted in a plane or within the same layer 803, as shown in the cross-sectional view 805. In particular, the cross-sectional view 805 shows a cross section of the reference components 824, 825, 826 through the cutting plane 807 of the receiver 820. In addition, the cross-sectional view 805 has been rotated 90 degrees to match the orientation of the components in the plan view of the receiver 820. As shown in the cross-sectional view 805, the waveguides 825, 826 and the ring resonator 824 are adjacent to each other within the same dielectric layer 803 on the carrier substrate 801.

[0165] exist Fig. 11B 8, waveguides 825, 826 and a ring resonator 824 are stacked across multiple dielectric layers 803a-b on a carrier substrate 801, as shown in a cross-sectional view 805 along a cutting plane 807. For example, the waveguides 825, 826 are transferred adjacent to each other in a first layer 803a, and the ring resonator 824 is transferred above the waveguides 825, 826 in a second layer 803b.

[0166] Figures 12A-12B An example embodiment is shown having a computing platform 1200 with multiple computing hubs 1210a-i connected via an optical interconnect 1208. As described below, the computing platform 1200 includes various selectively transferred optical and electrical components, including logic (eg, CMOS) devices such as XPUs. Fig. 12A A plan view of computing platform 1200 is shown in FIG. Fig. 12B A cross section of one of the computing hubs 1210 on the computing platform 1200 is shown in FIG.

[0167] like Fig. 12A As shown, computing platform 1200 is a large-scale computing platform having multiple computing hubs 1210a-i interconnected with off-system laser sources 1220 (e.g., via glass fiber connections) through a waveguide array 1208 on an interposer 1202. However, in other embodiments, laser sources 1220 may be integrated on system 1200.

[0168] like Fig. 12BAs shown, each computing hub 1210 includes one or more XPUs 1211 having various integrated components for optical communication, including an integrated photodiode (PD) 1212, a receive-side (Rx) transimpedance amplifier (TIA) 1213, a high-speed transmit-side (Tx) data encoder 1214 coupled to an embedded ring resonator 1215, and an optical waveguide 1208. These various optical and optoelectronic components (along with other components not shown, such as EICs, drivers, etc.) together form an optical transceiver that is used to represent the XPU 1211 and memory groups (not shown) on the corresponding computing hub 1210 and to send and / or receive optical signals (e.g., data packets) between the XPU 1211 and the memory groups. In various embodiments, the XPU 1211 may include any type of processing unit, such as a central processing unit (CPU), a graphics processing unit, an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), etc.

[0169] These various components are integrated on an interposer 1202, with a waveguide network 1208 for optical input / output (I / O) between the compute hubs 1210a-i, and electrical interconnects 1206 for power (e.g., from an IC package (not shown)) and I / O (e.g., I / O between components within each compute hub 1210a-i, I / O between other components in the compute hubs 1210a-i or system 1200, and I / O between other components in the same IC package). The computing platform 1200 also includes an interlayer dielectric (ILD) material 1206 that separates the respective components and a carrier substrate 1201 (e.g., a silicon thermally processed carrier) for structural support.

[0170] In the illustrated embodiment, selective transfer techniques are used to interconnect both computing devices and photonic devices across an interposer 1202 (such as a passive glass or silicon interposer or an active interposer). The waveguide network 1208 can be fabricated directly on top of the interposer 1202, or fabricated elsewhere and selectively transferred to the interposer 1202. Additionally, subcomponents can be prefabricated or sequentially transferred using the same method to create a high-speed transmission (Tx) data encoding system 1214, where the ring resonator 1215 is coupled to the waveguide 1208 within the footprint and vertically across the network to maintain close spacing with the waveguide 1208 below. This has the advantage of allowing thermal control with good isolation. Hybrid fusion and hybrid bonding interconnects 1206 are used to maintain interconnections with nearby XPUs 1211 and / or memory solutions and power from the package. Additionally, discrete photodiodes (PDs) 1212 can be selectively transferred above the waveguide array 1208, and evanescent coupling (among other methods) can be utilized to maximize current output. In some embodiments, the transimpedance amplifier (TIA) 1213 may be fabricated or selectively transferred above the photodiode layer (not shown), or located nearby with close spacing so that vertical interconnects (e.g., TSVs) may be employed to allow direct vertical electrical coupling to the XPU 1211 (e.g., utilizing 3D interconnects). The system architecture allows for off-package I / O and XPU-to-XPU or memory hub interconnects with high data rates, which is critical for extreme lateral system scaling. In some embodiments, electrical connections may be made between different top chiplets using monolithic interconnects or using assembled interconnect chiplets.

[0171] Figures 13A-13B An example embodiment of an optical package 1300 according to some embodiments is shown. In particular, Fig.13A and Fig. 13B A cross-sectional view and a plan view of the optical component 1300 are shown, respectively. In some embodiments, as described throughout the present disclosure, one or more components of the optical package 1300 can be selectively transferred. In addition, in some embodiments, certain components of the EIC 1306 and / or PIC 1304 can be separated into separate chiplets or components and selectively transferred near each other to improve performance.

[0172] In the illustrated embodiment, the optical package 1300 includes an XPU 1308 and a plurality of optical interfaces (eg, optical transceivers) 1310 on a package substrate 1302 , and optical cables 1320 inserted into respective optical interfaces 1310 .

[0173] Each optical interface 1310 includes an optical coupler 1312, a photonic integrated circuit (PIC) 1304, and an electronic integrated circuit (EIC) 1306. The EIC 1306 is attached to the top surface of the package substrate 1302, the PIC 1304 is attached to the top surface of the corresponding EIC 1306, and the optical coupler 1312 is attached to the side / edge of the corresponding PIC 1304.

[0174] The EIC 1306 is used to control the PIC 1304 and output digital signals based on the optical signals received by the PIC 1304. In some embodiments, the EIC 1306 can receive analog and digital input signals and output analog and digital output signals. The EIC 1306 may include digital, analog and / or telemetry (e.g., performance monitoring) circuit systems to perform control functions and signal processing, including components and circuit systems such as drivers, transimpedance amplifiers (TIA), carrier phase recovery (CPR), clock and data recovery (CDR), error correction, serializer / deserializer (serializer / deserializer), equalizer, sampler, mixer, amplifier, temperature control (e.g., heater), analog-to-digital converter (ADC) and digital-to-analog converter (DAC), control and switching, controller / computing engine, power delivery, power conversion, etc. The EIC 1306 is electrically coupled to the package substrate 1302 via conductive contacts 1307 (eg, bumps / micro-bumps), and the EIC 1306 is further electrically coupled to the XPU 1308 via a bridge 1303 embedded in the substrate 1302 .

[0175] The PICs 1304 are used to send and / or receive optical signals (e.g., on behalf of the XPUs 1308) via the optical fiber array 1324. Each PIC 1304 includes components and circuitry for sending and receiving optical signals, such as a laser diode (LD) / modulator (LD-MOD) (e.g., for transmitting optical signals), a photodiode (PD) (e.g., for receiving optical signals), an optical waveguide, an optical coupler, a collimating / refocusing lens, a mirror, etc. Each PIC 1304 is controlled by an associated EIC 1306 and is electrically coupled to the top surface of the EIC 1306 via conductive contacts 1305 (e.g., bumps / micro-bumps).

[0176] An optical coupler 1312 is also attached to each PIC 1304. The optical coupler 1312 (which may also be referred to as an optical interposer) is used to optically couple or transmit an optical signal (e.g., light) between the PIC 1304 and another optical component (such as an optical cable 1320). In some embodiments, the optical coupler 1312 may include an interface attached to the PIC 1304, an interface for mating with an optical ferrule 1322 on the optical cable 1320, and a waveguide for transmitting optical signals between the corresponding interfaces. The optical coupler 1312 may optionally include various other optical and / or electrical routing features, such as through-glass vias, reflectors, etc.

[0177] Each optical cable 1320 includes an optical ferrule 1322 attached to a bundle of optical (e.g., glass) fibers 1324 (which may be referred to as a fiber array or fiber array unit (FAU)). The optical ferrule 1322 may be used to optically couple or transmit optical signals between the fiber array 1324 and the optical coupler 1312. In some embodiments, the optical ferrule 1322 may include an interface attached to the fiber array 1324 (e.g., a hole in the ferrule 1322 into which the optical fiber 1324 is inserted), an interface mating with the optical coupler 1312, and a waveguide that transmits optical signals between the corresponding interfaces.

[0178] In some embodiments, for example, the optical coupler 1312 and the optical ferrule 1322 may include complementary pluggable interfaces designed to mate. For example, the optical coupler 1312 may include an optical receptacle, and the optical ferrule 1322 may include a corresponding optical plug designed to mate with the optical receptacle (or vice versa). In this manner, each PIC 1304 is optically coupled to an associated optical fiber array 1324 via a mating optical coupler 1312 and optical ferrule 1322.

[0179] Furthermore, in some embodiments, the optical coupler 1312 and the optical ferrule 1322 may include complementary mating and alignment features (e.g., mating protrusions and sockets, pins and pinholes, grooves) to ensure that they mate with each other with the necessary degree of alignment, since the waveguide in the ferrule 1322 must be precisely aligned with the waveguide in the optical coupler 1312. For example, when the optical ferrule 1322 is inserted into the optical coupler 1312, their respective mating and alignment features engage, which enables the waveguide in the ferrule 1322 to be precisely aligned with the waveguide in the optical coupler 1312. In this way, the PIC 1304 is optically coupled to the optical fiber array 1324 via the mating optical coupler 1312 and the ferrule 1322, which enables the PIC 1304 to send and receive optical signals via the optical fiber array 1324.

[0180] In some embodiments, the optical coupler 1312 and / or the optical ferrule 1322 can be made of glass, and their respective features (e.g., interfaces, mating / alignment features, waveguides) can be patterned in the glass (e.g., using laser etching techniques).

[0181] The optical fiber array 1324 can be used to send optical signals to other components (not shown) and receive optical signals from other components (not shown). For example, the other end of the optical fiber array 1324 can be optically coupled to other components (not shown), such as other computing components that are part of the same device or system as the optical package 1300 (e.g., processors, XPUs, network interface controllers (NICs), storage bodies, memories, I / O devices, other integrated circuits), external devices or systems, switches, another optical connector (e.g., a connector similar to the optical coupler 1312 and / or the optical ferrule 1322, a standard optical connector such as a mechanical transmission (MT) or multi-fiber push-on (MPO) connector), an optical cable, etc.

[0182] The XPU 1308 is attached to the top surface of the package substrate 1302. In addition, the XPU 1308 is electrically coupled to the package substrate 1302 via conductive contacts 1309 (e.g., bumps / micro-bumps), which serve as a first level interconnect (FLI) for the XPU 1308. The XPU 1308 is also electrically coupled to the EIC 1306 via a bridge 1303 (e.g., an embedded multi-die interconnect bridge (EMIB)) embedded in the substrate 1302. In this way, the XPU 1308 can communicate using the EIC 1306 through a corresponding optical interface 1310.

[0183] XPU 1308 may include any type or combination of integrated circuit systems that communicate optically using optical interface 1310. For example, XPU 1308 may include any type or combination of processing units or other computing components, including but not limited to microcontrollers, microprocessors, processor cores, central processing units (CPUs), graphics processing units (GPUs), vision processing units (VPUs), tensor processing units (TPUs), application specific integrated circuits (ASICs), field programmable gate arrays (FPGAs), input / output (I / O) controllers and devices, switches, network interface controllers (NICs), persistent storage devices, and memories.

[0184] The package substrate 1302 includes conductive contacts 1301 (e.g., balls, pads) on the bottom surface that serve as second-level interconnects (SLI) to next-level components such as a printed circuit board (e.g., motherboard) and / or another integrated circuit package (not shown). The package substrate 1302 also includes conductive traces (not shown) patterned in the substrate to provide power and input / output (I / O) to the corresponding components in the package 1300 (e.g., XPU 1308, EIC 1306, PIC 1304).

[0185] In some embodiments, optical package 1300 can be part of an electronic device or system, such as a mobile device, a wearable device, a computer, a server, a video playback device, a video game console, a display device, a camera, or an appliance. For example, optical package 1300 and various other electronic components can be electrically coupled to a circuit board within the electronic device.

[0186] It should be understood that optical package 1300 is presented as an example only. In other embodiments, certain components may be omitted, added, rearranged, modified, or combined. For example, embodiments may include any number, combination, or arrangement of PICs and EICs (e.g., for higher bandwidth and / or redundancy), optical connectors, optical couplers, optical ferrules, optical interposers, optical fibers, bridges, XPUs or other computing components, substrates, surface cavities in substrates, conductive contacts, conductive traces, vias, integrated circuit packaging, etc.

[0187] Example Embodiments

[0188] Fig.14 1400 and die 1402, which may be included in any of the embodiments disclosed herein. Wafer 1400 may be comprised of semiconductor material and may include one or more die 1402 having integrated circuit structures formed on a surface of wafer 1400. Individual die 1402 may be repeating units of an integrated circuit product including any suitable integrated circuit. After fabrication of the semiconductor product is complete, wafer 1400 may undergo a singulation process in which die 1402 are separated from one another to provide discrete “chips” of an integrated circuit product. Chip 1402 may be any die disclosed herein. Die 1402 may include one or more transistors (e.g., the transistors discussed below). Fig.15Some of the transistors 1540 of the present invention), supporting circuitry for transmitting electrical signals to the transistors, passive components (e.g., signal traces, resistors, capacitors, or inductors), and / or any other integrated circuit components. In some embodiments, wafer 1400 or die 1402 may include memory devices (e.g., random access memory (RAM) devices, such as static RAM (SRAM) devices, magnetic RAM (MRAM) devices, resistive RAM (RRAM) devices, conductive bridge RAM (CBRAM) devices, etc.), logic devices (e.g., AND, OR, NAND, or NOR gates), or any other suitable circuit elements. Multiple of these devices may be combined on a single die 1402. For example, a memory array formed by multiple memory devices may be formed on a die that is connected to a processor unit (e.g., Fig.17 The processor unit 1702) or other logic configured to store information in a memory device or execute instructions stored in a memory array is on the same die 1402. Various of the microelectronic assemblies disclosed herein can be manufactured using die-to-wafer assembly techniques, in which some of the dies are attached to a wafer 1400 including other of the dies, and the wafer 1400 is then singulated.

[0189] Fig.15 1402. FIG. 1403 is a cross-sectional side view of an integrated circuit device 1500 that may be included in any embodiment disclosed herein (eg, in any die). One or more integrated circuit devices 1500 may be included in one or more die 1402 ( Fig.14 ). The integrated circuit device 1500 may be formed on a die substrate 1502 (eg, Fig.14 1400) and may be included in a die (e.g., Fig.14 The die substrate 1502 may be a semiconductor substrate composed of a semiconductor material system including, for example, an n-type or p-type material system (or a combination of the two). The die substrate 1502 may include, for example, a crystalline substrate formed using bulk silicon or a silicon-on-insulator (SOI) substructure. In some embodiments, the die substrate 1502 may be formed using an alternative material that may or may not be combined with silicon, including but not limited to germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide. Other materials classified as Group II-VI, Group III-V, or Group IV may also be used to form the die substrate 1502. Although several examples of materials that may form the die substrate 1502 are described herein, any material that may serve as the basis for the integrated circuit device 1500 may be used. The die substrate 1502 may be a singulated die (e.g., Fig.14 of a die 1402) or a wafer (e.g., Fig.14 A portion of wafer 1400).

[0190] The integrated circuit device 1500 may include one or more device layers 1504 disposed on a die substrate 1502. The device layer 1504 may include features of one or more transistors 1540 (e.g., metal oxide semiconductor field effect transistors (MOSFETs)) formed on the die substrate 1502. The transistor 1540 may include, for example, one or more source and / or drain (S / D) regions 1520, a gate 1522 for controlling the flow of current between the S / D regions 1520, and one or more S / D contacts 1524 for transmitting electrical signals to / from the S / D regions 1520. The transistor 1540 may include additional features that are not shown for clarity, such as device isolation regions, gate contacts, etc. The transistor 1540 is not limited to Fig.15 The types and configurations shown in , and may include a variety of other types and configurations, such as planar transistors, non-planar transistors, or a combination of the two. Non-planar transistors may include FinFET transistors (e.g., dual-gate transistors or tri-gate transistors), and wrap-around or full-ring gate transistors (e.g., nanoribbon, nanosheet, or nanowire transistors).

[0191] The transistor 1540 may include a gate 1522 formed of at least two layers, namely, a gate dielectric and a gate electrode. The gate dielectric may include one layer or a stack of layers. One or more layers may include silicon oxide, silicon dioxide, silicon carbide, and / or a high-k dielectric material.

[0192] High-k dielectric materials may include elements such as hafnium, silicon, oxygen, titanium, tantalum, lanthanum, aluminum, zirconium, barium, strontium, yttrium, lead, scandium, niobium, and zinc. Examples of high-k materials that may be used in gate dielectrics include, but are not limited to, hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanate, barium titanate, strontium titanate, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate. In some embodiments, when high-k materials are used, an annealing process may be performed on the gate dielectric to improve its quality.

[0193] The gate electrode may be formed on the gate dielectric and may include at least one p-type work function metal or n-type work function metal, depending on whether the transistor 1540 is a p-type metal oxide semiconductor (PMOS) transistor or an n-type metal oxide semiconductor (NMOS) transistor. In some embodiments, the gate electrode may be composed of a stack of two or more metal layers, wherein one or more metal layers are work function metal layers and at least one metal layer is a fill metal layer. Additional metal layers, such as barrier layers, may be included for other purposes.

[0194] For PMOS transistors, metals that can be used for the gate electrode include, but are not limited to, ruthenium, palladium, platinum, cobalt, nickel, conductive metal oxides (e.g., ruthenium oxide), and any metal discussed below with reference to NMOS transistors (e.g., for work function adjustment). For NMOS transistors, metals that can be used for the gate electrode include, but are not limited to, hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, carbides of these metals (e.g., hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and aluminum carbide), and any metal discussed above with reference to PMOS transistors (e.g., for work function adjustment).

[0195] In some embodiments, when a cross section of transistor 1540 is observed along the source-channel-drain direction, the gate electrode may be composed of a U-shaped structure including a bottom portion substantially parallel to the surface of die substrate 1502 and two sidewall portions substantially perpendicular to the top surface of die substrate 1502. In other embodiments, at least one of the metal layers forming the gate electrode may simply be a planar layer substantially parallel to the top surface of die substrate 1502 and does not include a sidewall portion substantially perpendicular to the top surface of die substrate 1502. In other embodiments, the gate electrode may be composed of a combination of a U-shaped structure and a planar non-U-shaped structure. For example, the gate electrode may be composed of one or more U-shaped metal layers formed on top of one or more planar non-U-shaped layers.

[0196] In some embodiments, a pair of sidewall spacers may be formed on opposite sides of the gate stack to enclose the gate stack therebetween. The sidewall spacers may be formed of materials such as silicon nitride, silicon oxide, silicon carbide, carbon-doped silicon nitride, and silicon oxynitride. The process of forming sidewall spacers is well known in the art and typically includes deposition and etching process steps. In some embodiments, multiple pairs of spacers may be used, for example, two, three, or four pairs of sidewall spacers may be formed on opposite sides of the gate stack.

[0197] The S / D region 1520 may be formed within the die substrate 1502 adjacent to the gate 1522 of each transistor 1540. The S / D region 1520 may be formed using, for example, an implantation / diffusion process or an etching / deposition process. In the former process, dopants such as boron, aluminum, antimony, phosphorus, or arsenic may be ion-implanted into the die substrate 1502 to form the S / D region 1520. An annealing process to activate the dopants and further diffuse them into the die substrate 1502 may follow the ion implantation process. In the latter process, the die substrate 1502 may first be etched to form a groove at the location of the S / D region 1520. Then, an epitaxial deposition process may be performed to fill the groove with the material used to manufacture the S / D region 1520. In some embodiments, the S / D region 1520 may be manufactured using a silicon alloy such as silicon germanium or silicon carbide. In some embodiments, the epitaxially deposited silicon alloy may be in-situ doped with a dopant such as boron, arsenic, or phosphorus. In some embodiments, S / D region 1520 may be formed using one or more alternative semiconductor materials, such as germanium or a III-V material or alloy. In further embodiments, S / D region 1520 may be formed using one or more layers of metal and / or metal alloy.

[0198] The device layer 1504 may be provided with one or more interconnect layers (in Fig.15 1500) to and / or from devices (e.g., transistors 1540) in device layer 1504. For example, conductive features (e.g., gates 1522 and S / D contacts 1524) of device layer 1504 can be electrically coupled to interconnect structures 1528 of interconnect layers 1506-1510. One or more interconnect layers 1506-1510 can form a metallization stack (also referred to as an "ILD stack") 1519 of integrated circuit device 1500.

[0199] Interconnect structure 1528 may be arranged within interconnect layers 1506-1510 to transmit electrical signals according to various designs; in particular, the arrangement is not limited to Fig.15 The specific configuration of the interconnect structure 1528 shown in FIG. Fig.15 A particular number of interconnect layers 1506 - 1510 are shown in FIG. 1 , but embodiments of the present disclosure include integrated circuit devices having more or fewer interconnect layers than shown.

[0200] In some embodiments, the interconnect structure 1528 may include wires 1528a and / or vias 1528b filled with a conductive material such as metal. The wires 1528a may be arranged to transmit electrical signals in a direction substantially parallel to a plane of the surface of the die substrate 1502 on which the device layer 1504 is formed. Fig.15From the perspective of FIG. 1 , the wire 1528a can transmit electrical signals in a direction into and out of the page and / or in a direction across the page. The vias 1528b can be arranged to transmit electrical signals in a direction substantially perpendicular to the surface of the die substrate 1502 on which the device layer 1504 is formed. In some embodiments, the vias 1528b can electrically couple the wires 1528a of different interconnect layers 1506-1510 together.

[0201] The interconnect layers 1506-1510 may include a dielectric material 1526 disposed between interconnect structures 1528, such as Fig.15 1506-1510. In some embodiments, the dielectric material 1526 disposed between the interconnect structures 1528 in different ones of the interconnect layers 1506-1510 may have different compositions; in other embodiments, the composition of the dielectric material 1526 between different interconnect layers 1506-1510 may be the same. The device layer 1504 may include a dielectric material 1526 disposed between the transistor 1540 and the bottom layer of the metallization stack. The dielectric material 1526 included in the device layer 1504 may have a different composition than the dielectric material 1526 included in the interconnect layers 1506-1510; in other embodiments, the composition of the dielectric material 1526 in the device layer 1504 may be the same as the dielectric material 1526 included in any one of the interconnect layers 1506-1510.

[0202] A first interconnect layer 1506 (referred to as metal 1 or "M1") can be formed directly on the device layer 1504. In some embodiments, the first interconnect layer 1506 can include wires 1528a and / or vias 1528b, as shown. The wires 1528a of the first interconnect layer 1506 can be coupled to contacts (e.g., S / D contacts 1524) of the device layer 1504. The vias 1528b of the first interconnect layer 1506 can be coupled to the wires 1528a of the second interconnect layer 1508.

[0203] A second interconnect layer 1508 (referred to as metal 2 or "M2") may be formed directly on the first interconnect layer 1506. In some embodiments, the second interconnect layer 1508 may include vias 1528b to couple lines 1528a of the second interconnect layer 1508 with lines 1528a of the third interconnect layer 1510. Although the lines 1528a and vias 1528b are structurally outlined with lines within respective interconnect layers for clarity, in some embodiments, the lines 1528a and vias 1528b may be structurally and / or materially continuous (e.g., filled simultaneously during a dual damascene process).

[0204] A third interconnect layer 1510 (referred to as metal 3 or "M3") (and additional interconnect layers as desired) may be formed in succession on the second interconnect layer 1508 according to similar techniques and configurations as described in connection with the second interconnect layer 1508 or the first interconnect layer 1506. In some embodiments, interconnect layers that are "higher" (i.e., farther from the device layer 1504) in the metallization stack 1519 in the integrated circuit device 1500 may be thicker than interconnect layers lower in the metallization stack 1519, wherein the lines 1528a and vias 1528b in the higher interconnect layers are thicker than the lines and vias in the lower interconnect layers.

[0205] The integrated circuit device 1500 may include a solder resist material 1534 (eg, polyimide or similar material) formed on the interconnect layers 1506-1510 and one or more conductive contacts 1536. Fig.15 , the conductive contact 1536 is shown as taking the form of a bonding pad. The conductive contact 1536 may be electrically coupled to the interconnect structure 1528 and configured to transmit the electrical signal of the (one or more) transistors 1540 to an external device. For example, a solder joint may be formed on one or more conductive contacts 1536 to mechanically and / or electrically couple the integrated circuit die including the integrated circuit device 1500 to another component (e.g., a printed circuit board). The integrated circuit device 1500 may include additional or alternative structures to transmit electrical signals from the interconnect layers 1506-1510; for example, the conductive contact 1536 may include other similar features (e.g., pillars) that transmit electrical signals to external components. The conductive contact 1536 may be used as any conductive contact described throughout the present disclosure.

[0206] In some embodiments where the integrated circuit device 1500 is a double-sided die, the integrated circuit device 1500 may include another metallization stack (not shown) on the opposite side of the device layer(s) 1504. The metallization stack may include multiple interconnect layers, as discussed above with reference to the interconnect layers 1506-1510, to provide conductive paths (e.g., including conductive lines and vias) between the device layer(s) 1504 and additional conductive contacts (not shown) on the side of the integrated circuit device 1500 opposite the conductive contacts 1536. These additional conductive contacts may be used as any of the conductive contacts described throughout the present disclosure.

[0207] In other embodiments where the integrated circuit device 1500 is a double-sided die, the integrated circuit device 1500 may include one or more through-silicon vias (TSVs) through the die substrate 1502; these TSVs may contact the device layer(s) 1504 and may provide a conductive path between the device layer(s) 1504 and additional conductive contacts (not shown) on the side of the integrated circuit device 1500 opposite the conductive contacts 1536. These additional conductive contacts may be used as any conductive contacts described throughout the present disclosure. In some embodiments, the TSVs extending through the substrate may be used to transmit power and ground signals from the conductive contacts on the opposite side of the integrated circuit device 1500 from the conductive contacts 1536 to the transistors 1540 and any other components integrated into the die 1500, and the metallization stack 1519 may be used to transmit I / O signals from the conductive contacts 1536 to the transistors 1540 and any other components integrated into the die 1500.

[0208] Multiple integrated circuit devices 1500 can be stacked with one or more TSVs in each stacked device to provide a connection between one of the devices and any other device in the stack. For example, one or more high bandwidth memory (HBM) integrated circuit dies can be stacked on top of a base integrated circuit die, and the TSVs in the HBM die can provide a connection between a single HBM and the base integrated circuit die. The conductive contacts can provide additional connections between adjacent integrated circuit dies in the stack. In some embodiments, the conductive contacts can be fine pitch solder bumps (microbumps).

[0209] Fig.16 16 is a cross-sectional side view of an integrated circuit device assembly 1600 that may include any of the embodiments disclosed herein (e.g., optical and / or optoelectronic components selectively transferred from a donor wafer). In some embodiments, the integrated circuit device assembly 1600 may be a microelectronic assembly. The integrated circuit device assembly 1600 includes a plurality of components disposed on a circuit board 1602 (which may be a motherboard, a system board, a mainboard, etc.). The integrated circuit device assembly 1600 includes components disposed on a first side 1640 of the circuit board 1602 and an opposite second side 1642 of the circuit board 1602; typically, the components may be disposed on one or both of the surfaces 1640 and 1642. Any of the integrated circuit components discussed below with reference to the integrated circuit device assembly 1600 may take the form of any suitable embodiment in the embodiments of the microelectronic assembly 100 disclosed herein.

[0210] In some embodiments, circuit board 1602 may be a printed circuit board (PCB) comprising multiple metal (or interconnect) layers separated from each other by layers of dielectric material and interconnected by conductive vias. Each metal layer includes conductive traces. Any one or more metal layers may be formed in a desired circuit pattern to transmit electrical signals between components coupled to circuit board 1602 (optionally in combination with other metal layers). In other embodiments, circuit board 1602 may be a non-PCB substrate. Fig.16 The integrated circuit device assembly 1600 shown in FIG. 1 includes a package-on-interposer structure 1636 coupled to a first side 1640 of a circuit board 1602 via a coupling component 1616. The coupling component 1616 can electrically and mechanically couple the package-on-interposer structure 1636 to the circuit board 1602 and can include solder balls (e.g., Fig.16 ), pins (e.g., as part of a pin grid array (PGA)), contacts (e.g., as part of a land grid array (LGA)), male and female portions of a socket, adhesives, underfill materials, and / or any other suitable electrical and / or mechanical coupling structures. Coupling component 1616 may be used as the coupling component shown or described for any of the substrate assemblies or substrate assembly components described herein, where appropriate.

[0211] The package-on-interposer structure 1636 may include an integrated circuit component 1620 coupled to the interposer 1604 via a coupling component 1618. The coupling component 1618 may take any suitable form for the application, such as those discussed above with reference to the coupling component 1616. Fig.16 A single integrated circuit component 1620 is shown in FIG. 1 , but multiple integrated circuit components may be coupled to interposer 1604 ; indeed, additional interposers may be coupled to interposer 1604 . Interposer 1604 may provide an intermediate substrate for bridging circuit board 1602 and integrated circuit components 1620 .

[0212] Integrated circuit component 1620 may be a device including one or more integrated circuit dies (eg, Fig.14 The tube core 1402, Fig.15The integrated circuit device 1500 of the present invention is a packaged or unpackaged integrated circuit product of an integrated circuit device 1500) and / or one or more other suitable components. The packaged integrated circuit component includes one or more integrated circuit dies mounted on a packaging substrate, wherein the integrated circuit die and the packaging substrate are encapsulated in a housing material such as metal, plastic, glass, or ceramic. In one example of an unpackaged integrated circuit component 1620, a single monolithic integrated circuit die includes solder bumps attached to contacts on the die. The solder bumps allow the die to be directly attached to the interposer 1604. The integrated circuit component 1620 may include one or more computing system components, such as one or more processor units (e.g., a system on a chip (SoC), a processor core, a graphics processor unit (GPU), an accelerator, a chipset processor), an I / O controller, a memory, or a network interface controller. In some embodiments, the integrated circuit component 1620 may include one or more additional active or passive devices, such as capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, electrostatic discharge (ESD) devices, and memory devices.

[0213] In embodiments where integrated circuit component 1620 includes multiple integrated circuit dies, the dies may be of the same type (a homogeneous multi-die integrated circuit component) or two or more different types (a heterogeneous multi-die integrated circuit component). A multi-die integrated circuit component may be referred to as a multi-chip package (MCP) or a multi-chip module (MCM).

[0214] In addition to including one or more processor units, integrated circuit component 1620 may include additional components such as embedded DRAM, stacked high bandwidth memory (HBM), shared cache memory, input / output (I / O) controller, or memory controller. Any of these additional components may be located on the same integrated circuit die as the processor unit, or on one or more integrated circuit dies separate from the integrated circuit die that includes the processor unit. These separate integrated circuit dies may be referred to as "chiplets." In embodiments where the integrated circuit component includes multiple integrated circuit dies, the interconnections between the dies may be provided by a packaging substrate, one or more silicon interposers, one or more silicon bridges (such as silicon interposers) embedded in the packaging substrate, or a plurality of silicon interposers. It is provided by an embedded multi-die interconnect bridge (EMIB)) or a combination thereof.

[0215] Typically, interposer 1604 can extend connections to a wider pitch or reroute connections to different connections. For example, interposer 1604 can couple integrated circuit component 1620 to a set of ball grid array (BGA) conductive contacts of coupling component 1616 for coupling to circuit board 1602. Fig.16In the illustrated embodiment, integrated circuit component 1620 and circuit board 1602 are attached to opposite sides of interposer 1604; in other embodiments, integrated circuit component 1620 and circuit board 1602 may be attached to the same side of interposer 1604. In some embodiments, three or more components may be interconnected through interposer 1604.

[0216] In some embodiments, the interposer 1604 may be formed as a PCB, including multiple metal layers separated from each other by dielectric material layers and interconnected by conductive vias. In some embodiments, the interposer 1604 may be formed of epoxy, glass fiber reinforced epoxy, epoxy with inorganic fillers, ceramic materials, or polymer materials such as polyimide. In some embodiments, the interposer 1604 may be formed of alternating rigid or flexible materials, which may include the same materials as those described above for semiconductor substrates, such as silicon, germanium, and other III-V and IV materials. The interposer 1604 may include metal interconnects 1608 and vias 1610, including but not limited to through-holes 1610-1 (which extend from the first side 1650 of the interposer 1604 to the second side 1654 of the interposer 1604), blind vias 1610-2 (which extend from the first side 1650 or the second side 1654 of the interposer 1604 to the internal metal layer), and buried vias 1610-3 (which connect the internal metal layer).

[0217] In some embodiments, interposer 1604 may include a silicon interposer. Through-silicon vias (TSVs) extending through the silicon interposer may connect connections on a first side of the silicon interposer to an opposite second side of the silicon interposer. In some embodiments, interposer 1604 including a silicon interposer may further include one or more routing layers to route connections on a first side of interposer 1604 to an opposite second side of interposer 1604.

[0218] Interposer 1604 may further include embedded devices 1614, including both passive devices and active devices. These devices may include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, electrostatic discharge (ESD) devices, and memory devices. More complex devices such as radio frequency devices, power amplifiers, power management devices, antennas, arrays, sensors, and micro-electromechanical systems (MEMS) devices may also be formed on interposer 1604. Interposer package structure 1636 may take the form of any interposer package structure known in the art. In some embodiments, the interposer may include a non-printed circuit board.

[0219] Integrated circuit device assembly 1600 may include integrated circuit component 1624 coupled to first side 1640 of circuit board 1602 via coupling component 1622. Coupling component 1622 may take the form of any of the embodiments discussed above with reference to coupling component 1616, and integrated circuit component 1624 may take the form of any of the embodiments discussed above with reference to integrated circuit component 1620.

[0220] Fig.16 The integrated circuit device assembly 1600 shown in the figure includes a package-on-package structure 1634 coupled to the second side 1642 of the circuit board 1602 by a coupling component 1628. The package-on-package structure 1634 may include an integrated circuit component 1626 and an integrated circuit component 1632 coupled together by a coupling component 1630, such that the integrated circuit component 1626 is disposed between the circuit board 1602 and the integrated circuit component 1632. The coupling components 1628 and 1630 may take the form of any embodiment of the coupling component 1616 discussed above, and the integrated circuit components 1626 and 1632 may take the form of any embodiment of the integrated circuit component 1620 discussed above. The package-on-package structure 1634 may be configured according to any package-on-package structure known in the art.

[0221] Fig.17 1 is a block diagram of an example electrical device 1700 that may include one or more of the embodiments disclosed herein. For example, any suitable component in the components of the electrical device 1700 may include one or more selectively transferred optical and / or optoelectronic components, integrated circuit dies, integrated circuit device assembly 1600, integrated circuit component 1620, integrated circuit device 1500, or integrated circuit die 1402 disclosed herein. Fig.17 1700, but any one or more of these components may be omitted or duplicated as appropriate for the application. In some embodiments, some or all of the components included in the electrical device 1700 may be attached to one or more motherboards, mainboards, or system boards. In some embodiments, one or more of these components are manufactured on a single system-on-chip (SoC) die.

[0222] Additionally, in various embodiments, the electrical device 1700 may not include Fig.17, but the electrical device 1700 may include interface circuitry for coupling to one or more of the components. For example, the electrical device 1700 may not include the display device 1706, but may include display device interface circuitry (e.g., connectors and driver circuitry) to which the display device 1706 may be coupled. In another set of examples, the electrical device 1700 may not include the audio input device 1724 or the audio output device 1708, but may include audio input or output device interface circuitry (e.g., connectors and supporting circuitry) to which the audio input device 1724 or the audio output device 1708 may be coupled.

[0223] The electrical device 1700 may include one or more processor units 1702 (e.g., one or more processor units). As used herein, the term "processor unit," "processing unit," or "processor" may refer to any device or part of a device that processes electronic data from registers and / or memory to convert the electronic data into other electronic data that can be stored in registers and / or memory. The processor unit 1702 may include one or more digital signal processors (DSPs), application specific integrated circuits (ASICs), central processing units (CPUs), graphics processing units (GPUs), general purpose GPUs (GPGPUs), accelerated processing units (APUs), field programmable gate arrays (FPGAs), neural network processing units (NPUs), data processor units (DPUs), accelerators (e.g., graphics accelerators, compression accelerators, artificial intelligence accelerators), controller cryptographic processors (special processors that execute encryption algorithms in hardware), server processors, controllers, or any other suitable type of processor unit. In this way, the processor unit may be referred to as an XPU (or xPU).

[0224] The electrical device 1700 may include a memory 1704, which itself may include one or more memory devices, such as volatile memory (e.g., dynamic random access memory (DRAM), static random access memory (SRAM)), non-volatile memory (e.g., read-only memory (ROM), flash memory, chalcogenide-based phase change non-voltage memory), solid-state memory, and / or a hard disk drive. In some embodiments, the memory 1704 may include memory located on the same integrated circuit die as the processor unit 1702. The memory may be used as a cache memory (e.g., level 1 (L1), level 2 (L2), level 3 (L3), level 4 (L4), last level cache (LLC)), and may include embedded dynamic random access memory (eDRAM) or spin-transfer torque magnetic random access memory (STT-MRAM).

[0225] In some embodiments, the electrical device 1700 may include one or more processor units 1702 that are heterogeneous or asymmetric with another processor unit 1702 in the electrical device 1700. Various differences may exist between the processing units 1702 in the system in terms of a range of merit metrics including architectural, microarchitectural, thermal, power consumption characteristics, etc. These differences may effectively manifest themselves as being asymmetric and heterogeneous among the processor units 1702 in the electrical device 1700.

[0226] In some embodiments, the electrical device 1700 may include a communication component 1712 (e.g., one or more communication components). For example, the communication component 1712 may manage wireless communications for transmitting data to and from the electrical device 1700. The term "wireless" and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communication channels, etc. that can communicate data through a non-solid medium using modulated electromagnetic radiation. The term "wireless" does not mean that the associated devices do not contain any wires, although in some embodiments they may not.

[0227] The communication component 1712 can implement any of a variety of wireless standards or protocols, including but not limited to Institute of Electrical and Electronics Engineers (IEEE) standards, including Wi-Fi (IEEE802.11 series), IEEE 802.16 standards (e.g., IEEE802.16-1505 revision), Long Term Evolution (LTE) project, and any revisions, updates and / or amendments (e.g., Advanced LTE project, Ultra Mobile Broadband (UMB) project (also known as "3GPP2"), etc.). Broadband wireless access (BWA) networks compatible with IEEE 802.16 are generally referred to as WiMAX networks, which is an acronym standing for Worldwide Interoperability for Microwave Access, which is a certification mark for products that have passed IEEE 802.16 standard conformance and interoperability testing. The communication component 1712 can operate according to a Global System for Mobile Communications (GSM), General Packet Radio Service (GPRS), Universal Mobile Telecommunications System (UMTS), High Speed ​​Packet Access (HSPA), Evolved HSPA (E-HSPA), or LTE network. The communication component 1712 can operate according to Enhanced Data GSM Evolution (EDGE), GSM EDGE Radio Access Network (GERAN), Universal Terrestrial Radio Access Network (UTRAN), or Evolved UTRAN (E-UTRAN). The communication component 1712 can operate according to Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Digital Enhanced Cordless Telecommunications (DECT), Evolution Data Optimized (EV-DO) and its derivatives, and any other wireless protocol designated as 3G, 4G, 5G and later. In other embodiments, the communication component 1712 can operate according to other wireless protocols. The electrical device 1700 may include an antenna 1722 to facilitate wireless communication and / or receive other wireless communications (e.g., AM or FM radio transmissions).

[0228] In some embodiments, the communication component 1712 can manage wired communications, such as electrical, optical, or any other suitable communication protocol (e.g., IEEE 802.3 Ethernet standard). As described above, the communication component 1712 can include multiple communication components. For example, the first communication component 1712 can be dedicated to shorter-range wireless communications such as Wi-Fi or Bluetooth, and the second communication component 1712 can be dedicated to longer-range wireless communications such as global positioning systems (GPS), EDGE, GPRS, CDMA, WiMAX, LTE, EV-DO or others. In some embodiments, the first communication component 1712 can be dedicated to wireless communications, and the second communication component 1712 can be dedicated to wired communications.

[0229] The electrical device 1700 may include a battery / power circuit system 1714. The battery / power circuit system 1714 may include one or more energy storage devices (e.g., batteries or capacitors) and / or circuit systems for coupling components of the electrical device 1700 to an energy source separate from the electrical device 1700 (e.g., AC line power).

[0230] The electrical device 1700 may include a display device 1706 (or corresponding interface circuitry, as discussed above). The display device 1706 may include one or more embedded or wired or wirelessly connected external visual indicators, such as a head-up display, a computer monitor, a projector, a touch screen display, a liquid crystal display (LCD), a light emitting diode display, or a flat panel display.

[0231] Electrical device 1700 may include an audio output device 1708 (or corresponding interface circuitry, as discussed above). Audio output device 1708 may include any embedded or wired or wirelessly connected external device that generates an audible indicator, such as a speaker, headphones, or earbuds.

[0232] The electrical device 1700 may include an audio input device 1724 (or corresponding interface circuitry, as discussed above). The audio input device 1724 may include any embedded or wired or wirelessly connected device that produces a signal representing sound, such as a microphone, a microphone array, or a digital musical instrument (e.g., a musical instrument with a musical instrument digital interface (MIDI) output). The electrical device 1700 may include a global navigation satellite system (GNSS) device 1718 (or corresponding interface circuitry, as discussed above), such as a global positioning system (GPS) device. The GNSS device 1718 may communicate with a satellite-based system and may determine the geographic location of the electrical device 1700 based on information received from one or more GNSS satellites, as is known in the art.

[0233] The electrical device 1700 may include other output device(s) 1710 (or corresponding interface circuitry, as discussed above). Examples of other output device(s) 1710 may include an audio codec, a video codec, a printer, a wired or wireless transmitter for providing information to other devices, or an additional storage device.

[0234] The electrical device 1700 may include other input device(s) 1720 (or corresponding interface circuitry, as discussed above). Examples of other input device(s) 1720 may include an accelerometer, a gyroscope, a compass, an image capture device (e.g., a monoscopic or stereo camera), a trackball, a trackpad, a touchpad, a keyboard, a cursor control device such as a mouse, a stylus, a touch screen, a proximity sensor, a microphone, a barcode reader, a quick response (QR) code reader, an electrocardiogram (ECG) sensor, a PPG (photoplethysmogram) sensor, a galvanic skin response sensor, any other sensor, or a radio frequency identification (RFID) reader.

[0235] The electrical device 1700 may have any desired form factor, such as a handheld or mobile electrical device (e.g., a cellular phone, a smart phone, a mobile Internet device, a music player, a tablet computer, a laptop computer, a 2-in-1 convertible computer, a portable all-in-one computer, a netbook computer, an ultrabook computer, a personal digital assistant (PDA), an ultra-mobile personal computer, a portable game console, etc.), a desktop electrical device, a server, a rack-level computing solution (e.g., a blade, tray or sled computing system), a workstation or other networked computing component, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a fixed game console, a smart TV, a vehicle control unit, a digital camera, a digital video recorder, a wearable electrical device, or an embedded computing system (e.g., a computing system as part of a vehicle, a smart home appliance, a consumer electronic product or equipment, a manufacturing equipment). In some embodiments, the electrical device 1700 may be any other electronic device that processes data. In some embodiments, the electrical device 1700 may include multiple discrete physical components. Given the range of devices that the electrical device 1700 may be as indicated in various embodiments, in some embodiments, the electrical device 1700 may be referred to as a computing device or a computing system.

[0236] Example

[0237] Provided below are illustrative examples of the technology described throughout the present disclosure. Embodiments of these technologies may include any one or more and any combination of the examples described below. In some embodiments, at least one of the systems or components set forth in one or more of the foregoing figures may be configured to perform one or more operations, techniques, processes and / or methods set forth in the following examples.

[0238] Example 1 includes a microelectronic assembly comprising: one or more optical waveguides; a photodetector for converting an optical signal received on the one or more optical waveguides into a current; a transimpedance amplifier (TIA) for converting the current into a voltage; and an electronic integrated circuit (EIC) for outputting a digital signal based on the voltage, wherein the EIC and the TIA are on separate integrated circuit (IC) dies.

[0239] Example 2 includes the microelectronic assembly of Example 1, further comprising a mesa structure below the TIA, wherein the mesa structure has a similar footprint as the TIA.

[0240] Example 3 includes the microelectronic assembly of Example 2, wherein: the mesa structure includes at least one of a dielectric material or a metal; and the TIA is bonded to the mesa structure via a dielectric bond, a metal bond, or a hybrid dielectric and metal bond.

[0241] Example 4 includes the microelectronic assembly of any of Examples 1-3, further comprising a mesa structure below the photodetector, wherein the mesa structure has a similar footprint as the photodetector.

[0242] Example 5 includes the microelectronic assembly of any of Examples 1-4, wherein: the TIA is adjacent to the photodetector; or the TIA is above the photodetector.

[0243] Example 6 includes the microelectronic assembly of any of Examples 1-5, wherein: the TIA has a thickness of 5 micrometers (μm) or less; or the TIA has a thickness of less than 1 mm. 2 (mm 2 ) area.

[0244] Example 7 includes the microelectronic assembly of any of Examples 1-6, further comprising: a modulator for modulating an optical signal for transmission on the one or more optical waveguides; and a driver for controlling the modulator, wherein the driver and the EIC are on separate IC dies.

[0245] Example 8 includes the microelectronic assembly of Example 7, further comprising a mesa structure below the driver, wherein the mesa structure has a similar footprint as the driver.

[0246] Example 9 includes a microelectronic assembly of any of Examples 1-8, wherein the EIC includes one or more of: a carrier phase recovery circuit system; a clock and data recovery circuit system; an error correction circuit system; a serializer and deserializer circuit system; an equalizer circuit system; a sampler circuit system; a mixer circuit system; an amplifier circuit system; a temperature control circuit system; or an analog-to-digital and digital-to-analog conversion circuit system.

[0247] Example 10 includes the microelectronic assembly of any of Examples 1-9, further comprising: a processing unit; and an optical transceiver that sends and receives optical signals on behalf of the processing unit, wherein the optical transceiver includes the one or more optical waveguides, the photodetector, the TIA, and the EIC.

[0248] Example 11 includes an electronic device comprising: a plurality of integrated circuit (IC) components, wherein the plurality of IC components include: a plurality of optical waveguides; a ring resonator for modulating an optical signal for transmission on one or more of the optical waveguides; a driver for controlling the ring resonator; a photodetector for converting an optical signal received on one or more of the optical waveguides into a current; and a transimpedance amplifier (TIA) for converting the current into a voltage; and one or more mesa structures, the one or more mesa structures being below one or more of the plurality of IC components, wherein each mesa structure is below a corresponding one of the plurality of IC components and has a similar footprint as the corresponding IC component.

[0249] Example 12 includes the electronic device of Example 11, wherein: each mesa structure includes at least one of a dielectric material or a metal; and each IC component is bonded to each mesa structure via a dielectric bond, a metal bond, or a hybrid dielectric and metal bond.

[0250] Example 13 includes the electronic device of any of Examples 11-12, wherein: the plurality of IC components further include an electronic integrated circuit (EIC) to output a digital signal based on the voltage; and the EIC, the TIA, and the driver are on separate IC dies.

[0251] Example 14 includes the electronic device of any of Examples 11-13, wherein the electronic device is an optical transceiver.

[0252] Example 15 includes the electronic device of any of Examples 11-13, wherein the plurality of IC components further comprises a processing unit, wherein the processing unit comprises a central processing unit, a graphics processing unit, an application specific integrated circuit, or a field programmable gate array.

[0253] Example 16 includes a method comprising: receiving a first substrate, wherein the first substrate includes a release layer and an integrated circuit (IC) component layer above the release layer, wherein the IC component layer includes one or more optical waveguides, ring resonators, drivers, photodetectors, transimpedance amplifiers, or electronic integrated circuits; receiving a second substrate, wherein the second substrate includes one or more bonding areas; partially bonding the first substrate to the second substrate, wherein one or more IC components on the first substrate are bonded to the one or more bonding areas on the second substrate, wherein the one or more IC components are from the IC component layer; and separating the first substrate from the second substrate, wherein the one or more IC components are separated from the first substrate and remain on the second substrate.

[0254] Example 17 includes the method of Example 16, further comprising, before separating the first substrate from the second substrate: weakening the release layer using a laser; or removing a portion of the release layer using a laser.

[0255] Example 18 includes the method of any of Examples 16-17, wherein the release layer comprises at least one of a metal layer or a dielectric layer.

[0256] Example 19 includes the method of any one of Examples 16-18, wherein receiving the first substrate includes forming the first substrate, wherein forming the first substrate includes: receiving a base substrate; forming the release layer above the base substrate; forming or transferring the IC component layer above the release layer; and partially singulating the IC component layer.

[0257] Example 20 includes the method of any of Examples 16-19, wherein the one or more adhesion regions include one or more raised structures, wherein the one or more raised structures include at least one of a dielectric material or a metal.

[0258] Although the concepts of the present disclosure are susceptible to various modifications and alternative forms, specific embodiments thereof have been shown by way of example in the drawings and described in detail herein. However, it should be understood that the concepts of the present disclosure are not intended to be limited to the specific forms disclosed, but on the contrary, all modifications, equivalent transformations and alternatives consistent with the present disclosure and the appended claims are intended to be covered.

[0259] In the accompanying drawings, some structural or method features may be shown in a specific arrangement and / or order. However, it should be understood that such a specific arrangement and / or order may not be required. On the contrary, in some embodiments, these features may be arranged in a manner and / or order different from that shown in the illustrative drawings. Additionally, the inclusion of structural or method features in a particular drawing does not mean that such features are required in all embodiments, and in some embodiments, such features may not be included or may be combined with other features. In addition, it should be understood that the various embodiments shown in the drawings are illustrative representations and are not necessarily drawn to scale.

[0260] In addition, the illustrations and / or descriptions of various embodiments may be simplified or approximated for ease of understanding, and therefore, they may not necessarily reflect the level of accuracy or variations that may exist in actual embodiments. For example, while some of the drawings generally indicate straight lines, right angles, and smooth surfaces, actual implementations of the disclosed embodiments may have less than perfect straight lines and right angles, and some features may have surface topography or otherwise be non-smooth, given the real-world limitations of manufacturing processes. Similarly, the illustrations and / or descriptions of how components are arranged may be simplified or approximated for ease of understanding, and may vary within certain error ranges in actual embodiments (e.g., due to manufacturing processes, etc.).

[0261] Unless otherwise stated, the use of ordinal adjectives "first," "second," and "third," etc. to describe common objects merely indicates different instances of the similar objects being referred to and is not intended to imply that the objects so described must be in a given order temporally, spatially, sequentially, or in any other manner.

[0262] The terms "substantially," "close," "approximately," "near," and "about" generally refer to within + / - 10% of a target value (unless otherwise indicated). Similarly, terms describing spatial relationships, such as "perpendicular," "orthogonal," or "coplanar," may refer to being substantially within the described spatial relationship (e.g., within + / - 10 degrees of orthogonality).

[0263] Certain terms may also be used in the foregoing description for reference purposes only, and are therefore not intended to be limiting. For example, terms such as "upper," "lower," "above," "below," "bottom," and "top" refer to directions in the drawings to which reference is made. Terms such as "front," "rear," "back," and "side" describe the orientation and / or position of portions of a component within a consistent but arbitrary reference system, which becomes clear by reference to the text and associated drawings describing the component in question. Such terminology may include the words specifically mentioned above, derivatives thereof, and words of similar meaning.

[0264] As used herein, the terms "over", "under", "between", "adjacent", "to", and "on" may refer to the relative position of a layer or component with respect to other layers or components. For example, a layer that is "over", "under", or "on", "adjacent", or joined "to" another layer may be directly in contact with the other layer, or may have one or more intervening layers. A layer that is "between" layers may be directly in contact with the layers, or may have one or more intervening layers.

[0265] The meanings of "a", "an" and "the" include plural references. The meaning of "in" includes "in" and "on".

[0266] For purposes of this disclosure, the phrases "A and / or B" and "A or B" mean (A), (B), or (A and B). For purposes of this disclosure, the phrases "A, B, and / or C" mean (A), (B), (C), (A and B), (A and C), (B and C), or (A, B, and C).

[0267] The views labeled "Section," "Profile," and "Plan" correspond to orthogonal planes within a Cartesian coordinate system. Thus, section and profile views are taken in the xz plane, and plan views are taken in the xy plane. Typically, a profile view in the xz plane is a section view.

[0268] The term "package" generally refers to a self-contained carrier of one or more dies, wherein the dies are attached to or embedded in a package substrate and may be packaged for protection, with integrated or wire-bonded interconnects between the dies, and leads, pins, or bumps on the external portion of the package substrate. A package may contain a single die or multiple dies that provide the corresponding functions. The package may be mounted on a printed circuit board for interconnection with other packaged integrated circuits and discrete components to form a larger circuit.

[0269] The term "core" generally refers to a substrate of an integrated circuit package including non-flexible rigid materials built on a board, card or wafer. Typically, a small printed circuit board is used as a core, on which the integrated circuit devices and discrete passive components can be soldered. Typically, the core has vias extending from one side to the other, allowing the circuit system on one side of the core to be directly coupled to the circuit system on the opposite side of the core. The core can also be used as a platform for building layers of conductors and dielectric materials.

[0270] The term "coreless" generally refers to the substrate of the integrated circuit package not having a core. The lack of a core can allow for a higher density packaging architecture because the through vias can have relatively large size and pitch compared to high density interconnects.

[0271] The term "pad side" generally refers to the side of the substrate of an integrated circuit package that is closest to the attachment plane of a printed circuit board, motherboard, or other package. This is in contrast to the term "die side", which generally refers to the side of the substrate of an integrated circuit package to which one or more dies are attached.

[0272] The terms "dielectric" and "dielectric material" generally refer to any type or amount of non-conductive material. In some cases, dielectric materials can be used to form the structure of a package substrate. For example, dielectric materials can be incorporated into an integrated circuit package as a laminate film layer or as a resin molded on an integrated circuit die mounted on a substrate.

[0273] The term "metallization" generally refers to a metal layer formed on, over, and / or through a dielectric material of a package substrate. The metal layer is typically patterned to form metal structures, such as traces and bond pads. The metallization of a package substrate may be limited to a single layer or multiple layers separated by dielectric layers.

[0274] The term "bonding pad" generally refers to a metallization structure that terminates integrated traces and vias in integrated circuit packages and dies. The term "solder pad" may occasionally replace "bonding pad" and may have the same or similar meaning.

[0275] The term "bump" generally refers to a conductive layer or structure formed on a bonding pad, which is usually made of solder or metal and has a rounded or curved shape, hence the term "bump".

[0276] The term "substrate" generally refers to a planar platform including dielectric and / or metallization structures. A substrate can mechanically support and electrically couple one or more IC dies on a single platform, wherein one or more IC dies are encapsulated by a moldable dielectric material. A substrate can include bumps or pads as bonding interconnects on one or both sides. For example, one side of a substrate (commonly referred to as the "die side") may include bumps or pads for chip or die bonding. The opposite side of the substrate (commonly referred to as the "pad side") may include bumps or pads for bonding the package to a printed circuit board.

[0277] The term "assembly" generally refers to the grouping of components into a single functional unit. For example, certain components may be permanently joined together, integrated together, and / or mechanically assembled (e.g., where the components may be removable) into a functional unit.

[0278] The terms "coupled" or "connected" mean a direct or indirect connection, such as a direct electrical, mechanical, magnetic or fluid connection between the objects that are connected, or an indirect connection through one or more passive or active intermediary devices.

[0279] The term "circuit" or "module" may refer to one or more passive and / or active components arranged to cooperate with each other to provide a desired functionality. The term "signal" may refer to at least one current signal, voltage signal, magnetic signal, or data / clock signal.

Claims

1. A microelectronic assembly comprising: one or more waveguides; a photodetector for converting an optical signal received on the one or more waveguides into an electrical current; a transimpedance amplifier (TIA) for converting the current into a voltage; and An electronic integrated circuit (EIC) is configured to output a digital signal based on the voltage, wherein the EIC and the TIA are on separate integrated circuit (IC) dies.

2. The microelectronic assembly of claim 1 , further comprising a mesa structure below the TIA, wherein The mesa structure has a similar footprint as the TIA.

3. The microelectronic assembly of claim 2, wherein: The mesa structure comprises at least one of a dielectric material or a metal; and The TIA is bonded to the mesa structure via dielectric bonding, metal bonding, or hybrid dielectric and metal bonding.

4. The microelectronic assembly of claim 1 further comprising a mesa structure below the photodetector, wherein: The mesa structure has a similar footprint as the photodetector.

5. The microelectronic assembly of claim 1 , further comprising: a modulator for modulating an optical signal for transmission on the one or more waveguides; as well as A driver is provided for controlling the modulator, wherein the driver and the EIC are on separate IC dies.

6. The microelectronic assembly of claim 5 further comprising a mesa structure below the driver, wherein: The mesa structure has a similar footprint as the driver.

7. A microelectronic assembly according to any one of claims 1 to 6, wherein: The TIA is adjacent to the photodetector; or The TIA is above the photodetector.

8. A microelectronic assembly according to any one of claims 1 to 6, wherein: The TIA has a thickness of 5 micrometers (μm) or less; or The TIA has a size less than 1 mm 2 (mm 2 ) area.

9. The microelectronic assembly according to any one of claims 1 to 6, wherein: The EIC includes one or more of the following: Carrier phase recovery circuit system; Clock and data recovery circuitry; Error correction circuit system; Serializer and deserializer circuitry; Equalizer circuit system; Sampler circuitry; or Mixer circuit system.

10. The microelectronic assembly according to any one of claims 1 to 6, further comprising: Processing unit; as well as An optical transceiver that sends and receives optical signals on behalf of the processing unit, wherein the optical transceiver includes the one or more waveguides, the photodetector, the TIA, and the EIC.

11. An electronic device, comprising: a plurality of integrated circuit (IC) components, wherein the plurality of IC components comprises: Multiple waveguides; a ring resonator for modulating an optical signal for transmission on one or more of the waveguides; A driver, the driver is used to control the ring resonator; a photodetector for converting an optical signal received on one or more of the waveguides into an electric current; and a transimpedance amplifier (TIA) for converting the current into a voltage; and one or more mesa structures, the one or more mesa structures being below one or more IC components among the plurality of IC components, wherein each mesa structure is below a corresponding IC component among the plurality of IC components and has a similar footprint as the corresponding IC component.

12. The electronic device according to claim 11, wherein: Each mesa structure comprises at least one of a dielectric material or a metal; and The various IC components are bonded to the various mesa structures via dielectric bonding, metal bonding, or hybrid dielectric and metal bonding.

13. The electronic device according to any one of claims 11 to 12, wherein: The plurality of IC components further include an electronic integrated circuit (EIC) to output a digital signal based on the voltage; and The EIC, the TIA, and the driver are on separate IC dies.

14. The electronic device according to any one of claims 11 to 12, wherein: The electronic device is an optical transceiver.

15. The electronic device according to any one of claims 11 to 12, wherein: The plurality of IC components further include a processing unit, wherein the processing unit includes a central processing unit, a graphics processing unit, an application specific integrated circuit, or a field programmable gate array.

16. A method comprising: Receiving a first substrate, wherein the first substrate comprises a release layer and an integrated circuit (IC) component layer over the release layer, wherein the IC component layer comprises one or more waveguides, ring resonators, drivers, photodetectors, transimpedance amplifiers, or electronic integrated circuits; receiving a second substrate, wherein the second substrate comprises one or more bonding structures; partially bonding the first substrate to the second substrate, wherein one or more IC components on the first substrate are bonded to the one or more bonding structures on the second substrate, wherein the one or more IC components are from the IC component layer; and The first substrate is separated from the second substrate, wherein the one or more IC components are separated from the first substrate and remain on the second substrate.

17. The method according to claim 16, wherein: The release layer includes at least one of a metal layer or a dielectric layer.

18. The method according to claim 16, wherein: The one or more bonding structures include at least one of a dielectric material or a metal.

19. The method according to any one of claims 16 to 18, further comprising, before separating the first substrate from the second substrate: Weakening the release layer using a laser; or Portions of the release layer are removed using a laser.

20. The method according to any one of claims 16 to 18, wherein: Receiving the first substrate includes forming the first substrate, wherein forming the first substrate includes: receiving a base substrate; forming the release layer over the base substrate; forming or transferring the IC component layer over the release layer; and The IC component layer is partially singulated.

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