A secondary electron emission structure and multiplier for weak ion signal amplification based on silicon wafer

Abstract

The present invention belongs to the technical field of magnetically selected cesium atomic clocks, and specifically relates to a silicon wafer-based secondary electron emission structure and multiplier for amplifying weak ion signals. The secondary electron emission structure comprises a rectangular silicon wafer, electrodes, and an accelerating grid. The electrodes are fixed to both ends of the rectangular silicon wafer, and the accelerating grid is connected to the electrodes. The rectangular silicon wafer with the electrodes at both ends and the accelerating grid form a multiplication stage. The rectangular silicon wafer is coated with a composite secondary electron emission film, which is activated before use.

Description

Technical Field

[0001] The present invention belongs to the technical field of magnetically selected cesium atomic clocks, and in particular relates to a secondary electron emission structure and a multiplier for amplifying weak ion signals based on a silicon wafer. Background Art

[0002] Magnetically selected cesium microwave clocks are already widely used as primary frequency standards for commercial applications, including timekeeping, frequency metrology, navigation, communications, and scientific research. Further reducing the cost of magnetically selected cesium atomic clocks and improving their performance, lifespan, and reliability are key technical approaches to achieving their wider and more sustainable application. The box-grid multiplier, a key component of magnetically selected cesium atomic clocks, significantly impacts their cost, performance, and lifespan.

[0003] The box-grid multiplier used in magnetically selected cesium atomic clocks typically consists of a circular arc-shaped dynode with a grid, a collector, a ceramic plate, and a voltage-divider resistor. The secondary electron-emitting thin film is primarily made of MgO, and the current mainstream methods are silver-magnesium alloy oxidation and magnetron sputtering (Li Jie, Research on Performance Enhancement Technology for Separated-Dynode Electron Multipliers, Vacuum Electronics Technology, 2023; Wang Haodong, A Method for Preparing Magnesium Oxide Secondary Emitters). Currently, existing MgO box-grid multipliers suffer from complex structures and manufacturing processes, as well as high costs. Patents CN114395747B, "A high-emission-coefficient, bombardment-resistant secondary electron emission film structure and preparation method," CN117524829A, "A high-gain electron multiplier and its manufacturing method," CN116978769A, "A three-dimensionally arranged multi-stage dynode multiplication structure and an electron multiplier containing the same," and CN 114446762A, "A long-life electron multiplier for cesium clocks," illustrate the complexity of MgO multilayer films. Difficulties include multilayer film design, mixed oxide and metal coating, complex dynode structure, voltage divider resistor welding, and lengthy process flows.

[0004] For example, existing MgO box-grid multipliers require minimal assembly time after magnetron sputtering coating. Patent CN109243959B, "A Structure and Assembly Method for an Electron Multiplier," utilizes planar voltage-dividing resistors and planar transition electrodes to reduce welding workload. Patent CN112185784B, "An Assembly Tool and Assembly Method for a Dynode of an Electron Multiplier," designs the critical dynode assembly tool. Patent CN110828259B, "A Tool for Rapid and Accurate Assembly of an Electron Multiplier," designs the assembly tool for the entire structure. Furthermore, MgO box-grid multipliers are primarily manufactured before use, making mass production unsuitable for cost reduction. For example, patent CN115783519A, "An Electron Multiplier Storage Device and Storage Method," demonstrates the difference in secondary electron emission coefficients between MgO films stored in the atmosphere, stored in a storage device, and freshly prepared. The best performance is still achieved with freshly prepared MgO films. Summary of the Invention

[0005] The present application provides a secondary electron emission structure for amplifying weak ion signals based on a silicon wafer and an electron multiplier thereof, which can solve the problems of complex structure and process and high cost of the multiplier used in magnetically selected cesium atomic clocks.

[0006] The technical solutions for implementing the present invention are as follows:

[0007] In the first aspect, an embodiment of the present application provides a secondary electron emission structure for amplifying weak ion signals based on a silicon wafer, comprising a rectangular silicon wafer, an electrode sheet and an acceleration gate, wherein the electrode sheets are fixed at both ends of the rectangular silicon wafer, and the acceleration gate is connected to the electrode sheets; the rectangular silicon wafer with electrode sheets at both ends and the acceleration gate constitute a multiplication stage; wherein: the surface of the rectangular silicon wafer is coated with a composite secondary electron emission film, and the composite secondary electron emission film is activated before use.

[0008] Furthermore, the resistivity of the rectangular silicon wafer of the present invention is 2.3 x 10 5 The resistance between the electrodes at both ends is about 0.5MΩ~10MΩ.

[0009] Furthermore, one surface of the rectangular silicon wafer of the present invention is pre-polished to a roughness better than 2 nm and is used for coating a composite secondary electron emission thin film.

[0010] Furthermore, before the composite secondary electron emission film is plated on the rectangular silicon wafer of the present invention, polyimide films are pasted to the two ends of the fixed electrode sheet, and the polyimide films are torn off after the coating is completed.

[0011] Furthermore, the rectangular silicon wafer described in the present invention is coated with a full-metal composite secondary electron emission film on the polished surface, which is composed of a first layer of Mg film, a second layer of Ag film or Au film, and a third layer of Mg film from the silicon crystal surface; the thickness of the first layer of Mg film of the composite secondary electron emission film is 20 to 40 nm, the thickness of the second layer of Ag film or Au film is 20 to 30 nm, and the thickness of the third layer of Mg film is 20 to 40 nm.

[0012] Furthermore, before coating the composite secondary electron emission film on the rectangular silicon wafer of the present invention, polyimide film is pasted on the two ends of the electrode sheet where the electrode sheet needs to be fixed. After coating, the polyimide film is torn off to ensure that there is no composite secondary electron emission film on the electrode sheet installation surface.

[0013] Furthermore, the composite secondary electron emission film of the present invention is activated before use, that is, maintained at 400-500° C. and 10-1000 Pa of CO 2 or O 2 for 1-12 hours.

[0014] Furthermore, the electrode sheet of the present invention is integrated with the acceleration grid.

[0015] On the second aspect, an embodiment of the present application is a multiplier for a magnetically selected cesium atomic clock using a secondary electron emission structure for amplifying weak ion signals on a silicon wafer, including multiple multiplication stages formed by the secondary electron emission structure, a collecting electrode, a ceramic plate, a fixing stud, a magnetic shielding shell, a dynode electrode lead and a signal line. The multiple multiplication stages are sequentially installed between two ceramic plates, the ceramic plates are fixed with multiple fixing studs, and the outermost layer is wrapped with a magnetic shielding shell, leaving only the dynode electrode leads, signal output lines and ion entrance holes.

[0016] Furthermore, in two adjacent secondary electron emission structures, the present invention aligns the output acceleration gate of the previous emission structure with the input acceleration gate of the next emission structure, connecting the output electrode of the previous emission structure with the input electrode of the next emission structure.

[0017] Beneficial effects:

[0018] First, the present application adopts silicon wafers and composite secondary electron emission films. The polishing cost of silicon wafers is low, and the surface roughness reaches the sub-nanometer level, which can effectively improve the roughness of the composite secondary electron emission film and increase the amplification factor. The resistance of the silicon wafer itself is used to form a voltage divider to reduce the use of discrete resistors, simplify the structure, and increase the operating temperature of the multiplier. The pre-plated composite secondary electron emission film is a layered structure of all-metal materials, which is simple to plate and activated before use. It solves the contradiction between batch production and single use of multipliers, shortens the exposure time of the multiplier to the atmosphere, improves performance and life, and the multiplier has a simple structure, can be assembled in batches, has high reliability, and greatly reduces costs.

[0019] Second, the secondary electron emission structure of the multiplier is not activated during assembly, so no special protection is required and multiple pieces can be manufactured and assembled in one batch; it is activated before being installed on the magnetically selected cesium atomic clock, greatly shortening the time the multiplier is exposed to the atmosphere before use. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following briefly introduces the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0021] Figure 1 Schematic diagram of a silicon wafer-based secondary electron emission structure provided according to an embodiment of the present application, comprising (a) a coated silicon wafer with an electrode sheet, (b) an accelerating gate, (c) a silicon wafer dynode, and (d) a silicon wafer with a composite secondary electron emission film coated on its surface;

[0022] Figure 2 A pre-plated composite secondary electron emission thin film structure is provided according to an embodiment of the present application;

[0023] Figure 3 Schematic diagram of an electron multiplier based on a silicon wafer secondary electron emission structure according to an embodiment of the present application, including (a) a top view, (b) a bottom view, and (c) a front view;

[0024] Figure 4 Schematic diagram of a silicon wafer and accelerating gate integrated secondary electron emission structure and its integrated electron multiplier provided according to an embodiment of the present application, including (a) a front view of the silicon wafer and accelerating gate integrated secondary electron emission structure, (b) a top view of the silicon wafer and accelerating gate integrated secondary electron emission structure, (c) a top view of the integrated electron multiplier, and (d) a bottom view of the integrated electron multiplier;

[0025] Figure 5 Silicon wafer with electrodes, (a) two-terminal electrodes, (b) three-terminal electrodes, (c) annular electrode, (d) equipotential lines of two-terminal electrodes, (e) three-terminal electrodes, (f) annular electrode equipotential lines;

[0026] Figure 6 It is a secondary electron emission structure on a silicon wafer substrate;

[0027] Figure 7 It is the secondary emission of electrons incident on the dynode of the silicon wafer substrate;

[0028] Figure 8 It is the secondary emission of electrons incident on the two-stage cascaded silicon wafer substrate dynode;

[0029] Figure 9 Cesium ions are incident on a 10-stage cascade of silicon wafer substrate dynode multipliers.

[0030] In the figure: 1- rectangular silicon wafer, 2- electrode sheet, 3- accelerating grid, 4- connection between electrode sheet and accelerating grid, 5- polished surface of rectangular silicon wafer, 6- composite secondary electron emission film, 21- first layer of Mg film, 22- second layer of Ag or Au film, 23- third layer of Mg film, 31- first stage silicon wafer multiplication stage, 32- second stage silicon wafer multiplication stage, 33- third stage silicon wafer multiplication stage, 34- fourth stage silicon wafer multiplication stage, 35- fifth stage silicon wafer multiplication stage, 36- sixth stage silicon wafer multiplication stage, 37- seventh stage silicon wafer multiplication stage, 38- eighth stage silicon wafer multiplication stage, 39- ninth stage silicon wafer multiplication stage, 40- final stage silicon wafer multiplication stage, 41- collector, 42- upper ceramic plate, 43- lower ceramic plate, 44- fixing stud, 45- magnetic shielding shell , 46-first-stage silicon wafer multiplication stage lead, 47-last silicon wafer multiplication stage lead, 48-signal line, 49-ion inflow perforation; 51-integrated acceleration gate; 61-first-stage silicon wafer integrated multiplication stage, 62-second-stage silicon wafer integrated multiplication stage, 63-third-stage silicon wafer integrated multiplication stage, 64-fourth-stage silicon wafer integrated multiplication stage, 65-fifth-stage silicon wafer integrated multiplication stage, 66-sixth-stage silicon wafer integrated multiplication stage, 67-seventh-stage silicon wafer integrated multiplication stage, 68-eighth-stage silicon wafer integrated multiplication stage, 69-ninth-stage silicon wafer integrated multiplication stage, 70-last-stage silicon wafer integrated multiplication stage, 71-input lead, 72-input electrode, 73-silicon wafer, 74-output electrode, 75-output lead, 76-acceleration gate. DETAILED DESCRIPTION

[0031] In order to enable those skilled in the art to better understand the present invention, the following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments in the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts should fall within the scope of protection of this application.

[0032] It should be noted that the terms "first", "second", etc. in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or sequential order. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present application described here. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0033] In this application, terms such as "upper," "lower," "left," "right," "front," "back," "top," "bottom," "inner," "outer," "center," "vertical," "horizontal," "transverse," and "longitudinal" indicate positions or locations based on the positions or locations shown in the accompanying drawings. These terms are primarily intended to better describe this application and its embodiments and are not intended to limit the devices, elements, or components indicated to having a specific orientation, or to being constructed or operated in a specific orientation.

[0034] Furthermore, some of the above terms may be used to express other meanings besides indicating a position or location. For example, the term "on" may also be used to indicate a dependency or connection in certain circumstances. Those skilled in the art will understand the specific meanings of these terms in this application based on the specific circumstances.

[0035] Additionally, the term "plurality" shall mean two or more.

[0036] It should be noted that, in the absence of conflict, the embodiments and features of the embodiments in this application can be combined with each other. The present application will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0037] like Figure 1 As shown, the present application provides a secondary electron emission structure for amplifying weak cesium ion signals based on a silicon wafer, namely a silicon wafer dynode, comprising a rectangular silicon wafer 1, an electrode sheet 2 and an accelerating gate 3, wherein: the substrate of the rectangular silicon wafer 1 is a silicon material with a resistivity of 2.3 x 10 5Ω·cm, and the resistance formed between the two end electrodes 2 is 0.5MΩ to 10MΩ. A rectangular silicon wafer 1 is polished on one side to form a polished surface 5, and then a composite secondary electron emission film 6 is deposited on the polished surface 5 using magnetron sputtering. Before depositing the composite secondary electron emission film 6, the rectangular silicon wafer 1 may be affixed with a polyimide film near the ends of the electrode sheets 2. After the film is deposited, the polyimide film is removed to ensure that the mounting surface near the electrode sheets 2 is free of the composite secondary electron emission film 6. The rectangular silicon wafer 1 and the electrode sheets 2 can be connected and secured by various methods such as laser welding and brazing, making them suitable for use in vacuum and high-temperature conditions.

[0038] like Figure 2 As shown, the composite secondary electron emission film 6 includes three layers: a first Mg film 21, a second Ag film or Au film 22, and a third Mg film 23. The thickness of the first Mg film 21 is 20-40 nm, the thickness of the second Ag film or Au film 22 is 20-30 nm, and the thickness of the third Mg film 23 is 20-40 nm. The composite secondary electron emission film is a metal film that can be assembled and stored for a long time after plating. It is activated before use. The activation method is to maintain it in a CO2 or O2 atmosphere of 400°C to 500°C and 10Pa to 1000Pa, or even a CO2 / O2 combination, for (1-12) hours. When using CO2, 400°C, 1000Pa, and 12 hours are recommended, while when using O2, 500°C, 100Pa, and 1 hour are recommended.

[0039] Specifically, the embodiment of the present application also provides a 10-stage magnetically selected cesium atomic clock multiplier using a secondary electron emission structure for amplifying weak ion signals based on a silicon wafer, such as Figure 3 As shown, it includes 10 silicon wafer multiplication stages (31 to 40) formed by a secondary electron emission structure, a collecting electrode 41, an upper ceramic plate 42, a lower ceramic plate 43, a fixing stud 44, a magnetic shielding shell 45, a first silicon wafer multiplication stage lead 46, a last silicon wafer multiplication stage lead 47 and a signal line 48. Multiple silicon wafer multiplication stages are sequentially installed between the upper ceramic plate 42 and the lower ceramic plate 43. Holes are opened on the ceramic plate for inserting the various pins extending from the electrode sheet 2. The ceramic plate is fixed with multiple fixing studs, and the outermost layer is wrapped with a magnetic shielding shell, leaving only the first silicon wafer multiplication stage lead 46, the last silicon wafer multiplication stage lead 47, the signal output line 48 and the ion inflow perforation 49.

[0040] Furthermore, the secondary electron emission structure of the 10-stage multiplier is not activated when it is stored before assembly and use, so no special protection is required and multiple pieces can be manufactured and assembled in one batch. When in use, it needs to be installed in front of the magnetically selected cesium atomic clock for activation, which greatly shortens the time the multiplier is directly exposed to the atmosphere before use, improves the amplification factor and its attenuation, and enhances the performance and life of the multiplier for the magnetically selected cesium atomic clock.

[0041] Furthermore, the number of stages of a silicon-wafer multiplier can be designed based on the desired magnification. For example, for an ion current signal, the magnification of the first silicon-wafer multiplier is calculated as 0.8, and the magnification of the subsequent silicon-wafer multiplier is calculated as 4. Thus, 10 stages can achieve approximately 210,000x. If the required magnification is 50,000x, a 9-stage silicon-wafer multiplier can be selected, the final silicon-wafer multiplier of the 10-stage silicon-wafer multiplier can be removed, and the collector can be installed in the original final silicon-wafer multiplier position.

[0042] The present application also provides another embodiment of a 10-stage magnetically selected cesium atomic clock multiplier based on a secondary electron emission structure for amplifying weak ion signals on a silicon wafer, such as Figure 4 As shown, a coated silicon wafer 1 with electrode sheets, an electrode sheet 2, and an integrated accelerating gate 51 are integrated together to form an integrated dynode based on a silicon wafer. Compared to a conventional accelerating gate 3, the structure of the integrated accelerating gate 51 allows for electrode sheet welding and fixation, and lacks the extended pins of the electrode sheet 2. This reduces the number of fixing holes required on the ceramic plate during further assembly to form the multiplier by half, and the number of interconnecting wires between the integrated dynodes is also reduced by half. This offers the advantages of a higher level of integration and better consistency.

[0043] More specifically, the embodiments of the present application provide a secondary electron emission structure for amplifying weak ion signals based on a silicon wafer and a multiplier using the structure. The silicon wafer realizes the voltage divider resistor function to increase the operating temperature of the multiplier. The silicon wafer has been batch polished and has good roughness. The composite secondary electron emission film is a metal material before activation and can be batch coated and stored for a long time. It is only activated before use. Therefore, the silicon wafer multiplier can be mass-produced without voltage divider resistors and complex components, effectively reducing costs. The entire multiplier has a compact structure, good consistency, and high reliability, which improves the performance and life of the multiplier for magnetically selected cesium atomic clocks.

[0044] The present invention is described by taking the design of a silicon wafer electron multiplier for a cesium atomic clock as an example.

[0045] The electron multiplier used in cesium atomic clocks typically consists of a box-grid structure consisting of nine quarter-circular stainless steel dynodes (the aforementioned secondary electron emission structure). Each dynode is either constructed from a stainless steel substrate with a secondary electron emission film plated on its surface, or from a silver-magnesium alloy or beryllium-copper alloy with a secondary electron emission film formed on its surface through an oxidation process. Each stage is connected by a 6M to 8MΩ discrete resistor, resulting in a total gain of ≥100,000, amplifying a 1pA current signal to 100nA. Therefore, achieving a gain of 100,000 is the design goal for silicon wafer electron multipliers.

[0046] Silicon wafers are semiconductor materials that can form resistance themselves. Therefore, electron multipliers using high-resistance silicon wafers as the base material to form dynodes do not require discrete resistors. R represents resistance, ρ represents resistivity, S represents cross-sectional area (= thickness × width), and L represents length. The resistance calculation formula for silicon wafers is R = ρL / S. The resistivity range of high-resistance silicon wafers is relatively wide, usually within 1×10 3 ~1ⅹ10 6 Ω·cm, the resistivity range of the silicon wafer selected for making the electron multiplier in the present invention is 1×10 5 Ω·cm~1ⅹ10 6 Ω·cm. For example, if the resistivity of high-resistance silicon wafer is 2.3×10 5 Ω·cm, a thickness of 0.775mm, and a width of 10mm, then a length of 20mm yields a resistance of 5.93MΩ. The actual resistance can be measured directly between the electrodes of the silicon wafer using a multimeter.

[0047] The gate and base of a dynode based on stainless steel or silver-magnesium alloy are both metal and have the same potential, resulting in a near-invisible internal electric field and no deflection, convergence, or divergence of the atomic beam. Unlike the inherent conductivity of stainless steel or silver-magnesium alloy, a dynode based on a silicon wafer experiences a potential difference, creating an internal electric field. This requires an electrode on the back of the silicon wafer (the front of the wafer is coated with a secondary electron emission film) to apply voltage and generate current.

[0048] The present invention proposes the following three silicon wafer electrode shapes, positions and potential equipotential lines: Figure 5 As shown in the figure, the equipotential lines are horizontal for the two-terminal electrode configuration, horizontal and vertically symmetrical for the three-terminal electrode configuration, and circular for the annular electrode configuration. Analysis of the equipotential lines indicates that the annular electrode has a stronger effect on converging the electron beam toward the center, while the three-terminal electrode has a stronger effect on diverging the electron beam toward the ends. The two-terminal electrode configuration deflects the electron beam toward the output electrode. The deflection, convergence, or divergence of the electron beam by the silicon wafer dynode within the electron multiplier can have a beneficial effect on the secondary electron emission film lifetime and gain, improving electron multiplier performance. The next design step will be conducted using the two-terminal electrode configuration as an example.

[0049] In order to accelerate the incident electrons or ions, the dynode can also include an accelerating grid. For cesium atomic clocks using silicon wafers, the accelerating grid of the dynode can only be connected to the input electrode. Here, a silicon wafer with electrodes at both ends is used. The three-dimensional diagram of the dynode with the accelerating grid is shown in the figure below. Figure 6 As shown,

[0050] While stainless steel or silver-magnesium alloy-based dynodes are entirely metal, all surfaces are at the same potential. However, on a silicon wafer-based dynode, the accelerating gate and its connected input electrode are at the same potential. The voltages on the silicon wafer surface vary, except for the surface with the electrodes. The input electrode has a lower potential (larger absolute value), while the output electrode has a higher potential (smaller absolute value). The potential on the silicon wafer surface changes linearly from the input electrode potential to the output electrode potential.

[0051] The front of the silicon wafer is coated with a secondary electron emission film. When an electron beam is incident on the accelerating grid of a silicon wafer dynode, the electrons tend to fall to the output electrode side with a larger potential difference, which has a deflection and convergence effect on the incident electron beam. At the same time, multiple secondary electrons are generated on the secondary electron emission film on the front of the silicon wafer. According to tests, a voltage difference of 200V can generate 4 to 5 secondary electrons for one electron. Figure 7 shown.

[0052] Furthermore, two silicon wafer dynodes are cascaded, that is, the output acceleration gate of the previous dynode is directly opposite to the input acceleration gate of the next dynode, and the output electrode of the previous dynode is connected to the input electrode of the next stage with a wire, such as Figure 8 As shown in the figure, after two stages of amplification, the incident beam can be amplified 16 to 25 times.

[0053] By analogy, with each additional cascade level, the gain is amplified by 4 to 5 times, so theoretically, 10 levels can reach at least 4 10 = 1048576 times, using secondary emission to amplify 1pA current to 1μA current, which is much smaller than the current flowing through the silicon chip (200V / 5.93MΩ=33.7μA). 10-stage cascade silicon chip multiplier can be used Figure 9 It means that the resistance voltage division of the silicon chip itself is used, and the position of the electrodes on the silicon chip is relied upon to deflect, converge or diverge the electron beam, thereby improving the performance indicators such as the gain and life of the electron multiplier.

[0054] The purpose of the present invention is to address the shortcomings of the above-mentioned technology and reduce the manufacturing cost of the multiplier while keeping the performance basically unchanged from the perspective of simplifying the secondary electron multiplication structure, multi-layer MgO mixed film structure and simultaneous production of multiple pieces.

[0055] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in the present invention should be included in the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be based on the scope of protection of the claims.

Claims

1. A secondary electron emission structure for amplifying weak ion signals based on a silicon wafer, characterized in that: The device comprises a rectangular silicon wafer, an electrode sheet and an accelerating grid, wherein the electrode sheets are fixed at both ends of the rectangular silicon wafer and the accelerating grid is connected to the electrode sheets; the rectangular silicon wafer with the electrode sheets at both ends and the accelerating grid constitute a multiplication stage; wherein: the surface of the rectangular silicon wafer is coated with a composite secondary electron emission film, and the composite secondary electron emission film is activated before use; The rectangular silicon wafer is plated with a full-metal composite secondary electron emission film on the polished surface, which is sequentially arranged from the silicon crystal surface: a first layer of Mg film, a second layer of Ag film or Au film, and a third layer of Mg film; the first layer of Mg film of the composite secondary electron emission film has a thickness of 20 to 40 nm, the second layer of Ag film or Au film has a thickness of 20 to 30 nm, and the third layer of Mg film has a thickness of 20 to 40 nm.

2. The secondary electron emission structure for amplifying weak ion signals based on a silicon wafer according to claim 1, characterized in that: The resistivity of the rectangular silicon wafer is 2.3 x 10 5 The resistance between the electrodes at both ends is about 0.5MΩ~10MΩ.

3. The secondary electron emission structure for amplifying weak ion signals based on a silicon wafer according to claim 1, characterized in that: One surface of the rectangular silicon wafer is pre-polished to a roughness better than 2 nm and is used for coating a composite secondary electron emission thin film.

4. The secondary electron emission structure for amplifying weak ion signals based on a silicon wafer according to claim 1, characterized in that: Before coating the composite secondary electron emission film on the rectangular silicon wafer, the two ends of the fixed electrode sheet are pasted with polyimide film, and the polyimide film is torn off after the coating is completed.

5. The secondary electron emission structure for amplifying weak ion signals based on a silicon wafer according to claim 1, characterized in that: The composite secondary electron emission film is activated before use, that is, maintained at 400-500° C. and 10-1000 Pa of CO 2 or O 2 for 1-12 hours.

6. The secondary electron emission structure for amplifying weak ion signals based on a silicon wafer according to claim 1, characterized in that: The electrode sheet is integrated with the accelerating grid.

7. A multiplier based on a secondary electron emission structure for amplifying weak ion signals on a silicon wafer, using the secondary electron emission structure according to any one of claims 1 to 6, characterized in that: It includes multiple multiplication stages formed by secondary electron emission structure, collecting electrodes, ceramic plates, fixing studs, magnetic shielding shells, multiplication electrode leads and signal lines. Multiple multiplication stages are installed in sequence between two ceramic plates. The ceramic plates are fixed with multiple fixing studs. The outermost layer is wrapped with a magnetic shielding shell, leaving only the multiplication electrode leads, signal output lines and ion entrance holes.

8. The multiplier based on the secondary electron emission structure for amplifying weak ion signals of silicon wafer according to claim 7, characterized in that: In two adjacent secondary electron emission structures, the output acceleration gate of the previous emission structure is aligned with the input acceleration gate of the next emission structure, and the output electrode of the previous emission structure is connected to the input electrode of the next emission structure.

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