Data storage method, controller and control equipment

Abstract

The invention discloses a data storage method, a controller and control equipment, and relates to the technical field of storage. The controller obtains first data to be stored and generates a corresponding ECC according to the first data, the generated ECC is used for performing error correction on the first data and comprises a first part of ECC and a second part of ECC, the error correction capability of the complete ECC for the first data is higher than that of the first part of ECC for the first data, and the error correction capability of the complete ECC for the second data is higher than that of the second part of ECC for the second data. And the controller writes the first data and the first part of ECC into the first storage space and writes the second part of ECC into the second storage space. As the data volume of the ECC is generally smaller than the quantity of the first data, the storage resources occupied for storing the first data can be effectively reduced; and moreover, the complete ECC has higher error correction capability than the first part ECC, so that the reliability of storing the first data can be effectively ensured. Therefore, the data storage cost can be reduced while the reliability of data storage is ensured.

Description

Technical Field

[0001] The present application relates to the field of storage technology, and in particular to a data storage method, a controller, and a control device. Background Art

[0002] Data mirroring means storing a copy of the same data in multiple storage spaces, and each storage space will store the error correcting code (ECC) corresponding to the data. In this way, when the data needs to be read, the controller can read the data and the corresponding ECC from one of the storage spaces. If the ECC read from the storage space indicates that there are no errors in the data, or indicates that the errors in the data are correctable, the controller can directly return the correct data; if the ECC read from the storage space indicates that there are uncorrectable errors in the data, the controller can read the correct data from other storage spaces and return it. In this way, by storing the same data in multiple storage spaces, the reliability of data storage can be guaranteed.

[0003] However, storing the same data in multiple storage spaces separately will occupy more storage resources, which will lead to higher data storage costs and limit the total amount of data that can be stored in the multiple storage spaces. Summary of the invention

[0004] The present application provides a data storage method to reduce the data storage cost and increase the total amount of data that can be stored in multiple storage spaces while ensuring the reliability of data storage. In addition, the present application also provides a corresponding controller, a control device, a computer-readable storage medium, and a computer program product.

[0005] In a first aspect, the present application provides a data storage method, which can be executed by a corresponding controller, which can be a memory controller, or a controller in a hard disk, etc. During the data storage process, the controller obtains first data to be stored, and generates a corresponding ECC (error correction code) based on the first data. The generated ECC is used to correct errors in the first data, and the ECC includes a first partial ECC and a second partial ECC. The error correction capability of the complete ECC (i.e., the first partial ECC + the second partial ECC) for the first data is higher than the error correction capability of the first partial ECC for the first data, so that the controller writes the first data and the first partial ECC into the first storage space, and writes the second partial ECC into the second storage space.

[0006] Since the first data can be stored only in the first storage space during the process of storing the first data, and the amount of ECC data stored in the first storage space and the second storage space is usually less than the amount of data to be stored, this can effectively reduce the storage resources required to store the first data. In addition, not only can the first part of the ECC in the ECC correct errors for the first data, but the complete ECC can also correct errors for the first data based on a higher error correction capability, which can effectively ensure the reliability of storing the first data. In this way, the controller can reduce the cost of data storage and increase the total amount of data that can be stored in multiple storage spaces while ensuring the reliability of data storage.

[0007] In addition, this data storage method has no requirements for the data access granularity of the processor. Therefore, it can support the processor to read and write data with a smaller data access granularity (such as 64 bytes), which can enable the data reading and writing performance in the first storage space to reach a higher level.

[0008] In a possible implementation, the controller can also respond to the read instruction sent by the processor, read the first part of the ECC and the first data in the first storage space, and analyze the read first data according to the first part of the ECC to obtain an analysis result; when the analysis result indicates that the read first data has an uncorrectable error, the controller reads the second part of the ECC in the second storage space, and corrects the read first data according to the first part of the ECC and the second part of the ECC to obtain the first target data; finally, the controller feeds back the first target data to the processor. In this way, when the first part of the ECC cannot correct the error of the read first data, the controller uses the complete ECC with higher error correction capability to correct the error of the read first data, which can ensure that the processor can finally obtain the correct first data, thereby ensuring the reliability of the first data storage.

[0009] Optionally, when the analysis result indicates that the first data read has a correctable error, the controller can use the first part of the ECC to correct the error of the first data read, obtain the second target data, and feed back the second target data to the processor. In this way, the processor can eventually obtain the correct data, improving the reliability of data storage.

[0010] In a possible implementation, when the controller writes the first data and the first partial ECC into the first storage space, the controller may first determine the data amount of the first partial ECC based on the amount of the first data, such as the ratio between the amount of the first data and the data amount of the first partial ECC is 4:1, etc., and determine the first partial ECC from the complete ECC based on the data amount of the first partial ECC, so that the controller then writes the first data and the determined first partial ECC into the first storage space. In this way, the controller can write the partial ECC and the first data into the same storage space, so that when the first data is subsequently read, when there are a small number of errors in the read first data, the first partial ECC can be used to first verify whether an error occurs in the first data.

[0011] In a possible implementation, when the controller determines the first partial ECC from the complete ECC according to the data amount of the first partial ECC, it can specifically select a plurality of continuous symbols from the complete ECC according to the data amount, wherein each symbol includes a preset number of bits of data, and the selected plurality of symbols can be used as the first partial ECC. In this way, the controller can obtain the first partial ECC stored in the same storage space as the first data by continuously selecting a plurality of symbols.

[0012] Optionally, the controller may also select multiple discontinuous symbols from the complete ECC, which is not limited to this.

[0013] In a possible implementation, the first storage space and the second storage space are located in a storage medium, and the storage medium also includes a third storage space (and more storage spaces), so that the controller can also obtain the second data to be stored and generate the ECC corresponding to the second data, so that when the second data does not meet the reliability storage condition (such as the second data is data with low storage reliability requirements, etc.), the controller can write the second data and the ECC corresponding to the second data into the third storage space. In this way, for data with high data storage reliability requirements, the corresponding first storage space and second storage space can be flexibly divided for storage according to the address space, and for data with low data storage reliability requirements, there is no need to divide it into multiple storage spaces to store the data, thereby improving the flexibility of data storage.

[0014] In one possible implementation, the storage medium used in the first storage space is the same as the storage medium used in the second storage space, such as the storage media used in both storage spaces are dynamic random access memory (DRAM), and the data storage method in the first storage space matches the data storage method in the second storage space.

[0015] Optionally, the storage medium used by the first storage space may be different from the storage medium used by the second storage space, or the data storage method in the first storage space may not match the data storage method in the second storage space.

[0016] In a possible implementation, the storage particles corresponding to the first storage space and the storage particles corresponding to the second storage space belong to different channels or columns. In this way, the first storage space and the second storage space are implemented using storage particles on different channels or different columns, which can effectively reduce the probability of simultaneous failure of the storage particles corresponding to the two storage spaces.

[0017] In a possible implementation, the first storage space and the second storage space are storage spaces in a memory; or, the first storage space and the second storage space are used to persistently store the first data. In this way, the above method can be used in a memory data storage scenario or a data persistent storage scenario to ensure the reliability of data storage while reducing the cost of data storage.

[0018] In a possible implementation, when the controller generates an error correction code ECC according to the first data, it can specifically obtain a coding matrix first, and then use the coding matrix to encode the first data to obtain the ECC corresponding to the first data, the data amount of the ECC corresponding to the first data is greater than or equal to a threshold, and the threshold is determined based on the amount of the first data, for example, the larger the amount of the first data, the higher the threshold. In this way, the controller uses the coding matrix to generate the ECC corresponding to the first data.

[0019] In a second aspect, the present application provides a controller comprising modules for executing the data storage method in the first aspect or any possible implementation manner of the first aspect.

[0020] In a third aspect, the present application provides a controller, comprising a power supply circuit and a processing circuit, wherein the power supply circuit is used to power the processing circuit, and the processing circuit is used to execute the data storage method in the first aspect or any possible implementation of the first aspect.

[0021] In a fourth aspect, the present application provides a controller, which includes a processor and a memory. The processor and the memory communicate with each other. The processor is used to execute instructions stored in the memory so that the controller executes the data storage method in the first aspect or any one of the implementations of the first aspect. It should be noted that the memory can be integrated into the processor or can be independent of the processor. The computing device may also include a bus. The processor is connected to the memory via the bus. The memory may include a readable memory and a random access memory.

[0022] In a fifth aspect, the present application provides a control device, which includes the controller described in any implementation of the second to fourth aspects above, and the controller is used to execute the operating steps of the data storage method described in the first aspect or any implementation of the first aspect.

[0023] In a sixth aspect, the present application provides a computer-readable storage medium, wherein instructions are stored in the computer-readable storage medium, which, when executed on a control device, enables the control device to execute the operating steps of the data storage method described in the first aspect or any one of the implementations of the first aspect.

[0024] In a seventh aspect, the present application provides a computer program product comprising instructions, which, when executed on a control device, enables the control device to execute the operating steps of the data storage method described in the first aspect or any one of the implementations of the first aspect.

[0025] Based on the implementations provided in the above aspects, this application can also be further combined to provide more implementations. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 A schematic diagram of the structure of an exemplary data storage system provided in this application;

[0027] Figure 2 A schematic diagram of a data storage method provided in this application;

[0028] Figure 3 A schematic diagram of encoding data using a coding matrix;

[0029] Figure 4 A schematic diagram of using a first storage space and a second storage space to store first data and ECC;

[0030] Figure 5 is a schematic diagram of two different storage spaces on the storage medium 103;

[0031] Figure 6 is a schematic diagram of encoding the first data based on the (100, 64) RS8 encoding method;

[0032] Figure 7 A schematic diagram of the structure of a controller provided in this application;

[0033] Figure 8 A schematic diagram of the structure of another controller provided in this application;

[0034] Fig. 9 A schematic diagram of the structure of another controller provided in this application. DETAILED DESCRIPTION

[0035] In order to reduce the cost of data storage and increase the amount of data that can be stored in multiple storage spaces, the present application provides a data storage method, which stores the data and the partial ECC corresponding to the data in one storage space, and stores the other partial ECC corresponding to the data in another storage space, thereby ensuring the reliability of data storage while reducing the storage resources required for data storage. This can reduce the cost required for data storage, so that more data can be stored in the same storage space.

[0036] To facilitate understanding of the technical solution of the present application, the relevant technical terms involved in the present application are explained below.

[0037] Error correction code refers to a code used to detect whether data has errors and correct erroneous data. In this application, when the controller writes data to the storage space, it will also write the error correction code corresponding to the data, so as to use the error correction code to determine whether the data written to the storage space has errors, and when it is determined that the data in the storage space has errors, the error correction code is used to correct the erroneous data to obtain the correct data content.

[0038] RS (Reed-Solomon) coding is a coding method that uses a polynomial over a finite field to represent data and redundant data. The redundant data can be constructed using polynomial operations for error detection and correction. In the coding process, it is usually processed in units of symbols, where each symbol can include m (m is a positive integer, such as 8, etc.) bits of data. The resulting coding result may include n (n is a positive integer) symbols, and the n symbols are generated according to a certain association relationship based on k (k is a positive integer less than n) data symbols to be transmitted / stored. The remaining (nk) symbols can be used as error correction codes for error detection and correction of data symbols. The form of RS coding can be identified by (n, k).

[0039] The coding matrix, in this application, refers to a matrix used to encode data to generate an error correction code.

[0040] Storage particles, also known as chips, are the basic units for storing data. Each particle can transmit 4 or 8 bits of data at a time, that is, the bit width is 4 bits or 8 bits.

[0041] A rank, in this application, refers to a set of particles. The number of particles included in each rank can be determined according to the data access granularity of the controller for the storage space and the bit width of each particle. For example, if the data access granularity of the controller is 64 bits and the bit width of each particle is 8 bits, then a rank can include 8 (i.e., 64 / 8) particles.

[0042] A channel, in this application, refers to a channel through which a controller reads and writes data to a storage space. Each channel may include one or more ranks. Generally, the more channels there are, the faster the controller reads and writes data to the storage space.

[0043] See also Figure 1 , showing a schematic diagram of the structure of a data storage system provided by the present application. Figure 1 As shown, the data storage system 100 may include a processor 101, a controller 102 and a storage medium 103, and the processor 101, the controller 102 and the storage medium 103 may be connected via a bus, which may be, for example, a double data rate (DDR) bus, an inter-integrated circuit (I2C) bus, or the like.

[0044] The processor 101 is used to provide the controller 102 with data to be stored, and instruct the controller 102 to write the data into the storage medium 103. Further, the processor 101 can also instruct the controller 102 to read data from the storage medium 103. Exemplarily, the processor 101 can be a central processing unit (CPU), an application-specific integrated circuit (ASIC), a programmable logic device (PLD), a complex programmable logical device (CPLD), a field-programmable gate array (FPGA), a generic array logic (GAL), a system on chip (SoC), a software-defined infrastructure (SDI) chip, an artificial intelligence (AI) chip, a data processing unit (DPU), and any other processor or any combination thereof.

[0045] The controller 102 is responsible for reading and writing data from the storage medium 103, including writing new data provided by the processor 101 into the storage medium 103, and reading data stored in the storage medium 103 and feeding the data back to the processor 101. Exemplarily, the controller 102 may be hardware such as an application specific integrated circuit (ASIC), a programmable logic device (PLD), a complex programmable logic device (CPLD), a field programmable gate array (FPGA), etc.

[0046] The storage medium 103 is used to store the data provided by the processor 101 and supports the controller 102 to read the stored data. The storage medium 103 can be a storage medium used as a memory, such as a dynamic random access memory (DRAM), a dual-inline-memory-module (DIMM), a storage class memory (SCM), etc.; in this case, the storage medium 103 can be used to temporarily store data, and the controller 102 can specifically be a memory controller. Alternatively, the storage medium 103 can be a storage medium for persistent storage of data, such as a storage medium such as a solid state drive (SSD) or a hard disk drive (HDD).

[0047] When the controller 102 writes new data to the storage medium 103, if the data is backed up and stored in the storage medium 103, that is, the same data is stored in multiple storage spaces in the storage medium 103, so that when an error occurs in the data stored in one of the storage spaces, the controller 102 can read the correct data from other storage spaces. This data storage method will cause the data to occupy more storage resources in the storage medium 103, resulting in a high data storage cost and limiting the total amount of data that can be stored in the storage medium 103, such as a 2GB (gigabyte) storage space can only store 1GB of data at most.

[0048] Based on this, the controller 102 provided in the present application will first obtain the data to be stored in the process of writing new data to the storage medium 103. The data can be the data provided by the processor 101, and generate ECC (error correction code) according to the first data. The ECC is used to correct the data to be written (when the written data has an error, the ECC is used to correct the error). Under normal circumstances, the error correction of the data includes error detection and error correction, wherein error detection refers to detecting whether the written data has an error, and error correction refers to correcting the erroneous data in the written data to correct data. The generated ECC includes a first part of the ECC and a second part of the ECC, and the first part of the ECC also has the ability to correct errors for the data, and the complete ECC has a higher error correction capability for the data than the first part of the ECC. Then, the controller 102 writes the data and the first part of the ECC into the first storage space in the storage medium 103, and writes the second part of the ECC into the second storage space in the storage medium 103.

[0049] Since in the process of storing data, the data can be stored only in one storage space in the storage medium 103, and the amount of ECC data stored in the first storage space and the second storage space is usually less than the amount of data to be stored, this can effectively reduce the storage resources required for data storage. In addition, not only can the first part of the ECC in the ECC correct errors for the data, but the complete ECC can also correct errors for the data based on a higher error correction capability, which can effectively ensure the reliability of data storage. In this way, the controller 102 can reduce the data storage cost and increase the total amount of data that can be stored in the storage medium 103 while ensuring the reliability of data storage.

[0050] In addition, this data storage method has no requirements for the data access granularity of the processor 101, and therefore, can support the processor 101 to read and write data with a smaller data access granularity (such as 64 bytes), which can enable the data read and write performance in the first storage space to reach a higher level. Furthermore, in the storage medium 103, for data with higher data storage reliability requirements, the corresponding first storage space and second storage space can be flexibly divided for storage according to the address space, and for data with lower data storage reliability requirements, there is no need to divide it into multiple storage spaces to store the data, thereby improving the flexibility of data storage.

[0051] In actual application, the data storage system 100 can be applied to a centralized storage scenario or a distributed storage scenario. In a centralized storage scenario, a disk-control separation architecture or a disk-control integrated architecture can be adopted between the processor 101 and the controller 102 and the storage medium 103 in the data storage system 100. In a distributed storage scenario, a storage-computing integrated architecture or a storage-computing separation structure can be adopted between the processor 101 and the controller 102 and the storage medium 103 in the data storage system 100. That is, the processor 101 can be located in the same hardware entity as the controller 102 and the storage medium 103, such as in the same server; or, the processor 101 can be located in a different hardware entity from the controller 102 and the storage medium 103, such as the processor 101 is located in the server, the controller 102 and the storage medium 103 are located in the hard disk, and the server and the hard disk can be connected through a peripheral component interconnect express (PCIe) bus.

[0052] It is worth noting that the above Figure 1The data storage system 100 shown is only used as an exemplary description. In other possible data storage systems, the number of processors may be multiple, and the multiple processors may be processors of the same or different types, and the multiple processors may instruct the controller 102 to read and write data to the storage medium 103. Alternatively, in other possible data storage systems, more number or more types of storage media may be included, for example, Figure 1 Based on the data storage system 100 shown, a storage medium A may also be included, and the storage medium 103 is used as a memory to temporarily store data, while the storage medium A is used as a hard disk to persistently store data. Alternatively, in other possible data storage systems, other types of devices may also be included, such as network cards and other devices. The specific architecture of the data storage system is not limited in this application.

[0053] Next, the data storage method provided by the present application is described in conjunction with the accompanying drawings.

[0054] See also Figure 2 , Figure 2 A schematic diagram of a data storage method provided in this application, which can be applied to Figure 1 The data storage system 100 shown in FIG. 1 may be applied to other applicable data storage systems. Figure 1 The data storage system 100 shown is taken as an example for illustrative description.

[0055] in, Figure 2 The data storage method shown may specifically include:

[0056] S201: The processor 101 provides the controller 102 with first data to be stored.

[0057] In this embodiment, the processor 101 can process services such as data merging, data computing services, etc. during operation, and the processor 101 can generate corresponding business data during the process of processing the services. For the convenience of distinction and description, the business data generated by the processor 101 is referred to as first data below, and the first data can be temporarily stored or persistently stored in the file storage system 100.

[0058] In actual application, the processor 101 may also obtain data input by the user, so that the processor 101 may provide the data input by the user as the first data to the controller 102 to instruct the controller 102 to cache or persistently store the first data.

[0059] S202: The controller 102 generates an ECC according to the first data, and the ECC includes a first partial ECC and a second partial ECC, wherein the generated ECC is used to correct errors of the first data, and the error correction capability of the ECC for the first data is higher than the error correction capability of the first partial ECC for the first data.

[0060] In a possible implementation, the controller 102 may obtain a predefined encoding matrix, for example, a technician may pre-configure the encoding matrix in the controller 102. In this way, the controller 102 may encode the first data using the encoding matrix, and the obtained encoding result includes the first data and the ECC, so that the ECC may be extracted from the encoding result.

[0061] Generally, the larger the data volume of the generated ECC, the stronger the error correction capability of the ECC for the first data. The error correction capability described in this embodiment includes error detection and error correction. Error detection means that the controller 102 can detect whether an error occurs in the data stored in the storage medium 103 according to the ECC; error correction means that the controller 102 can correct the erroneous data stored in the storage medium 103 according to the ECC to obtain correct data.

[0062] Therefore, the data amount of the ECC generated by the controller 102 may be greater than or equal to a threshold value, which is determined according to the amount of the first data. Normally, the data amount of the generated ECC will be less than the amount of the first data. For example, the first data may be 256 bits of data, then the data amount of the generated ECC may be 144 bits (or more than 144 bits, etc.). Accordingly, the number of rows of the coding matrix for generating the ECC may be determined according to the amount of data written to the storage space by the controller 102 when performing a data write operation and the data amount of the ECC corresponding to the data, and the coding matrix has the property that any submatrix is ​​reversible.

[0063] For example, if Figure 3 As shown in FIG. 1 , assuming that the number of data written into the storage space by the controller 102 in one write operation is (n×m) bits, the data to be written can be arranged into n data blocks, each data block can include m bits, n and m are both positive integers greater than 1, and the data in each data block can constitute a data symbol. Then, the controller 102 can adopt the following method: Figure 3 The coding matrix shown in FIG. 1 includes (n×(n+k)) data blocks. The values ​​of the data blocks included in each of the first n rows in the coding matrix are as follows: Figure 3As shown, the value of the data block included in each row from the (n+1)th row to the (n+kth row) in the coding matrix can be predefined according to the coding algorithm. Then, the controller 102 can multiply the coding matrix with the matrix composed of n data blocks to obtain the following: Figure 3 The encoding result shown in FIG. 1 includes (n+k) data blocks. The first n data blocks are the data to be written, and the (n+1)th to (n+k)th data blocks are the ECCs corresponding to the data. In this way, the controller 102 can generate (k×m) bits of ECC during a write operation, so that the (n×m) bits of data and the (k×m) bits of ECC can be stored in the storage medium 103 later.

[0064] In actual application, the amount of the first data to be stored may be greater than (n×m) bits, then the controller 102 may perform multiple write operations on the first data, and generate corresponding ECCs during each write operation, so as to generate ECCs corresponding to the first data. For example, assuming that n is 64, m is 8, and k is 36, the amount of data written into the storage space by the controller 102 during one write operation is 512 bits, and each time the controller 102 writes 512 bits, the 288-bit ECC corresponding to the 512 bits will be written together. When the amount of the first data is 256 bytes (i.e., 2048 bits), the controller 102 may perform 4 data write operations, and each time a data write operation is performed, a 288-bit ECC will be generated for the 512 bits written, and the total amount of ECCs corresponding to the first data is 1152 bits (288bit×4), i.e., 144 bytes.

[0065] In this embodiment, the controller 102 can divide the ECC generated for the first data into two parts, which are referred to as the first ECC and the second ECC below. Each ECC has an error correction capability for the first data, and the error correction capability of the complete ECC (i.e., the first ECC + the second ECC) is higher than the error correction capability of any one of the ECCs.

[0066] As an implementation example, the number of the first part ECC can be determined according to the number of the first data. Specifically, the controller 102 can determine the data amount of the first part ECC according to the number of the first data, and determine the first part ECC from the generated complete ECC according to the data amount of the first part ECC. For example, when the first data includes 512 bits, the controller 102 can generate a 288-bit complete ECC, and further determine that the data amount of the first part ECC is 128 bits. At this time, the ratio between the number of the first data and the data amount of the first part ECC can be 4:1.

[0067] Furthermore, the complete ECC generated by the controller 102 may include multiple symbols, such as Figure 3 The K symbols (ie, symbols C1 to Ck) shown in FIG. 1 include each symbol including a preset number of bits of data, such as 8 bits of data.

[0068] Then, in one example, in the process of determining the first partial ECC from the complete ECC, the controller 102 can select multiple consecutive symbols from the complete ECC according to the data amount of the first partial ECC, such as consecutively selecting symbol C1, symbol C2, ..., symbol Cx as the first partial ECC (including x symbols), and the remaining symbols Cx+1 to symbol Ck can be used as the second partial ECC (including kx symbols).

[0069] In another example, the controller 102 can select multiple discontinuous symbols from the complete ECC based on the data amount of the first partial ECC, such as selecting symbol C1, symbol C2, symbol C3, symbol C4, and selecting symbol C9, symbol C10, ..., symbol Cx+4 as the first partial ECC (including x symbols), and the remaining symbols C5, symbol C6, symbol C7, symbol C8, symbol Cx+5 to symbol Ck can be used as the second partial ECC (including kx symbols).

[0070] It should be noted that the above-mentioned implementation methods of determining the first partial ECC are only some exemplary descriptions. In other embodiments, the controller 102 may also select the first partial ECC from the complete ECC based on other methods, which is not limited to this.

[0071] The data amount of the first partial ECC may be different from the data amount of the second partial ECC. For example, assuming that the data amount of the complete ECC generated by the controller 102 is 144 bytes, the data amount of the first partial ECC may be 64 bytes, and the data amount of the second partial ECC may be 80 bytes. Alternatively, the data amount of the first partial ECC may be the same as the data amount of the second partial ECC.

[0072] In addition, the first partial ECC can be any part of the ECC in the complete ECC. For example, the first partial ECC can be Figure 3 The (n+1)th to (n+x)th data blocks in the equation, x is a positive integer less than k, and the second part of the ECC is Figure 3 For example, the first part of ECC can be Figure 3 The (n+5) to (n+8) data blocks in the first part of the ECC are Figure 3 The (n+1)th to (n+4)th data blocks, and the (n+8)th to (n+k)th data blocks.

[0073] S203 : the controller 102 writes the first data and the first part of the ECC into the first storage space in the storage medium 103 .

[0074] S204 : the controller 102 writes the second partial ECC into the second storage space in the storage medium 103 .

[0075] In this embodiment, the controller 102 may divide two storage spaces in the storage medium 103 for the first data, namely a first storage space and a second storage space, and the two storage spaces are used to store the first data to be stored and the ECC.

[0076] When storing data, the controller 102 writes all first data into one storage space, and writes different parts of the complete ECC into different storage spaces. Specifically, the controller 102 writes the first data and the first part of the ECC into the first storage space, and writes the second part of the ECC into the second storage space.

[0077] The following describes the implementation process of the controller 102 writing the first data into the storage space and the ECC implementation process for different implementation modes of the storage space.

[0078] In a first implementation, the first storage space and the second storage space are two different storage spaces on the same storage medium; or the first storage space and the second storage space are storage spaces of the same type but on different storage media. Then, the data storage method in the first storage space matches the data storage method in the second storage space.

[0079] For example, the first storage space can be divided into regions according to a ratio of 4:1, including: Figure 4The data storage area and the ECC storage area shown in the figure, wherein the size of the data storage area is 4 times the size of the ECC storage area. When the controller 102 writes the first data and the first part of the ECC into the first storage space, the data amount of the first part of the ECC is one-fourth of the amount of the first data. Assuming that the amount of the first data is 256 bytes, the data amount of the first part of the ECC is 64 bytes. Then, the controller 102 can write the 256-byte first data into the data storage area in the first storage space, and write the 64-byte first part of the ECC into the ECC storage area in the first storage space, as shown in FIG. Figure 4 shown.

[0080] Similarly, the second storage space can also be divided into regions in a ratio of 4:1, such as Figure 4 As shown in FIG. 1 , the size of area 1 is 4 times the size of area 2. When the controller 102 writes the second part of the ECC into the second storage space, the controller 102 may further divide the second part of the ECC into a first subset and a second subset at a ratio of 4:1, wherein the amount of data in the first subset is 4 times the amount of data in the second subset. Assuming that the amount of data in the second part of the ECC is 80 bytes, the amount of data in the first subset is 64 bytes, and the amount of data in the second subset is 16 bytes. Then, the controller 102 may write the first subset of 64 bytes in the second part of the ECC into area 1, and write the second subset of 16 bytes in the second part of the ECC into area 2, as shown in FIG. Figure 4 shown.

[0081] At this time, the size of the first storage space may be different from the size of the second storage space. For example, the size of the first storage space may be one quarter of the size of the second storage space, thereby effectively saving storage resources required for data storage.

[0082] Further, when the first storage space and the second storage space are different storage spaces on the same storage medium, the first storage space can be implemented using the first part of the storage particles on the storage medium, and the second storage space can be implemented using the second part of the storage particles on the storage medium. In addition, the storage particles corresponding to the first storage space and the storage particles corresponding to the second storage space belong to different channels. In this case, the first storage space and the second storage space can correspond to different channels on the storage medium 103. Alternatively, the storage particles corresponding to the first storage space and the storage particles corresponding to the second storage space belong to different columns. In this case, the first storage space and the second storage space can correspond to different columns on the storage medium 103. In this way, the storage particles corresponding to the two storage spaces are independent of each other.

[0083] For example, if Figure 5As shown, the storage medium 103 may have two channels, namely channel 0 and channel 1, wherein each channel may include one or more columns. Figure 5 In the example, each channel includes 4 columns. Each column can include multiple storage particles. Figure 5 In the example, each column includes 8 storage channels. Then, the first storage space and the second storage space can be storage space A in channel 0 and storage space B in channel 1, respectively; or, the first storage space and the second storage space can be storage space A in column 0 included in channel 0 and storage space C in column 3 included in channel 0, respectively.

[0084] In this way, the first storage space and the second storage space are implemented using storage particles on different channels or different columns, which can effectively reduce the probability of simultaneous failure of storage particles corresponding to the two storage spaces. In actual application scenarios, the probability of simultaneous failure of storage particles on different channels or different columns is close to 0; and based on the simulation test of the standard test set SPECint2017, it can be determined that the reliability of using two storage spaces to store the first data is similar to the reliability of mirroring the first data.

[0085] In a second implementation, the first storage space and the second storage space are storage spaces on different types of storage media, such as the first storage space is located on a DIMM, and the second storage space is located on an SCM. In this case, the data storage method in the first storage space may be different from the data storage method in the second storage space. For example, the first storage space may be divided into regions at a ratio of 4:1, and the controller 102 may write the first data and the first part of the ECC into the first storage space in the same manner as described above. Figure 4 The method shown is the same; and there is no need to divide the area in the second storage space. When the controller 102 writes the second part of the ECC into the second storage space, it can directly write the second part of the ECC into a continuous address area in the second storage space, without the need to store the second part of the ECC separately in a 4:1 ratio.

[0086] In actual application, after completing the writing of the first data and the ECC, the controller 102 may also return a notification of successful data writing to the processor 101 .

[0087] Since the first data can be stored in only one storage space during data storage, and the amount of ECC data stored in multiple different storage spaces is usually smaller than the amount of the first data, this can effectively reduce the storage resources required for data storage. In addition, not only can the first part of the ECC correct errors for the first data, but the complete ECC (i.e., the first part of the ECC + the second part of the ECC) can also correct errors for the first data based on a higher error correction capability, which can effectively ensure the reliability of the first data storage.

[0088] To further understand that different partial ECCs stored in the two storage spaces can ensure the reliability of the first data storage, the following further introduces the process of the controller 102 using the first partial ECC and the second partial ECC to correct the errors of the read first data. Figure 2 The method shown may also include the following steps.

[0089] S205: The processor 101 sends a read command for reading first data to the controller 102.

[0090] Typically, the controller 102 can execute an operation process of reading data from the storage medium 103 under a read command from the processor 101. The read command may include information indicating the storage address and data size of the first data, so that the controller 102 can determine the first data to be read according to the read command.

[0091] S206: The controller 102 reads the first data and the first part of the ECC in the first storage space.

[0092] S207: The controller 102 analyzes the first data according to the first partial ECC to obtain an analysis result.

[0093] In this embodiment, the controller 102 may determine whether the read first data has an uncorrected error (UCE) according to the first partial ECC.

[0094] The first partial ECC has an error correction capability for the first data, and the error correction capability is related to the data volume of the first ECC. Generally, the higher the data volume of the first partial ECC, the higher the error correction capability for the first data.

[0095] When the first data is stored on the storage medium 103, the voltage of some storage cells may change unexpectedly, resulting in storage errors in the data stored in the first data using the some storage cells, so that some data in the first data read by the controller 102 may have errors. Therefore, after reading the first part of the ECC and the first data, the controller 102 can analyze the first data using the first ECC to obtain a corresponding analysis result, which can be used to indicate whether the read first data has errors.

[0096] If the controller 102 determines that no error occurs in the first data according to the analysis result, the controller 102 may directly return the first data to the processor 101 , for example, by feeding the first data back to the processor 101 via a DDR bus.

[0097] If the controller 102 determines, based on the analysis result, that an error occurs in the first data, but the error is a correctable error (corrected error, CE) based on the first partial ECC, the controller 102 can use the first partial ECC to correct the error of the read first data to obtain correct data, hereinafter referred to as target data 2. Then, the controller 102 feeds back the target data 2 to the memory 101 so that the processor 101 obtains the correct first data (i.e., target data 2).

[0098] The controller 102 uses ECC to correct data errors. There are related applications in actual application scenarios, and the specific implementation of the error correction process will not be described in detail.

[0099] If it is determined that an error occurs in the first data, and the error is an uncorrectable error based on the first partial ECC (ie, exceeds the error correction capability of the first partial ECC), the controller 102 may continue to execute subsequent steps to correct the errors of the read first data.

[0100] S208: When the analysis result indicates that the read first data has an uncorrectable error, the controller 102 reads a second portion of the ECC in the second storage space.

[0101] S209 : The controller 102 performs error correction on the read first data according to the first partial ECC and the second partial ECC to obtain target data 1 .

[0102] It can be understood that, since the error correction capability of the complete ECC is higher than that of the first partial ECC, when the controller 102 cannot correct the error of the read first data only according to the first partial ECC, the controller 102 can read the second partial ECC from the second storage space. In this way, the controller 102 can combine the first partial ECC and the second partial ECC to obtain a complete ECC, so that the complete ECC with higher error correction capability can be used to correct the first data to obtain correct data, which is hereinafter referred to as target data 1.

[0103] Taking the controller 102 performing RS encoding on the first data as an example, assuming that the amount of the first data is 512 bits, the controller 102 can encode the first data in the encoding format of (100, 64) RS8, that is, the controller 102 can generate a data symbol with 8 bits of data as a unit, so that 64 data symbols can be generated according to the first data. In addition, the controller 102 will also generate 36 ECC symbols for error correction of the first data for the 512 bits of data, such as Figure 6 As shown, the number of all symbols is 100 (64+36). The first part of the ECC may include 16 ECC symbols, which are stored in the first storage space; the second part of the ECC may include 20 ECC symbols, which are stored in the second storage space. Figure 6 shown.

[0104] When the controller 102 uses the first part of the ECC to perform error correction on 64 data symbols (i.e., the first data), at most 8 (i.e., 16 / 2) data symbols with errors can be corrected. That is, the number of data symbols that can be corrected by the first part of the ECC is half of the number of symbols corresponding to the first part of the ECC.

[0105] When the number of erroneous data symbols is greater than 8, the controller 102 can use 36 data symbols (including the first part ECC and the second part ECC) to correct 64 data symbols, and can correct up to 18 (ie, 36 / 2) erroneous data symbols.

[0106] Therefore, when the number of erroneous data symbols does not exceed 8, the controller 102 can directly use the 16 ECC symbols in the first storage space to complete data error correction, and feedback the correct first data to the processor 101. When the number of erroneous data symbols exceeds 8 but does not exceed 18, the controller 102 can use all 36 ECC symbols to complete data error correction, and feedback the correct first data to the processor 101. When the number of erroneous data symbols exceeds 18, the controller 102 can feedback notification information such as data storage error or data reading failure to the processor 102.

[0107] S210: The controller 102 feeds back the target data 1 to the processor 101, so that the processor 101 can obtain the correct first data (ie, the target data 1).

[0108] In this embodiment, since the first part of the ECC also has the error correction capability for ECC, in most scenarios of reading the first data, the controller 102 can only use the first part of the ECC to complete the error correction of the read first data, and there is no need to read the second part of the ECC from the second storage space. This can ensure that the performance of the processor 101 in reading the first data reaches a high level.

[0109] Moreover, when the first partial ECC cannot achieve error correction, the controller 102 can use the complete ECC with higher error correction capability to correct the read first data, which can ensure that the processor 101 can obtain the correct first data, thereby ensuring the reliability of the first data stored in the storage medium 103.

[0110] It is worth noting that the above is an exemplary description using the storage and reading of the first data by the controller 102 as an example. For other data provided by the processor 102, the controller 102 can use a similar method to store and read the other data to improve the reliability of data storage. Alternatively, the controller 102 can use different read and write methods to store and read other data provided by the processor 101. The following is an exemplary description using the controller 102 reading and writing the second data in other ways as an example.

[0111] In a first possible implementation, the controller 102 may detect whether the second data meets the reliability storage condition after receiving the second data provided by the processor 101. Exemplarily, detecting whether the second data meets the reliability storage condition may be, for example, detecting whether the importance level sent by the processor 101 for the second data indicates that the second data is to be reliably stored.

[0112] For example, the processor 101 can not only provide the second data to the controller 102, but also provide the controller 102 with the importance level corresponding to the second data. The importance level of the data can be indicated, for example, by using a corresponding flag bit. When the value of the flag bit is "1", it represents that the importance level of the data is high, that is, the second data meets the reliability storage condition, then the controller 102 can refer to the above-mentioned process of storing the first data to store the data. When the value of the flag bit is "0", it represents that the importance level of the data is low, that is, the second data does not meet the reliability storage condition, then the controller 102 can use other storage methods to store the data.

[0113] In this embodiment, assuming that the second data does not meet the reliability storage condition, the controller 102 can encode the second data using a new encoding matrix to obtain the ECC corresponding to the second data. Wherein, when the quantity of the first data and the second data is the same, the data amount of the ECC generated by the controller 102 for the second data is less than the data amount of the ECC generated for the first data.

[0114] Then, the controller 102 may divide a third storage space in the storage medium 103, and the third storage space does not overlap with the first storage space and the second storage space. In addition, the controller 102 may write the second data and the ECC corresponding to the second data into the third storage space (i.e., there is no need to use multiple storage spaces to store the ECC corresponding to the second data).

[0115] Accordingly, when the processor 101 instructs the controller 102 to read the second data, the controller 102 can read the second data and the ECC corresponding to the second data at the same time, and use the ECC to detect whether the read second data has an error. When no error occurs, the controller 102 can directly feed back the read second data to the processor 101; when an error occurs, the controller 102 uses the ECC to correct the read second data to obtain the correct second data, and feeds back the correct second data obtained after error correction to the processor 101.

[0116] In a second possible implementation, after receiving the second data provided by the processor 101, the controller 102 may detect whether it has received indication information of the processor 101 for reliability storage of the second data, and the indication information may be, for example, a reliability storage label. If the indication information is received, the controller 102 may determine that the second data meets the reliability storage condition, and store the first data in accordance with the above-mentioned storage method for the first data. Assuming that the controller 102 does not receive the indication information, the controller 102 may determine that the second data does not meet the reliability storage condition. At this time, the controller 102 may directly write the second data into the third storage space created in the storage medium 103, i.e., there is no need to generate and store ECC for the second data.

[0117] Accordingly, when the processor 101 requests the controller 102 to read the second data, the controller 102 can directly feed back the read second data to the processor 101 without performing error detection and error correction on the read second data.

[0118] It can be understood that the above implementation examples are only for illustrative purposes. In actual applications, the controller 102 may also use other methods to store and read the second data, and this is not limited.

[0119] In this way, in the storage medium 103, for data with higher requirements for data storage reliability (such as the first data), the controller 102 can flexibly divide the data into corresponding multiple storage spaces according to the address space and the storage space to store the data and its corresponding ECC. For data with lower requirements for data storage reliability, there is no need to divide it into multiple storage spaces to store the data and its corresponding ECC, or there is no need to store ECC for the data, etc., thereby supporting multiple data storage methods and improving the flexibility of data storage.

[0120] It is worth noting that other reasonable step combinations that can be thought of by those skilled in the art based on the above description also fall within the scope of protection of this application. Secondly, those skilled in the art should also be familiar with the fact that the embodiments described in the specification are all preferred embodiments, and the actions involved are not necessarily required by this application.

[0121] Combination of the above Figures 1 to 6 The data storage method provided in the embodiment of the present application is introduced, and then the controller provided in the embodiment of the present application is introduced with reference to the accompanying drawings.

[0122] See also Figure 7 , which shows a schematic diagram of the structure of a controller. Figure 7 As shown, the controller 700 includes:

[0123] An acquisition module 701 is used to acquire first data to be stored;

[0124] A generating module 702 is used to generate an error correction code ECC according to the first data, wherein the ECC includes a first part ECC and a second part ECC, the ECC is used to correct errors of the first data, and the error correction capability of the ECC for the first data is higher than the error correction capability of the first part ECC for the first data;

[0125] The writing module 703 is used to write the first data and the first part of the ECC into the first storage space; and write the second part of the ECC into the second storage space.

[0126] In a possible implementation manner, the controller 700 further includes:

[0127] A reading module 704, configured to read the first part of the ECC and the first data in the first storage space in response to a read instruction sent by the processor;

[0128] An analysis module 705 is used to analyze the first data according to the first part of ECC to obtain an analysis result;

[0129] The reading module 704 is further configured to read the second part of the ECC in the second storage space when the analysis result indicates that the first data read has an uncorrectable error;

[0130] An error correction module 706, configured to perform error correction on the read first data according to the first partial ECC and the second partial ECC to obtain first target data;

[0131] The feedback module 707 is used to feed back the first target data to the processor.

[0132] In a possible implementation manner, the writing module 703 is used to:

[0133] Determining the data amount of the first partial ECC according to the amount of the first data;

[0134] determining the first partial ECC from the ECC according to the data amount;

[0135] The first data and the first partial ECC are written into the first storage space.

[0136] In a possible implementation manner, the writing module 703 is used to:

[0137] According to the data amount, a plurality of continuous symbols are selected from the ECC, each of the plurality of symbols includes a preset number of bits of data, and the first partial ECC is the plurality of symbols.

[0138] In a possible implementation manner, the first storage space and the second storage space are located in a storage medium, and the storage medium further includes a third storage space;

[0139] The acquisition module 701 is used to acquire the second data to be stored;

[0140] The generating module 702 is used to generate an ECC corresponding to the second data;

[0141] The writing module 703 is used to write the second data and the ECC corresponding to the second data into the third storage space when the second data does not meet the reliability storage condition.

[0142] In a possible implementation, the storage medium used by the first storage space is the same as the storage medium used by the second storage space, and the data storage method in the first storage space matches the data storage method in the second storage space.

[0143] In a possible implementation manner, the storage particles corresponding to the first storage space and the storage particles corresponding to the second storage space belong to different channels or columns.

[0144] In a possible implementation manner, the first storage space and the second storage space are storage spaces in a memory;

[0145] Alternatively, the first storage space and the second storage space are used to persistently store the first data.

[0146] In a possible implementation, the generating module 702 is used to:

[0147] Get the encoding matrix;

[0148] The first data is encoded using the encoding matrix to obtain an ECC corresponding to the first data, wherein a data amount of the ECC corresponding to the first data is greater than or equal to a threshold, and the threshold is determined based on the amount of the first data.

[0149] because Figure 7 The controller 700 shown corresponds to Figure 2 The controller 102 in the method shown, therefore Figure 7 The specific implementation method of the controller 700 shown and its technical effects can be found in the relevant descriptions of the aforementioned embodiments, and will not be elaborated here.

[0150] Figure 8 A schematic diagram of the hardware structure of a controller 800 provided in this application, the controller 800 can, for example, implement the above Figure 2 The controller 102 in the illustrated embodiment etc.

[0151] like Figure 8 As shown, the controller 800 includes a processor 801, a memory 802, and a communication interface 803. The processor 801, the memory 802, and the communication interface 803 communicate via a bus 804, and may also communicate via other means such as wireless transmission. The memory 802 is used to store instructions, and the processor 801 is used to execute the instructions stored in the memory 802. Furthermore, the controller 800 may also include a memory unit 805, and the memory unit 805 may be connected to the processor 801, the storage medium 802, and the communication interface 803 via a bus 804. The memory 802 stores program code, and the processor 801 may call the program code stored in the memory 802 to perform the following operations:

[0152] Acquire first data to be stored;

[0153] generating an error correction code ECC according to the first data, the ECC comprising a first part ECC and a second part ECC, the ECC being used to correct errors of the first data, and the error correction capability of the ECC for the first data being higher than the error correction capability of the first part ECC for the first data;

[0154] Writing the first data and the first part of ECC into a first storage space;

[0155] The second part of the ECC is written into the second storage space.

[0156] It should be understood that in the embodiment of the present application, the processor 801 may be a CPU, and the processor 801 may also be other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field programmable gate arrays (FPGAs) or other programmable logic devices, discrete gate or transistor logic devices, discrete device components, etc. A general-purpose processor may be a microprocessor or any conventional processor, etc.

[0157] The memory 802 may include a read-only memory and a random access memory, and provides instructions and data to the processor 801. The memory 802 may also include a nonvolatile random access memory.

[0158] The memory 802 may be a volatile memory or a nonvolatile memory, or may include both volatile and nonvolatile memories. Among them, the nonvolatile memory may be a read-only memory (ROM), a programmable ROM (PROM), an erasable PROM (EPROM), an electrically erasable programmable ROM (EEPROM), or a flash memory. The volatile memory may be a random access memory (RAM), which is used as an external cache. By way of example and not limitation, many forms of RAM are available, such as static RAM (SRAM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), double data rate synchronous dynamic random access memory (DDR SDRAM), enhanced synchronous dynamic random access memory (ESDRAM), synchronous link DRAM (SLDRAM), and direct rambus RAM (DR RAM).

[0159] The communication interface 803 is used to communicate with other devices connected to the controller 800, such as a processor. In addition to the data bus, the bus 804 may also include a power bus, a control bus, and a status signal bus. However, for the sake of clarity, various buses are labeled as bus 804 in the figure.

[0160] It should be understood that the controller 800 according to the embodiment of the present application may correspond to the controller 102 in the embodiment of the present application, and may correspond to the controller 800 executing the operation according to the embodiment of the present application. Figure 2 The method executed by the controller 102 in the method shown, the above and other operations and / or functions implemented by the controller 800 are respectively to achieve Figure 2 For the sake of brevity, the process of the corresponding method in will not be repeated here.

[0161] Fig. 9 The hardware structure diagram of a controller 900 provided in this application is shown in FIG. 9 . The controller 900 can implement the above Figure 2 The controller 102 in the illustrated embodiment, etc. Fig. 9As shown, the controller 900 includes a power supply circuit 901 and a processing circuit 902, wherein the power supply circuit 901 is used to supply power to the processing circuit 902, and the processing circuit 902 is used to perform the following operations:

[0162] Acquire first data to be stored;

[0163] generating an error correction code ECC according to the first data, the ECC comprising a first part ECC and a second part ECC, the ECC being used to correct errors of the first data, and the error correction capability of the ECC for the first data being higher than the error correction capability of the first part ECC for the first data;

[0164] Writing the first data and the first part of ECC into a first storage space;

[0165] The second part of the ECC is written into the second storage space.

[0166] It should be understood that the controller 900 according to the embodiment of the present application may correspond to the controller 102 in the embodiment of the present application, and may correspond to the controller executing the operation according to the embodiment of the present application. Figure 2 The method executed by the controller 102 in the method shown, the above and other operations and / or functions implemented by the controller 900 are respectively to achieve Figure 2 For the sake of brevity, the process of the corresponding method in will not be repeated here.

[0167] An embodiment of the present application further provides a control device, which includes the controller described in each of the above embodiments, and the control device can implement the methods or functions performed by the controller in each of the above embodiments.

[0168] The embodiment of the present application also provides a computer-readable storage medium. The computer-readable storage medium can be any available medium that the control device can store or a data storage device such as a data center containing one or more available media. The available medium can be a magnetic medium (e.g., a floppy disk, a hard disk, a tape), an optical medium (e.g., a DVD), or a semiconductor medium (e.g., a solid-state hard disk). The computer-readable storage medium includes instructions that instruct the control device to execute the above-mentioned data storage method.

[0169] The embodiment of the present application also provides a computer program product. The computer program product includes one or more computer instructions. When the computer instructions are loaded and executed on a control device, the process or function described in the embodiment of the present application is generated in whole or in part.

[0170] The computer instructions may be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, the computer instructions may be transmitted from one website, computer or data center to another website, computer or data center via wired (e.g., coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) means.

[0171] The computer program product may be a software installation package, which may be downloaded and executed on a computing device when any of the aforementioned data storage methods is required.

[0172] The above embodiments can be implemented in whole or in part by software, hardware, firmware or any other combination. When implemented using software, the above embodiments can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded or executed on a computer, the process or function described in the embodiment of the present application is generated in whole or in part. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, the computer instructions can be transmitted from a website site, computer, server or data center to another website site, computer, server or data center by wired (e.g., coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) mode. The computer-readable storage medium can be any available medium that a computer can access or a data storage device such as a server or data center that contains one or more available media sets. The available medium can be a magnetic medium (e.g., a floppy disk, a hard disk, a tape), an optical medium (e.g., a DVD), or a semiconductor medium. The semiconductor medium can be a solid-state hard disk.

[0173] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any technician familiar with the technical field can easily think of various equivalent modifications or replacements within the technical scope disclosed in the present application, and these modifications or replacements should be included in the protection scope of the present application. Therefore, the protection scope of the present application shall be based on the protection scope of the claims.

Claims

1. A data storage method, characterized in that: The method comprises: Acquire first data to be stored; generating an error correction code ECC according to the first data, the ECC comprising a first partial ECC and a second partial ECC, the ECC being used to correct errors of the first data, and the error correction capability of the ECC for the first data being higher than the error correction capability of the first partial ECC for the first data; Writing the first data and the first part of ECC into a first storage space; The second part of the ECC is written into the second storage space.

2. The method according to claim 1, characterized in that The method further comprises: In response to a read instruction sent by a processor, read the first portion of ECC and the first data in the first storage space; Analyze the first data according to the first part of ECC to obtain an analysis result; When the analysis result indicates that the read first data has an uncorrectable error, reading the second part of the ECC in the second storage space; According to the first partial ECC and the second partial ECC, error correction is performed on the read first data to obtain first target data; The first target data is fed back to the processor.

3. The method according to claim 1 or 2, characterized in that: Writing the first data and the first part of the ECC into the first storage space includes: Determining the data amount of the first partial ECC according to the amount of the first data; determining the first partial ECC from the ECC according to the data amount; The first data and the first partial ECC are written into the first storage space.

4. The method according to claim 3, characterized in that The determining the first partial ECC from the ECC according to the data amount includes: According to the data amount, a plurality of continuous symbols are selected from the ECC, each of the plurality of symbols includes a preset number of bits of data, and the first partial ECC is the plurality of symbols.

5. The method according to any one of claims 1 to 4, characterized in that: The first storage space and the second storage space are located in a storage medium, and the storage medium also includes a third storage space; The method further comprises: Acquire second data to be stored; generating an ECC corresponding to the second data; When the second data does not meet the reliability storage condition, the second data and the ECC corresponding to the second data are written into the third storage space.

6. The method according to any one of claims 1 to 5, characterized in that: The storage medium used by the first storage space is the same as the storage medium used by the second storage space, and the data storage method in the first storage space matches the data storage method in the second storage space.

7. The method according to any one of claims 1 to 6, characterized in that: The storage particles corresponding to the first storage space and the storage particles corresponding to the second storage space belong to different channels or columns.

8. The method according to any one of claims 1 to 7, characterized in that: The first storage space and the second storage space are storage spaces in the memory; Alternatively, the first storage space and the second storage space are used to persistently store the first data.

9. The method according to any one of claims 1 to 8, characterized in that: Generating an error correction code ECC according to the first data includes: Get the encoding matrix; The first data is encoded using the encoding matrix to obtain an ECC corresponding to the first data, wherein a data amount of the ECC corresponding to the first data is greater than or equal to a threshold, and the threshold is determined based on the amount of the first data.

10. A controller, characterized in that: The controller comprises: An acquisition module, used for acquiring first data to be stored; a generating module, configured to generate an error correction code ECC according to the first data, the ECC comprising a first partial ECC and a second partial ECC, the ECC being used to correct errors of the first data, and having a higher error correction capability of the ECC for the first data than that of the first partial ECC for the first data; A writing module is used to write the first data and the first part of the ECC into a first storage space; and write the second part of the ECC into a second storage space.

11. The controller according to claim 10, characterized in that: The controller further comprises: a reading module, configured to read the first part of the ECC and the first data in the first storage space in response to a reading instruction sent by the processor; An analysis module, configured to analyze the first data according to the first part of the ECC to obtain an analysis result; The reading module is further configured to read the second part of the ECC in the second storage space when the analysis result indicates that the first data read has an uncorrectable error; an error correction module, configured to perform error correction on the read first data according to the first partial ECC and the second partial ECC to obtain first target data; A feedback module is used to feed back the first target data to the processor.

12. The controller according to claim 10 or 11, characterized in that: The writing module is used for: Determining the data amount of the first partial ECC according to the amount of the first data; determining the first partial ECC from the ECC according to the data amount; The first data and the first partial ECC are written into the first storage space.

13. The controller according to claim 12, characterized in that: The writing module is used for: According to the data amount, a plurality of continuous symbols are selected from the ECC, each of the plurality of symbols includes a preset number of bits of data, and the first partial ECC is the plurality of symbols.

14. The controller according to any one of claims 10 to 13, characterized in that: The first storage space and the second storage space are located in a storage medium, and the storage medium also includes a third storage space; The acquisition module is used to acquire the second data to be stored; The generating module is used to generate the ECC corresponding to the second data; The writing module is used to write the second data and the ECC corresponding to the second data into the third storage space when the second data does not meet the reliability storage condition.

15. The controller according to any one of claims 10 to 14, characterized in that: The storage medium used by the first storage space is the same as the storage medium used by the second storage space, and the data storage method in the first storage space matches the data storage method in the second storage space.

16. The controller according to any one of claims 10 to 15, characterized in that: The storage particles corresponding to the first storage space and the storage particles corresponding to the second storage space belong to different channels or columns.

17. The controller according to any one of claims 10 to 16, characterized in that: The first storage space and the second storage space are storage spaces in the memory; Alternatively, the first storage space and the second storage space are used to persistently store the first data.

18. The controller according to any one of claims 10 to 17, characterized in that: The generating module is used for: Get the encoding matrix; The first data is encoded using the encoding matrix to obtain an ECC corresponding to the first data, wherein a data amount of the ECC corresponding to the first data is greater than or equal to a threshold, and the threshold is determined based on the amount of the first data.

19. A controller, characterized in that: The method comprises a power supply circuit and a processing circuit, wherein the power supply circuit is used to supply power to the processing circuit, and the processing circuit is used to execute the method according to any one of claims 1 to 9.

20. A controller, characterized in that: Including processor and memory; The processor is configured to execute instructions stored in the memory so as to enable the computing device to perform the steps of the method according to any one of claims 1 to 9.

21. A control device, characterized in that: The control device comprises the controller according to any one of claims 10 to 20.

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