Data processing methods, apparatus, computer equipment and storage media

Abstract

This application relates to a data processing method, apparatus, computer device, storage medium, and computer program product. The method includes retrieving complex data to be processed from memory; storing the real part of each complex data in a first storage segment of a cache; storing the imaginary part of each complex data in a second storage segment of the cache; performing calculations on the real parts of the data in the first storage segment using a vector arithmetic unit in the Ascend NPU to obtain real part calculation results; and performing calculations on the imaginary parts of the data in the second storage segment to obtain imaginary part calculation results. This method can improve data processing efficiency.

Description

Technical Field

[0001] This application relates to the field of computer technology, and in particular to a data processing method, apparatus, computer equipment, storage medium, and computer program product. Background Technology

[0002] Polar coordinate operators, through their forward computation function, transform a set of real tensor coordinates x and y into an imaginary tensor z using polar coordinates. This transformation is commonly used in imaginary number computation processing for intelligent speech, image processing, and signal processing. The computation of polar coordinate operators is deployed in GPUs, such as the CPU backend and CUDA backend in the PyTorch framework. However, directly porting the CUDA backend code to the Ascend NPU would consume significant computational resources and be inefficient. Summary of the Invention

[0003] Therefore, it is necessary to provide a data processing method, apparatus, computer equipment, computer-readable storage medium, and computer program product that can improve computing efficiency in response to the above-mentioned technical problems.

[0004] Firstly, this application provides a data processing method. Applied to the Ascend NPU, the method includes:

[0005] Retrieve each complex number data to be processed from memory, store the real part of each complex number data in the first storage segment of the cache, and store the imaginary part of each complex number data in the second storage segment of the cache;

[0006] The vector arithmetic unit in the Ascend NPU performs calculations on each real part of the data in the first storage segment to obtain the real part calculation result, and performs calculations on each imaginary part of the data in the second storage segment to obtain the imaginary part calculation result;

[0007] Based on the first storage location change function, the real part calculation result of each complex number is obtained from the first storage segment and the corresponding imaginary part calculation result is obtained from the second storage segment, and the real part calculation result and the imaginary part calculation result of each complex number are stored in the memory accordingly.

[0008] In one embodiment, the step of obtaining the real part calculation result of each complex number data from the first storage segment and the corresponding imaginary part calculation result from the second storage segment based on the first storage location change function includes:

[0009] Based on the first storage location change function, the first position information of the real part calculation result and the second position information of the corresponding imaginary part calculation result are obtained from the first mask tensor array; wherein, the real part calculation result and the imaginary part calculation result appear alternately in the first mask tensor array;

[0010] Based on the first location information, the real part calculation result is obtained from the first storage segment, and based on the second location information, the imaginary part calculation result is obtained from the second storage segment.

[0011] In one embodiment, after retrieving the complex data to be processed from memory, the method further includes:

[0012] Obtain the gradient data to be processed from the memory;

[0013] Based on the second storage location change function, the real part of each gradient data in each gradient data is stored in the first cache segment of the cache, and the imaginary part of each gradient data is stored in the second cache segment of the cache.

[0014] And the third cache segment of the cache stores the real part of each complex data in the complex data, and the fourth cache segment of the cache stores the imaginary part of each complex data in the complex data;

[0015] The data corresponding to the first cache segment, the second cache segment, the third cache segment, and the fourth cache segment are fused to obtain the target data.

[0016] In one embodiment, the target data includes the magnitude of the gradient data, and the process of fusing the data corresponding to the first cache segment, the second cache segment, the third cache segment, and the fourth cache segment to obtain the target data includes:

[0017] Invert each virtual part of the data in the second cache segment to obtain inverted data, and then overwrite the inverted data storage into the second cache segment.

[0018] Divide each real part data in the third buffer segment by the length of the corresponding complex modulus of the gradient data to obtain the processed real part data, and store the processed real part data in the fifth buffer segment;

[0019] Divide each imaginary data in the fourth cache segment by the length of the corresponding complex modulus of the gradient data to obtain the processed imaginary data, and store the processed imaginary data in the sixth cache segment;

[0020] The real data processed in the fifth cache segment and the real data in the first cache segment are fused together to obtain the first fused data;

[0021] The processed virtual part data in the sixth cache segment and the virtual part data in the second cache segment are fused to obtain the second fused data;

[0022] The first fused data and the second fused data are fused to obtain the magnitude of the gradient data.

[0023] In one embodiment, the target data includes the angle data of the gradient data, and the step of fusing the data corresponding to the first cache segment, the second cache segment, the third cache segment, and the fourth cache segment to obtain the target data includes:

[0024] Invert each imaginary part of the data in the fourth cache segment to obtain inverted data, and store the inverted data in the fourth cache segment;

[0025] The real data in the first cache segment and the imaginary data in the fourth cache segment are fused to obtain the third fused data;

[0026] The imaginary data in the second cache segment and the real data in the third cache segment are fused to obtain the fourth fused data;

[0027] The third and fourth fused data are fused to obtain the angle data of the gradient data.

[0028] In one embodiment, the step of storing the real part of each complex data in the first cache segment of the cache based on the second storage location change function, and storing the imaginary part of each complex data in the second cache segment of the cache, includes:

[0029] Based on the second storage location change function, the third position information of the real part data and the fourth position information of the complex data are determined from the second mask tensor array; wherein, the real part data and the complex data are stored adjacent to each other in the second mask tensor.

[0030] Based on the third location information, the real part data of each complex number in each real part data is stored in the first cache segment of the cache;

[0031] Based on the fourth location information, the imaginary part of each complex number in the complex number data is stored in the second cache segment of the cache.

[0032] Secondly, this application also provides a data processing apparatus. The apparatus includes:

[0033] The acquisition module is used to acquire each complex number data to be processed from memory, store the real part of each complex number data in the first storage segment of the cache, and store the imaginary part of each complex number data in the second storage segment of the cache.

[0034] The calculation module is used to perform calculations on each real part data in the first storage segment based on the vector arithmetic unit in the Ascend NPU to obtain the real part calculation result, and to perform calculations on each imaginary part data in the second storage segment to obtain the imaginary part calculation result;

[0035] The storage module is used to obtain the real part calculation result of each complex number data from the first storage segment and the corresponding imaginary part calculation result from the second storage segment based on the first storage location change function, and to store the real part calculation result and the imaginary part calculation result of each complex number data into the memory.

[0036] In one embodiment, the storage module is further configured to:

[0037] Based on the first storage location change function, the first position information of the real part calculation result and the second position information of the corresponding imaginary part calculation result are obtained from the first mask tensor array; wherein, the real part calculation result and the imaginary part calculation result appear alternately in the first mask tensor array;

[0038] Based on the first location information, the real part calculation result is obtained from the first storage segment, and based on the second location information, the imaginary part calculation result is obtained from the second storage segment.

[0039] In one embodiment, the device further includes a processing module.

[0040] A processing module is used to retrieve the gradient data to be processed from the memory;

[0041] Based on the second storage location change function, the real part of each gradient data in each gradient data is stored in the first cache segment of the cache, and the imaginary part of each gradient data is stored in the second cache segment of the cache.

[0042] And the third cache segment of the cache stores the real part of each complex data in the complex data, and the fourth cache segment of the cache stores the imaginary part of each complex data in the complex data;

[0043] The data corresponding to the first cache segment, the second cache segment, the third cache segment, and the fourth cache segment are fused to obtain the target data.

[0044] In one embodiment, the processing module is further configured to:

[0045] Invert each virtual part of the data in the second cache segment to obtain inverted data, and then overwrite the inverted data storage into the second cache segment.

[0046] Divide each real part data in the third buffer segment by the length of the corresponding complex modulus of the gradient data to obtain the processed real part data, and store the processed real part data in the fifth buffer segment;

[0047] Divide each imaginary data in the fourth cache segment by the length of the corresponding complex modulus of the gradient data to obtain the processed imaginary data, and store the processed imaginary data in the sixth cache segment;

[0048] The real data processed in the fifth cache segment and the real data in the first cache segment are fused together to obtain the first fused data;

[0049] The processed virtual part data in the sixth cache segment and the virtual part data in the second cache segment are fused to obtain the second fused data;

[0050] The first fused data and the second fused data are fused to obtain the magnitude of the gradient data.

[0051] In one embodiment, the processing module is further configured to:

[0052] Invert each imaginary part of the data in the fourth cache segment to obtain inverted data, and store the inverted data in the fourth cache segment;

[0053] The real data in the first cache segment and the imaginary data in the fourth cache segment are fused to obtain the third fused data;

[0054] The imaginary data in the second cache segment and the real data in the third cache segment are fused to obtain the fourth fused data;

[0055] The third and fourth fused data are fused to obtain the angle data of the gradient data.

[0056] In one embodiment, the processing module is further configured to:

[0057] Information, and fourth position information of complex data; wherein, in the second mask tensor, each real part of the data is stored adjacently, and each complex data is stored adjacently;

[0058] Based on the third location information, the real part data of each complex number in each real part data is stored in the first cache segment of the cache;

[0059] Based on the fourth location information, the imaginary part of each complex number in the complex number data is stored in the second cache segment of the cache.

[0060] Thirdly, this application also provides a computer device. The computer device includes a memory and a processor, the memory storing a computer program, and the processor executing the computer program to implement the methods described in any embodiment of this disclosure.

[0061] Fourthly, this application also provides a computer-readable storage medium. The computer-readable storage medium stores a computer program thereon, which, when executed by a processor, implements the methods described in any embodiment of the present disclosure.

[0062] Fifthly, this application also provides a computer program product. The computer program product includes a computer program that, when executed by a processor, implements the methods described in any embodiment of this disclosure.

[0063] The aforementioned data processing methods, devices, computer equipment, storage media, and computer program products take into account that the Ascend NPU uses the Da Vinci architecture, where a vector computation core consists of a scalar operator and a vector operator. For example, performing one float operation (scalar operator) and performing 64 float vector operations (vector operator) takes the same amount of time. The time consumption primarily depends on the number of instructions, not the actual computational load. Furthermore, the Ascend NPU has extremely low scalar computational power, moderate vector computational power, and enormous matrix computational power. Therefore, to improve processing efficiency, the real part A of each complex number (AB form) is stored in the first storage segment, and the real part A of each complex number (AB form) is stored in the second storage segment, forming the form (AAAABBBB). Then, the Ascend NPU's scalar operator uniformly processes AAAA and BBBB, improving the processing efficiency of complex number operations. Attached Figure Description

[0064] Figure 1 This is a flowchart illustrating a data processing method in one embodiment;

[0065] Figure 2 This is a schematic diagram of the Ascend NPU structure in one embodiment;

[0066] Figure 3 Here is a flowchart of the first storage location change function processing in one embodiment;

[0067] Figure 4 This is a flowchart illustrating the data processing method in another embodiment;

[0068] Figure 5 This is a flowchart of the second storage location change function processing in one embodiment;

[0069] Figure 6This is a flowchart illustrating the data processing method in another embodiment;

[0070] Figure 7 This is a flowchart illustrating the data processing method in another embodiment;

[0071] Figure 8 This is a structural block diagram of a data processing device in one embodiment;

[0072] Figure 9 This is an internal structural diagram of a computer device in one embodiment;

[0073] Figure 10 This is an internal structural diagram of a computer device in one embodiment. Detailed Implementation

[0074] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0075] In one embodiment, such as Figure 1 As shown, a data processing method is provided. This embodiment illustrates the method applied to a terminal, but it is understood that the method can also be applied to a server, or to a system including both a terminal and a server, and implemented through interaction between the terminal and the server. In this embodiment, the method includes the following steps:

[0076] Step S101: Obtain each complex number data to be processed from memory, store the real part of each complex number data into the first storage segment of the cache, and store the imaginary part of each complex number data into the second storage segment of the cache.

[0077] This embodiment can be used for forward kernel functions, which are used for model inference. The operator principle formula is as follows:

[0078] z=abs×cos(angle)+abs×sin(angle)i (1)

[0079] Here, abs and angle are the tensors input to the operator, both of which are real numbers and support FP32 / FP16 precision. z is the tensor output to the operator, which is an ordinal number and supports COMPLEX64 / COMPLEX32 precision.

[0080] In the specific implementation process, operator initialization can be performed first. Specifically, the Tiling block parameters are determined, and the required block size and loop count are calculated. The queues TQue and local buffers TBuf need to be initialized. The total buffer size cannot exceed the size of the Unified Buffer in the Ascend NPU, ensuring that the total amount of TBuf and TQue fills the Unified Buffer, while each buffer's length meets 32-byte alignment. A total of two TQUEs with the VECIN attribute, one TQUE with the VECOUT attribute, and one TBuf with the VECCALC attribute are allocated. All three TQues can be double-buffered to ensure parallel read / write pipelines. In an exemplary embodiment, the GlobalTensor from global memory can be copied to the queue TQue and accessed as a LocalTensor, physically stored in the Unified Buffer of the Ascend NPU. DataCopyPad is used during copying, and misaligned tail block data is padded separately.

[0081] In the specific calculation process, taking the complex number z = A + Bi as an example, the real part of each complex number is stored in the first storage segment of the cache (e.g., TBuf). For example, the format stored in the first storage segment is AAAA. Similarly, the imaginary part of each complex number is stored in the second storage segment of the cache. For example, the format stored in the second storage segment is BBBB. If the first storage segment represents the first half of the cache and the second storage segment represents the second half of the cache, then the data stored in the cache is in the format AAAABBBB.

[0082] Step S103: Calculate the real part data in the first storage segment based on the vector arithmetic unit in the Ascend NPU to obtain the real part calculation result, and calculate the imaginary part data in the second storage segment to obtain the imaginary part calculation result.

[0083] In one exemplary embodiment, reference is made to Figure 2 As shown, Figure 2 The diagram shows the structure of an Ascend NPU. Although it belongs to the same category of parallel computing architecture as the GPU in terms of concept, it is very different from the GPU architecture in terms of hardware implementation details.

[0084] First, the NPU programming model is SPMD (Single Programming Multiple Data), while the GPU programming model is SIMT (Single Instruction Multiple Data). Each computational core (Block) does not share data in on-chip memory. Developers only need to focus on writing single-core operators and data partitioning. Each computational core has only one thread, and only one computational instruction (scalar / vector / matrix multiplier-adder) can be issued per clock cycle.

[0085] However, GPUs have several threads per computing core (NVIDIA GPUs have 32), hence the term "Warp." Each thread can share memory or synchronize events within the block. Each thread can issue a single general computation instruction (scalar), or the entire Warp can perform a matrix multiplication-addition operation. Therefore, GPUs have a large number of threads, making their scalar computing power very abundant. The Ascend NPU has extremely low scalar computing power, moderate vector computing power, and enormous matrix computing power. For example, the Ascend 910B has a clock speed of 1.8GHz and 40 cores. For vector computation involving a set of 64 FP32 floating-point numbers, the matrix multiplication-addition operation requires 16×16×16 operations, resulting in a scalar computing power of 1.8×40×10⁻⁶. 9 ÷10 12 = 0.072 TFLOPS, vector computing power is 1.8 × 64 × 40 × 10 9 ÷10 12 = 4.608 TFLOPS, matrix multiplication and addition computational power is 1.8 × 16 × 16 × 16 × 40 × 10 9 ÷10 12 = 294.912 TFLOPS. The polar coordinate transformation operations involved in the embodiments of this disclosure do not involve matrix multiplication and addition. For example... Figure 2 As shown, the main computational units involved are scalar operators and vector operators. Therefore, vector operators should be used as much as possible when designing kernel functions.

[0086] In the specific calculation process, the data of a single computing core can be divided into N loops. Each time a preset length (e.g., tileLength) is accessed, the calculation can be divided into two branches: first, the real part data (abs × cos(angle)) can be calculated, and then the imaginary part data (abs × sin(angle)) can be calculated. The calculation results can be stored in the first storage segment and the second storage segment respectively. In an exemplary embodiment, the pseudocode can be represented as follows:

[0087] zLocalBuf[0:tileLength]=Cos(yLocal);

[0088] zLocalBuf[0:tileLength]=Mul(zLocalBuf[0:tileLength],xLocal);

[0089] zLocalBuf[tileLength:2*tileLength]=Sin(yLocal);

[0090] zLocalBuf[tileLength:2*tileLength]=Mul(zLocalBuf[tileLength:2*tileLength],xLocal);

[0091] In the pseudocode above, zLocalBuf is a buffer (TBuf) used during operator initialization to temporarily cache and store the final calculation results. xLocal and yLocal are the representation variables of abs and angle in the local buffer, respectively. The length of zLocalBuf is 2xtileLength, with the first half (0 to tileLength-1) storing the real part data and the second half (tileLength to 2xtileLength-1) storing the imaginary part data.

[0092] Step S105: Based on the first storage location change function, obtain the real part calculation result of each complex number data from the first storage segment and the corresponding imaginary part calculation result from the second storage segment, and store the real part calculation result and the imaginary part calculation result of each complex number data into the memory.

[0093] In one embodiment, obtaining the real part calculation result of each complex number data from the first storage segment and the corresponding imaginary part calculation result from the second storage segment based on the first storage location change function includes:

[0094] Based on the first storage location change function, the first position information of the real part calculation result and the second position information of the corresponding imaginary part calculation result are obtained from the first mask tensor array; wherein, the real part calculation result and the imaginary part calculation result appear alternately in the first mask tensor array.

[0095] Based on the first location information, the real part calculation result is obtained from the first storage segment, and based on the second location information, the imaginary part calculation result is obtained from the second storage segment.

[0096] The first storage location change function may include the Gather function in the Ascend NPU, which is an Ascend built-in function that utilizes MTE storage transformation.

[0097] Specifically, the real and imaginary part calculation results alternate in the first mask tensor array. For example, refer to... Figure 3 As shown, in the first mask tensor array (Gather Mask), there are the following information: first position information 0 for the real part calculation result, second position information 128 for the imaginary part calculation result, first position information 1 for the real part calculation result, second position information 129 for the imaginary part calculation result, and first position information 2 for the real part calculation result. (Continue to refer to...) Figure 3The first storage segment is denoted as a0 to a127, and the second storage segment is denoted as b0 to b127. Based on the first mask tensor array, position 0 (a0) and position 128 (b0) are stored together; similarly, position 1 (a1) and position 129 (b1) are stored together, and so on. Thus, the data originally in the form AAAABBBB is transformed into the form ABABABAB, where A represents the real part of the complex number and B represents the imaginary part. In an exemplary embodiment, the calculation results of the real and imaginary parts of each complex number are stored correspondingly in global memory.

[0098] In the above embodiments, considering that the Ascend NPU uses the Da Vinci architecture, where a vector computation core consists of a scalar operator and a vector operator, the time taken to perform one float operation (scalar operator) and 64 float vector operations (vector operator) is the same. The time consumption mainly depends on the number of instructions, not the actual computational load. Furthermore, the Ascend NPU has extremely low scalar computation power, moderate vector computation power, and enormous matrix computation power. Therefore, to improve processing efficiency, the real part A of each complex number (AB form) is stored in the first storage segment, and the real part A of each complex number (AB form) is stored in the second storage segment, forming the form (AAAABBBB). Then, the Ascend NPU's scalar operator is used to uniformly process AAAA and BBBB, improving the processing efficiency of complex number operations.

[0099] In one embodiment, reference Figure 4 As shown, after retrieving the complex data to be processed from memory, the process further includes:

[0100] Step S401: Obtain the gradient data to be processed from the memory.

[0101] In this embodiment, it can be used for inverse kernel functions, primarily for model training. The principle formula of the operator is as follows:

[0102]

[0103] Here, grad_abs and grad_angle are the output tensors of the inverse kernel function, both of which are real numbers and support FP32 / FP16 precision. `z` is the conjugate complex number of the input gradient, where `z` is the input (corresponding to the forward output `z`), which is a complex tensor with precision supporting `COMPLEX64` / `COMPLEX32`. `sgn(z)` denotes the sign function, and `Re()` extracts the real part of the complex number.

[0104] Since the output only requires the real part Re, the calculation of the imaginary part can be omitted, thus simplifying the calculation. By decomposing the calculation steps of equations (2) and (3), we obtain the following calculation steps:

[0105] z_sgn = sgn(z) (4)

[0106]

[0107] grad_abs = grad_conj_re ×Re(z_sgn) - grad_conj_im ×Im(z_sgn) (7)

[0108]

[0109] In this embodiment of the disclosure, the gradient data is a vector representing the maximum value of the directional derivative of a function at a given point along that direction. In other words, the function changes most rapidly and at its maximum rate (the magnitude of the gradient) along that direction at that point. The gradient can be used to indicate the direction and rate of change of the loss function in the parameter space.

[0110] Step S403: Based on the second storage location change function, store the real part of each gradient data in the first cache segment of the cache, and store the imaginary part of each gradient data in the second cache segment of the cache.

[0111] In one embodiment, the step of storing the real part data of each complex data in the first cache segment of the cache and storing the imaginary part data of each complex data in the second cache segment of the cache based on the second storage location change function includes: determining third location information of the real data and fourth location information of the complex data from the second mask tensor array based on the second storage location change function; storing the real part data of each complex data in the first cache segment of the cache based on the third location information; and storing the imaginary part data of each complex data in the second cache segment of the cache based on the fourth location information.

[0112] In the specific implementation, the real data in the second mask tensor are stored contiguously, and the imaginary data are stored contiguously. (See reference) Figure 5 As shown, in the second mask tensor array (Gather Mask), the third position information of the real part data (0, 2, 4, etc.) are adjacent, and the fourth position information of the imaginary part data (1, 3, 5, etc.) are adjacent. (Continue to refer to...) Figure 5The third position information, 0, 2, 4, etc., all correspond to real part data, meaning the data corresponding to positions 0, 2, 4, etc., in the "Input" field are moved to adjacent positions. Figure 5 In the "Gather calculation," a0a1…a127. The fourth position information 1, 3, 5, etc., all correspond to real part data, that is, the data corresponding to the 1st, 3rd, 5th, etc. in the "Input" are moved to the adjacent positions. Figure 5 In the "Gather calculation", b0b1…b127. Thus, the data in the original ABABABAB is transformed into the form AAAABBBBB, where A can represent the real part and B can represent the imaginary part.

[0113] After understanding the function of the second position change function, we will reallocate the storage locations of the real and imaginary parts of each complex number data, as well as the real and imaginary parts of each gradient data.

[0114] Specifically, the first buffer segment (denoted as tmp1) buffers the real part of the gradient data, and the second buffer segment (denoted as tmp2) buffers the imaginary part of the gradient data.

[0115] Step S405 involves storing the real part of each complex data in the third cache segment of the cache and storing the imaginary part of each complex data in the fourth cache segment of the cache.

[0116] Specifically, the third cache segment (denoted as tmp3) caches the real part of the complex data, and the fourth cache segment (denoted as tmp4) caches the imaginary part of the complex data.

[0117] Step S407: Perform fusion processing on the data corresponding to the first cache segment, the second cache segment, the third cache segment, and the fourth cache segment to obtain the target data.

[0118] In one embodiment, reference Figure 6 As shown, the target data includes the magnitude of the gradient data. The process of fusing the data corresponding to the first cache segment, the second cache segment, the third cache segment, and the fourth cache segment to obtain the target data includes:

[0119] Step S601: Invert each virtual part of the data in the second cache segment to obtain inverted data, and then overwrite the inverted data storage in the second cache segment.

[0120] Specifically, referring to formula (4), the imaginary part data in the second cache segment can be inverted first, and the inverted data can be stored in the second cache segment.

[0121] Step S603: Divide each real part data in the third buffer segment by the length of the corresponding complex modulus of the gradient data to obtain the processed real part data, and store the processed real part data in the fifth buffer segment.

[0122] Specifically, referring to formula (5), each real part of the data in the third buffer segment is divided by the length of the complex modulus of the corresponding gradient data to obtain the processed real part data grad_conj_re. The processed real part data grad_conj_re is then stored in the fifth buffer segment (denoted as tmp5).

[0123] Step S605: Divide each imaginary data in the fourth buffer segment by the length of the corresponding complex modulus of the gradient data to obtain the processed imaginary data, and store the processed imaginary data in the sixth buffer segment.

[0124] Specifically, referring to formula (6), each imaginary data in the fourth buffer segment is divided by the length of the corresponding gradient data complex modulus to obtain the processed imaginary data grad_conj_im, and the processed imaginary data grad_conj_im is stored in the sixth buffer segment (denoted as tmp6).

[0125] Step S607: The real data processed in the fifth cache segment and the real data in the first cache segment are fused to obtain the first fused data.

[0126] Specifically, referring to formula (7), the real part data grad_conj_re processed in the fifth cache segment is fused with the real part data Re(z_sgn) in the first cache segment to obtain the first fused sum data: grad_conj_re×Re(z_sgn).

[0127] Step S609: The processed virtual part data in the sixth cache segment and the virtual part data in the second cache segment are fused to obtain the second fused data.

[0128] Specifically, referring to formula (7), the virtual part data grad_conj_im processed in the sixth cache segment is fused with Im(z_sgn) in the second cache segment to obtain the second fused data: grad_conj_im×Im(z_sgn).

[0129] Step S611: Perform fusion processing on the first fused data and the second fused data to obtain the magnitude of the gradient data.

[0130] Specifically, referring to formula (7), the first fused data grad_conj_re×Re(z_sgn) and the second fused data grad_conj_im×Im(z_sgn) are fused to obtain the magnitude of the gradient data grad_abs.

[0131] In one embodiment, reference Figure 7 As shown, the target data includes the angle data of the gradient data. The process of fusing the data corresponding to the first cache segment, the second cache segment, the third cache segment, and the fourth cache segment to obtain the target data includes:

[0132] Step S701: Invert the virtual part data in the fourth cache segment to obtain inverted data, and store the inverted data in the fourth cache segment.

[0133] Specifically, the fourth cache segment (denoted as tmp4) caches the imaginary part of the complex number data. Referring to equation (8), the imaginary part of the complex number data is inverted to obtain the inverted data: -Im(z). The inverted data is stored in the fourth cache segment, and the original data in the fourth cache segment is cleared.

[0134] Step S703: The real data in the first cache segment and the imaginary data in the fourth cache segment are fused to obtain the third fused data.

[0135] Specifically, referring to equation (8), the first buffer segment (denoted as tmp1) buffers the real part of the gradient data: The imaginary data -Im(z) in the fourth buffer segment are fused with the above two parts to obtain the third fused data, which is represented as:

[0136] Step S705: The imaginary data in the second cache segment and the real data in the third cache segment are fused to obtain the fourth fused data.

[0137] Specifically, referring to equation (8), the imaginary parts of the gradient data stored in the second buffer segment are as follows: The real data in the third buffer segment: Re(z). The above two data parts are fused to obtain the fourth fused data, represented as:

[0138] Step S707: Perform fusion processing on the third fused data and the fourth fused data to obtain the angle data of the gradient data.

[0139] Specifically, refer to Figure 8 As shown, for the third fused data and the fourth fused data The gradient data is then fused to obtain the angle data grad_angle.

[0140] In the above data processing method, the storage locations of each complex number or gradient data are changed by the first storage location transformation function and the second storage location transformation function, thereby making full use of the powerful vector processor in the Ascend NPU and improving the computational efficiency.

[0141] It should be understood that although the steps in the flowcharts of the embodiments described above are shown sequentially according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least some steps in the flowcharts of the embodiments described above may include multiple steps or multiple stages. These steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these steps or stages is not necessarily sequential, but can be performed alternately or in turn with other steps or at least some of the steps or stages of other steps.

[0142] Based on the same inventive concept, this application also provides a data processing apparatus for implementing the data processing method described above. The solution provided by this apparatus is similar to the implementation scheme described in the above method; therefore, the specific limitations in one or more data processing apparatus embodiments provided below can be found in the limitations of the data processing method described above, and will not be repeated here.

[0143] In one embodiment, such as Figure 8 As shown, a data processing apparatus 800 is provided. The apparatus includes:

[0144] The acquisition module 801 is used to acquire each complex number data to be processed from memory, store the real part of each complex number data in the first storage segment of the cache, and store the imaginary part of each complex number data in the second storage segment of the cache.

[0145] The calculation module 803 is used to perform calculations on each real part data in the first storage segment based on the vector arithmetic unit in the Ascend NPU to obtain the real part calculation result, and to perform calculations on each imaginary part data in the second storage segment to obtain the imaginary part calculation result;

[0146] The storage module 805 is used to obtain the real part calculation result of each complex number data from the first storage segment and the corresponding imaginary part calculation result from the second storage segment based on the first storage location change function, and to store the real part calculation result and the imaginary part calculation result of each complex number data into the memory.

[0147] In one embodiment, the storage module is further configured to:

[0148] Based on the first storage location change function, the first position information of the real part calculation result and the second position information of the corresponding imaginary part calculation result are obtained from the first mask tensor array; wherein, the real part calculation result and the imaginary part calculation result appear alternately in the first mask tensor array;

[0149] Based on the first location information, the real part calculation result is obtained from the first storage segment, and based on the second location information, the imaginary part calculation result is obtained from the second storage segment.

[0150] In one embodiment, the device further includes a processing module.

[0151] A processing module is used to retrieve the gradient data to be processed from the memory;

[0152] Based on the second storage location change function, the real part of each gradient data in each gradient data is stored in the first cache segment of the cache, and the imaginary part of each gradient data is stored in the second cache segment of the cache.

[0153] And the third cache segment of the cache stores the real part of each complex data in the complex data, and the fourth cache segment of the cache stores the imaginary part of each complex data in the complex data;

[0154] The data corresponding to the first cache segment, the second cache segment, the third cache segment, and the fourth cache segment are fused to obtain the target data.

[0155] In one embodiment, the processing module is further configured to:

[0156] Invert each virtual part of the data in the second cache segment to obtain inverted data, and then overwrite the inverted data storage into the second cache segment.

[0157] Divide each real part data in the third buffer segment by the length of the corresponding complex modulus of the gradient data to obtain the processed real part data, and store the processed real part data in the fifth buffer segment;

[0158] Divide each imaginary data in the fourth cache segment by the length of the corresponding complex modulus of the gradient data to obtain the processed imaginary data, and store the processed imaginary data in the sixth cache segment;

[0159] The real data processed in the fifth cache segment and the real data in the first cache segment are fused together to obtain the first fused data;

[0160] The processed virtual part data in the sixth cache segment and the virtual part data in the second cache segment are fused to obtain the second fused data;

[0161] The first fused data and the second fused data are fused to obtain the magnitude of the gradient data.

[0162] In one embodiment, the processing module is further configured to:

[0163] Invert each imaginary part of the data in the fourth cache segment to obtain inverted data, and store the inverted data in the fourth cache segment;

[0164] The real data in the first cache segment and the imaginary data in the fourth cache segment are fused to obtain the third fused data;

[0165] The imaginary data in the second cache segment and the real data in the third cache segment are fused to obtain the fourth fused data;

[0166] The third and fourth fused data are fused to obtain the angle data of the gradient data.

[0167] In one embodiment, the processing module is further configured to:

[0168] Information, and fourth position information of complex data; wherein, in the second mask tensor, each real part of the data is stored adjacently, and each complex data is stored adjacently;

[0169] Based on the third location information, the real part data of each complex number in each real part data is stored in the first cache segment of the cache;

[0170] Based on the fourth location information, the imaginary part of each complex number in the complex number data is stored in the second cache segment of the cache.

[0171] Each module in the aforementioned data processing device can be implemented entirely or partially through software, hardware, or a combination thereof. These modules can be embedded in or independent of the processor in a computer device, or stored in the memory of a computer device as software, so that the processor can call and execute the operations corresponding to each module.

[0172] In one embodiment, a computer device is provided, which may be a server, and its internal structure diagram may be as follows: Figure 9 As shown, this computer device includes a processor, memory, input / output interfaces (I / O), and a communication interface. The processor, memory, and I / O interfaces are connected via a system bus, and the communication interface is also connected to the system bus via the I / O interfaces. The processor provides computational and control capabilities. The memory includes non-volatile storage media and internal memory. The non-volatile storage media stores the operating system, computer programs, and a database. The internal memory provides the environment for the operation of the operating system and computer programs stored in the non-volatile storage media. The database stores data for data processing. The I / O interfaces are used for exchanging information between the processor and external devices. The communication interface is used for communicating with external terminals via a network connection. When the computer program is executed by the processor, it implements a data processing method.

[0173] In one embodiment, a computer device is provided, which may be a terminal, and its internal structure diagram may be as follows: Figure 10 As shown, the computer device includes a processor, memory, input / output interfaces, a communication interface, a display unit, and an input device. The processor, memory, and input / output interfaces are connected via a system bus, and the communication interface, display unit, and input device are also connected to the system bus via the input / output interfaces. The processor provides computational and control capabilities. The memory includes non-volatile storage media and internal memory. The non-volatile storage media stores the operating system and computer programs. The internal memory provides an environment for the operation of the operating system and computer programs stored in the non-volatile storage media. The input / output interfaces are used for exchanging information between the processor and external devices. The communication interface is used for wired or wireless communication with external terminals; wireless communication can be achieved through Wi-Fi, mobile cellular networks, NFC (Near Field Communication), or other technologies. When the computer program is executed by the processor, it implements a data processing method. The display unit of the computer device is used to form a visually visible image. It can be a display screen, a projection device, or a virtual reality imaging device. The display screen can be an LCD screen or an e-ink screen. The input device of the computer device can be a touch layer covering the display screen, or buttons, trackballs, or touchpads set on the casing of the computer device, or external keyboards, touchpads, or mice, etc.

[0174] Those skilled in the art will understand that Figure 10The structure shown is merely a block diagram of a portion of the structure related to the present application and does not constitute a limitation on the computer device to which the present application is applied. Specific computer devices may include more or fewer components than those shown in the figure, or combine certain components, or have different component arrangements.

[0175] It should be noted that the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for analysis, data stored, data displayed, etc.) involved in this application are all information and data authorized by the user or fully authorized by all parties, and the collection, use and processing of the relevant data shall comply with the relevant laws, regulations and standards of the relevant countries and regions.

[0176] Those skilled in the art will understand that all or part of the processes in the methods of the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer-readable storage medium, and when executed, it can include the processes of the embodiments of the above methods. Any references to memory, databases, or other media used in the embodiments provided in this application can include at least one of non-volatile and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetic random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. By way of illustration and not limitation, RAM can take many forms, such as Static Random Access Memory (SRAM) or Dynamic Random Access Memory (DRAM). The databases involved in the embodiments provided in this application may include at least one type of relational database and non-relational database. Non-relational databases may include, but are not limited to, blockchain-based distributed databases. The processors involved in the embodiments provided in this application may be general-purpose processors, central processing units, graphics processing units, digital signal processors, programmable logic devices, quantum computing-based data processing logic devices, etc., and are not limited to these.

[0177] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0178] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of this patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this application should be determined by the appended claims.

Claims

1. A data processing method, characterized in that, Applied to Ascend NPU, the method includes: Retrieve each complex number data to be processed from memory, store the real part of each complex number data in the first storage segment of the cache, and store the imaginary part of each complex number data in the second storage segment of the cache; The vector arithmetic unit in the Ascend NPU performs calculations on each real part of the data in the first storage segment to obtain the real part calculation result, and performs calculations on each imaginary part of the data in the second storage segment to obtain the imaginary part calculation result; Based on the first storage location change function, the first position information of the real part calculation result and the second position information of the corresponding imaginary part calculation result are obtained from the first mask tensor array; wherein, the real part calculation result and the imaginary part calculation result appear alternately in the first mask tensor array; Based on the first location information, the real part calculation result is obtained from the first storage segment, and based on the second location information, the imaginary part calculation result is obtained from the second storage segment. The real part calculation result and the imaginary part calculation result of each complex number are then stored in the memory. Obtain the gradient data to be processed from the memory; Based on the second storage location change function, the real part of each gradient data in each gradient data is stored in the first cache segment of the cache, and the imaginary part of each gradient data in each gradient data is stored in the second cache segment of the cache; And store the real part of each complex data in the third cache segment of the cache, and store the imaginary part of each complex data in the fourth cache segment of the cache; The data corresponding to the first cache segment, the second cache segment, the third cache segment, and the fourth cache segment are fused to obtain the target data.

2. The method according to claim 1, characterized in that, The target data includes the magnitude of the gradient data. The process of fusing the data corresponding to the first cache segment, the second cache segment, the third cache segment, and the fourth cache segment to obtain the target data includes: Invert each virtual part of the data in the second cache segment to obtain inverted data, and then overwrite the inverted data storage into the second cache segment. Divide each real part data in the third buffer segment by the length of the corresponding complex modulus of the gradient data to obtain the processed real part data, and store the processed real part data in the fifth buffer segment; Divide each imaginary data in the fourth cache segment by the length of the corresponding complex modulus of the gradient data to obtain the processed imaginary data, and store the processed imaginary data in the sixth cache segment; The real data processed in the fifth cache segment and the real data in the first cache segment are fused together to obtain the first fused data; The processed virtual part data in the sixth cache segment and the virtual part data in the second cache segment are fused to obtain the second fused data; The first fused data and the second fused data are fused to obtain the magnitude of the gradient data.

3. The method according to claim 1, characterized in that, The target data includes the angle data of the gradient data. The process of fusing the data corresponding to the first cache segment, the second cache segment, the third cache segment, and the fourth cache segment to obtain the target data includes: Invert each imaginary part of the data in the fourth cache segment to obtain inverted data, and store the inverted data in the fourth cache segment; The real data in the first cache segment and the imaginary data in the fourth cache segment are fused to obtain the third fused data; The imaginary data in the second cache segment and the real data in the third cache segment are fused to obtain the fourth fused data; The third and fourth fused data are fused to obtain the angle data of the gradient data.

4. The method according to claim 1, characterized in that, The step of storing the real part of each complex number in the first cache segment of the cache and storing the imaginary part of each complex number in the second cache segment of the cache, based on the second storage location change function, includes: Based on the second storage location change function, the third position information of the real part data and the fourth position information of the imaginary part data are determined from the second mask tensor array; wherein, the real part data and the imaginary part data in the second mask tensor are stored adjacent to each other; Based on the third location information, each real part of the real part data is stored in the first cache segment of the cache; Based on the fourth location information, each imaginary part of the complex data is stored in the second cache segment of the cache.

5. A data processing apparatus, characterized in that, The device includes: The acquisition module is used to acquire each complex number data to be processed from memory, store the real part of each complex number data in the first storage segment of the cache, and store the imaginary part of each complex number data in the second storage segment of the cache. The calculation module is used to perform calculations on each real part data in the first storage segment based on the vector arithmetic unit in the Ascend NPU to obtain the real part calculation result, and to perform calculations on each imaginary part data in the second storage segment to obtain the imaginary part calculation result; A storage module is configured to, based on a first storage location change function, obtain the real part calculation result of each complex number from the first storage segment and the corresponding imaginary part calculation result from the second storage segment, and store the real part calculation result and the imaginary part calculation result of each complex number into the memory accordingly; the storage module is further configured to: obtain first position information of the real part calculation result and second position information of the corresponding imaginary part calculation result from a first mask tensor array based on the first storage location change function; wherein, the real part calculation result and the imaginary part calculation result alternate in the first mask tensor array; obtain the real part calculation result from the first storage segment based on the first position information, and obtain the imaginary part calculation result from the second storage segment based on the second position information; The processing module is used to obtain the gradient data to be processed from the memory; based on the second storage location change function, store the real part of each gradient data in the first cache segment of the cache, store the imaginary part of each gradient data in the second cache segment of the cache; store the real part of each complex data in the third cache segment of the cache, and store the imaginary part of each complex data in the fourth cache segment of the cache; and perform fusion processing on the data corresponding to the first cache segment, the second cache segment, the third cache segment, and the fourth cache segment respectively to obtain the target data.

6. The apparatus according to claim 5, characterized in that, The processing module is also used for: Invert each imaginary part of the data in the second cache segment to obtain inverted data, and then overwrite the inverted data storage in the second cache segment; Divide each real part data in the third buffer segment by the length of the corresponding complex modulus of the gradient data to obtain the processed real part data, and store the processed real part data in the fifth buffer segment; Divide each imaginary data in the fourth cache segment by the length of the corresponding complex modulus of the gradient data to obtain the processed imaginary data, and store the processed imaginary data in the sixth cache segment; The real data processed in the fifth cache segment and the real data in the first cache segment are fused together to obtain the first fused data; The processed virtual part data in the sixth cache segment and the virtual part data in the second cache segment are fused to obtain the second fused data; The first fused data and the second fused data are fused to obtain the magnitude of the gradient data.

7. The apparatus according to claim 5, wherein the processing module is further configured to: Invert each imaginary part of the data in the fourth cache segment to obtain inverted data, and store the inverted data in the fourth cache segment; The real data in the first cache segment and the imaginary data in the fourth cache segment are fused to obtain the third fused data; The imaginary data in the second cache segment and the real data in the third cache segment are fused to obtain the fourth fused data; The third and fourth fused data are fused to obtain the angle data of the gradient data.

8. A computer device comprising a memory and a processor, wherein the memory stores a computer program, characterized in that, When the processor executes the computer program, it implements the steps of the method according to any one of claims 1 to 4.

9. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by a processor, it implements the steps of the method according to any one of claims 1 to 4.

10. A computer program product, comprising a computer program, characterized in that, When the computer program is executed by a processor, it implements the steps of the method according to any one of claims 1 to 4.

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