Random number generation circuit, circuit control method and storage and calculation integrated chip

By designing a random number generation circuit including a memristor circuit, a capacitor array circuit and a random number output circuit in the memory and calculation integrated chip, the problem of large area occupancy of the random number generation circuit in the memory and calculation integrated chip is solved, and the same or similar random number generation speed under different resistance states is achieved, and the chip area is reduced.

CN119718252APending Publication Date: 2025-03-28INTERNATIONAL INNOVATION CENTER OF TSINGHUA UNIVERSITY SHANGHAI +1
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Patent Information

Application Number
CN202411728081.7
Authority / Receiving Office
CN · China
Patent Type
Applications(China)
Current Assignee / Owner
Filing Date
2024-11-28
Publication Date
2025-03-28

AI Technical Summary

Technical Problem

There is a problem that the chip area is large when applying the random number generation circuit using memristor as the TRNG entropy source device to the memory and computing integrated chip.

Method used

A random number generation circuit is designed, including a memristor circuit, a capacitance array circuit and a random number output circuit. Through the capacitance array circuit, the capacitor number sub-circuit matches the current resistive state of the memristor circuit to achieve the same or similar random number generation speed under different resistive states.

Benefits of technology

With this design, the memristor circuit in the memory integrated chip can be used as the entropy source of the random number generation circuit without adding special devices, so as to reduce the area of ​​the memory integrated chip.

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Abstract

The invention relates to a random number generation circuit, a circuit control method and a storage and calculation integrated chip. The random number generation circuit comprises a memristor circuit, a capacitor array circuit and a random number output circuit, the memristor circuit is connected with the random number output circuit, and the capacitor array circuit is arranged between the memristor circuit and the random number output circuit; the capacitor array circuit comprises a plurality of capacitor sub-circuits which are connected in parallel; the first end of at least one capacitor sub-circuit in the capacitor array circuit is configured to be connected with the memristor circuit, the first ends of the other capacitor sub-circuits are configured to be disconnected with the memristor circuit, and at least one capacitor sub-circuit is matched with the current resistance state of the memristor circuit; the random number output circuit is used for outputting a target random number. By adopting the random number generation circuit, the area of the storage and calculation integrated chip can be reduced.
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