Cross-architecture instruction processing method and processor based on pattern matching and fusion

Abstract

The invention discloses a cross-architecture instruction processing method and processor based on pattern matching and fusion, the method is used for converting a first instruction sequence in a first instruction set into a second instruction sequence in a second instruction set, and the method comprises the following steps: determining a target instruction set from the first instruction set, the target instruction set comprises a plurality of target first instruction sequences, a target second instruction sequence used for replacing the target first instruction sequences is determined from the second instruction set, and the number of instructions included in the target second instruction sequence is not larger than the number of instructions included in the target first instruction sequence; obtaining a to-be-processed first instruction sequence, judging whether a target first instruction sequence matched with the first instruction sequence exists in the target instruction set or not, and if yes, replacing the first instruction sequence with a target second instruction sequence corresponding to the target first instruction sequence; and if not, translating the first instruction sequence into a second instruction sequence. According to the invention, the processing efficiency of the cross-architecture instruction can be improved.

Description

Technical Field

[0001] The present invention relates to the field of computer technology, and in particular to a cross-architecture instruction processing method and processor based on pattern matching and fusion. Background Art

[0002] In the field of computer science, the development of processor architecture has always been a hot topic. With the development of technology, processors have evolved from a single CISC (complex instruction set computer) architecture to a RISC (reduced instruction set computer) architecture. The RISC architecture has received more and more attention due to its simplicity, efficiency, and modularity. However, in practical applications, due to historical reasons and the complexity of the software ecosystem, many existing software and operating systems are designed based on the CISC architecture, such as the X86 architecture. Therefore, how to run X86 instructions on a RISC architecture processor has become an important issue.

[0003] Among the existing solutions, a widely used solution is to use Dynamic Binary Translation (DBT). DBT technology translates X86 instructions into RISC-V instructions by running an X86 simulator on a RISC architecture processor. This method can implement the operation of X86 instructions on RISC architecture processors without modifying existing software. However, this method requires a large amount of memory and computing resources, and due to the existence of the simulator, the execution efficiency is low.

[0004] Although DBT technology can solve the problem of X86 instructions running on RISC architecture processors to a certain extent, it has some significant limitations. First, DBT technology requires a large amount of memory and computing resources, which is a huge challenge for embedded systems with limited resources. Secondly, due to the existence of the simulator, the execution efficiency is low and cannot meet application scenarios with high real-time requirements. In addition, DBT technology may encounter performance bottlenecks when processing complex instruction sequences, affecting the overall performance of the system.

[0005] The disclosure of the above background technology content is only used to assist in understanding the inventive concept and technical solution of the present invention. It does not necessarily belong to the prior art of the present application, nor does it necessarily provide technical guidance. In the absence of clear evidence that the above content has been disclosed before the filing date of the present application, the above background technology should not be used to evaluate the novelty and creativity of the present application. Summary of the invention

[0006] The purpose of the present invention is to provide a cross-architecture instruction processing method and processor based on pattern matching and fusion, which can improve the processing efficiency of cross-architecture instructions and reduce resource consumption.

[0007] To achieve the above object, the technical solution adopted by the present invention is as follows: A cross-architecture instruction processing method based on pattern matching and fusion is used to convert a first instruction sequence in a first instruction set into a second instruction sequence in a second instruction set, wherein the first instruction set and the second instruction set are based on different instruction set architectures, the first instruction sequence includes one or more instructions, and the second instruction sequence includes one or more instructions, and the method comprises the following steps: Determine a target instruction set from the first instruction set, the target instruction set includes a plurality of target first instruction sequences, the target first instruction sequence is a part of the plurality of first instruction sequences, determine a target second instruction sequence from the second instruction set for replacing the target first instruction sequence, the target second instruction sequence corresponds to the target first instruction sequence one-to-one, and the number of instructions included in the target second instruction sequence is not greater than the number of instructions included in the corresponding target first instruction sequence; Acquire a first instruction sequence to be processed, determine whether there is a target first instruction sequence matching the first instruction sequence in the target instruction set, and if so, replace the first instruction sequence with the target second instruction sequence corresponding to the target first instruction sequence; If not present, the first instruction sequence is translated into a second instruction sequence.

[0008] Furthermore, any one of the above-mentioned technical solutions or a combination of multiple technical solutions further includes the following steps: Classifying the plurality of target first instruction sequences in the target instruction set according to the function type to construct a function mode library, wherein the function mode library comprises a plurality of sub-mode libraries, wherein the sub-mode libraries comprise the target first instruction sequences with the same function type, and the function types corresponding to the target first instruction sequences comprised in different sub-mode libraries are different; A unique function type is configured for each of the sub-pattern libraries, and the function type corresponding to the sub-pattern library corresponds to the function type corresponding to the target first instruction sequence included therein; It is determined whether the target first instruction sequence that matches the first instruction sequence exists in the target instruction set by: Determine a function type corresponding to the first instruction sequence and use it as a first function type; Determine whether there is a function type corresponding to the sub-pattern library corresponding to the first function type; if so, match the first instruction sequence with a target first instruction sequence included in the sub-pattern library of the corresponding function type; if the match is successful, the target first instruction sequence matching the first instruction sequence exists in the target instruction set; If the match is unsuccessful or the function types corresponding to the sub-pattern libraries are not the first function types, then the target first instruction sequence matching the first instruction sequence does not exist in the target instruction set.

[0009] Further, based on any one of the above-mentioned technical solutions or a combination of multiple technical solutions, the sub-pattern library includes one or more of a load-operate-store sub-pattern library, an inter-register operation sub-pattern library, an address calculation and memory access sub-pattern library, and a loop control sub-pattern library; Wherein, the load-operate-store sub-mode library includes the following target first instruction sequences: a load data from memory instruction sequence, an execute ALU instruction sequence, and a store back to memory instruction sequence; The inter-register operation sub-pattern library includes the following target first instruction sequences: a continuous register addition and subtraction operation instruction sequence, a shift instruction sequence and a logic operation instruction sequence; The memory access sub-mode library includes the following target first instruction sequence: an address calculation instruction sequence based on an offset and a base address; The loop control sub-pattern library includes the following target first instruction sequences: a conditional jump operation instruction sequence and a loop instruction sequence.

[0010] Further, based on any one of the above technical solutions or a combination of multiple technical solutions, it also includes obtaining the first instruction sequence to be processed in the following manner: Determine the maximum length of the target first instruction sequence in the target instruction set; A sliding window is used to detect the input first instruction stream in real time, the length of the sliding window is not less than the maximum length, and the first instruction stream includes a plurality of the first instruction sequences.

[0011] Further, based on any one of the technical solutions or a combination of multiple technical solutions mentioned above, two adjacent detection ranges of the sliding window are connected or have overlapping parts.

[0012] Further, based on any one of the above-mentioned technical solutions or a combination of multiple technical solutions, the first instruction sequence is translated into the second instruction sequence in the following manner: Using a parallel decoding unit to perform parallel processing and field separation on multiple instructions in the first instruction sequence, including extracting operation codes, operands and prefix information; Each instruction in the first instruction sequence is translated through a lookup table or a preset translation rule, and the second instruction sequence is determined according to the translation results of each instruction.

[0013] Further, based on any one of the above technical solutions or a combination of multiple technical solutions, translating the first instruction sequence into a second instruction sequence further includes: configuring a cache unit, the cache unit being configured to store a plurality of previous first instruction sequences and a previous second instruction sequence for replacing the previous first instruction sequence, the first instruction set including the previous first instruction sequence, and the second instruction set including the previous second instruction sequence; The usage frequency of the previous first instruction sequence is higher than the preset first usage frequency, and / or the time period of the most recent usage of the previous first instruction sequence relative to the current time period is within a preset time period range; Determine whether the first instruction sequence is one of the plurality of first instruction sequences, and if so, directly use the corresponding second instruction sequence to replace the first instruction sequence; A preferred method is to determine whether the first instruction sequence is one of the plurality of first instruction sequences and to translate each instruction by the lookup table or the preset translation rule in parallel, which can effectively shorten the instruction translation time and improve the instruction translation efficiency; Another preferred manner is to determine whether the first instruction sequence is one of the plurality of previous first instruction sequences before translating the first instruction sequence into the second instruction sequence, which can improve translation efficiency and greatly reduce resource consumption.

[0014] Further, based on any one of the above-mentioned technical solutions or a combination of multiple technical solutions, translating the first instruction sequence into a second instruction sequence further includes: The first instruction sequence that does not conform to the specification is identified by checking the legality of the operation code and the operand, and a prompt message is issued.

[0015] Further, based on any one of the technical solutions or a combination of multiple technical solutions described above, the method is used to convert a first instruction stream into a second instruction stream, the first instruction stream includes multiple first instruction sequences, and the second instruction stream includes multiple second instruction sequences.

[0016] Further, based on any one of the above-mentioned technical solutions or a combination of multiple technical solutions, for the current first instruction sequence in the first instruction stream, if the target first instruction sequence matching the current first instruction sequence does not exist in the target instruction set, the current first instruction sequence is translated into a second instruction sequence; While translating the current first instruction sequence, for a first instruction sequence following the current first instruction sequence in the first instruction stream, it is determined whether there is a target first instruction sequence matching the first instruction sequence in the target instruction set.

[0017] Further, based on any one of the above-mentioned technical solutions or a combination of multiple technical solutions, the first instruction set is based on the X86 architecture, and the second instruction set is based on the RISC-V architecture; or, The first instruction set is based on the ARM architecture, and the second instruction set is based on the RISC-V architecture.

[0018] Furthermore, based on any one of the technical solutions or a combination of multiple technical solutions mentioned above, the usage frequency of the target first instruction sequence is higher than the preset second usage frequency, that is, preferably, the first instruction sequences used frequently can be screened out according to the usage frequencies of each first instruction sequence in the first instruction set, and then it can be further determined whether the first instruction sequences used frequently can be merged into a second instruction sequence with a smaller number of instructions. If so, the first instruction sequence is determined to be the target first instruction sequence, and the set of all the obtained target first instruction sequences is determined as the target instruction set.

[0019] According to another aspect of the present invention, the present invention provides a cross-architecture instruction processor based on pattern matching and fusion, which is used to convert an instruction sequence in a first instruction set into an instruction sequence in a second instruction set, wherein the first instruction set and the second instruction set are based on different instruction set architectures; The cross-architecture instruction processor based on pattern matching and fusion includes an instruction fusion hardware module and a translation module; the instruction fusion hardware module is configured to determine whether there is a target first instruction sequence matching the first instruction sequence to be processed in the target instruction set, and if so, replace the first instruction sequence with a target second instruction sequence corresponding to the target first instruction sequence; If not, translating the first instruction sequence into a second instruction sequence using a translation module, where the second instruction sequence includes one or more instructions in a second instruction set; The target instruction set includes a plurality of the target first instruction sequences, the target first instruction sequence includes one or more instructions in the first instruction set, and the target first instruction sequence satisfies the following conditions: The second instruction set contains the target second instruction sequence for replacing the target first instruction sequence, and the number of instructions included in the target second instruction sequence is not greater than the number of instructions included in the corresponding target first instruction sequence.

[0020] Further, based on any one of the technical solutions or a combination of multiple technical solutions described above, the instruction fusion hardware module is configured with a function mode library, the function mode library includes multiple sub-mode libraries, the sub-mode libraries include the target first instruction sequences with the same function type, and the function types corresponding to the target first instruction sequences included in different sub-mode libraries are different; Each of the sub-pattern libraries is configured with a unique function type, and the function type corresponding to the sub-pattern library corresponds to the function type corresponding to the target first instruction sequence included therein; The instruction fusion hardware module is further configured to determine whether there is a target first instruction sequence matching the first instruction sequence in the target instruction set by: Determine a function type corresponding to the first instruction sequence and use it as a first function type; Determine whether there is a function type corresponding to the sub-pattern library corresponding to the first function type; if so, match the first instruction sequence with a target first instruction sequence included in the sub-pattern library corresponding to the function type; if the match is successful, the target first instruction sequence exists in the target instruction set and matches the first instruction sequence; If the match is unsuccessful or the function types corresponding to the sub-pattern libraries are not the first function types, then the target first instruction sequence matching the first instruction sequence does not exist in the target instruction set.

[0021] Further, based on any one of the above technical solutions or a combination of multiple technical solutions, the translation module includes a hardware translator and a cache unit, and the hardware translator is configured to translate the first instruction sequence into a second instruction sequence; The cache unit is configured to store a plurality of previous first instruction sequences and a previous second instruction sequence for replacing the previous first instruction sequence, the first instruction set includes the previous first instruction sequence, and the second instruction set includes the previous second instruction sequence; The usage frequency of the previous first instruction sequence is higher than the preset first usage frequency, and / or the time period of the most recent usage moment of the previous first instruction sequence relative to the current moment is within a preset time period range; The hardware translator is used to translate the first instruction sequence into a second instruction sequence, and it is determined whether the first instruction sequence is one of the multiple prior first instruction sequences. If so, the corresponding prior second instruction sequence is directly used to replace the first instruction sequence; if not, the translation result obtained by translating the first instruction sequence by the hardware translator is used as the second instruction sequence.

[0022] The beneficial effects brought by the technical solution provided by the present invention are as follows: a. The present invention realizes the processing of the first instruction sequence to the second instruction sequence by means of instruction matching and fusion and instruction translation, which reduces the use of simulators and improves the efficiency of instruction execution. Compared with the traditional DBT technology, this solution can realize the operation of X86 instructions on RISC architecture processors under more efficient conditions, and the method is applied to the pipeline of the processor for processing cross-architecture instructions, and no additional memory and computing resources are required, which can reduce pipeline pauses and improve the real-time performance of instruction processing. It has significant advantages in resource consumption. Compared with DBT technology, this method is more suitable for application scenarios with high real-time requirements, and is also particularly suitable for embedded systems with limited resources; b. The present invention can directly convert the corresponding first instruction sequence into a second instruction sequence with fewer instructions by performing pattern matching and fusion optimization on the first instruction sequence or the first instruction stream, thereby avoiding the performance bottleneck of the cross-architecture instruction processing system and improving the overall performance of the system. Compared with the traditional DBT technology, the present method can also perform better when processing complex instruction sequences; c. The present invention sets a cache unit to store the most recently used first instruction sequence and / or the frequently used first instruction sequence. If the cache unit hits the first instruction sequence to be translated, the second instruction sequence obtained by the previous translation can be directly output, which can reduce the overhead caused by repeated translation, improve the translation efficiency of the first instruction and reduce the consumption of resources. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0024] Figure 1 A flowchart of a cross-architecture instruction processing method based on pattern matching and fusion provided for an exemplary embodiment of the present invention; Figure 2 A schematic diagram of a process of processing an X86 instruction stream into a RISC-V instruction stream provided for an exemplary embodiment of the present invention; Figure 3 A flowchart of a first method for translating a first instruction sequence provided for an exemplary embodiment of the present invention; Figure 4 A flowchart of a second method for translating a first instruction sequence provided for an exemplary embodiment of the present invention; Figure 5A module block diagram of a cross-architecture instruction processor based on pattern matching and fusion is provided for an exemplary embodiment of the present invention. DETAILED DESCRIPTION

[0025] In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0026] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, device, product or equipment that includes a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or equipment.

[0027] Based on the deficiencies of the prior art, the present application aims to provide a cross-architecture instruction processing method and processor based on pattern matching and fusion, so as to realize high-efficiency and low-resource-consumption cross-architecture instruction processing and operation, including running the X86 instruction set on the RISC-V architecture, and running the ARM instruction set on the RISC-V architecture, etc., which can promote the development of the instruction set architecture towards high performance, high efficiency, low power consumption and multi-architecture fusion.

[0028] In one embodiment of the present invention, a cross-architecture instruction processing method based on pattern matching and fusion is provided, which is used to convert a first instruction sequence in a first instruction set into a second instruction sequence in a second instruction set, wherein the first instruction set and the second instruction set are based on different instruction set architectures, the first instruction sequence includes one or more instructions, and the second instruction sequence includes one or more instructions. Among them, the first instruction set is based on the X86 architecture, and the second instruction set is based on the RISC-V architecture, so as to realize the cross-architecture operation of the X86 instruction set based on the RISC-V architecture; it can also be that the first instruction set is based on the ARM architecture, and the second instruction set is based on the RISC-V architecture, so as to realize the cross-architecture operation of the ARM instruction set based on the RISC-V architecture. It should be noted that this method is not limited to these two cross-architecture instruction processing methods, and is also applicable to other cross-architecture instruction processing situations.

[0029] In this embodiment, see Figure 1 , the cross-architecture instruction processing method based on pattern matching and fusion includes the following steps: Determine a target instruction set from the first instruction set, the target instruction set includes multiple target first instruction sequences, determine a target second instruction sequence from the second instruction set for replacing the target first instruction sequence, the number of instructions included in the target second instruction sequence is not greater than the number of instructions included in the target first instruction sequence, and is used to merge / convert the first instruction sequence with more instructions into a second instruction sequence with fewer instructions (at least not more), for example, to merge (combine) three X86 instructions (LOAD, ALU operation, and STORE) into a composite RISC-V instruction; Acquire a first instruction sequence to be processed, determine whether there is a target first instruction sequence matching the first instruction sequence in the target instruction set, and if so, replace the first instruction sequence with the target second instruction sequence corresponding to the target first instruction sequence; If not present, the first instruction sequence is translated into a second instruction sequence.

[0030] Among them, through a predetermined target instruction set and a predetermined target second instruction sequence for replacing each target first instruction sequence in the target instruction set, through matching judgment, the successfully matched first instruction sequence is directly replaced with the corresponding target second instruction sequence and output, which can effectively improve the efficiency and accuracy of cross-architecture instruction processing / translation.

[0031] In addition, since the number of instructions included in the target second instruction sequence is not greater than the number of instructions included in the target first instruction sequence, this method can achieve the matching and fusion of the first instruction sequence into a smaller second instruction sequence. Compared with the existing dynamic binary translation (DBT) technology, the number of translated instructions can be effectively reduced. Compared with the existing technology, this method has significant advantages in improving cross-architecture instruction execution efficiency, reducing resource consumption, optimizing instruction flow, and improving real-time performance and compatibility.

[0032] In one embodiment of the present invention, in order to further improve the execution efficiency of cross-architecture instruction processing, reduce resource consumption and avoid performance bottlenecks, a cross-architecture instruction processing method based on pattern matching and fusion is further implemented in the following way.

[0033] See also Figure 1 and Figure 2 , multiple target first instruction sequences in the target instruction set are classified according to function types to construct a function mode library, the function mode library includes multiple sub-mode libraries, the sub-mode libraries include the target first instruction sequences with the same function type, and the function types corresponding to the target first instruction sequences included in different sub-mode libraries are different.

[0034] A unique function type is configured for each sub-pattern library, and the function type corresponding to the sub-pattern library corresponds to the function type corresponding to the target first instruction sequence included therein. It should be noted that the correspondence here includes identical, consistent and matching.

[0035] Taking the X86 instruction set or the ARM instruction set as an example, the functional types of the first instruction sequence included therein usually include load-operation-store (LOAD-OP-STORE), inter-register operations, address calculation and memory access, and loop control, etc. Among them, load usually refers to loading data from memory to registers (such as MOV EAX, [addr]), operation usually refers to operating on the loaded data (such as addition, subtraction, etc., such as ADD EAX, EBX), and storage usually refers to storing the processed data back to the memory (such as MOV [addr], EAX).

[0036] Accordingly, the functional pattern library includes but is not limited to the following sub-pattern libraries: one or more of a load-operate-store sub-pattern library, an inter-register operation sub-pattern library, an address calculation and memory access sub-pattern library, and a loop control sub-pattern library.

[0037] The load-operate-store sub-pattern library includes the following target first instruction sequences: a load data instruction sequence from a memory, an execute ALU (arithmetic and logic unit) instruction sequence, and a store back to memory instruction sequence. Accordingly, the function type of the load-operate-store sub-pattern library is determined to be load-operate-store.

[0038] The inter-register operation sub-pattern library includes the following target first instruction sequences: continuous register addition and subtraction operation instruction sequences, shift instruction sequences and logic operation instruction sequences. Accordingly, the function type of the inter-register operation sub-pattern library is determined to be inter-register operation.

[0039] The memory access sub-pattern library includes the following target first instruction sequence: an address calculation instruction sequence based on an offset and a base address. Accordingly, the function type of the memory access sub-pattern library is determined to be memory access.

[0040] The loop control sub-pattern library includes the following target first instruction sequences: a conditional jump operation instruction sequence and a loop instruction sequence. Accordingly, the function type of the loop control sub-pattern library is determined to be loop control.

[0041] In this embodiment, it is not necessary to compare the first instruction sequence to be processed with each target first instruction sequence in the target instruction set one by one to determine whether there is the target first instruction sequence matching the first instruction sequence, and efficient pattern matching is performed in the following manner: Determine a function type corresponding to the first instruction sequence and use it as a first function type; Determine whether there is a function type corresponding to the sub-pattern library that corresponds to the first function type; if so, match the first instruction sequence with a target first instruction sequence included in the sub-pattern library; if the match succeeds, the target first instruction sequence exists in the target instruction set and matches the first instruction sequence; If the match is unsuccessful or the function types corresponding to the sub-pattern libraries are not the first function types, then the target first instruction sequence matching the first instruction sequence does not exist in the target instruction set.

[0042] It should be noted that the names and functional types of each sub-pattern library described in this embodiment are only exemplary, and the names and functional types of each sub-pattern library are not used to limit the protection scope of this application. In other embodiments, the names of each sub-pattern library and its corresponding functional type can also be determined by numbering, labeling, etc., such as sub-pattern library 1, sub-pattern library 2, ..., sub-pattern library n (n is an integer not less than 2), and the corresponding functional types are determined as type 1, type 2, ..., type n. As long as the multiple target first instruction sequences in the target instruction set are classified according to the functional type to construct a functional pattern library including multiple sub-pattern libraries, and the same sub-pattern library includes the target first instruction sequence with the same functional type, and the target first instruction sequences included in different sub-pattern libraries have different functional types, they all fall within the protection scope of this application.

[0043] The present application proposes to classify multiple target first instruction sequences in the target instruction set according to the function type, rather than classifying them according to other methods such as the frequency of use, because based on the classification of the function type, the function type corresponding to the first instruction sequence can be quickly determined by extracting the operation code of the first instruction sequence to be processed, thereby narrowing the matching range of the first instruction sequence. If the classification is performed according to the instruction length or the frequency of use, the function mode library cannot be matched by the operation code of the first instruction sequence. However, when determining the target instruction set from the first instruction set, the first instruction sequence with high frequency of use (the frequency of use is higher than the preset second frequency of use) can be screened out according to the frequency of use, and the first instruction sequence that can be merged into a second instruction sequence with fewer (or equal) instructions can be further screened out from the first instruction sequence with high frequency of use, thereby obtaining the target instruction set.

[0044] The method is not only applicable to converting the first instruction sequence into the second instruction sequence, but also applicable to converting a first instruction stream into a second instruction stream, wherein the first instruction stream includes a plurality of the first instruction sequences, and the second instruction stream includes a plurality of the second instruction sequences.

[0045] In one embodiment of the present invention, the first instruction stream is detected, matched and translated in a timely manner to output the second instruction stream in real time in the following manner. Figure 3 As shown, a sliding window detection mechanism is used to obtain the first instruction sequence to be processed. The sliding window can analyze the input instruction stream in real time and detect in real time whether the input first instruction stream, such as the X86 instruction stream, conforms to the pattern in the pattern library. The function of the sliding window is to maintain a fixed length of instruction stream queue, and gradually slide to check whether there is a sequence matching the pattern library.

[0046] Preferably, the size of the sliding window can be adjusted dynamically, and the size, i.e., the length, of the sliding window can be adjusted according to the length definition of the longest first instruction sequence in the functional mode library, and two adjacent detection ranges of the sliding window are connected or have overlapping parts to ensure that all possible first instruction sequences are covered.

[0047] Therefore, before using the sliding window to perform matching detection on the first instruction stream, the maximum length of the target first instruction sequence in the target instruction set must be determined first. Then, the length of the sliding window is defined to be not less than the maximum length, and the first instruction stream includes multiple first instruction sequences, which are usually multiple first instruction sequences input sequentially.

[0048] Matching algorithm: Each time the sliding window moves, the instruction sequence in the window is matched and compared with each sub-pattern library in the above-mentioned functional pattern library. In the sliding window, the sub-pattern library consistent with its functional type is determined according to the operation code of the extracted instruction sequence. Preferably, hardware parallel logic is used to achieve simultaneous matching of multiple sub-pattern libraries. If there is a sub-pattern library consistent with the functional type corresponding to the instruction sequence extracted by the sliding window, the instruction sequence is compared with the target first instruction sequence in the sub-pattern library, and the match is successful if they are consistent. If the match is successful, the instruction fusion logic step is directly entered, that is, the corresponding target second instruction sequence is directly used to replace the first instruction sequence and output. If the match fails, the first instruction sequence is translated into the second instruction sequence by hardware translation or software translation (such as the above-mentioned DBT technology).

[0049] It should be noted that, in this embodiment, Figure 1 and Figure 2 As shown, for the current first instruction sequence in the first instruction stream, if the target first instruction sequence does not exist in the target instruction set and matches the current first instruction sequence, the current first instruction sequence is translated into a second instruction sequence. And when translating the current first instruction sequence, it is also determined whether the target first instruction sequence in the target instruction set matches the first instruction sequence after the current first instruction sequence in the first instruction stream. That is, for the first instruction sequence that is not successfully matched, it will be directly passed to the translation logic process without interfering with the normal operation of the pattern matching and instruction fusion logic, that is, the pattern matching judgment and instruction fusion output process of the subsequent first instruction sequence obtained by the sliding window can be synchronized with the translation process of the first instruction sequence that failed to match first, therefore, the efficiency of cross-architecture instruction processing, operation, and execution can be more efficiently improved.

[0050] In one embodiment of the present invention, a method for translating the first instruction sequence efficiency based on hardware acceleration is provided, such as Figure 3As shown, a cache unit is pre-configured, and the cache unit is configured to store multiple first instruction sequences and a second instruction sequence for replacing the first instruction sequence. The first instruction set includes the first instruction sequence, and the second instruction set includes the second instruction sequence. It should be noted that the first instruction sequence is the first instruction sequence that failed to match before entering the translation process, and these first instruction sequences also meet the following conditions: the frequency of use of the first instruction sequence is higher than the preset first frequency of use, and / or the time period of the most recent use of the first instruction sequence is within the preset time period range relative to the current time period. The second instruction sequence is the translation result corresponding to the first instruction sequence. By setting the cache unit, the overhead caused by repeated translation can be reduced, the translation efficiency can be improved, and the consumption of resources can be reduced.

[0051] Preferably, the cache unit is configured as a two-level cache structure, including a first-level cache structure and a second-level cache structure, wherein the first-level cache structure stores the most recent first instruction sequence and its translation result, and the second-level cache structure stores the frequently used first instruction sequence and its translation result.

[0052] Determine whether the first instruction sequence is one of the plurality of previous first instruction sequences in the two-level cache structure; if so, directly use the corresponding previous second instruction sequence to replace the first instruction sequence; if not, translate the first instruction sequence into the second instruction sequence in the following manner: The parallel decoding logic is used to perform parallel processing and field separation on multiple instructions in the first instruction sequence, including extracting operation codes, operands, and prefix information. The parallel decoding logic supports parsing multiple bytes at the same time, and improves the decoding speed of the first instruction sequence through pipeline design.

[0053] Each of the instructions is translated through a look-up table (LUT) or a preset translation rule, and the second instruction sequence is determined according to the translation results of each of the instructions.

[0054] The mapping from X86 to RISC-V instructions is achieved through a lookup table (LUT). The translation process includes: searching the LUT according to the rules of retrieving the corresponding RISC-V instruction template according to the opcode of the first instruction sequence; for the processing of complex instructions, such as complex X86 instructions that require multiple RISC-V instructions to complete, multi-stage translation logic is designed to gradually generate a complete second instruction sequence.

[0055] like Figure 3The instruction translation process shown in the figure first queries the cache unit, and if there is no previous translation result of the current first instruction sequence, then translates the current first instruction sequence by looking up the table, which can take into account both translation efficiency and resource consumption. In another embodiment of the present invention, Figure 3 Different from the process shown in FIG. 1 , in this embodiment, the translation process of the first instruction sequence is as follows: Figure 4 As shown, when translating the current first instruction sequence, the cache unit and LUT are queried in parallel. If a previous translation record is hit in the cache unit, the translation result is directly output and the lookup table translation method is terminated. If there is no previous translation record hit in the cache unit, the translation result is obtained with the lookup table. This process consumes more resources, but can greatly shorten the translation time and improve the translation efficiency of the first instruction sequence.

[0056] The method further comprises: identifying the first instruction sequence that does not conform to the specification by checking the legality of the operation code and the operand and issuing a prompt message. Lookup table (LUT) match failure: If the instruction cannot find a match in the LUT, the instruction is considered illegal and an exception signal is triggered.

[0057] The following is a specific application example to illustrate how the cross-architecture instruction processing method based on pattern matching and fusion proposed in this application improves the translation efficiency and processing efficiency of cross-architecture instructions.

[0058] For an X86 instruction sequence (instruction sequence 1) of the function type of load-operate-store, the first instruction sequence 1 is: MOV EAX, [0×1000]; load data from memory to EAX; ADD EAX,EBX;EAX=EAX+EBX; MOV [0×1000], EAX; store the value of EAX back to memory; The RISC-V instruction sequence obtained by translating (without fusion) the X86 instruction sequence (instruction sequence 1) is as follows: LW t0, 0×1000(t1); load memory data to t0; ADD t0, t0, t2; t0=t0+t2; SW t0, 0×1000(t1); store the value of t0 back to the memory; The X86 instruction sequence (instruction sequence 1) is fused to obtain the RISC-V instruction sequence (target second instruction sequence 1): AMOADD W t0, t0, (0×1000); perform an atomic addition operation on address 0×1000.

[0059] It can be seen that the pattern matching fusion method can directly use the shorter and more concise target second instruction sequence 1 to replace the first instruction sequence 1, which not only does not require a long translation time, but also can reduce the instruction length and improve the instruction execution efficiency.

[0060] For an X86 instruction sequence (instruction sequence 2) whose function type is address calculation and memory access, the first instruction sequence 2 is: LEA EAX, [EBX+ECX*4]; load the address of EBX+ECX*4 into EAX; MOV [EAX], EDX; Store the value of EDX into the calculated address.

[0061] The RISC-V instruction sequence obtained by translating (without fusion) the X86 instruction sequence (instruction sequence 2) is as follows: ADD t0, tl, t2; t0=tl+t2; SLL t0, t0, 2; t0 = t0 * 4 SW t3, 0(t0); stores the value of t3 into the address calculated at t0.

[0062] The X86 instruction sequence (instruction sequence 2) is fused to obtain the RISC-V instruction sequence (target second instruction sequence 2): AMOADD.W t0, t3, (t1+t2*4); perform an addition operation at address t1+t2*4.

[0063] It can be seen that if the translation method is adopted, instruction sequence 2 will usually be translated into a longer RISC-V instruction sequence. However, by adopting the pattern matching fusion method, the shorter target second instruction sequence 2 can be directly used to replace the first instruction sequence 2. Not only does it not require a long translation time, but it can also reduce the instruction length and improve the instruction execution efficiency.

[0064] In one embodiment of the present invention, a cross-architecture instruction processor based on pattern matching and fusion is provided, which is used to convert an instruction sequence in a first instruction set into an instruction sequence in a second instruction set, wherein the first instruction set and the second instruction set are based on different instruction set architectures.

[0065] The cross-architecture instruction processor based on pattern matching and fusion includes an instruction fusion hardware module (abbreviated as IFHM) and a translation module (abbreviated as HTA). The instruction fusion hardware module and the translation module are configured to process a first instruction stream in parallel, and the priority of the instruction fusion hardware module is higher than the priority of the translation module.

[0066] like Figure 5As shown, the cross-architecture instruction processor based on pattern matching and fusion includes a decoder, an instruction fusion hardware module and a translation module. The first instruction stream input to the processor, such as an X86 instruction stream, is first decoded and field separated by the decoder, and the decoded X86 instruction stream can be obtained and output to the instruction fusion hardware module.

[0067] The instruction fusion hardware module includes a sliding window detection module, a pattern matching module and a functional pattern library. The functional pattern library stores a target instruction set, the target instruction set includes a plurality of target first instruction sequences, the target first instruction sequence includes one or more instructions in the first instruction set, and the target first instruction sequence satisfies the following conditions: The second instruction set contains the target second instruction sequence for replacing the target first instruction sequence, and the number of instructions included in the target second instruction sequence is not greater than the number of instructions included in the corresponding target first instruction sequence.

[0068] More preferably, multiple target first instruction sequences in the target instruction set are classified by function type to construct corresponding sub-pattern libraries, a unique function type is configured for each sub-pattern library, and the function type corresponding to the sub-pattern library corresponds to the function type corresponding to the target first instruction sequence included therein. Therefore, the functional pattern library includes multiple sub-pattern libraries, each of which includes multiple target first instruction sequences with the same function type, and the function types corresponding to the target first instruction sequences included in different sub-pattern libraries are different.

[0069] The sliding window detection module is configured to use a sliding window to analyze the input instruction stream in real time, that is, to detect the input X86 instruction stream in real time. Its function is to maintain an instruction stream queue of a fixed length, gradually slide and extract the corresponding instruction sequence, and cooperate with the pattern matching module to perform pattern matching judgment on the current first instruction sequence, thereby being able to quickly identify the first instruction sequence that can be integrated in the first instruction stream.

[0070] The pattern matching module is configured to determine whether there is a target first instruction sequence matching the first instruction sequence to be processed in the target instruction set; if so, replace the first instruction sequence with a target second instruction sequence corresponding to the target first instruction sequence; if not, transmit the first instruction sequence that fails the pattern matching to the translation module, and use the translation module to translate the first instruction sequence into the corresponding second instruction sequence.

[0071] Based on a functional pattern library including a plurality of sub-pattern libraries, the instruction fusion hardware module is further configured to determine whether there is a target first instruction sequence matching the first instruction sequence in the target instruction set by: Determine a function type corresponding to the first instruction sequence and use it as a first function type; Determine whether there is a function type corresponding to the sub-pattern library that corresponds to the first function type; if so, match the first instruction sequence with a target first instruction sequence included in the sub-pattern library; if the match succeeds, the target first instruction sequence exists in the target instruction set and matches the first instruction sequence; If the match fails or the function types corresponding to the sub-pattern libraries do not correspond to the first function type, the target first instruction sequence matching the first instruction sequence does not exist in the target instruction set.

[0072] The instruction fusion hardware module stores common / high-frequency X86 instruction sequences through a functional pattern library, and fuses the matching X86 instruction sequences into efficient RISC-V composite instructions according to predefined fusion rules, that is, converts multiple instructions into efficient RISC-V instructions, thereby reducing the number of instructions and optimizing execution efficiency.

[0073] The translation module includes a hardware translator and a cache unit, and the hardware translator is configured to translate the first instruction sequence into a second instruction sequence.

[0074] The cache unit stores previous translation results, and is configured to store a plurality of previous first instruction sequences and a previous second instruction sequence for replacing the previous first instruction sequence, wherein the first instruction set includes the previous first instruction sequence, and the second instruction set includes the previous second instruction sequence.

[0075] Wherein, the usage frequency of the previous first instruction sequence is higher than the preset first usage frequency, and / or, the time period of the most recent usage of the previous first instruction sequence relative to the current time period is within the preset time period range. Preferably, the cache unit is a two-level cache structure, including a first-level cache structure and a second-level cache structure. Wherein, the first-level cache structure stores the most recent first instruction sequence and its translation results; the second-level cache structure stores the first instruction sequence and its translation results that are used frequently.

[0076] The hardware translator is used to translate the first instruction sequence into a second instruction sequence, and it is determined whether the first instruction sequence is one of the multiple previous first instruction sequences. If so, the corresponding previous second instruction sequence is directly used to replace the first instruction sequence; if not, the translation result obtained by translating the first instruction sequence by the hardware translator is used as the second instruction sequence. It should be noted that it is possible to first determine whether there is a translation record that hits the current first instruction sequence in the cache unit. If so, it is directly called and output; if not, the hardware translator is used to translate the first instruction sequence. It is also possible to set the cache unit to search for the previous translation record and the hardware translator to perform the translation to be performed simultaneously to further improve the translation efficiency of the first instruction sequence.

[0077] The design of the cache unit can improve the translation performance of the translation module and reduce the overhead of repeated translation. The hardware translator uses multi-byte parallel decoding technology to quickly parse X86 instructions, including information such as opcodes, operands, and prefixes, and uses a lookup table to complete instruction mapping and translate it into an equivalent RISC-V instruction sequence.

[0078] The cross-architecture instruction processor based on pattern matching and fusion proposed in the above embodiments adopts a hardware modular design approach, and realizes efficient instruction translation and execution optimization from X86 to RISC-V through the collaborative work of the instruction fusion hardware module and the translation module.

[0079] In summary, the present invention forms an efficient X86 to RISC-V translation and optimized execution architecture through the collaborative working mechanism of hardware translation acceleration and instruction fusion optimization and modular pipeline integration. The combination of these technical means greatly improves the instruction execution efficiency, reduces power consumption, and provides strong hardware support for the migration of the X86 ecosystem to RISC-V.

[0080] Therefore, it can be widely used in the fields of software development, embedded systems, servers and cloud computing. In terms of software development, the technical solution described in the above embodiment can efficiently merge and translate X86 instructions into RISC-V instructions, which can greatly improve the efficiency of software development. In addition, developers can use existing X86 development tools and libraries without worrying about the differences in the underlying hardware architecture. In addition, since the technical solution can achieve high execution efficiency of cross-architecture instruction processing, it can meet application scenarios with high real-time requirements, such as game development, multimedia processing, etc. Applying the technical solution to embedded systems can efficiently run X86 instructions in resource-limited embedded systems, which is a huge advantage for resource-limited embedded systems. For example, in applications such as smart homes and smart wearable devices, the technical solution can provide high-performance, low-power computing support to meet the requirements of the device for real-time and energy consumption. In the field of servers and cloud computing, high performance and low latency are crucial. By optimizing the instruction flow and execution efficiency, the technical solution can significantly improve the performance of the server, reduce latency, and improve the overall efficiency of the system. In addition, due to the high execution efficiency of the technical solution, the number of servers can be reduced, the operating cost can be reduced, and the economic benefit can be improved. In general, this technical solution has broad application prospects in software development, embedded systems, servers, cloud computing and other fields, meeting the market demand for high-efficiency, low-power, and high-performance computing.

[0081] It should be noted that the cross-architecture instruction processor embodiment based on pattern matching and fusion provided by the present invention has the same inventive concept as the above-mentioned cross-architecture instruction processing method embodiment based on pattern matching and fusion. The entire content of the cross-architecture instruction processing method embodiment based on pattern matching and fusion is incorporated into the cross-architecture instruction processor embodiment based on pattern matching and fusion by introduction.

[0082] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or device including the elements.

[0083] The above is only a specific implementation of the present application. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principles of the present application. These improvements and modifications should also be regarded as the scope of protection of the present application.

Claims

1. A cross-architecture instruction processing method based on pattern matching and fusion, characterized in that: The method is used to convert a first instruction sequence in a first instruction set into a second instruction sequence in a second instruction set, wherein the first instruction set and the second instruction set are based on different instruction set architectures, and the method comprises the following steps: Determine a target instruction set from the first instruction set, the target instruction set including a plurality of target first instruction sequences, determine a target second instruction sequence from the second instruction set for replacing the target first instruction sequence, the number of instructions included in the target second instruction sequence being no greater than the number of instructions included in the corresponding target first instruction sequence; Acquire a first instruction sequence to be processed, determine whether there is a target first instruction sequence matching the first instruction sequence in the target instruction set, and if so, replace the first instruction sequence with the target second instruction sequence corresponding to the target first instruction sequence; If not present, the first instruction sequence is translated into a second instruction sequence.

2. The cross-architecture instruction processing method based on pattern matching and fusion according to claim 1, characterized in that: The following steps are also included: Classifying the plurality of target first instruction sequences in the target instruction set according to the function type to construct a function mode library, wherein the function mode library comprises a plurality of sub-mode libraries, wherein the sub-mode libraries comprise the target first instruction sequences with the same function type, and the function types corresponding to the target first instruction sequences comprised in different sub-mode libraries are different; A unique function type is configured for each of the sub-pattern libraries, and the function type corresponding to the sub-pattern library corresponds to the function type corresponding to the target first instruction sequence included therein; It is determined whether the target first instruction sequence that matches the first instruction sequence exists in the target instruction set by: Determine a function type corresponding to the first instruction sequence and use it as a first function type; Determine whether there is a function type corresponding to the sub-pattern library corresponding to the first function type; if so, match the first instruction sequence with a target first instruction sequence included in the sub-pattern library of the corresponding function type; if the match is successful, the target first instruction sequence matching the first instruction sequence exists in the target instruction set; If the match fails or the function types corresponding to the sub-pattern libraries do not correspond to the first function type, the target first instruction sequence matching the first instruction sequence does not exist in the target instruction set.

3. The cross-architecture instruction processing method based on pattern matching and fusion according to claim 2, characterized in that: The sub-pattern library includes one or more of a load-operate-store sub-pattern library, an inter-register operation sub-pattern library, an address calculation and memory access sub-pattern library, and a loop control sub-pattern library; Wherein, the load-operate-store sub-mode library includes the following target first instruction sequences: a load data from memory instruction sequence, an execute ALU instruction sequence, and a store back to memory instruction sequence; The inter-register operation sub-pattern library includes the following target first instruction sequences: a continuous register addition and subtraction operation instruction sequence, a shift instruction sequence and a logic operation instruction sequence; The memory access sub-mode library includes the following target first instruction sequence: an address calculation instruction sequence based on an offset and a base address; The loop control sub-pattern library includes the following target first instruction sequences: a conditional jump operation instruction sequence and a loop instruction sequence.

4. The cross-architecture instruction processing method based on pattern matching and fusion according to claim 1, characterized in that: The method also includes obtaining a first instruction sequence to be processed by: Determine the maximum length of the target first instruction sequence in the target instruction set; A sliding window is used to detect an input first instruction stream, the length of the sliding window is not less than the maximum length, and the first instruction stream includes a plurality of the first instruction sequences.

5. The cross-architecture instruction processing method based on pattern matching and fusion according to claim 4, characterized in that: Two adjacent detection ranges of the sliding window are connected or have overlapping parts.

6. The cross-architecture instruction processing method based on pattern matching and fusion according to claim 1, characterized in that: The first instruction sequence is translated into the second instruction sequence in the following manner: Parallel processing and field separation of multiple instructions in the first instruction sequence, including extracting operation code, operand and prefix information; Each instruction in the first instruction sequence is translated through a lookup table or a preset translation rule, and the second instruction sequence is determined according to the translation results of each instruction.

7. The cross-architecture instruction processing method based on pattern matching and fusion according to claim 6, characterized in that: Translating the first instruction sequence into a second instruction sequence further includes: configuring a cache unit, the cache unit being configured to store a plurality of previous first instruction sequences and a previous second instruction sequence for replacing the previous first instruction sequence, the first instruction set including the previous first instruction sequence, and the second instruction set including the previous second instruction sequence; The usage frequency of the previous first instruction sequence is higher than the preset first usage frequency, and / or the time period of the most recent usage of the previous first instruction sequence relative to the current time period is within a preset time period range; It is determined whether the first instruction sequence is one of the plurality of previous first instruction sequences; if so, the first instruction sequence is directly replaced by the corresponding previous second instruction sequence.

8. The cross-architecture instruction processing method based on pattern matching and fusion according to claim 6, characterized in that: The first instruction sequence is translated into a second instruction sequence, further comprising: The first instruction sequence that does not conform to the specification is identified by checking the legality of the operation code and the operand, and a prompt message is issued.

9. The cross-architecture instruction processing method based on pattern matching and fusion according to claim 1, characterized in that: The method is used to convert a first instruction stream into a second instruction stream, wherein the first instruction stream includes a plurality of first instruction sequences, and the second instruction stream includes a plurality of second instruction sequences.

10. The cross-architecture instruction processing method based on pattern matching and fusion according to claim 9, characterized in that: For a current first instruction sequence in the first instruction stream, if the target first instruction sequence matching the current first instruction sequence does not exist in the target instruction set, translating the current first instruction sequence into a second instruction sequence; When translating the current first instruction sequence, it is simultaneously determined whether there is a target first instruction sequence in the target instruction set that matches the first instruction sequence after the current first instruction sequence.

11. The cross-architecture instruction processing method based on pattern matching and fusion according to claim 1, characterized in that: The first instruction set is based on the X86 architecture, and the second instruction set is based on the RISC-V architecture; or, The first instruction set is based on the ARM architecture, and the second instruction set is based on the RISC-V architecture.

12. The cross-architecture instruction processing method based on pattern matching and fusion according to claim 1, characterized in that: The usage frequency of the target first instruction sequence is higher than a preset second usage frequency.

13. A cross-architecture instruction processor based on pattern matching and fusion, characterized in that: Used to convert an instruction sequence in a first instruction set into an instruction sequence in a second instruction set, wherein the first instruction set and the second instruction set are based on different instruction set architectures; The cross-architecture instruction processor based on pattern matching and fusion includes an instruction fusion hardware module and a translation module; the instruction fusion hardware module is configured to determine whether there is a target first instruction sequence matching the first instruction sequence to be processed in the target instruction set, and if so, replace the first instruction sequence with a target second instruction sequence corresponding to the target first instruction sequence; If not, translating the first instruction sequence into a second instruction sequence using a translation module, where the second instruction sequence includes one or more instructions in a second instruction set; The target instruction set includes a plurality of the target first instruction sequences, the target first instruction sequence includes one or more instructions in the first instruction set, and the target first instruction sequence satisfies the following conditions: The second instruction set contains the target second instruction sequence for replacing the target first instruction sequence, and the number of instructions included in the target second instruction sequence is not greater than the number of instructions included in the corresponding target first instruction sequence.

14. The cross-architecture instruction processor based on pattern matching and fusion according to claim 13, characterized in that: The instruction fusion hardware module is configured with a function mode library, the function mode library includes a plurality of sub-mode libraries, the sub-mode library includes a plurality of the target first instruction sequences with the same function type, and the function types corresponding to the target first instruction sequences included in different sub-mode libraries are different; Each of the sub-pattern libraries is configured with a unique function type, and the function type corresponding to the sub-pattern library corresponds to the function type corresponding to the target first instruction sequence included therein; The instruction fusion hardware module is further configured to determine whether there is a target first instruction sequence matching the first instruction sequence in the target instruction set by: Determine a function type corresponding to the first instruction sequence and use it as a first function type; Determine whether there is a function type corresponding to the sub-pattern library corresponding to the first function type; if so, match the first instruction sequence with a target first instruction sequence included in the sub-pattern library of the corresponding function type; if the match is successful, the target first instruction sequence exists in the target instruction set and matches the first instruction sequence; If the match fails or the function types corresponding to the sub-pattern libraries do not correspond to the first function type, the target first instruction sequence matching the first instruction sequence does not exist in the target instruction set.

15. The cross-architecture instruction processor based on pattern matching and fusion according to claim 13, characterized in that: The translation module includes a hardware translator and a cache unit, wherein the hardware translator is configured to translate the first instruction sequence into a second instruction sequence; The cache unit is configured to store a plurality of previous first instruction sequences and a previous second instruction sequence for replacing the previous first instruction sequence, the first instruction set includes the previous first instruction sequence, and the second instruction set includes the previous second instruction sequence; The usage frequency of the previous first instruction sequence is higher than the preset first usage frequency, and / or the time period of the most recent usage moment of the previous first instruction sequence relative to the current moment is within a preset time period range; The hardware translator is used to translate the first instruction sequence into a second instruction sequence, and it is determined whether the first instruction sequence is one of the multiple prior first instruction sequences. If so, the corresponding prior second instruction sequence is directly used to replace the first instruction sequence; if not, the translation result obtained by translating the first instruction sequence by the hardware translator is used as the second instruction sequence.

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