Intelligent processor and data dimension expansion method thereof
By copying data along the first dimension of input blocked data in the register of the intelligent processor, the problem of multiple access to main memory caused by data expansion in the prior art is solved, which improves processing efficiency and reduces costs.
Patent Information
- Application Number
- CN202411764435.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-03
- Publication Date
- 2025-03-28
AI Technical Summary
When performing element-by-element operations, the input data needs to be expanded, resulting in multiple accesses of the main memory during the data expansion period, reducing overall system efficiency and increasing the implementation cost of the main memory.
An intelligent processor is designed, including registers, direct memory access controllers, instruction control circuits and operation circuits. Data dimension expansion is implemented by copying data in the register along the first dimension of input chunked data, thereby performing dimension expansion operations in high-speed registers.
By expanding data in registers, the processor's processing efficiency of expanding tensor data is improved, the overall system cost is reduced, and the efficiency of performing element-by-element operations is improved.
Smart Images
Figure CN119718427A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of processor technology, and in particular to an intelligent processor and a data dimension expansion method thereof. Background Art
[0002] Element-wise operations are common in the fields of data processing and deep learning. Generally speaking, in order to correctly perform element-wise operations, the dimension of the input data must be the same as the dimension of the output data. In the prior art, when the dimension of the input data is different from the dimension of the output data, the central processing unit will expand the dimension of the input data in the main memory, causing the main memory to be accessed multiple times during the data expansion period, thereby reducing the overall system efficiency. On the other hand, the above approach requires the main memory to have a large storage space, resulting in a significant increase in the implementation cost of the main memory. Summary of the invention
[0003] One of the purposes of this application is to provide an intelligent processor and a data dimension expansion method thereof to improve the deficiencies of the prior art.
[0004] In some embodiments, the intelligent processor includes a register, a direct memory access controller, an instruction control circuit, and an operation circuit. The direct memory access controller obtains an input block data of an input tensor data from a memory and stores the input block data to the register. The instruction control circuit copies the input block data along a first dimension of the input block data in the register according to the size of an output block data of an output tensor data to generate a first block data, and the first block data has the same size as the output block data. The operation circuit performs an element-by-element operation using the first block data to generate the output block data.
[0005] In some embodiments, the data dimension expansion method performed by the intelligent processor includes the following operations: reading an input block data of an input tensor data from a memory and storing the input block data to a register in the intelligent processor; and copying the input block data along a first dimension of the input block data in the register according to the size of an output block data of an output tensor data to generate a first block data, wherein the first block data and the output block data have the same size, and the first block data is used to perform an element-by-element operation to generate the output block data.
[0006] The features, implementation and effects of the present application are described in detail below with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS
[0007] Figure 1 A schematic diagram of an intelligent processor is drawn according to some embodiments of the present application;
[0008] Figure 2 According to some embodiments of the present application, Figure 1 A flowchart of the relevant operations performed by the central processing unit and the intelligent processor;
[0009] Figure 3 A schematic diagram of expanding the innermost dimension of input block data according to some embodiments of the present application is drawn;
[0010] Figure 4 A schematic diagram of expanding the secondary inner dimension of input block data according to some embodiments of the present application; and
[0011] Figure 5 The present invention is a flowchart of a data dimension expansion method drawn according to some embodiments of the present application.
[0012] Reference numerals:
[0013] 100: Intelligent processor;
[0014] 101: CPU;
[0015] 102: memory;
[0016] 110: register;
[0017] 120: Direct memory access controller;
[0018] 130: command control circuit;
[0019] 140: Operational circuit;
[0020] 500: Data dimension expansion method;
[0021] CMD: default command;
[0022] D1B: first block data;
[0023] DIB: input block data;
[0024] DIN: input tensor data;
[0025] DO: output tensor data;
[0026] DOB: output block data;
[0027] S201, S202, S203, S204: operation;
[0028] S205, S206, S207, S208: operation;
[0029] S510, S520: Operation. DETAILED DESCRIPTION
[0030] All words used herein have their ordinary meanings. The definitions of the above words in commonly used dictionaries, including any use examples of the words discussed herein in the content of this application are only examples and should not limit the scope and meaning of this application. Similarly, this application is not limited to the various embodiments shown in this specification.
[0031] As used herein, "coupled" or "connected" may refer to two or more elements making direct physical or electrical contact with each other, or making indirect physical or electrical contact with each other, or may refer to two or more elements operating or acting on each other. As used herein, the term "circuit" may refer to a device composed of at least one transistor and / or at least one active and passive element connected in a certain manner to process signals.
[0032] Figure 1 A schematic diagram of an intelligent processor 100 is drawn according to some embodiments of the present application. The intelligent processor 100 can execute multiple default instructions CMD issued by the central processor 101 to perform data dimension expansion (if necessary) and element-wise operations on the input tensor data DIN, thereby generating output tensor data DO.
[0033] The intelligent processor 100 includes a register 110, a direct memory access controller 120, an instruction control circuit 130, and an operation circuit 140. In some embodiments, the register 110 may be a virtual register, which may be, but not limited to, a high-speed memory. In some embodiments, the operation circuit 140 may be a vector core circuit. In some embodiments, the operation circuit 140 may include, but not limited to, a convolution processing circuit, a vector processing circuit, a scaling processing circuit, and the like.
[0034] The direct memory access controller 120 is coupled to the memory 102 to obtain a plurality of input tile data DIB of the input tensor data DIN from the memory 102, and sequentially store the plurality of input tile data DIB in the register 110. The instruction control circuit 130 copies the input tile data DIB along the first dimension of the input tile data DIB in the register 110 according to the size of the output tile data DOB of the output tensor data DO to generate the first tile data D1B. In some embodiments, the aforementioned first dimension may include, but is not limited to, the outermost dimension and the second outermost dimension. The operation here will be referred to later. Figure 2 , Figure 3 as well as Figure 4The operation circuit 140 may perform element-by-element operation on the first block data D1B to generate a plurality of output block data DOB, and then sequentially output the plurality of output block data DOB as output tensor data DO. The direct memory access controller 120 may sequentially obtain the plurality of output block data DOB from the memory 102, and sequentially store the obtained plurality of output block data DOB to the memory 102 to be combined into output tensor data DO.
[0035] In order to perform element-by-element operations, it is generally required that the shape and size of the input tensor data DIN be consistent with the shape and size of the output tensor data DO. The shape and size of tensor data are usually defined by dimensions. For example, the size of the output tensor data DO can be expressed as [3, 32, 256, 18], which means that the output tensor data DO is a 4-dimensional tensor data, where the dimension number of the outermost dimension is 3, the dimension number of the second outer dimension is 32, the dimension number of the second inner dimension is 256, and the dimension number of the innermost dimension is 18. For the convenience of description, in the following description, the total number of dimensions of the data is defined as N (in order of 0, 1, 2, ..., N-3, N-2, N-1, continuing the above example, N is 4), where the 0th dimension is the outermost dimension, the 1st to N-3rd dimensions are the second outer dimensions, the N-2th dimension is the second inner dimension, and the N-1th dimension is the innermost dimension. If the shape and size of the input tensor data DIN are inconsistent with the shape and size of the output tensor data DO, the central processor 101 will configure the corresponding default instruction CMD to expand the dimension of the input tensor data DIN through the intelligent processor 100 so that element-by-element operations can be performed correctly.
[0036] In practical applications, considering the limited data capacity of the register 110, if the size of the input tensor data DIN is large, the direct memory access controller 120 cannot store all the input tensor data DIN in the register 110 for operation at one time. Therefore, the direct memory access controller 120 will split the input tensor data DIN into multiple input block data DIB, and store the multiple input block data DIB block by block in the register 110 for subsequent operation. Similarly, the operation circuit 140 also generates multiple output block data DOB block by block, and outputs the multiple output block data DOB in sequence as output tensor data DO through the direct memory access controller 120, and stores the output tensor data DO in the memory 102. Therefore, when performing element-by-element operations, it is also required that the shape and size of the input block data DIB be the same as the shape and size of the output block data DOB.
[0037] In some embodiments, the central processor 101 can obtain the input tensor data DIN from the memory 102, and determine whether the shape and size of the input tensor data DIN are the same as the shape and size of the output tensor data DO. In this way, the central processor 101 can determine whether the input tensor data DIN needs to be expanded. If so, the central processor 101 will divide the input tensor data DIN (that is, configure the shape and size of the input block data DI B) and configure the corresponding multiple default instructions CMD, so that the intelligent processor 100 executes these default instructions CMD to perform the aforementioned multiple operations. The operations here will be referred to later. Figure 2 Detailed description of the process.
[0038] Figure 2 According to some embodiments of the present application, Figure 1 Flow chart of related operations performed by the central processor 101 and the intelligent processor 100. Operations S201 to S204 are multiple operations performed by the central processor 101, and operations S205 to S208 are multiple operations performed by the intelligent processor 100.
[0039] In operation S201, confirm whether the dimension of the input tensor data DIN is the same as the dimension of the output tensor data DO. If the same, confirm that the input tensor data DIN does not need to be expanded. If different, perform operation S202. For example, if the shape size of the output tensor data DO is [3, 32, 256, 18] and the shape size of the input tensor data DIN is [3, 32, 256, 18], the central processor 101 can determine that the dimension of the input tensor data DIN is the same as the dimension of the output tensor data DO. Alternatively, if the shape size of the output tensor data DO is [3, 32, 256, 18] and the shape size of the input tensor data DIN is [3, 32, 256, 1], the central processor 101 can determine that the dimension of the input tensor data DIN is different from the dimension of the output tensor data DO (that is, the innermost dimensions of the two are different).
[0040] In operation S202, it is confirmed whether the dimension number of the non-aligned dimension of the input tensor data DIN is 1. If not, it is confirmed that the dimension expansion of the input tensor data DIN is not supported. If so, operation S203 is performed. For example, in the aforementioned example, the dimension number of the innermost dimension of the input tensor data DIN is 1. Under this condition, the central processor 101 can confirm that the input tensor data DIN can be expanded. On the other hand, if the dimension number of the innermost dimension of the input tensor data DIN is not 1, the central processor 101 can confirm that the input tensor data DIN cannot be expanded.
[0041] In operation S203, the input tensor data DIN is dimensionally merged. For example, the shape size of the first input tensor data DIN to be processed is [1, 32, 256, 18], the shape size of the second input tensor data DIN to be processed is [3, 32, 256, 1], and the shape size of the output tensor data DO is [3, 32, 256, 18]. The above three data have the same number of dimensions in the consecutive N-3rd dimension and the N-2nd dimension (that is, the dimension number of the N-3rd dimension is 32, and the dimension number of the N-2nd dimension is 256). Under this condition, the central processing unit 101 can merge the N-3rd dimension with the N-2nd dimension, and the merged dimension number is the product of the two 8192 (that is, 32×256). The shape size of the merged first input tensor data DIN becomes [1,8192,18], the shape size of the merged second input tensor data DIN becomes [3,8192,1], and the shape size of the merged output tensor data DO becomes [3,8192,18]. By merging dimensions, the total dimension of the tensor data can be reduced to reduce the complexity of subsequent operations. In some embodiments, operation S203 is an optional operation.
[0042] In operation S204 , the shape and size of the output block data DOB are configured according to the storage capacity of the register 110 and the shape and size of the output tensor data DO, and a plurality of corresponding default instructions CMD are configured accordingly.
[0043] Generally speaking, the data arrangement of tensor data is based on the innermost dimension (i.e., the N-1th dimension) being prioritized. Therefore, the central processing unit 101 will also configure the shape and size of the output block data DOB based on the innermost dimension being prioritized. In some embodiments, the central processing unit 101 may configure the dimension number of each of the 0th to N-3th dimensions of the output block data DOB to 1, and configure the dimension numbers of the N-2th and N-1th dimensions according to the storage capacity of the register 110. For example, the dimension number of the N-1th dimension of the output block data DOB may be the minimum of the storage capacity of the register 110 and the dimension number of the N-1th dimension of the output tensor data DO, which may be expressed as tile(N-1)=min(VR size, the dimension number of the N-1th dimension), where tile(N-1) is the dimension number of the N-1th dimension of the output block data DOB, and VR size is the storage capacity of the register 110. The dimension number of the N-2th dimension of the output block data DOB may be the minimum of a preset ratio and the dimension number of the N-2th dimension of the output tensor data DO, wherein the default ratio is the storage capacity of the register 110 divided by the dimension number of the N-1th dimension of the output block data DOB. The dimension number of the N-2th dimension of the output block data DOB may be expressed as tile(N-2)=min(VR size / tile(N-1), dimension number of the N-2th dimension), wherein tile(N-2) is the dimension number of the N-2th dimension of the output block data DOB, and VR size is the dimension number of the N-2th dimension of the output tensor data DO.
[0044] For example, if the shape size of the merged output tensor data DO is [3, 6, 256, 16], the storage capacity of the register 110 is 1024, the dimension number tile(N-1) of the N-1th dimension of the output block data DOB may be min(1024, 16) = 16, and the dimension number tile(N-2) of the N-2th dimension of the output block data DOB may be min(1024 / 16, 256) = 64. In this way, it can be confirmed that the shape size of the output block data DOB is [1, 1, 64, 16].
[0045] In operation S205, the default instructions CMD are executed, and multiple input block data DIB of the input tensor data DIN are obtained from the memory 102 according to the shape and size of the configured output block data DOB, and are sequentially stored in the register 110. For example, the intelligent processor 100 can execute multiple default instructions CMD issued by the central processor 101, and read multiple input block data DIB from the memory 102 block by block according to the shape and size of the output block data DOB configured in operation S204, and sequentially store these input block data DIB to the register 110 to start element-by-element operation.
[0046] In operation S206, the N-1th dimension of the input block data DIB is selectively expanded to generate the first block data D1B. In some embodiments, the central processing unit 101 may determine in advance in the aforementioned operations S201 and S203 whether the N-1th dimension of the input block data DIB needs to be expanded. If so, the central processing unit 101 may insert corresponding data copy instructions in multiple default instructions CMD so that the intelligent processor 100 automatically expands the N-1th dimension of the input block data DIB when executing the data copy instruction. Alternatively, in other embodiments, the intelligent processor 100 may determine whether to expand the N-1th dimension of the input block data DIB according to the number of dimensions of the N-1th dimension of the input block data DIB and the number of dimensions of the N-1th dimension of the output block data DOB when executing multiple default instructions CMD.
[0047] For explanation of operation S206, please refer to Figure 3 , Figure 3 A schematic diagram is drawn for expanding the innermost dimension (i.e., the N-1th dimension) of the input block data DIB according to some embodiments of the present application. If the N-1th dimension of the input block data DIB needs to be expanded, the dimension number of the N-1th dimension of the input tensor data DIN and the dimension number of the N-1th dimension of the input block data DIB are both 1. For example, the shape size of the input tensor data DIN can be [d(0), d(1), ..., d(n-3), d(n-2), 1], and the shape size of the input block data DIB can be [1, 1, ..., 1, t(n-2), 1]. Under this condition, the instruction control circuit 130 can execute a data copy instruction from a plurality of default instructions CMD to expand the shape size of the input block data DIB to be the same as the shape size of the output block data DOB, which can be, for example, [1, 1, ..., 1, t(n-2), t(n-1)]. For example, the shape size of the output tensor data DO is [3, 6, 256, 16], the shape size of the output block data DOB is [1, 1, 64, 16], the shape size of the input tensor data DIN is [3, 6, 256, 1], and the shape size of the input block data DIB is [1, 1, 64, 1]. Under this condition, if Figure 3As shown, the instruction control circuit 130 can execute the aforementioned data copy instruction to copy the input block data DIB multiple times along the N-1th dimension of the input block data DIB in the register 110, wherein the number of multiple copies is the same as the number of dimensions of the N-1th dimension of the output block data DOB (16 times in this example) to generate the first block data D1B. In this way, the shape and size of the first block data D1B can be the same as the output block data DOB, so that the operation circuit 140 performs element-by-element operations based on this. Specifically, in this example, the input block data DIB contains 64 small block data (such as the blocks shown in the figure) in the N-2 dimension. After the aforementioned copy operation, the instruction control circuit 130 can generate 16×64 small block data and output these small block data as the first block data D1B.
[0048] In some embodiments, the aforementioned data copy instruction may be, but is not limited to, “vCopyElement byX”, which is one of the instructions executable by the intelligent processor 100 and functions to copy all elements X times, where X is 16 in the aforementioned example.
[0049] Continue to refer to Figure 2 , in operation S207, the N-2th dimension of the input block data DIB is selectively expanded to generate the first block data D1B. Similarly, in some embodiments, the central processing unit 101 may determine in advance in the aforementioned operations S201 and S203 whether the N-2th dimension of the input block data DIB needs to be expanded. If so, the central processing unit 101 may insert corresponding data copy instructions in multiple default instructions CMD so that the intelligent processor 100 automatically expands the N-2th dimension of the input block data DIB when executing the data copy instruction. Alternatively, in other embodiments, the intelligent processor 100 may determine whether to expand the N-2th dimension of the input block data DIB according to the number of dimensions of the N-2th dimension of the input block data DIB and the number of dimensions of the N-2th dimension of the output block data DOB when executing multiple default instructions CMD.
[0050] For explanation of operation S207, please refer to Figure 4 , Figure 4A schematic diagram is drawn for expanding the secondary inner dimension (i.e., the N-2th dimension) of the input block data DIB according to some embodiments of the present application. If the N-2th dimension of the input block data DIB needs to be expanded, the dimension number of the N-2th dimension of the input tensor data DIN and the dimension number of the N-2th dimension of the input block data DIB are both 1. For example, the shape size of the input tensor data DIN can be [d(0), d(1), ..., d(n-3), 1, d(n-1)], and the shape size of the input block data DIB can be [1, 1, ..., 1, 1, t(n-1)]. Under this condition, the instruction control circuit 130 can execute a data copy instruction from a plurality of default instructions CMD to expand the shape size of the input block data DIB to be the same as the shape size of the output block data DOB, for example, [1, 1, ..., 1, t(n-2), t(n-1)]. For example, the shape size of the output tensor data DO is [3, 6, 256, 16], the shape size of the output block data DOB is [1, 1, 64, 16], the shape size of the input tensor data DIN is [3, 6, 1, 16], and the shape size of the input block data DIB is [1, 1, 1, 16]. Under this condition, if Figure 4 As shown, the instruction control circuit 130 can execute the aforementioned data copy instruction to copy the input block data DIB multiple times along the N-2th dimension of the input block data DIB in the register 110, wherein the number of multiple copies is the same as the number of dimensions of the N-2th dimension of the output block data DOB (64 times in this example) to generate the first block data D1B. In this way, the shape and size of the first block data D1B can be the same as the output block data DOB, so that the operation circuit 140 performs element-by-element operations based on this. Specifically, in this example, the input block data DIB contains 16 small block data (such as the blocks shown in the figure) in the N-1 dimension. After the aforementioned copy operation, the instruction control circuit 130 can generate 64×16 small block data and output these small block data as the first block data D1B.
[0051] In some embodiments, the aforementioned data copy instruction may be, but is not limited to, “vCopyNbyX”, which is one of the instructions executable by the intelligent processor 100 and functions to copy N elements X times, where, in the aforementioned example, N is 16 and X is 64.
[0052] Continue to refer to Figure 2 In operation S208, the first block data D1B after dimension expansion is used to perform element-by-element operation to generate output block data DOB, and the output block data DOB is stored in the memory 102 to generate output tensor data DO.
[0053] Through the above operation, the shape and size of the first block data D1B can be the same as the shape and size of the output block data DOB. Under this condition, the operation circuit 140 can use the first block data D1B to perform element-by-element operations to generate a corresponding output block data DOB. Repeat the above operation until all the output block data DOB are generated, and the direct memory access controller 120 can store multiple output block data DOB from the register 110 in sequence to the memory 102 to be combined into the output tensor data DO.
[0054] Since the central processing unit 101 configures the number of dimensions of each of the 0th dimension to the N-3th dimension of the output block data DOB to be 1, the number of dimensions of each of the 0th dimension to the N-3th dimension of the input block data DIB (i.e., each is 1) will be respectively the same as the number of dimensions of each of the 0th dimension to the N-3th dimension of the output block data DOB (i.e., each is 1). Therefore, the intelligent processor 100 does not need to perform data dimension expansion on the 0th dimension to the N-3th dimension of the input block data. Specifically, the number of dimensions (i.e., 1) of the outermost dimension (i.e., 0th dimension) of the input block data DIB is the same as the number of dimensions (i.e., 1) of the outermost dimension (i.e., 0th dimension) of the output block data DOB, and the number of dimensions (i.e., 1) of the second outer dimension (e.g., which may be the N-3th dimension) of the input block data DIB is the same as the number of dimensions (i.e., 1) of the second outer dimension (e.g., which may be the N-3th dimension) of the output block data DOB. In this way, for the x-th dimension of the input block data DIB (where x is any value from 0 to N-3), the operation circuit 140 can reuse the same input block data DIB on the x-th dimension to perform element-by-element operations without expanding the input block data DIB.
[0055] In some related technologies, when processing element-by-element operations with inconsistent dimensions, the central processing unit inserts a block operator before the input tensor data that needs to be expanded, so as to copy the input tensor data in the main memory, thereby realizing data expansion. However, multiple data access and copying in the main memory will cause the overall processing efficiency to decrease, and will also significantly increase the storage space required for the main memory, thereby causing the implementation cost of the main memory to increase excessively. Different from the above-mentioned related technologies, the instruction control circuit 130 performs multiple data copies on the input block data DIB in the register 110, thereby equivalently expanding the input block data DIB. In other words, in some embodiments of the present application, the data expansion operation is performed on the register 110 (rather than the memory 102) with high-speed data access capability, thereby improving the overall processing efficiency and saving the implementation cost of the memory 102. In this way, the intelligent processor 100 can improve the processing efficiency and implementation cost of expanding the dimension of tensor data, thereby bringing clear improvements to related application fields that can use element-by-element operations (for example, may include, but are not limited to, related applications such as machine learning, deep learning and / or neural networks).
[0056] Figure 5 Flowchart of a data dimension expansion method 500 drawn according to some embodiments of the present application. In some embodiments, the data dimension expansion method 500 may be, but is not limited to, Figure 1 The intelligent processor 100 executes.
[0057] In operation S510, an input block data of an input tensor data is read from a memory and stored in a register in an intelligent processor. In operation S520, the input block data is copied along a first dimension of the input block data in the register according to the size of an output block data of an output tensor data to generate first block data, wherein the first block data and the output block data have the same size, and the plurality of first block data are used to perform an element-by-element operation to generate the output block data.
[0058] The description of the above-mentioned data dimension expansion method 500 can refer to the above-mentioned multiple embodiments, so it is not repeated here. The above-mentioned multiple operations are only examples and are not limited to being performed in the order in this example. Without violating the operation mode and scope of each embodiment of the present application, these operations can be appropriately added, replaced, omitted, performed in a different order, or can be performed simultaneously or partially simultaneously.
[0059] In summary, the intelligent processor and data dimension expansion method provided in some embodiments of the present application can perform high-speed data dimension expansion processing within the registers in the intelligent processor, thereby effectively saving overall costs and significantly improving the overall efficiency of data dimension expansion and performing element-by-element operations.
[0060] Although the embodiments of the present application are described above, these embodiments are not intended to limit the present application. Technicians in this technical field may change the technical features of the present application based on the explicit or implicit contents of the present application. All these changes may fall within the scope of patent protection sought by the present application. The scope of patent protection of the present application shall be based on the scope of the patent application of this specification.
Claims
1. An intelligent processor, characterized in that: include: A register; a direct memory access controller, which obtains an input block data of an input tensor data from a memory, and stores the input block data in the register; an instruction control circuit, which copies the input block data along a first dimension of the input block data in the register according to the size of an output block data of an output tensor data to generate a first block data, wherein the first block data and the output block data have the same size; and An operation circuit performs an element-by-element operation using the first block data to generate the output block data.
2. The intelligent processor according to claim 1, characterized in that The first dimension includes an innermost dimension or a first inner dimension of the input block data.
3. The intelligent processor according to claim 1, characterized in that When the first dimension is an innermost dimension of the input block data, the instruction control circuit copies the input block data multiple times along the first dimension, and the number of the multiple copies is the same as the number of dimensions of an innermost dimension of the output block data.
4. The intelligent processor according to claim 1, characterized in that When the first dimension is a primary inner dimension of the input block data, the instruction control circuit copies the input block data multiple times along the first dimension, and the number of the multiple copies is the same as the number of dimensions of the primary inner dimension of the output block data.
5. The intelligent processor according to claim 1, characterized in that The dimension number of the first dimension is 1.
6. The intelligent processor according to claim 1, characterized in that The number of dimensions of an outermost dimension of the input block data is the same as the number of dimensions of an outermost dimension of the output block data.
7. The intelligent processor according to claim 1, characterized in that The number of dimensions of the primary outer dimension of the input block data is the same as the number of dimensions of the primary outer dimension of the output block data.
8. The intelligent processor according to claim 1, characterized in that The dimension number of an outermost dimension or a first outer dimension of the input block data is 1.
9. The intelligent processor according to claim 1, wherein: The instruction control circuit copies the input block data in response to a data copy instruction, and the copy instruction is generated by a central processing unit based on the fact that the number of dimensions of the input tensor data and the output tensor data in the first dimension are different and the number of dimensions of the input tensor data in the first dimension is 1.
10. A data dimension expansion method, characterized in that: Executed by an intelligent processor, the data dimension expansion method includes: Reading an input block data of an input tensor data from a memory, and storing the input block data in a register in the intelligent processor; and Copying the input block data along a first dimension of the input block data in the register according to a size of an output block data of an output tensor data to generate a first block data, The first block data and the output block data have the same size, and the first block data is used to perform an element-by-element operation to generate the output block data.